hw: Add support for LSI SAS1068 (mptsas) device
[qemu.git] / include / hw / timer / allwinner-a10-pit.h
1 #ifndef AW_A10_PIT_H
2 #define AW_A10_PIT_H
3
4 #include "hw/ptimer.h"
5
6 #define TYPE_AW_A10_PIT "allwinner-A10-timer"
7 #define AW_A10_PIT(obj) OBJECT_CHECK(AwA10PITState, (obj), TYPE_AW_A10_PIT)
8
9 #define AW_A10_PIT_TIMER_NR 6
10 #define AW_A10_PIT_TIMER_IRQ 0x1
11 #define AW_A10_PIT_WDOG_IRQ 0x100
12
13 #define AW_A10_PIT_TIMER_IRQ_EN 0
14 #define AW_A10_PIT_TIMER_IRQ_ST 0x4
15
16 #define AW_A10_PIT_TIMER_CONTROL 0x0
17 #define AW_A10_PIT_TIMER_EN 0x1
18 #define AW_A10_PIT_TIMER_RELOAD 0x2
19 #define AW_A10_PIT_TIMER_MODE 0x80
20
21 #define AW_A10_PIT_TIMER_INTERVAL 0x4
22 #define AW_A10_PIT_TIMER_COUNT 0x8
23 #define AW_A10_PIT_WDOG_CONTROL 0x90
24 #define AW_A10_PIT_WDOG_MODE 0x94
25
26 #define AW_A10_PIT_COUNT_CTL 0xa0
27 #define AW_A10_PIT_COUNT_RL_EN 0x2
28 #define AW_A10_PIT_COUNT_CLR_EN 0x1
29 #define AW_A10_PIT_COUNT_LO 0xa4
30 #define AW_A10_PIT_COUNT_HI 0xa8
31
32 #define AW_A10_PIT_TIMER_BASE 0x10
33 #define AW_A10_PIT_TIMER_BASE_END \
34 (AW_A10_PIT_TIMER_BASE * 6 + AW_A10_PIT_TIMER_COUNT)
35
36 #define AW_A10_PIT_DEFAULT_CLOCK 0x4
37
38 typedef struct AwA10PITState AwA10PITState;
39
40 typedef struct AwA10TimerContext {
41 AwA10PITState *container;
42 int index;
43 } AwA10TimerContext;
44
45 struct AwA10PITState {
46 /*< private >*/
47 SysBusDevice parent_obj;
48 /*< public >*/
49 qemu_irq irq[AW_A10_PIT_TIMER_NR];
50 ptimer_state * timer[AW_A10_PIT_TIMER_NR];
51 AwA10TimerContext timer_context[AW_A10_PIT_TIMER_NR];
52 MemoryRegion iomem;
53 uint32_t clk_freq[4];
54
55 uint32_t irq_enable;
56 uint32_t irq_status;
57 uint32_t control[AW_A10_PIT_TIMER_NR];
58 uint32_t interval[AW_A10_PIT_TIMER_NR];
59 uint32_t count[AW_A10_PIT_TIMER_NR];
60 uint32_t watch_dog_mode;
61 uint32_t watch_dog_control;
62 uint32_t count_lo;
63 uint32_t count_hi;
64 uint32_t count_ctl;
65 };
66
67 #endif