hw: Add support for LSI SAS1068 (mptsas) device
[qemu.git] / include / hw / timer / i8254_internal.h
1 /*
2 * QEMU 8253/8254 - internal interfaces
3 *
4 * Copyright (c) 2011 Jan Kiszka, Siemens AG
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #ifndef QEMU_I8254_INTERNAL_H
26 #define QEMU_I8254_INTERNAL_H
27
28 #include "hw/hw.h"
29 #include "hw/i386/pc.h"
30 #include "hw/isa/isa.h"
31
32 typedef struct PITChannelState {
33 int count; /* can be 65536 */
34 uint16_t latched_count;
35 uint8_t count_latched;
36 uint8_t status_latched;
37 uint8_t status;
38 uint8_t read_state;
39 uint8_t write_state;
40 uint8_t write_latch;
41 uint8_t rw_mode;
42 uint8_t mode;
43 uint8_t bcd; /* not supported */
44 uint8_t gate; /* timer start */
45 int64_t count_load_time;
46 /* irq handling */
47 int64_t next_transition_time;
48 QEMUTimer *irq_timer;
49 qemu_irq irq;
50 uint32_t irq_disabled;
51 } PITChannelState;
52
53 typedef struct PITCommonState {
54 ISADevice dev;
55 MemoryRegion ioports;
56 uint32_t iobase;
57 PITChannelState channels[3];
58 } PITCommonState;
59
60 #define TYPE_PIT_COMMON "pit-common"
61 #define PIT_COMMON(obj) \
62 OBJECT_CHECK(PITCommonState, (obj), TYPE_PIT_COMMON)
63 #define PIT_COMMON_CLASS(klass) \
64 OBJECT_CLASS_CHECK(PITCommonClass, (klass), TYPE_PIT_COMMON)
65 #define PIT_COMMON_GET_CLASS(obj) \
66 OBJECT_GET_CLASS(PITCommonClass, (obj), TYPE_PIT_COMMON)
67
68 typedef struct PITCommonClass {
69 ISADeviceClass parent_class;
70
71 void (*set_channel_gate)(PITCommonState *s, PITChannelState *sc, int val);
72 void (*get_channel_info)(PITCommonState *s, PITChannelState *sc,
73 PITChannelInfo *info);
74 void (*pre_save)(PITCommonState *s);
75 void (*post_load)(PITCommonState *s);
76 } PITCommonClass;
77
78 int pit_get_out(PITChannelState *s, int64_t current_time);
79 int64_t pit_get_next_transition_time(PITChannelState *s, int64_t current_time);
80 void pit_get_channel_info_common(PITCommonState *s, PITChannelState *sc,
81 PITChannelInfo *info);
82 void pit_reset_common(PITCommonState *s);
83
84 #endif /* !QEMU_I8254_INTERNAL_H */