Merge remote-tracking branch 'remotes/vivier/tags/trivial-branch-for-6.2-pull-request...
[qemu.git] / include / hw / xtensa / xtensa-isa.h
1 /* Interface definition for configurable Xtensa ISA support.
2 *
3 * Copyright (c) 2001-2013 Tensilica Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
17 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
19 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
20 * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #ifndef HW_XTENSA_XTENSA_ISA_H
26 #define HW_XTENSA_XTENSA_ISA_H
27
28 #ifdef __cplusplus
29 extern "C" {
30 #endif
31
32 /*
33 * Version number: This is intended to help support code that works with
34 * versions of this library from multiple Xtensa releases.
35 */
36
37 #define XTENSA_ISA_VERSION 7000
38
39 /*
40 * This file defines the interface to the Xtensa ISA library. This
41 * library contains most of the ISA-specific information for a
42 * particular Xtensa processor. For example, the set of valid
43 * instructions, their opcode encodings and operand fields are all
44 * included here.
45 *
46 * This interface basically defines a number of abstract data types.
47 *
48 * . an instruction buffer - for holding the raw instruction bits
49 * . ISA info - information about the ISA as a whole
50 * . instruction formats - instruction size and slot structure
51 * . opcodes - information about individual instructions
52 * . operands - information about register and immediate instruction operands
53 * . stateOperands - information about processor state instruction operands
54 * . interfaceOperands - information about interface instruction operands
55 * . register files - register file information
56 * . processor states - internal processor state information
57 * . system registers - "special registers" and "user registers"
58 * . interfaces - TIE interfaces that are external to the processor
59 * . functional units - TIE shared functions
60 *
61 * The interface defines a set of functions to access each data type.
62 * With the exception of the instruction buffer, the internal
63 * representations of the data structures are hidden. All accesses must
64 * be made through the functions defined here.
65 */
66
67 typedef struct xtensa_isa_opaque { int unused; } *xtensa_isa;
68
69
70 /*
71 * Most of the Xtensa ISA entities (e.g., opcodes, regfiles, etc.) are
72 * represented here using sequential integers beginning with 0. The
73 * specific values are only fixed for a particular instantiation of an
74 * xtensa_isa structure, so these values should only be used
75 * internally.
76 */
77
78 typedef int xtensa_opcode;
79 typedef int xtensa_format;
80 typedef int xtensa_regfile;
81 typedef int xtensa_state;
82 typedef int xtensa_sysreg;
83 typedef int xtensa_interface;
84 typedef int xtensa_funcUnit;
85
86
87 /* Define a unique value for undefined items. */
88
89 #define XTENSA_UNDEFINED -1
90
91
92 /*
93 * Overview of using this interface to decode/encode instructions:
94 *
95 * Each Xtensa instruction is associated with a particular instruction
96 * format, where the format defines a fixed number of slots for
97 * operations. The formats for the core Xtensa ISA have only one slot,
98 * but FLIX instructions may have multiple slots. Within each slot,
99 * there is a single opcode and some number of associated operands.
100 *
101 * The encoding and decoding functions operate on instruction buffers,
102 * not on the raw bytes of the instructions. The same instruction
103 * buffer data structure is used for both entire instructions and
104 * individual slots in those instructions -- the contents of a slot need
105 * to be extracted from or inserted into the buffer for the instruction
106 * as a whole.
107 *
108 * Decoding an instruction involves first finding the format, which
109 * identifies the number of slots, and then decoding each slot
110 * separately. A slot is decoded by finding the opcode and then using
111 * the opcode to determine how many operands there are. For example:
112 *
113 * xtensa_insnbuf_from_chars
114 * xtensa_format_decode
115 * for each slot {
116 * xtensa_format_get_slot
117 * xtensa_opcode_decode
118 * for each operand {
119 * xtensa_operand_get_field
120 * xtensa_operand_decode
121 * }
122 * }
123 *
124 * Encoding an instruction is roughly the same procedure in reverse:
125 *
126 * xtensa_format_encode
127 * for each slot {
128 * xtensa_opcode_encode
129 * for each operand {
130 * xtensa_operand_encode
131 * xtensa_operand_set_field
132 * }
133 * xtensa_format_set_slot
134 * }
135 * xtensa_insnbuf_to_chars
136 */
137
138
139 /* Error handling. */
140
141 /*
142 * Error codes. The code for the most recent error condition can be
143 * retrieved with the "errno" function. For any result other than
144 * xtensa_isa_ok, an error message containing additional information
145 * about the problem can be retrieved using the "error_msg" function.
146 * The error messages are stored in an internal buffer, which should
147 * not be freed and may be overwritten by subsequent operations.
148 */
149
150 typedef enum xtensa_isa_status_enum {
151 xtensa_isa_ok = 0,
152 xtensa_isa_bad_format,
153 xtensa_isa_bad_slot,
154 xtensa_isa_bad_opcode,
155 xtensa_isa_bad_operand,
156 xtensa_isa_bad_field,
157 xtensa_isa_bad_iclass,
158 xtensa_isa_bad_regfile,
159 xtensa_isa_bad_sysreg,
160 xtensa_isa_bad_state,
161 xtensa_isa_bad_interface,
162 xtensa_isa_bad_funcUnit,
163 xtensa_isa_wrong_slot,
164 xtensa_isa_no_field,
165 xtensa_isa_out_of_memory,
166 xtensa_isa_buffer_overflow,
167 xtensa_isa_internal_error,
168 xtensa_isa_bad_value
169 } xtensa_isa_status;
170
171 xtensa_isa_status xtensa_isa_errno(xtensa_isa isa);
172
173 char *xtensa_isa_error_msg(xtensa_isa isa);
174
175
176
177 /* Instruction buffers. */
178
179 typedef uint32_t xtensa_insnbuf_word;
180 typedef xtensa_insnbuf_word *xtensa_insnbuf;
181
182
183 /* Get the size in "insnbuf_words" of the xtensa_insnbuf array. */
184
185 int xtensa_insnbuf_size(xtensa_isa isa);
186
187
188 /* Allocate an xtensa_insnbuf of the right size. */
189
190 xtensa_insnbuf xtensa_insnbuf_alloc(xtensa_isa isa);
191
192
193 /* Release an xtensa_insnbuf. */
194
195 void xtensa_insnbuf_free(xtensa_isa isa, xtensa_insnbuf buf);
196
197
198 /*
199 * Conversion between raw memory (char arrays) and our internal
200 * instruction representation. This is complicated by the Xtensa ISA's
201 * variable instruction lengths. When converting to chars, the buffer
202 * must contain a valid instruction so we know how many bytes to copy;
203 * thus, the "to_chars" function returns the number of bytes copied or
204 * XTENSA_UNDEFINED on error. The "from_chars" function first reads the
205 * minimal number of bytes required to decode the instruction length and
206 * then proceeds to copy the entire instruction into the buffer; if the
207 * memory does not contain a valid instruction, it copies the maximum
208 * number of bytes required for the longest Xtensa instruction. The
209 * "num_chars" argument may be used to limit the number of bytes that
210 * can be read or written. Otherwise, if "num_chars" is zero, the
211 * functions may read or write past the end of the code.
212 */
213
214 int xtensa_insnbuf_to_chars(xtensa_isa isa, const xtensa_insnbuf insn,
215 unsigned char *cp, int num_chars);
216
217 void xtensa_insnbuf_from_chars(xtensa_isa isa, xtensa_insnbuf insn,
218 const unsigned char *cp, int num_chars);
219
220
221
222 /* ISA information. */
223
224 /* Initialize the ISA information. */
225
226 xtensa_isa xtensa_isa_init(void *xtensa_modules, xtensa_isa_status *errno_p,
227 char **error_msg_p);
228
229
230 /* Deallocate an xtensa_isa structure. */
231
232 void xtensa_isa_free(xtensa_isa isa);
233
234
235 /* Get the maximum instruction size in bytes. */
236
237 int xtensa_isa_maxlength(xtensa_isa isa);
238
239
240 /*
241 * Decode the length in bytes of an instruction in raw memory (not an
242 * insnbuf). This function reads only the minimal number of bytes
243 * required to decode the instruction length. Returns
244 * XTENSA_UNDEFINED on error.
245 */
246
247 int xtensa_isa_length_from_chars(xtensa_isa isa, const unsigned char *cp);
248
249
250 /*
251 * Get the number of stages in the processor's pipeline. The pipeline
252 * stage values returned by other functions in this library will range
253 * from 0 to N-1, where N is the value returned by this function.
254 * Note that the stage numbers used here may not correspond to the
255 * actual processor hardware, e.g., the hardware may have additional
256 * stages before stage 0. Returns XTENSA_UNDEFINED on error.
257 */
258
259 int xtensa_isa_num_pipe_stages(xtensa_isa isa);
260
261
262 /* Get the number of various entities that are defined for this processor. */
263
264 int xtensa_isa_num_formats(xtensa_isa isa);
265
266 int xtensa_isa_num_opcodes(xtensa_isa isa);
267
268 int xtensa_isa_num_regfiles(xtensa_isa isa);
269
270 int xtensa_isa_num_states(xtensa_isa isa);
271
272 int xtensa_isa_num_sysregs(xtensa_isa isa);
273
274 int xtensa_isa_num_interfaces(xtensa_isa isa);
275
276 int xtensa_isa_num_funcUnits(xtensa_isa isa);
277
278
279
280 /* Instruction formats. */
281
282 /* Get the name of a format. Returns null on error. */
283
284 const char *xtensa_format_name(xtensa_isa isa, xtensa_format fmt);
285
286
287 /*
288 * Given a format name, return the format number. Returns
289 * XTENSA_UNDEFINED if the name is not a valid format.
290 */
291
292 xtensa_format xtensa_format_lookup(xtensa_isa isa, const char *fmtname);
293
294
295 /*
296 * Decode the instruction format from a binary instruction buffer.
297 * Returns XTENSA_UNDEFINED if the format is not recognized.
298 */
299
300 xtensa_format xtensa_format_decode(xtensa_isa isa, const xtensa_insnbuf insn);
301
302
303 /*
304 * Set the instruction format field(s) in a binary instruction buffer.
305 * All the other fields are set to zero. Returns non-zero on error.
306 */
307
308 int xtensa_format_encode(xtensa_isa isa, xtensa_format fmt,
309 xtensa_insnbuf insn);
310
311
312 /*
313 * Find the length (in bytes) of an instruction. Returns
314 * XTENSA_UNDEFINED on error.
315 */
316
317 int xtensa_format_length(xtensa_isa isa, xtensa_format fmt);
318
319
320 /*
321 * Get the number of slots in an instruction. Returns XTENSA_UNDEFINED
322 * on error.
323 */
324
325 int xtensa_format_num_slots(xtensa_isa isa, xtensa_format fmt);
326
327
328 /*
329 * Get the opcode for a no-op in a particular slot.
330 * Returns XTENSA_UNDEFINED on error.
331 */
332
333 xtensa_opcode xtensa_format_slot_nop_opcode(xtensa_isa isa, xtensa_format fmt,
334 int slot);
335
336
337 /*
338 * Get the bits for a specified slot out of an insnbuf for the
339 * instruction as a whole and put them into an insnbuf for that one
340 * slot, and do the opposite to set a slot. Return non-zero on error.
341 */
342
343 int xtensa_format_get_slot(xtensa_isa isa, xtensa_format fmt, int slot,
344 const xtensa_insnbuf insn, xtensa_insnbuf slotbuf);
345
346 int xtensa_format_set_slot(xtensa_isa isa, xtensa_format fmt, int slot,
347 xtensa_insnbuf insn, const xtensa_insnbuf slotbuf);
348
349
350
351 /* Opcode information. */
352
353 /*
354 * Translate a mnemonic name to an opcode. Returns XTENSA_UNDEFINED if
355 * the name is not a valid opcode mnemonic.
356 */
357
358 xtensa_opcode xtensa_opcode_lookup(xtensa_isa isa, const char *opname);
359
360
361 /*
362 * Decode the opcode for one instruction slot from a binary instruction
363 * buffer. Returns the opcode or XTENSA_UNDEFINED if the opcode is
364 * illegal.
365 */
366
367 xtensa_opcode xtensa_opcode_decode(xtensa_isa isa, xtensa_format fmt, int slot,
368 const xtensa_insnbuf slotbuf);
369
370
371 /*
372 * Set the opcode field(s) for an instruction slot. All other fields
373 * in the slot are set to zero. Returns non-zero if the opcode cannot
374 * be encoded.
375 */
376
377 int xtensa_opcode_encode(xtensa_isa isa, xtensa_format fmt, int slot,
378 xtensa_insnbuf slotbuf, xtensa_opcode opc);
379
380
381 /* Get the mnemonic name for an opcode. Returns null on error. */
382
383 const char *xtensa_opcode_name(xtensa_isa isa, xtensa_opcode opc);
384
385
386 /* Check various properties of opcodes. These functions return 0 if
387 * the condition is false, 1 if the condition is true, and
388 * XTENSA_UNDEFINED on error. The instructions are classified as
389 * follows:
390 *
391 * branch: conditional branch; may fall through to next instruction (B*)
392 * jump: unconditional branch (J, JX, RET*, RF*)
393 * loop: zero-overhead loop (LOOP*)
394 * call: unconditional call; control returns to next instruction (CALL*)
395 *
396 * For the opcodes that affect control flow in some way, the branch
397 * target may be specified by an immediate operand or it may be an
398 * address stored in a register. You can distinguish these by
399 * checking if the instruction has a PC-relative immediate
400 * operand.
401 */
402
403 int xtensa_opcode_is_branch(xtensa_isa isa, xtensa_opcode opc);
404
405 int xtensa_opcode_is_jump(xtensa_isa isa, xtensa_opcode opc);
406
407 int xtensa_opcode_is_loop(xtensa_isa isa, xtensa_opcode opc);
408
409 int xtensa_opcode_is_call(xtensa_isa isa, xtensa_opcode opc);
410
411
412 /*
413 * Find the number of ordinary operands, state operands, and interface
414 * operands for an instruction. These return XTENSA_UNDEFINED on
415 * error.
416 */
417
418 int xtensa_opcode_num_operands(xtensa_isa isa, xtensa_opcode opc);
419
420 int xtensa_opcode_num_stateOperands(xtensa_isa isa, xtensa_opcode opc);
421
422 int xtensa_opcode_num_interfaceOperands(xtensa_isa isa, xtensa_opcode opc);
423
424
425 /*
426 * Get functional unit usage requirements for an opcode. Each "use"
427 * is identified by a <functional unit, pipeline stage> pair. The
428 * "num_funcUnit_uses" function returns the number of these "uses" or
429 * XTENSA_UNDEFINED on error. The "funcUnit_use" function returns
430 * a pointer to a "use" pair or null on error.
431 */
432
433 typedef struct xtensa_funcUnit_use_struct {
434 xtensa_funcUnit unit;
435 int stage;
436 } xtensa_funcUnit_use;
437
438 int xtensa_opcode_num_funcUnit_uses(xtensa_isa isa, xtensa_opcode opc);
439
440 xtensa_funcUnit_use *xtensa_opcode_funcUnit_use(xtensa_isa isa,
441 xtensa_opcode opc, int u);
442
443
444
445 /* Operand information. */
446
447 /* Get the name of an operand. Returns null on error. */
448
449 const char *xtensa_operand_name(xtensa_isa isa, xtensa_opcode opc, int opnd);
450
451
452 /*
453 * Some operands are "invisible", i.e., not explicitly specified in
454 * assembly language. When assembling an instruction, you need not set
455 * the values of invisible operands, since they are either hardwired or
456 * derived from other field values. The values of invisible operands
457 * can be examined in the same way as other operands, but remember that
458 * an invisible operand may get its value from another visible one, so
459 * the entire instruction must be available before examining the
460 * invisible operand values. This function returns 1 if an operand is
461 * visible, 0 if it is invisible, or XTENSA_UNDEFINED on error. Note
462 * that whether an operand is visible is orthogonal to whether it is
463 * "implicit", i.e., whether it is encoded in a field in the
464 * instruction.
465 */
466
467 int xtensa_operand_is_visible(xtensa_isa isa, xtensa_opcode opc, int opnd);
468
469
470 /*
471 * Check if an operand is an input ('i'), output ('o'), or inout ('m')
472 * operand. Note: The output operand of a conditional assignment
473 * (e.g., movnez) appears here as an inout ('m') even if it is declared
474 * in the TIE code as an output ('o'); this allows the compiler to
475 * properly handle register allocation for conditional assignments.
476 * Returns 0 on error.
477 */
478
479 char xtensa_operand_inout(xtensa_isa isa, xtensa_opcode opc, int opnd);
480
481
482 /*
483 * Get and set the raw (encoded) value of the field for the specified
484 * operand. The "set" function does not check if the value fits in the
485 * field; that is done by the "encode" function below. Both of these
486 * functions return non-zero on error, e.g., if the field is not defined
487 * for the specified slot.
488 */
489
490 int xtensa_operand_get_field(xtensa_isa isa, xtensa_opcode opc, int opnd,
491 xtensa_format fmt, int slot,
492 const xtensa_insnbuf slotbuf, uint32_t *valp);
493
494 int xtensa_operand_set_field(xtensa_isa isa, xtensa_opcode opc, int opnd,
495 xtensa_format fmt, int slot,
496 xtensa_insnbuf slotbuf, uint32_t val);
497
498
499 /*
500 * Encode and decode operands. The raw bits in the operand field may
501 * be encoded in a variety of different ways. These functions hide
502 * the details of that encoding. The result values are returned through
503 * the argument pointer. The return value is non-zero on error.
504 */
505
506 int xtensa_operand_encode(xtensa_isa isa, xtensa_opcode opc, int opnd,
507 uint32_t *valp);
508
509 int xtensa_operand_decode(xtensa_isa isa, xtensa_opcode opc, int opnd,
510 uint32_t *valp);
511
512
513 /*
514 * An operand may be either a register operand or an immediate of some
515 * sort (e.g., PC-relative or not). The "is_register" function returns
516 * 0 if the operand is an immediate, 1 if it is a register, and
517 * XTENSA_UNDEFINED on error. The "regfile" function returns the
518 * regfile for a register operand, or XTENSA_UNDEFINED on error.
519 */
520
521 int xtensa_operand_is_register(xtensa_isa isa, xtensa_opcode opc, int opnd);
522
523 xtensa_regfile xtensa_operand_regfile(xtensa_isa isa, xtensa_opcode opc,
524 int opnd);
525
526
527 /*
528 * Register operands may span multiple consecutive registers, e.g., a
529 * 64-bit data type may occupy two 32-bit registers. Only the first
530 * register is encoded in the operand field. This function specifies
531 * the number of consecutive registers occupied by this operand. For
532 * non-register operands, the return value is undefined. Returns
533 * XTENSA_UNDEFINED on error.
534 */
535
536 int xtensa_operand_num_regs(xtensa_isa isa, xtensa_opcode opc, int opnd);
537
538
539 /*
540 * Some register operands do not completely identify the register being
541 * accessed. For example, the operand value may be added to an internal
542 * state value. By definition, this implies that the corresponding
543 * regfile is not allocatable. Unknown registers should generally be
544 * treated with worst-case assumptions. The function returns 0 if the
545 * register value is unknown, 1 if known, and XTENSA_UNDEFINED on
546 * error.
547 */
548
549 int xtensa_operand_is_known_reg(xtensa_isa isa, xtensa_opcode opc, int opnd);
550
551
552 /*
553 * Check if an immediate operand is PC-relative. Returns 0 for register
554 * operands and non-PC-relative immediates, 1 for PC-relative
555 * immediates, and XTENSA_UNDEFINED on error.
556 */
557
558 int xtensa_operand_is_PCrelative(xtensa_isa isa, xtensa_opcode opc, int opnd);
559
560
561 /*
562 * For PC-relative offset operands, the interpretation of the offset may
563 * vary between opcodes, e.g., is it relative to the current PC or that
564 * of the next instruction? The following functions are defined to
565 * perform PC-relative relocations and to undo them (as in the
566 * disassembler). The "do_reloc" function takes the desired address
567 * value and the PC of the current instruction and sets the value to the
568 * corresponding PC-relative offset (which can then be encoded and
569 * stored into the operand field). The "undo_reloc" function takes the
570 * unencoded offset value and the current PC and sets the value to the
571 * appropriate address. The return values are non-zero on error. Note
572 * that these functions do not replace the encode/decode functions; the
573 * operands must be encoded/decoded separately and the encode functions
574 * are responsible for detecting invalid operand values.
575 */
576
577 int xtensa_operand_do_reloc(xtensa_isa isa, xtensa_opcode opc, int opnd,
578 uint32_t *valp, uint32_t pc);
579
580 int xtensa_operand_undo_reloc(xtensa_isa isa, xtensa_opcode opc, int opnd,
581 uint32_t *valp, uint32_t pc);
582
583
584
585 /* State Operands. */
586
587 /*
588 * Get the state accessed by a state operand. Returns XTENSA_UNDEFINED
589 * on error.
590 */
591
592 xtensa_state xtensa_stateOperand_state(xtensa_isa isa, xtensa_opcode opc,
593 int stOp);
594
595
596 /*
597 * Check if a state operand is an input ('i'), output ('o'), or inout
598 * ('m') operand. Returns 0 on error.
599 */
600
601 char xtensa_stateOperand_inout(xtensa_isa isa, xtensa_opcode opc, int stOp);
602
603
604
605 /* Interface Operands. */
606
607 /*
608 * Get the external interface accessed by an interface operand.
609 * Returns XTENSA_UNDEFINED on error.
610 */
611
612 xtensa_interface xtensa_interfaceOperand_interface(xtensa_isa isa,
613 xtensa_opcode opc,
614 int ifOp);
615
616
617
618 /* Register Files. */
619
620 /*
621 * Regfiles include both "real" regfiles and "views", where a view
622 * allows a group of adjacent registers in a real "parent" regfile to be
623 * viewed as a single register. A regfile view has all the same
624 * properties as its parent except for its (long) name, bit width, number
625 * of entries, and default ctype. You can use the parent function to
626 * distinguish these two classes.
627 */
628
629 /*
630 * Look up a regfile by either its name or its abbreviated "short name".
631 * Returns XTENSA_UNDEFINED on error. The "lookup_shortname" function
632 * ignores "view" regfiles since they always have the same shortname as
633 * their parents.
634 */
635
636 xtensa_regfile xtensa_regfile_lookup(xtensa_isa isa, const char *name);
637
638 xtensa_regfile xtensa_regfile_lookup_shortname(xtensa_isa isa,
639 const char *shortname);
640
641
642 /*
643 * Get the name or abbreviated "short name" of a regfile.
644 * Returns null on error.
645 */
646
647 const char *xtensa_regfile_name(xtensa_isa isa, xtensa_regfile rf);
648
649 const char *xtensa_regfile_shortname(xtensa_isa isa, xtensa_regfile rf);
650
651
652 /*
653 * Get the parent regfile of a "view" regfile. If the regfile is not a
654 * view, the result is the same as the input parameter. Returns
655 * XTENSA_UNDEFINED on error.
656 */
657
658 xtensa_regfile xtensa_regfile_view_parent(xtensa_isa isa, xtensa_regfile rf);
659
660
661 /*
662 * Get the bit width of a regfile or regfile view.
663 * Returns XTENSA_UNDEFINED on error.
664 */
665
666 int xtensa_regfile_num_bits(xtensa_isa isa, xtensa_regfile rf);
667
668
669 /*
670 * Get the number of regfile entries. Returns XTENSA_UNDEFINED on
671 * error.
672 */
673
674 int xtensa_regfile_num_entries(xtensa_isa isa, xtensa_regfile rf);
675
676
677
678 /* Processor States. */
679
680 /* Look up a state by name. Returns XTENSA_UNDEFINED on error. */
681
682 xtensa_state xtensa_state_lookup(xtensa_isa isa, const char *name);
683
684
685 /* Get the name for a processor state. Returns null on error. */
686
687 const char *xtensa_state_name(xtensa_isa isa, xtensa_state st);
688
689
690 /*
691 * Get the bit width for a processor state.
692 * Returns XTENSA_UNDEFINED on error.
693 */
694
695 int xtensa_state_num_bits(xtensa_isa isa, xtensa_state st);
696
697
698 /*
699 * Check if a state is exported from the processor core. Returns 0 if
700 * the condition is false, 1 if the condition is true, and
701 * XTENSA_UNDEFINED on error.
702 */
703
704 int xtensa_state_is_exported(xtensa_isa isa, xtensa_state st);
705
706
707 /*
708 * Check for a "shared_or" state. Returns 0 if the condition is false,
709 * 1 if the condition is true, and XTENSA_UNDEFINED on error.
710 */
711
712 int xtensa_state_is_shared_or(xtensa_isa isa, xtensa_state st);
713
714
715
716 /* Sysregs ("special registers" and "user registers"). */
717
718 /*
719 * Look up a register by its number and whether it is a "user register"
720 * or a "special register". Returns XTENSA_UNDEFINED if the sysreg does
721 * not exist.
722 */
723
724 xtensa_sysreg xtensa_sysreg_lookup(xtensa_isa isa, int num, int is_user);
725
726
727 /*
728 * Check if there exists a sysreg with a given name.
729 * If not, this function returns XTENSA_UNDEFINED.
730 */
731
732 xtensa_sysreg xtensa_sysreg_lookup_name(xtensa_isa isa, const char *name);
733
734
735 /* Get the name of a sysreg. Returns null on error. */
736
737 const char *xtensa_sysreg_name(xtensa_isa isa, xtensa_sysreg sysreg);
738
739
740 /* Get the register number. Returns XTENSA_UNDEFINED on error. */
741
742 int xtensa_sysreg_number(xtensa_isa isa, xtensa_sysreg sysreg);
743
744
745 /*
746 * Check if a sysreg is a "special register" or a "user register".
747 * Returns 0 for special registers, 1 for user registers and
748 * XTENSA_UNDEFINED on error.
749 */
750
751 int xtensa_sysreg_is_user(xtensa_isa isa, xtensa_sysreg sysreg);
752
753
754
755 /* Interfaces. */
756
757 /*
758 * Find an interface by name. The return value is XTENSA_UNDEFINED if
759 * the specified interface is not found.
760 */
761
762 xtensa_interface xtensa_interface_lookup(xtensa_isa isa, const char *ifname);
763
764
765 /* Get the name of an interface. Returns null on error. */
766
767 const char *xtensa_interface_name(xtensa_isa isa, xtensa_interface intf);
768
769
770 /*
771 * Get the bit width for an interface.
772 * Returns XTENSA_UNDEFINED on error.
773 */
774
775 int xtensa_interface_num_bits(xtensa_isa isa, xtensa_interface intf);
776
777
778 /*
779 * Check if an interface is an input ('i') or output ('o') with respect
780 * to the Xtensa processor core. Returns 0 on error.
781 */
782
783 char xtensa_interface_inout(xtensa_isa isa, xtensa_interface intf);
784
785
786 /*
787 * Check if accessing an interface has potential side effects.
788 * Currently "data" interfaces have side effects and "control"
789 * interfaces do not. Returns 1 if there are side effects, 0 if not,
790 * and XTENSA_UNDEFINED on error.
791 */
792
793 int xtensa_interface_has_side_effect(xtensa_isa isa, xtensa_interface intf);
794
795
796 /*
797 * Some interfaces may be related such that accessing one interface
798 * has side effects on a set of related interfaces. The interfaces
799 * are partitioned into equivalence classes of related interfaces, and
800 * each class is assigned a unique identifier number. This function
801 * returns the class identifier for an interface, or XTENSA_UNDEFINED
802 * on error. These identifiers can be compared to determine if two
803 * interfaces are related; the specific values of the identifiers have
804 * no particular meaning otherwise.
805 */
806
807 int xtensa_interface_class_id(xtensa_isa isa, xtensa_interface intf);
808
809
810 /* Functional Units. */
811
812 /*
813 * Find a functional unit by name. The return value is XTENSA_UNDEFINED if
814 * the specified unit is not found.
815 */
816
817 xtensa_funcUnit xtensa_funcUnit_lookup(xtensa_isa isa, const char *fname);
818
819
820 /* Get the name of a functional unit. Returns null on error. */
821
822 const char *xtensa_funcUnit_name(xtensa_isa isa, xtensa_funcUnit fun);
823
824
825 /*
826 * Functional units may be replicated. See how many instances of a
827 * particular function unit exist. Returns XTENSA_UNDEFINED on error.
828 */
829
830 int xtensa_funcUnit_num_copies(xtensa_isa isa, xtensa_funcUnit fun);
831
832
833 #ifdef __cplusplus
834 }
835 #endif
836 #endif /* HW_XTENSA_XTENSA_ISA_H */