cpu: Move jmp_env field from CPU_COMMON to CPUState
[qemu.git] / include / qom / cpu.h
1 /*
2 * QEMU CPU model
3 *
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
19 */
20 #ifndef QEMU_CPU_H
21 #define QEMU_CPU_H
22
23 #include <signal.h>
24 #include <setjmp.h>
25 #include "hw/qdev-core.h"
26 #include "exec/hwaddr.h"
27 #include "qemu/queue.h"
28 #include "qemu/thread.h"
29 #include "qemu/tls.h"
30 #include "qemu/typedefs.h"
31
32 typedef int (*WriteCoreDumpFunction)(const void *buf, size_t size,
33 void *opaque);
34
35 /**
36 * vaddr:
37 * Type wide enough to contain any #target_ulong virtual address.
38 */
39 typedef uint64_t vaddr;
40 #define VADDR_PRId PRId64
41 #define VADDR_PRIu PRIu64
42 #define VADDR_PRIo PRIo64
43 #define VADDR_PRIx PRIx64
44 #define VADDR_PRIX PRIX64
45 #define VADDR_MAX UINT64_MAX
46
47 /**
48 * SECTION:cpu
49 * @section_id: QEMU-cpu
50 * @title: CPU Class
51 * @short_description: Base class for all CPUs
52 */
53
54 #define TYPE_CPU "cpu"
55
56 #define CPU(obj) OBJECT_CHECK(CPUState, (obj), TYPE_CPU)
57 #define CPU_CLASS(class) OBJECT_CLASS_CHECK(CPUClass, (class), TYPE_CPU)
58 #define CPU_GET_CLASS(obj) OBJECT_GET_CLASS(CPUClass, (obj), TYPE_CPU)
59
60 typedef struct CPUState CPUState;
61
62 typedef void (*CPUUnassignedAccess)(CPUState *cpu, hwaddr addr,
63 bool is_write, bool is_exec, int opaque,
64 unsigned size);
65
66 struct TranslationBlock;
67
68 /**
69 * CPUClass:
70 * @class_by_name: Callback to map -cpu command line model name to an
71 * instantiatable CPU type.
72 * @parse_features: Callback to parse command line arguments.
73 * @reset: Callback to reset the #CPUState to its initial state.
74 * @reset_dump_flags: #CPUDumpFlags to use for reset logging.
75 * @has_work: Callback for checking if there is work to do.
76 * @do_interrupt: Callback for interrupt handling.
77 * @do_unassigned_access: Callback for unassigned access handling.
78 * @memory_rw_debug: Callback for GDB memory access.
79 * @dump_state: Callback for dumping state.
80 * @dump_statistics: Callback for dumping statistics.
81 * @get_arch_id: Callback for getting architecture-dependent CPU ID.
82 * @get_paging_enabled: Callback for inquiring whether paging is enabled.
83 * @get_memory_mapping: Callback for obtaining the memory mappings.
84 * @set_pc: Callback for setting the Program Counter register.
85 * @synchronize_from_tb: Callback for synchronizing state from a TCG
86 * #TranslationBlock.
87 * @handle_mmu_fault: Callback for handling an MMU fault.
88 * @get_phys_page_debug: Callback for obtaining a physical address.
89 * @gdb_read_register: Callback for letting GDB read a register.
90 * @gdb_write_register: Callback for letting GDB write a register.
91 * @vmsd: State description for migration.
92 * @gdb_num_core_regs: Number of core registers accessible to GDB.
93 * @gdb_core_xml_file: File name for core registers GDB XML description.
94 *
95 * Represents a CPU family or model.
96 */
97 typedef struct CPUClass {
98 /*< private >*/
99 DeviceClass parent_class;
100 /*< public >*/
101
102 ObjectClass *(*class_by_name)(const char *cpu_model);
103 void (*parse_features)(CPUState *cpu, char *str, Error **errp);
104
105 void (*reset)(CPUState *cpu);
106 int reset_dump_flags;
107 bool (*has_work)(CPUState *cpu);
108 void (*do_interrupt)(CPUState *cpu);
109 CPUUnassignedAccess do_unassigned_access;
110 int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
111 uint8_t *buf, int len, bool is_write);
112 void (*dump_state)(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
113 int flags);
114 void (*dump_statistics)(CPUState *cpu, FILE *f,
115 fprintf_function cpu_fprintf, int flags);
116 int64_t (*get_arch_id)(CPUState *cpu);
117 bool (*get_paging_enabled)(const CPUState *cpu);
118 void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
119 Error **errp);
120 void (*set_pc)(CPUState *cpu, vaddr value);
121 void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb);
122 int (*handle_mmu_fault)(CPUState *cpu, vaddr address, int rw,
123 int mmu_index);
124 hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
125 int (*gdb_read_register)(CPUState *cpu, uint8_t *buf, int reg);
126 int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
127
128 int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu,
129 int cpuid, void *opaque);
130 int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
131 void *opaque);
132 int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu,
133 int cpuid, void *opaque);
134 int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
135 void *opaque);
136
137 const struct VMStateDescription *vmsd;
138 int gdb_num_core_regs;
139 const char *gdb_core_xml_file;
140 } CPUClass;
141
142 #ifdef HOST_WORDS_BIGENDIAN
143 typedef struct icount_decr_u16 {
144 uint16_t high;
145 uint16_t low;
146 } icount_decr_u16;
147 #else
148 typedef struct icount_decr_u16 {
149 uint16_t low;
150 uint16_t high;
151 } icount_decr_u16;
152 #endif
153
154 struct KVMState;
155 struct kvm_run;
156
157 #define TB_JMP_CACHE_BITS 12
158 #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
159
160 /**
161 * CPUState:
162 * @cpu_index: CPU index (informative).
163 * @nr_cores: Number of cores within this CPU package.
164 * @nr_threads: Number of threads within this CPU.
165 * @numa_node: NUMA node this CPU is belonging to.
166 * @host_tid: Host thread ID.
167 * @running: #true if CPU is currently running (usermode).
168 * @created: Indicates whether the CPU thread has been successfully created.
169 * @interrupt_request: Indicates a pending interrupt request.
170 * @halted: Nonzero if the CPU is in suspended state.
171 * @stop: Indicates a pending stop request.
172 * @stopped: Indicates the CPU has been artificially stopped.
173 * @tcg_exit_req: Set to force TCG to stop executing linked TBs for this
174 * CPU and return to its top level loop.
175 * @singlestep_enabled: Flags for single-stepping.
176 * @icount_extra: Instructions until next timer event.
177 * @icount_decr: Number of cycles left, with interrupt flag in high bit.
178 * This allows a single read-compare-cbranch-write sequence to test
179 * for both decrementer underflow and exceptions.
180 * @can_do_io: Nonzero if memory-mapped IO is safe.
181 * @env_ptr: Pointer to subclass-specific CPUArchState field.
182 * @current_tb: Currently executing TB.
183 * @gdb_regs: Additional GDB registers.
184 * @gdb_num_regs: Number of total registers accessible to GDB.
185 * @gdb_num_g_regs: Number of registers in GDB 'g' packets.
186 * @next_cpu: Next CPU sharing TB cache.
187 * @mem_io_pc: Host Program Counter at which the memory was accessed.
188 * @mem_io_vaddr: Target virtual address at which the memory was accessed.
189 * @kvm_fd: vCPU file descriptor for KVM.
190 *
191 * State of one CPU core or thread.
192 */
193 struct CPUState {
194 /*< private >*/
195 DeviceState parent_obj;
196 /*< public >*/
197
198 int nr_cores;
199 int nr_threads;
200 int numa_node;
201
202 struct QemuThread *thread;
203 #ifdef _WIN32
204 HANDLE hThread;
205 #endif
206 int thread_id;
207 uint32_t host_tid;
208 bool running;
209 struct QemuCond *halt_cond;
210 struct qemu_work_item *queued_work_first, *queued_work_last;
211 bool thread_kicked;
212 bool created;
213 bool stop;
214 bool stopped;
215 volatile sig_atomic_t exit_request;
216 volatile sig_atomic_t tcg_exit_req;
217 uint32_t interrupt_request;
218 int singlestep_enabled;
219 int64_t icount_extra;
220 sigjmp_buf jmp_env;
221
222 AddressSpace *as;
223 MemoryListener *tcg_as_listener;
224
225 void *env_ptr; /* CPUArchState */
226 struct TranslationBlock *current_tb;
227 struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE];
228 struct GDBRegisterState *gdb_regs;
229 int gdb_num_regs;
230 int gdb_num_g_regs;
231 QTAILQ_ENTRY(CPUState) node;
232
233 /* In order to avoid passing too many arguments to the MMIO helpers,
234 * we store some rarely used information in the CPU context.
235 */
236 uintptr_t mem_io_pc;
237 vaddr mem_io_vaddr;
238
239 int kvm_fd;
240 bool kvm_vcpu_dirty;
241 struct KVMState *kvm_state;
242 struct kvm_run *kvm_run;
243
244 /* TODO Move common fields from CPUArchState here. */
245 int cpu_index; /* used by alpha TCG */
246 uint32_t halted; /* used by alpha, cris, ppc TCG */
247 union {
248 uint32_t u32;
249 icount_decr_u16 u16;
250 } icount_decr;
251 uint32_t can_do_io;
252 };
253
254 QTAILQ_HEAD(CPUTailQ, CPUState);
255 extern struct CPUTailQ cpus;
256 #define CPU_NEXT(cpu) QTAILQ_NEXT(cpu, node)
257 #define CPU_FOREACH(cpu) QTAILQ_FOREACH(cpu, &cpus, node)
258 #define CPU_FOREACH_SAFE(cpu, next_cpu) \
259 QTAILQ_FOREACH_SAFE(cpu, &cpus, node, next_cpu)
260 #define first_cpu QTAILQ_FIRST(&cpus)
261
262 DECLARE_TLS(CPUState *, current_cpu);
263 #define current_cpu tls_var(current_cpu)
264
265 /**
266 * cpu_paging_enabled:
267 * @cpu: The CPU whose state is to be inspected.
268 *
269 * Returns: %true if paging is enabled, %false otherwise.
270 */
271 bool cpu_paging_enabled(const CPUState *cpu);
272
273 /**
274 * cpu_get_memory_mapping:
275 * @cpu: The CPU whose memory mappings are to be obtained.
276 * @list: Where to write the memory mappings to.
277 * @errp: Pointer for reporting an #Error.
278 */
279 void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
280 Error **errp);
281
282 /**
283 * cpu_write_elf64_note:
284 * @f: pointer to a function that writes memory to a file
285 * @cpu: The CPU whose memory is to be dumped
286 * @cpuid: ID number of the CPU
287 * @opaque: pointer to the CPUState struct
288 */
289 int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
290 int cpuid, void *opaque);
291
292 /**
293 * cpu_write_elf64_qemunote:
294 * @f: pointer to a function that writes memory to a file
295 * @cpu: The CPU whose memory is to be dumped
296 * @cpuid: ID number of the CPU
297 * @opaque: pointer to the CPUState struct
298 */
299 int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
300 void *opaque);
301
302 /**
303 * cpu_write_elf32_note:
304 * @f: pointer to a function that writes memory to a file
305 * @cpu: The CPU whose memory is to be dumped
306 * @cpuid: ID number of the CPU
307 * @opaque: pointer to the CPUState struct
308 */
309 int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
310 int cpuid, void *opaque);
311
312 /**
313 * cpu_write_elf32_qemunote:
314 * @f: pointer to a function that writes memory to a file
315 * @cpu: The CPU whose memory is to be dumped
316 * @cpuid: ID number of the CPU
317 * @opaque: pointer to the CPUState struct
318 */
319 int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
320 void *opaque);
321
322 /**
323 * CPUDumpFlags:
324 * @CPU_DUMP_CODE:
325 * @CPU_DUMP_FPU: dump FPU register state, not just integer
326 * @CPU_DUMP_CCOP: dump info about TCG QEMU's condition code optimization state
327 */
328 enum CPUDumpFlags {
329 CPU_DUMP_CODE = 0x00010000,
330 CPU_DUMP_FPU = 0x00020000,
331 CPU_DUMP_CCOP = 0x00040000,
332 };
333
334 /**
335 * cpu_dump_state:
336 * @cpu: The CPU whose state is to be dumped.
337 * @f: File to dump to.
338 * @cpu_fprintf: Function to dump with.
339 * @flags: Flags what to dump.
340 *
341 * Dumps CPU state.
342 */
343 void cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
344 int flags);
345
346 /**
347 * cpu_dump_statistics:
348 * @cpu: The CPU whose state is to be dumped.
349 * @f: File to dump to.
350 * @cpu_fprintf: Function to dump with.
351 * @flags: Flags what to dump.
352 *
353 * Dumps CPU statistics.
354 */
355 void cpu_dump_statistics(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
356 int flags);
357
358 #ifndef CONFIG_USER_ONLY
359 /**
360 * cpu_get_phys_page_debug:
361 * @cpu: The CPU to obtain the physical page address for.
362 * @addr: The virtual address.
363 *
364 * Obtains the physical page corresponding to a virtual one.
365 * Use it only for debugging because no protection checks are done.
366 *
367 * Returns: Corresponding physical page address or -1 if no page found.
368 */
369 static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
370 {
371 CPUClass *cc = CPU_GET_CLASS(cpu);
372
373 return cc->get_phys_page_debug(cpu, addr);
374 }
375 #endif
376
377 /**
378 * cpu_reset:
379 * @cpu: The CPU whose state is to be reset.
380 */
381 void cpu_reset(CPUState *cpu);
382
383 /**
384 * cpu_class_by_name:
385 * @typename: The CPU base type.
386 * @cpu_model: The model string without any parameters.
387 *
388 * Looks up a CPU #ObjectClass matching name @cpu_model.
389 *
390 * Returns: A #CPUClass or %NULL if not matching class is found.
391 */
392 ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model);
393
394 /**
395 * cpu_generic_init:
396 * @typename: The CPU base type.
397 * @cpu_model: The model string including optional parameters.
398 *
399 * Instantiates a CPU, processes optional parameters and realizes the CPU.
400 *
401 * Returns: A #CPUState or %NULL if an error occurred.
402 */
403 CPUState *cpu_generic_init(const char *typename, const char *cpu_model);
404
405 /**
406 * cpu_has_work:
407 * @cpu: The vCPU to check.
408 *
409 * Checks whether the CPU has work to do.
410 *
411 * Returns: %true if the CPU has work, %false otherwise.
412 */
413 static inline bool cpu_has_work(CPUState *cpu)
414 {
415 CPUClass *cc = CPU_GET_CLASS(cpu);
416
417 g_assert(cc->has_work);
418 return cc->has_work(cpu);
419 }
420
421 /**
422 * qemu_cpu_is_self:
423 * @cpu: The vCPU to check against.
424 *
425 * Checks whether the caller is executing on the vCPU thread.
426 *
427 * Returns: %true if called from @cpu's thread, %false otherwise.
428 */
429 bool qemu_cpu_is_self(CPUState *cpu);
430
431 /**
432 * qemu_cpu_kick:
433 * @cpu: The vCPU to kick.
434 *
435 * Kicks @cpu's thread.
436 */
437 void qemu_cpu_kick(CPUState *cpu);
438
439 /**
440 * cpu_is_stopped:
441 * @cpu: The CPU to check.
442 *
443 * Checks whether the CPU is stopped.
444 *
445 * Returns: %true if run state is not running or if artificially stopped;
446 * %false otherwise.
447 */
448 bool cpu_is_stopped(CPUState *cpu);
449
450 /**
451 * run_on_cpu:
452 * @cpu: The vCPU to run on.
453 * @func: The function to be executed.
454 * @data: Data to pass to the function.
455 *
456 * Schedules the function @func for execution on the vCPU @cpu.
457 */
458 void run_on_cpu(CPUState *cpu, void (*func)(void *data), void *data);
459
460 /**
461 * async_run_on_cpu:
462 * @cpu: The vCPU to run on.
463 * @func: The function to be executed.
464 * @data: Data to pass to the function.
465 *
466 * Schedules the function @func for execution on the vCPU @cpu asynchronously.
467 */
468 void async_run_on_cpu(CPUState *cpu, void (*func)(void *data), void *data);
469
470 /**
471 * qemu_get_cpu:
472 * @index: The CPUState@cpu_index value of the CPU to obtain.
473 *
474 * Gets a CPU matching @index.
475 *
476 * Returns: The CPU or %NULL if there is no matching CPU.
477 */
478 CPUState *qemu_get_cpu(int index);
479
480 /**
481 * cpu_exists:
482 * @id: Guest-exposed CPU ID to lookup.
483 *
484 * Search for CPU with specified ID.
485 *
486 * Returns: %true - CPU is found, %false - CPU isn't found.
487 */
488 bool cpu_exists(int64_t id);
489
490 #ifndef CONFIG_USER_ONLY
491
492 typedef void (*CPUInterruptHandler)(CPUState *, int);
493
494 extern CPUInterruptHandler cpu_interrupt_handler;
495
496 /**
497 * cpu_interrupt:
498 * @cpu: The CPU to set an interrupt on.
499 * @mask: The interupts to set.
500 *
501 * Invokes the interrupt handler.
502 */
503 static inline void cpu_interrupt(CPUState *cpu, int mask)
504 {
505 cpu_interrupt_handler(cpu, mask);
506 }
507
508 #else /* USER_ONLY */
509
510 void cpu_interrupt(CPUState *cpu, int mask);
511
512 #endif /* USER_ONLY */
513
514 #ifndef CONFIG_USER_ONLY
515
516 static inline void cpu_unassigned_access(CPUState *cpu, hwaddr addr,
517 bool is_write, bool is_exec,
518 int opaque, unsigned size)
519 {
520 CPUClass *cc = CPU_GET_CLASS(cpu);
521
522 if (cc->do_unassigned_access) {
523 cc->do_unassigned_access(cpu, addr, is_write, is_exec, opaque, size);
524 }
525 }
526
527 #endif
528
529 /**
530 * cpu_reset_interrupt:
531 * @cpu: The CPU to clear the interrupt on.
532 * @mask: The interrupt mask to clear.
533 *
534 * Resets interrupts on the vCPU @cpu.
535 */
536 void cpu_reset_interrupt(CPUState *cpu, int mask);
537
538 /**
539 * cpu_exit:
540 * @cpu: The CPU to exit.
541 *
542 * Requests the CPU @cpu to exit execution.
543 */
544 void cpu_exit(CPUState *cpu);
545
546 /**
547 * cpu_resume:
548 * @cpu: The CPU to resume.
549 *
550 * Resumes CPU, i.e. puts CPU into runnable state.
551 */
552 void cpu_resume(CPUState *cpu);
553
554 /**
555 * qemu_init_vcpu:
556 * @cpu: The vCPU to initialize.
557 *
558 * Initializes a vCPU.
559 */
560 void qemu_init_vcpu(CPUState *cpu);
561
562 #define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */
563 #define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */
564 #define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */
565
566 /**
567 * cpu_single_step:
568 * @cpu: CPU to the flags for.
569 * @enabled: Flags to enable.
570 *
571 * Enables or disables single-stepping for @cpu.
572 */
573 void cpu_single_step(CPUState *cpu, int enabled);
574
575 #ifdef CONFIG_SOFTMMU
576 extern const struct VMStateDescription vmstate_cpu_common;
577 #else
578 #define vmstate_cpu_common vmstate_dummy
579 #endif
580
581 #define VMSTATE_CPU() { \
582 .name = "parent_obj", \
583 .size = sizeof(CPUState), \
584 .vmsd = &vmstate_cpu_common, \
585 .flags = VMS_STRUCT, \
586 .offset = 0, \
587 }
588
589 #endif