hw/arm/virt-acpi-build: don't save VirtGuestInfo on AcpiBuildState
[qemu.git] / include / qom / cpu.h
1 /*
2 * QEMU CPU model
3 *
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
19 */
20 #ifndef QEMU_CPU_H
21 #define QEMU_CPU_H
22
23 #include "hw/qdev-core.h"
24 #include "disas/bfd.h"
25 #include "exec/hwaddr.h"
26 #include "exec/memattrs.h"
27 #include "qemu/bitmap.h"
28 #include "qemu/queue.h"
29 #include "qemu/thread.h"
30
31 typedef int (*WriteCoreDumpFunction)(const void *buf, size_t size,
32 void *opaque);
33
34 /**
35 * vaddr:
36 * Type wide enough to contain any #target_ulong virtual address.
37 */
38 typedef uint64_t vaddr;
39 #define VADDR_PRId PRId64
40 #define VADDR_PRIu PRIu64
41 #define VADDR_PRIo PRIo64
42 #define VADDR_PRIx PRIx64
43 #define VADDR_PRIX PRIX64
44 #define VADDR_MAX UINT64_MAX
45
46 /**
47 * SECTION:cpu
48 * @section_id: QEMU-cpu
49 * @title: CPU Class
50 * @short_description: Base class for all CPUs
51 */
52
53 #define TYPE_CPU "cpu"
54
55 /* Since this macro is used a lot in hot code paths and in conjunction with
56 * FooCPU *foo_env_get_cpu(), we deviate from usual QOM practice by using
57 * an unchecked cast.
58 */
59 #define CPU(obj) ((CPUState *)(obj))
60
61 #define CPU_CLASS(class) OBJECT_CLASS_CHECK(CPUClass, (class), TYPE_CPU)
62 #define CPU_GET_CLASS(obj) OBJECT_GET_CLASS(CPUClass, (obj), TYPE_CPU)
63
64 typedef enum MMUAccessType {
65 MMU_DATA_LOAD = 0,
66 MMU_DATA_STORE = 1,
67 MMU_INST_FETCH = 2
68 } MMUAccessType;
69
70 typedef struct CPUWatchpoint CPUWatchpoint;
71
72 typedef void (*CPUUnassignedAccess)(CPUState *cpu, hwaddr addr,
73 bool is_write, bool is_exec, int opaque,
74 unsigned size);
75
76 struct TranslationBlock;
77
78 /**
79 * CPUClass:
80 * @class_by_name: Callback to map -cpu command line model name to an
81 * instantiatable CPU type.
82 * @parse_features: Callback to parse command line arguments.
83 * @reset: Callback to reset the #CPUState to its initial state.
84 * @reset_dump_flags: #CPUDumpFlags to use for reset logging.
85 * @has_work: Callback for checking if there is work to do.
86 * @do_interrupt: Callback for interrupt handling.
87 * @do_unassigned_access: Callback for unassigned access handling.
88 * @do_unaligned_access: Callback for unaligned access handling, if
89 * the target defines #ALIGNED_ONLY.
90 * @virtio_is_big_endian: Callback to return %true if a CPU which supports
91 * runtime configurable endianness is currently big-endian. Non-configurable
92 * CPUs can use the default implementation of this method. This method should
93 * not be used by any callers other than the pre-1.0 virtio devices.
94 * @memory_rw_debug: Callback for GDB memory access.
95 * @dump_state: Callback for dumping state.
96 * @dump_statistics: Callback for dumping statistics.
97 * @get_arch_id: Callback for getting architecture-dependent CPU ID.
98 * @get_paging_enabled: Callback for inquiring whether paging is enabled.
99 * @get_memory_mapping: Callback for obtaining the memory mappings.
100 * @set_pc: Callback for setting the Program Counter register.
101 * @synchronize_from_tb: Callback for synchronizing state from a TCG
102 * #TranslationBlock.
103 * @handle_mmu_fault: Callback for handling an MMU fault.
104 * @get_phys_page_debug: Callback for obtaining a physical address.
105 * @get_phys_page_attrs_debug: Callback for obtaining a physical address and the
106 * associated memory transaction attributes to use for the access.
107 * CPUs which use memory transaction attributes should implement this
108 * instead of get_phys_page_debug.
109 * @asidx_from_attrs: Callback to return the CPU AddressSpace to use for
110 * a memory access with the specified memory transaction attributes.
111 * @gdb_read_register: Callback for letting GDB read a register.
112 * @gdb_write_register: Callback for letting GDB write a register.
113 * @debug_check_watchpoint: Callback: return true if the architectural
114 * watchpoint whose address has matched should really fire.
115 * @debug_excp_handler: Callback for handling debug exceptions.
116 * @write_elf64_note: Callback for writing a CPU-specific ELF note to a
117 * 64-bit VM coredump.
118 * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
119 * note to a 32-bit VM coredump.
120 * @write_elf32_note: Callback for writing a CPU-specific ELF note to a
121 * 32-bit VM coredump.
122 * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
123 * note to a 32-bit VM coredump.
124 * @vmsd: State description for migration.
125 * @gdb_num_core_regs: Number of core registers accessible to GDB.
126 * @gdb_core_xml_file: File name for core registers GDB XML description.
127 * @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop
128 * before the insn which triggers a watchpoint rather than after it.
129 * @gdb_arch_name: Optional callback that returns the architecture name known
130 * to GDB. The caller must free the returned string with g_free.
131 * @cpu_exec_enter: Callback for cpu_exec preparation.
132 * @cpu_exec_exit: Callback for cpu_exec cleanup.
133 * @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec.
134 * @disas_set_info: Setup architecture specific components of disassembly info
135 *
136 * Represents a CPU family or model.
137 */
138 typedef struct CPUClass {
139 /*< private >*/
140 DeviceClass parent_class;
141 /*< public >*/
142
143 ObjectClass *(*class_by_name)(const char *cpu_model);
144 void (*parse_features)(const char *typename, char *str, Error **errp);
145
146 void (*reset)(CPUState *cpu);
147 int reset_dump_flags;
148 bool (*has_work)(CPUState *cpu);
149 void (*do_interrupt)(CPUState *cpu);
150 CPUUnassignedAccess do_unassigned_access;
151 void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
152 MMUAccessType access_type,
153 int mmu_idx, uintptr_t retaddr);
154 bool (*virtio_is_big_endian)(CPUState *cpu);
155 int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
156 uint8_t *buf, int len, bool is_write);
157 void (*dump_state)(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
158 int flags);
159 void (*dump_statistics)(CPUState *cpu, FILE *f,
160 fprintf_function cpu_fprintf, int flags);
161 int64_t (*get_arch_id)(CPUState *cpu);
162 bool (*get_paging_enabled)(const CPUState *cpu);
163 void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
164 Error **errp);
165 void (*set_pc)(CPUState *cpu, vaddr value);
166 void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb);
167 int (*handle_mmu_fault)(CPUState *cpu, vaddr address, int rw,
168 int mmu_index);
169 hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
170 hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr,
171 MemTxAttrs *attrs);
172 int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs);
173 int (*gdb_read_register)(CPUState *cpu, uint8_t *buf, int reg);
174 int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
175 bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp);
176 void (*debug_excp_handler)(CPUState *cpu);
177
178 int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu,
179 int cpuid, void *opaque);
180 int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
181 void *opaque);
182 int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu,
183 int cpuid, void *opaque);
184 int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
185 void *opaque);
186
187 const struct VMStateDescription *vmsd;
188 int gdb_num_core_regs;
189 const char *gdb_core_xml_file;
190 gchar * (*gdb_arch_name)(CPUState *cpu);
191 bool gdb_stop_before_watchpoint;
192
193 void (*cpu_exec_enter)(CPUState *cpu);
194 void (*cpu_exec_exit)(CPUState *cpu);
195 bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
196
197 void (*disas_set_info)(CPUState *cpu, disassemble_info *info);
198 } CPUClass;
199
200 #ifdef HOST_WORDS_BIGENDIAN
201 typedef struct icount_decr_u16 {
202 uint16_t high;
203 uint16_t low;
204 } icount_decr_u16;
205 #else
206 typedef struct icount_decr_u16 {
207 uint16_t low;
208 uint16_t high;
209 } icount_decr_u16;
210 #endif
211
212 typedef struct CPUBreakpoint {
213 vaddr pc;
214 int flags; /* BP_* */
215 QTAILQ_ENTRY(CPUBreakpoint) entry;
216 } CPUBreakpoint;
217
218 struct CPUWatchpoint {
219 vaddr vaddr;
220 vaddr len;
221 vaddr hitaddr;
222 MemTxAttrs hitattrs;
223 int flags; /* BP_* */
224 QTAILQ_ENTRY(CPUWatchpoint) entry;
225 };
226
227 struct KVMState;
228 struct kvm_run;
229
230 #define TB_JMP_CACHE_BITS 12
231 #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
232
233 /* work queue */
234
235 /* The union type allows passing of 64 bit target pointers on 32 bit
236 * hosts in a single parameter
237 */
238 typedef union {
239 int host_int;
240 unsigned long host_ulong;
241 void *host_ptr;
242 vaddr target_ptr;
243 } run_on_cpu_data;
244
245 #define RUN_ON_CPU_HOST_PTR(p) ((run_on_cpu_data){.host_ptr = (p)})
246 #define RUN_ON_CPU_HOST_INT(i) ((run_on_cpu_data){.host_int = (i)})
247 #define RUN_ON_CPU_HOST_ULONG(ul) ((run_on_cpu_data){.host_ulong = (ul)})
248 #define RUN_ON_CPU_TARGET_PTR(v) ((run_on_cpu_data){.target_ptr = (v)})
249 #define RUN_ON_CPU_NULL RUN_ON_CPU_HOST_PTR(NULL)
250
251 typedef void (*run_on_cpu_func)(CPUState *cpu, run_on_cpu_data data);
252
253 struct qemu_work_item;
254
255 /**
256 * CPUState:
257 * @cpu_index: CPU index (informative).
258 * @nr_cores: Number of cores within this CPU package.
259 * @nr_threads: Number of threads within this CPU.
260 * @numa_node: NUMA node this CPU is belonging to.
261 * @host_tid: Host thread ID.
262 * @running: #true if CPU is currently running (lockless).
263 * @has_waiter: #true if a CPU is currently waiting for the cpu_exec_end;
264 * valid under cpu_list_lock.
265 * @created: Indicates whether the CPU thread has been successfully created.
266 * @interrupt_request: Indicates a pending interrupt request.
267 * @halted: Nonzero if the CPU is in suspended state.
268 * @stop: Indicates a pending stop request.
269 * @stopped: Indicates the CPU has been artificially stopped.
270 * @unplug: Indicates a pending CPU unplug request.
271 * @crash_occurred: Indicates the OS reported a crash (panic) for this CPU
272 * @tcg_exit_req: Set to force TCG to stop executing linked TBs for this
273 * CPU and return to its top level loop.
274 * @singlestep_enabled: Flags for single-stepping.
275 * @icount_extra: Instructions until next timer event.
276 * @icount_decr: Number of cycles left, with interrupt flag in high bit.
277 * This allows a single read-compare-cbranch-write sequence to test
278 * for both decrementer underflow and exceptions.
279 * @can_do_io: Nonzero if memory-mapped IO is safe. Deterministic execution
280 * requires that IO only be performed on the last instruction of a TB
281 * so that interrupts take effect immediately.
282 * @cpu_ases: Pointer to array of CPUAddressSpaces (which define the
283 * AddressSpaces this CPU has)
284 * @num_ases: number of CPUAddressSpaces in @cpu_ases
285 * @as: Pointer to the first AddressSpace, for the convenience of targets which
286 * only have a single AddressSpace
287 * @env_ptr: Pointer to subclass-specific CPUArchState field.
288 * @gdb_regs: Additional GDB registers.
289 * @gdb_num_regs: Number of total registers accessible to GDB.
290 * @gdb_num_g_regs: Number of registers in GDB 'g' packets.
291 * @next_cpu: Next CPU sharing TB cache.
292 * @opaque: User data.
293 * @mem_io_pc: Host Program Counter at which the memory was accessed.
294 * @mem_io_vaddr: Target virtual address at which the memory was accessed.
295 * @kvm_fd: vCPU file descriptor for KVM.
296 * @work_mutex: Lock to prevent multiple access to queued_work_*.
297 * @queued_work_first: First asynchronous work pending.
298 * @trace_dstate: Dynamic tracing state of events for this vCPU (bitmask).
299 *
300 * State of one CPU core or thread.
301 */
302 struct CPUState {
303 /*< private >*/
304 DeviceState parent_obj;
305 /*< public >*/
306
307 int nr_cores;
308 int nr_threads;
309 int numa_node;
310
311 struct QemuThread *thread;
312 #ifdef _WIN32
313 HANDLE hThread;
314 #endif
315 int thread_id;
316 uint32_t host_tid;
317 bool running, has_waiter;
318 struct QemuCond *halt_cond;
319 bool thread_kicked;
320 bool created;
321 bool stop;
322 bool stopped;
323 bool unplug;
324 bool crash_occurred;
325 bool exit_request;
326 uint32_t interrupt_request;
327 int singlestep_enabled;
328 int64_t icount_extra;
329 sigjmp_buf jmp_env;
330
331 QemuMutex work_mutex;
332 struct qemu_work_item *queued_work_first, *queued_work_last;
333
334 CPUAddressSpace *cpu_ases;
335 int num_ases;
336 AddressSpace *as;
337 MemoryRegion *memory;
338
339 void *env_ptr; /* CPUArchState */
340
341 /* Writes protected by tb_lock, reads not thread-safe */
342 struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE];
343
344 struct GDBRegisterState *gdb_regs;
345 int gdb_num_regs;
346 int gdb_num_g_regs;
347 QTAILQ_ENTRY(CPUState) node;
348
349 /* ice debug support */
350 QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints;
351
352 QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints;
353 CPUWatchpoint *watchpoint_hit;
354
355 void *opaque;
356
357 /* In order to avoid passing too many arguments to the MMIO helpers,
358 * we store some rarely used information in the CPU context.
359 */
360 uintptr_t mem_io_pc;
361 vaddr mem_io_vaddr;
362
363 int kvm_fd;
364 bool kvm_vcpu_dirty;
365 struct KVMState *kvm_state;
366 struct kvm_run *kvm_run;
367
368 /*
369 * Used for events with 'vcpu' and *without* the 'disabled' properties.
370 * Dynamically allocated based on bitmap requried to hold up to
371 * trace_get_vcpu_event_count() entries.
372 */
373 unsigned long *trace_dstate;
374
375 /* TODO Move common fields from CPUArchState here. */
376 int cpu_index; /* used by alpha TCG */
377 uint32_t halted; /* used by alpha, cris, ppc TCG */
378 union {
379 uint32_t u32;
380 icount_decr_u16 u16;
381 } icount_decr;
382 uint32_t can_do_io;
383 int32_t exception_index; /* used by m68k TCG */
384
385 /* Used to keep track of an outstanding cpu throttle thread for migration
386 * autoconverge
387 */
388 bool throttle_thread_scheduled;
389
390 /* Note that this is accessed at the start of every TB via a negative
391 offset from AREG0. Leave this field at the end so as to make the
392 (absolute value) offset as small as possible. This reduces code
393 size, especially for hosts without large memory offsets. */
394 uint32_t tcg_exit_req;
395 };
396
397 QTAILQ_HEAD(CPUTailQ, CPUState);
398 extern struct CPUTailQ cpus;
399 #define CPU_NEXT(cpu) QTAILQ_NEXT(cpu, node)
400 #define CPU_FOREACH(cpu) QTAILQ_FOREACH(cpu, &cpus, node)
401 #define CPU_FOREACH_SAFE(cpu, next_cpu) \
402 QTAILQ_FOREACH_SAFE(cpu, &cpus, node, next_cpu)
403 #define CPU_FOREACH_REVERSE(cpu) \
404 QTAILQ_FOREACH_REVERSE(cpu, &cpus, CPUTailQ, node)
405 #define first_cpu QTAILQ_FIRST(&cpus)
406
407 extern __thread CPUState *current_cpu;
408
409 /**
410 * cpu_paging_enabled:
411 * @cpu: The CPU whose state is to be inspected.
412 *
413 * Returns: %true if paging is enabled, %false otherwise.
414 */
415 bool cpu_paging_enabled(const CPUState *cpu);
416
417 /**
418 * cpu_get_memory_mapping:
419 * @cpu: The CPU whose memory mappings are to be obtained.
420 * @list: Where to write the memory mappings to.
421 * @errp: Pointer for reporting an #Error.
422 */
423 void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
424 Error **errp);
425
426 /**
427 * cpu_write_elf64_note:
428 * @f: pointer to a function that writes memory to a file
429 * @cpu: The CPU whose memory is to be dumped
430 * @cpuid: ID number of the CPU
431 * @opaque: pointer to the CPUState struct
432 */
433 int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
434 int cpuid, void *opaque);
435
436 /**
437 * cpu_write_elf64_qemunote:
438 * @f: pointer to a function that writes memory to a file
439 * @cpu: The CPU whose memory is to be dumped
440 * @cpuid: ID number of the CPU
441 * @opaque: pointer to the CPUState struct
442 */
443 int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
444 void *opaque);
445
446 /**
447 * cpu_write_elf32_note:
448 * @f: pointer to a function that writes memory to a file
449 * @cpu: The CPU whose memory is to be dumped
450 * @cpuid: ID number of the CPU
451 * @opaque: pointer to the CPUState struct
452 */
453 int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
454 int cpuid, void *opaque);
455
456 /**
457 * cpu_write_elf32_qemunote:
458 * @f: pointer to a function that writes memory to a file
459 * @cpu: The CPU whose memory is to be dumped
460 * @cpuid: ID number of the CPU
461 * @opaque: pointer to the CPUState struct
462 */
463 int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
464 void *opaque);
465
466 /**
467 * CPUDumpFlags:
468 * @CPU_DUMP_CODE:
469 * @CPU_DUMP_FPU: dump FPU register state, not just integer
470 * @CPU_DUMP_CCOP: dump info about TCG QEMU's condition code optimization state
471 */
472 enum CPUDumpFlags {
473 CPU_DUMP_CODE = 0x00010000,
474 CPU_DUMP_FPU = 0x00020000,
475 CPU_DUMP_CCOP = 0x00040000,
476 };
477
478 /**
479 * cpu_dump_state:
480 * @cpu: The CPU whose state is to be dumped.
481 * @f: File to dump to.
482 * @cpu_fprintf: Function to dump with.
483 * @flags: Flags what to dump.
484 *
485 * Dumps CPU state.
486 */
487 void cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
488 int flags);
489
490 /**
491 * cpu_dump_statistics:
492 * @cpu: The CPU whose state is to be dumped.
493 * @f: File to dump to.
494 * @cpu_fprintf: Function to dump with.
495 * @flags: Flags what to dump.
496 *
497 * Dumps CPU statistics.
498 */
499 void cpu_dump_statistics(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
500 int flags);
501
502 #ifndef CONFIG_USER_ONLY
503 /**
504 * cpu_get_phys_page_attrs_debug:
505 * @cpu: The CPU to obtain the physical page address for.
506 * @addr: The virtual address.
507 * @attrs: Updated on return with the memory transaction attributes to use
508 * for this access.
509 *
510 * Obtains the physical page corresponding to a virtual one, together
511 * with the corresponding memory transaction attributes to use for the access.
512 * Use it only for debugging because no protection checks are done.
513 *
514 * Returns: Corresponding physical page address or -1 if no page found.
515 */
516 static inline hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
517 MemTxAttrs *attrs)
518 {
519 CPUClass *cc = CPU_GET_CLASS(cpu);
520
521 if (cc->get_phys_page_attrs_debug) {
522 return cc->get_phys_page_attrs_debug(cpu, addr, attrs);
523 }
524 /* Fallback for CPUs which don't implement the _attrs_ hook */
525 *attrs = MEMTXATTRS_UNSPECIFIED;
526 return cc->get_phys_page_debug(cpu, addr);
527 }
528
529 /**
530 * cpu_get_phys_page_debug:
531 * @cpu: The CPU to obtain the physical page address for.
532 * @addr: The virtual address.
533 *
534 * Obtains the physical page corresponding to a virtual one.
535 * Use it only for debugging because no protection checks are done.
536 *
537 * Returns: Corresponding physical page address or -1 if no page found.
538 */
539 static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
540 {
541 MemTxAttrs attrs = {};
542
543 return cpu_get_phys_page_attrs_debug(cpu, addr, &attrs);
544 }
545
546 /** cpu_asidx_from_attrs:
547 * @cpu: CPU
548 * @attrs: memory transaction attributes
549 *
550 * Returns the address space index specifying the CPU AddressSpace
551 * to use for a memory access with the given transaction attributes.
552 */
553 static inline int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs)
554 {
555 CPUClass *cc = CPU_GET_CLASS(cpu);
556
557 if (cc->asidx_from_attrs) {
558 return cc->asidx_from_attrs(cpu, attrs);
559 }
560 return 0;
561 }
562 #endif
563
564 /**
565 * cpu_list_add:
566 * @cpu: The CPU to be added to the list of CPUs.
567 */
568 void cpu_list_add(CPUState *cpu);
569
570 /**
571 * cpu_list_remove:
572 * @cpu: The CPU to be removed from the list of CPUs.
573 */
574 void cpu_list_remove(CPUState *cpu);
575
576 /**
577 * cpu_reset:
578 * @cpu: The CPU whose state is to be reset.
579 */
580 void cpu_reset(CPUState *cpu);
581
582 /**
583 * cpu_class_by_name:
584 * @typename: The CPU base type.
585 * @cpu_model: The model string without any parameters.
586 *
587 * Looks up a CPU #ObjectClass matching name @cpu_model.
588 *
589 * Returns: A #CPUClass or %NULL if not matching class is found.
590 */
591 ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model);
592
593 /**
594 * cpu_generic_init:
595 * @typename: The CPU base type.
596 * @cpu_model: The model string including optional parameters.
597 *
598 * Instantiates a CPU, processes optional parameters and realizes the CPU.
599 *
600 * Returns: A #CPUState or %NULL if an error occurred.
601 */
602 CPUState *cpu_generic_init(const char *typename, const char *cpu_model);
603
604 /**
605 * cpu_has_work:
606 * @cpu: The vCPU to check.
607 *
608 * Checks whether the CPU has work to do.
609 *
610 * Returns: %true if the CPU has work, %false otherwise.
611 */
612 static inline bool cpu_has_work(CPUState *cpu)
613 {
614 CPUClass *cc = CPU_GET_CLASS(cpu);
615
616 g_assert(cc->has_work);
617 return cc->has_work(cpu);
618 }
619
620 /**
621 * qemu_cpu_is_self:
622 * @cpu: The vCPU to check against.
623 *
624 * Checks whether the caller is executing on the vCPU thread.
625 *
626 * Returns: %true if called from @cpu's thread, %false otherwise.
627 */
628 bool qemu_cpu_is_self(CPUState *cpu);
629
630 /**
631 * qemu_cpu_kick:
632 * @cpu: The vCPU to kick.
633 *
634 * Kicks @cpu's thread.
635 */
636 void qemu_cpu_kick(CPUState *cpu);
637
638 /**
639 * cpu_is_stopped:
640 * @cpu: The CPU to check.
641 *
642 * Checks whether the CPU is stopped.
643 *
644 * Returns: %true if run state is not running or if artificially stopped;
645 * %false otherwise.
646 */
647 bool cpu_is_stopped(CPUState *cpu);
648
649 /**
650 * do_run_on_cpu:
651 * @cpu: The vCPU to run on.
652 * @func: The function to be executed.
653 * @data: Data to pass to the function.
654 * @mutex: Mutex to release while waiting for @func to run.
655 *
656 * Used internally in the implementation of run_on_cpu.
657 */
658 void do_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data,
659 QemuMutex *mutex);
660
661 /**
662 * run_on_cpu:
663 * @cpu: The vCPU to run on.
664 * @func: The function to be executed.
665 * @data: Data to pass to the function.
666 *
667 * Schedules the function @func for execution on the vCPU @cpu.
668 */
669 void run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data);
670
671 /**
672 * async_run_on_cpu:
673 * @cpu: The vCPU to run on.
674 * @func: The function to be executed.
675 * @data: Data to pass to the function.
676 *
677 * Schedules the function @func for execution on the vCPU @cpu asynchronously.
678 */
679 void async_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data);
680
681 /**
682 * async_safe_run_on_cpu:
683 * @cpu: The vCPU to run on.
684 * @func: The function to be executed.
685 * @data: Data to pass to the function.
686 *
687 * Schedules the function @func for execution on the vCPU @cpu asynchronously,
688 * while all other vCPUs are sleeping.
689 *
690 * Unlike run_on_cpu and async_run_on_cpu, the function is run outside the
691 * BQL.
692 */
693 void async_safe_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data);
694
695 /**
696 * qemu_get_cpu:
697 * @index: The CPUState@cpu_index value of the CPU to obtain.
698 *
699 * Gets a CPU matching @index.
700 *
701 * Returns: The CPU or %NULL if there is no matching CPU.
702 */
703 CPUState *qemu_get_cpu(int index);
704
705 /**
706 * cpu_exists:
707 * @id: Guest-exposed CPU ID to lookup.
708 *
709 * Search for CPU with specified ID.
710 *
711 * Returns: %true - CPU is found, %false - CPU isn't found.
712 */
713 bool cpu_exists(int64_t id);
714
715 /**
716 * cpu_throttle_set:
717 * @new_throttle_pct: Percent of sleep time. Valid range is 1 to 99.
718 *
719 * Throttles all vcpus by forcing them to sleep for the given percentage of
720 * time. A throttle_percentage of 25 corresponds to a 75% duty cycle roughly.
721 * (example: 10ms sleep for every 30ms awake).
722 *
723 * cpu_throttle_set can be called as needed to adjust new_throttle_pct.
724 * Once the throttling starts, it will remain in effect until cpu_throttle_stop
725 * is called.
726 */
727 void cpu_throttle_set(int new_throttle_pct);
728
729 /**
730 * cpu_throttle_stop:
731 *
732 * Stops the vcpu throttling started by cpu_throttle_set.
733 */
734 void cpu_throttle_stop(void);
735
736 /**
737 * cpu_throttle_active:
738 *
739 * Returns: %true if the vcpus are currently being throttled, %false otherwise.
740 */
741 bool cpu_throttle_active(void);
742
743 /**
744 * cpu_throttle_get_percentage:
745 *
746 * Returns the vcpu throttle percentage. See cpu_throttle_set for details.
747 *
748 * Returns: The throttle percentage in range 1 to 99.
749 */
750 int cpu_throttle_get_percentage(void);
751
752 #ifndef CONFIG_USER_ONLY
753
754 typedef void (*CPUInterruptHandler)(CPUState *, int);
755
756 extern CPUInterruptHandler cpu_interrupt_handler;
757
758 /**
759 * cpu_interrupt:
760 * @cpu: The CPU to set an interrupt on.
761 * @mask: The interupts to set.
762 *
763 * Invokes the interrupt handler.
764 */
765 static inline void cpu_interrupt(CPUState *cpu, int mask)
766 {
767 cpu_interrupt_handler(cpu, mask);
768 }
769
770 #else /* USER_ONLY */
771
772 void cpu_interrupt(CPUState *cpu, int mask);
773
774 #endif /* USER_ONLY */
775
776 #ifdef CONFIG_SOFTMMU
777 static inline void cpu_unassigned_access(CPUState *cpu, hwaddr addr,
778 bool is_write, bool is_exec,
779 int opaque, unsigned size)
780 {
781 CPUClass *cc = CPU_GET_CLASS(cpu);
782
783 if (cc->do_unassigned_access) {
784 cc->do_unassigned_access(cpu, addr, is_write, is_exec, opaque, size);
785 }
786 }
787
788 static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr,
789 MMUAccessType access_type,
790 int mmu_idx, uintptr_t retaddr)
791 {
792 CPUClass *cc = CPU_GET_CLASS(cpu);
793
794 cc->do_unaligned_access(cpu, addr, access_type, mmu_idx, retaddr);
795 }
796 #endif
797
798 /**
799 * cpu_set_pc:
800 * @cpu: The CPU to set the program counter for.
801 * @addr: Program counter value.
802 *
803 * Sets the program counter for a CPU.
804 */
805 static inline void cpu_set_pc(CPUState *cpu, vaddr addr)
806 {
807 CPUClass *cc = CPU_GET_CLASS(cpu);
808
809 cc->set_pc(cpu, addr);
810 }
811
812 /**
813 * cpu_reset_interrupt:
814 * @cpu: The CPU to clear the interrupt on.
815 * @mask: The interrupt mask to clear.
816 *
817 * Resets interrupts on the vCPU @cpu.
818 */
819 void cpu_reset_interrupt(CPUState *cpu, int mask);
820
821 /**
822 * cpu_exit:
823 * @cpu: The CPU to exit.
824 *
825 * Requests the CPU @cpu to exit execution.
826 */
827 void cpu_exit(CPUState *cpu);
828
829 /**
830 * cpu_resume:
831 * @cpu: The CPU to resume.
832 *
833 * Resumes CPU, i.e. puts CPU into runnable state.
834 */
835 void cpu_resume(CPUState *cpu);
836
837 /**
838 * cpu_remove:
839 * @cpu: The CPU to remove.
840 *
841 * Requests the CPU to be removed.
842 */
843 void cpu_remove(CPUState *cpu);
844
845 /**
846 * cpu_remove_sync:
847 * @cpu: The CPU to remove.
848 *
849 * Requests the CPU to be removed and waits till it is removed.
850 */
851 void cpu_remove_sync(CPUState *cpu);
852
853 /**
854 * process_queued_cpu_work() - process all items on CPU work queue
855 * @cpu: The CPU which work queue to process.
856 */
857 void process_queued_cpu_work(CPUState *cpu);
858
859 /**
860 * cpu_exec_start:
861 * @cpu: The CPU for the current thread.
862 *
863 * Record that a CPU has started execution and can be interrupted with
864 * cpu_exit.
865 */
866 void cpu_exec_start(CPUState *cpu);
867
868 /**
869 * cpu_exec_end:
870 * @cpu: The CPU for the current thread.
871 *
872 * Record that a CPU has stopped execution and exclusive sections
873 * can be executed without interrupting it.
874 */
875 void cpu_exec_end(CPUState *cpu);
876
877 /**
878 * start_exclusive:
879 *
880 * Wait for a concurrent exclusive section to end, and then start
881 * a section of work that is run while other CPUs are not running
882 * between cpu_exec_start and cpu_exec_end. CPUs that are running
883 * cpu_exec are exited immediately. CPUs that call cpu_exec_start
884 * during the exclusive section go to sleep until this CPU calls
885 * end_exclusive.
886 */
887 void start_exclusive(void);
888
889 /**
890 * end_exclusive:
891 *
892 * Concludes an exclusive execution section started by start_exclusive.
893 */
894 void end_exclusive(void);
895
896 /**
897 * qemu_init_vcpu:
898 * @cpu: The vCPU to initialize.
899 *
900 * Initializes a vCPU.
901 */
902 void qemu_init_vcpu(CPUState *cpu);
903
904 #define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */
905 #define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */
906 #define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */
907
908 /**
909 * cpu_single_step:
910 * @cpu: CPU to the flags for.
911 * @enabled: Flags to enable.
912 *
913 * Enables or disables single-stepping for @cpu.
914 */
915 void cpu_single_step(CPUState *cpu, int enabled);
916
917 /* Breakpoint/watchpoint flags */
918 #define BP_MEM_READ 0x01
919 #define BP_MEM_WRITE 0x02
920 #define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE)
921 #define BP_STOP_BEFORE_ACCESS 0x04
922 /* 0x08 currently unused */
923 #define BP_GDB 0x10
924 #define BP_CPU 0x20
925 #define BP_ANY (BP_GDB | BP_CPU)
926 #define BP_WATCHPOINT_HIT_READ 0x40
927 #define BP_WATCHPOINT_HIT_WRITE 0x80
928 #define BP_WATCHPOINT_HIT (BP_WATCHPOINT_HIT_READ | BP_WATCHPOINT_HIT_WRITE)
929
930 int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
931 CPUBreakpoint **breakpoint);
932 int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags);
933 void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint);
934 void cpu_breakpoint_remove_all(CPUState *cpu, int mask);
935
936 /* Return true if PC matches an installed breakpoint. */
937 static inline bool cpu_breakpoint_test(CPUState *cpu, vaddr pc, int mask)
938 {
939 CPUBreakpoint *bp;
940
941 if (unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) {
942 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
943 if (bp->pc == pc && (bp->flags & mask)) {
944 return true;
945 }
946 }
947 }
948 return false;
949 }
950
951 int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
952 int flags, CPUWatchpoint **watchpoint);
953 int cpu_watchpoint_remove(CPUState *cpu, vaddr addr,
954 vaddr len, int flags);
955 void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint);
956 void cpu_watchpoint_remove_all(CPUState *cpu, int mask);
957
958 /**
959 * cpu_get_address_space:
960 * @cpu: CPU to get address space from
961 * @asidx: index identifying which address space to get
962 *
963 * Return the requested address space of this CPU. @asidx
964 * specifies which address space to read.
965 */
966 AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx);
967
968 void QEMU_NORETURN cpu_abort(CPUState *cpu, const char *fmt, ...)
969 GCC_FMT_ATTR(2, 3);
970 void cpu_exec_initfn(CPUState *cpu);
971 void cpu_exec_realizefn(CPUState *cpu, Error **errp);
972 void cpu_exec_unrealizefn(CPUState *cpu);
973
974 #ifdef CONFIG_SOFTMMU
975 extern const struct VMStateDescription vmstate_cpu_common;
976 #else
977 #define vmstate_cpu_common vmstate_dummy
978 #endif
979
980 #define VMSTATE_CPU() { \
981 .name = "parent_obj", \
982 .size = sizeof(CPUState), \
983 .vmsd = &vmstate_cpu_common, \
984 .flags = VMS_STRUCT, \
985 .offset = 0, \
986 }
987
988 #define UNASSIGNED_CPU_INDEX -1
989
990 #endif