numa: add -numa node,memdev= option
[qemu.git] / include / qom / cpu.h
1 /*
2 * QEMU CPU model
3 *
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
19 */
20 #ifndef QEMU_CPU_H
21 #define QEMU_CPU_H
22
23 #include <signal.h>
24 #include <setjmp.h>
25 #include "hw/qdev-core.h"
26 #include "exec/hwaddr.h"
27 #include "qemu/queue.h"
28 #include "qemu/thread.h"
29 #include "qemu/tls.h"
30 #include "qemu/typedefs.h"
31
32 typedef int (*WriteCoreDumpFunction)(const void *buf, size_t size,
33 void *opaque);
34
35 /**
36 * vaddr:
37 * Type wide enough to contain any #target_ulong virtual address.
38 */
39 typedef uint64_t vaddr;
40 #define VADDR_PRId PRId64
41 #define VADDR_PRIu PRIu64
42 #define VADDR_PRIo PRIo64
43 #define VADDR_PRIx PRIx64
44 #define VADDR_PRIX PRIX64
45 #define VADDR_MAX UINT64_MAX
46
47 /**
48 * SECTION:cpu
49 * @section_id: QEMU-cpu
50 * @title: CPU Class
51 * @short_description: Base class for all CPUs
52 */
53
54 #define TYPE_CPU "cpu"
55
56 /* Since this macro is used a lot in hot code paths and in conjunction with
57 * FooCPU *foo_env_get_cpu(), we deviate from usual QOM practice by using
58 * an unchecked cast.
59 */
60 #define CPU(obj) ((CPUState *)(obj))
61
62 #define CPU_CLASS(class) OBJECT_CLASS_CHECK(CPUClass, (class), TYPE_CPU)
63 #define CPU_GET_CLASS(obj) OBJECT_GET_CLASS(CPUClass, (obj), TYPE_CPU)
64
65 typedef struct CPUState CPUState;
66
67 typedef void (*CPUUnassignedAccess)(CPUState *cpu, hwaddr addr,
68 bool is_write, bool is_exec, int opaque,
69 unsigned size);
70
71 struct TranslationBlock;
72
73 /**
74 * CPUClass:
75 * @class_by_name: Callback to map -cpu command line model name to an
76 * instantiatable CPU type.
77 * @parse_features: Callback to parse command line arguments.
78 * @reset: Callback to reset the #CPUState to its initial state.
79 * @reset_dump_flags: #CPUDumpFlags to use for reset logging.
80 * @has_work: Callback for checking if there is work to do.
81 * @do_interrupt: Callback for interrupt handling.
82 * @do_unassigned_access: Callback for unassigned access handling.
83 * @do_unaligned_access: Callback for unaligned access handling, if
84 * the target defines #ALIGNED_ONLY.
85 * @memory_rw_debug: Callback for GDB memory access.
86 * @dump_state: Callback for dumping state.
87 * @dump_statistics: Callback for dumping statistics.
88 * @get_arch_id: Callback for getting architecture-dependent CPU ID.
89 * @get_paging_enabled: Callback for inquiring whether paging is enabled.
90 * @get_memory_mapping: Callback for obtaining the memory mappings.
91 * @set_pc: Callback for setting the Program Counter register.
92 * @synchronize_from_tb: Callback for synchronizing state from a TCG
93 * #TranslationBlock.
94 * @handle_mmu_fault: Callback for handling an MMU fault.
95 * @get_phys_page_debug: Callback for obtaining a physical address.
96 * @gdb_read_register: Callback for letting GDB read a register.
97 * @gdb_write_register: Callback for letting GDB write a register.
98 * @vmsd: State description for migration.
99 * @gdb_num_core_regs: Number of core registers accessible to GDB.
100 * @gdb_core_xml_file: File name for core registers GDB XML description.
101 *
102 * Represents a CPU family or model.
103 */
104 typedef struct CPUClass {
105 /*< private >*/
106 DeviceClass parent_class;
107 /*< public >*/
108
109 ObjectClass *(*class_by_name)(const char *cpu_model);
110 void (*parse_features)(CPUState *cpu, char *str, Error **errp);
111
112 void (*reset)(CPUState *cpu);
113 int reset_dump_flags;
114 bool (*has_work)(CPUState *cpu);
115 void (*do_interrupt)(CPUState *cpu);
116 CPUUnassignedAccess do_unassigned_access;
117 void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
118 int is_write, int is_user, uintptr_t retaddr);
119 int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
120 uint8_t *buf, int len, bool is_write);
121 void (*dump_state)(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
122 int flags);
123 void (*dump_statistics)(CPUState *cpu, FILE *f,
124 fprintf_function cpu_fprintf, int flags);
125 int64_t (*get_arch_id)(CPUState *cpu);
126 bool (*get_paging_enabled)(const CPUState *cpu);
127 void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
128 Error **errp);
129 void (*set_pc)(CPUState *cpu, vaddr value);
130 void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb);
131 int (*handle_mmu_fault)(CPUState *cpu, vaddr address, int rw,
132 int mmu_index);
133 hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
134 int (*gdb_read_register)(CPUState *cpu, uint8_t *buf, int reg);
135 int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
136
137 int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu,
138 int cpuid, void *opaque);
139 int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
140 void *opaque);
141 int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu,
142 int cpuid, void *opaque);
143 int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
144 void *opaque);
145
146 const struct VMStateDescription *vmsd;
147 int gdb_num_core_regs;
148 const char *gdb_core_xml_file;
149 } CPUClass;
150
151 #ifdef HOST_WORDS_BIGENDIAN
152 typedef struct icount_decr_u16 {
153 uint16_t high;
154 uint16_t low;
155 } icount_decr_u16;
156 #else
157 typedef struct icount_decr_u16 {
158 uint16_t low;
159 uint16_t high;
160 } icount_decr_u16;
161 #endif
162
163 typedef struct CPUBreakpoint {
164 vaddr pc;
165 int flags; /* BP_* */
166 QTAILQ_ENTRY(CPUBreakpoint) entry;
167 } CPUBreakpoint;
168
169 typedef struct CPUWatchpoint {
170 vaddr vaddr;
171 vaddr len_mask;
172 int flags; /* BP_* */
173 QTAILQ_ENTRY(CPUWatchpoint) entry;
174 } CPUWatchpoint;
175
176 struct KVMState;
177 struct kvm_run;
178
179 #define TB_JMP_CACHE_BITS 12
180 #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
181
182 /**
183 * CPUState:
184 * @cpu_index: CPU index (informative).
185 * @nr_cores: Number of cores within this CPU package.
186 * @nr_threads: Number of threads within this CPU.
187 * @numa_node: NUMA node this CPU is belonging to.
188 * @host_tid: Host thread ID.
189 * @running: #true if CPU is currently running (usermode).
190 * @created: Indicates whether the CPU thread has been successfully created.
191 * @interrupt_request: Indicates a pending interrupt request.
192 * @halted: Nonzero if the CPU is in suspended state.
193 * @stop: Indicates a pending stop request.
194 * @stopped: Indicates the CPU has been artificially stopped.
195 * @tcg_exit_req: Set to force TCG to stop executing linked TBs for this
196 * CPU and return to its top level loop.
197 * @singlestep_enabled: Flags for single-stepping.
198 * @icount_extra: Instructions until next timer event.
199 * @icount_decr: Number of cycles left, with interrupt flag in high bit.
200 * This allows a single read-compare-cbranch-write sequence to test
201 * for both decrementer underflow and exceptions.
202 * @can_do_io: Nonzero if memory-mapped IO is safe.
203 * @env_ptr: Pointer to subclass-specific CPUArchState field.
204 * @current_tb: Currently executing TB.
205 * @gdb_regs: Additional GDB registers.
206 * @gdb_num_regs: Number of total registers accessible to GDB.
207 * @gdb_num_g_regs: Number of registers in GDB 'g' packets.
208 * @next_cpu: Next CPU sharing TB cache.
209 * @opaque: User data.
210 * @mem_io_pc: Host Program Counter at which the memory was accessed.
211 * @mem_io_vaddr: Target virtual address at which the memory was accessed.
212 * @kvm_fd: vCPU file descriptor for KVM.
213 *
214 * State of one CPU core or thread.
215 */
216 struct CPUState {
217 /*< private >*/
218 DeviceState parent_obj;
219 /*< public >*/
220
221 int nr_cores;
222 int nr_threads;
223 int numa_node;
224
225 struct QemuThread *thread;
226 #ifdef _WIN32
227 HANDLE hThread;
228 #endif
229 int thread_id;
230 uint32_t host_tid;
231 bool running;
232 struct QemuCond *halt_cond;
233 struct qemu_work_item *queued_work_first, *queued_work_last;
234 bool thread_kicked;
235 bool created;
236 bool stop;
237 bool stopped;
238 volatile sig_atomic_t exit_request;
239 uint32_t interrupt_request;
240 int singlestep_enabled;
241 int64_t icount_extra;
242 sigjmp_buf jmp_env;
243
244 AddressSpace *as;
245 MemoryListener *tcg_as_listener;
246
247 void *env_ptr; /* CPUArchState */
248 struct TranslationBlock *current_tb;
249 struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE];
250 struct GDBRegisterState *gdb_regs;
251 int gdb_num_regs;
252 int gdb_num_g_regs;
253 QTAILQ_ENTRY(CPUState) node;
254
255 /* ice debug support */
256 QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints;
257
258 QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints;
259 CPUWatchpoint *watchpoint_hit;
260
261 void *opaque;
262
263 /* In order to avoid passing too many arguments to the MMIO helpers,
264 * we store some rarely used information in the CPU context.
265 */
266 uintptr_t mem_io_pc;
267 vaddr mem_io_vaddr;
268
269 int kvm_fd;
270 bool kvm_vcpu_dirty;
271 struct KVMState *kvm_state;
272 struct kvm_run *kvm_run;
273
274 /* TODO Move common fields from CPUArchState here. */
275 int cpu_index; /* used by alpha TCG */
276 uint32_t halted; /* used by alpha, cris, ppc TCG */
277 union {
278 uint32_t u32;
279 icount_decr_u16 u16;
280 } icount_decr;
281 uint32_t can_do_io;
282 int32_t exception_index; /* used by m68k TCG */
283
284 /* Note that this is accessed at the start of every TB via a negative
285 offset from AREG0. Leave this field at the end so as to make the
286 (absolute value) offset as small as possible. This reduces code
287 size, especially for hosts without large memory offsets. */
288 volatile sig_atomic_t tcg_exit_req;
289 };
290
291 QTAILQ_HEAD(CPUTailQ, CPUState);
292 extern struct CPUTailQ cpus;
293 #define CPU_NEXT(cpu) QTAILQ_NEXT(cpu, node)
294 #define CPU_FOREACH(cpu) QTAILQ_FOREACH(cpu, &cpus, node)
295 #define CPU_FOREACH_SAFE(cpu, next_cpu) \
296 QTAILQ_FOREACH_SAFE(cpu, &cpus, node, next_cpu)
297 #define first_cpu QTAILQ_FIRST(&cpus)
298
299 DECLARE_TLS(CPUState *, current_cpu);
300 #define current_cpu tls_var(current_cpu)
301
302 /**
303 * cpu_paging_enabled:
304 * @cpu: The CPU whose state is to be inspected.
305 *
306 * Returns: %true if paging is enabled, %false otherwise.
307 */
308 bool cpu_paging_enabled(const CPUState *cpu);
309
310 /**
311 * cpu_get_memory_mapping:
312 * @cpu: The CPU whose memory mappings are to be obtained.
313 * @list: Where to write the memory mappings to.
314 * @errp: Pointer for reporting an #Error.
315 */
316 void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
317 Error **errp);
318
319 /**
320 * cpu_write_elf64_note:
321 * @f: pointer to a function that writes memory to a file
322 * @cpu: The CPU whose memory is to be dumped
323 * @cpuid: ID number of the CPU
324 * @opaque: pointer to the CPUState struct
325 */
326 int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
327 int cpuid, void *opaque);
328
329 /**
330 * cpu_write_elf64_qemunote:
331 * @f: pointer to a function that writes memory to a file
332 * @cpu: The CPU whose memory is to be dumped
333 * @cpuid: ID number of the CPU
334 * @opaque: pointer to the CPUState struct
335 */
336 int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
337 void *opaque);
338
339 /**
340 * cpu_write_elf32_note:
341 * @f: pointer to a function that writes memory to a file
342 * @cpu: The CPU whose memory is to be dumped
343 * @cpuid: ID number of the CPU
344 * @opaque: pointer to the CPUState struct
345 */
346 int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
347 int cpuid, void *opaque);
348
349 /**
350 * cpu_write_elf32_qemunote:
351 * @f: pointer to a function that writes memory to a file
352 * @cpu: The CPU whose memory is to be dumped
353 * @cpuid: ID number of the CPU
354 * @opaque: pointer to the CPUState struct
355 */
356 int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
357 void *opaque);
358
359 /**
360 * CPUDumpFlags:
361 * @CPU_DUMP_CODE:
362 * @CPU_DUMP_FPU: dump FPU register state, not just integer
363 * @CPU_DUMP_CCOP: dump info about TCG QEMU's condition code optimization state
364 */
365 enum CPUDumpFlags {
366 CPU_DUMP_CODE = 0x00010000,
367 CPU_DUMP_FPU = 0x00020000,
368 CPU_DUMP_CCOP = 0x00040000,
369 };
370
371 /**
372 * cpu_dump_state:
373 * @cpu: The CPU whose state is to be dumped.
374 * @f: File to dump to.
375 * @cpu_fprintf: Function to dump with.
376 * @flags: Flags what to dump.
377 *
378 * Dumps CPU state.
379 */
380 void cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
381 int flags);
382
383 /**
384 * cpu_dump_statistics:
385 * @cpu: The CPU whose state is to be dumped.
386 * @f: File to dump to.
387 * @cpu_fprintf: Function to dump with.
388 * @flags: Flags what to dump.
389 *
390 * Dumps CPU statistics.
391 */
392 void cpu_dump_statistics(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
393 int flags);
394
395 #ifndef CONFIG_USER_ONLY
396 /**
397 * cpu_get_phys_page_debug:
398 * @cpu: The CPU to obtain the physical page address for.
399 * @addr: The virtual address.
400 *
401 * Obtains the physical page corresponding to a virtual one.
402 * Use it only for debugging because no protection checks are done.
403 *
404 * Returns: Corresponding physical page address or -1 if no page found.
405 */
406 static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
407 {
408 CPUClass *cc = CPU_GET_CLASS(cpu);
409
410 return cc->get_phys_page_debug(cpu, addr);
411 }
412 #endif
413
414 /**
415 * cpu_reset:
416 * @cpu: The CPU whose state is to be reset.
417 */
418 void cpu_reset(CPUState *cpu);
419
420 /**
421 * cpu_class_by_name:
422 * @typename: The CPU base type.
423 * @cpu_model: The model string without any parameters.
424 *
425 * Looks up a CPU #ObjectClass matching name @cpu_model.
426 *
427 * Returns: A #CPUClass or %NULL if not matching class is found.
428 */
429 ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model);
430
431 /**
432 * cpu_generic_init:
433 * @typename: The CPU base type.
434 * @cpu_model: The model string including optional parameters.
435 *
436 * Instantiates a CPU, processes optional parameters and realizes the CPU.
437 *
438 * Returns: A #CPUState or %NULL if an error occurred.
439 */
440 CPUState *cpu_generic_init(const char *typename, const char *cpu_model);
441
442 /**
443 * cpu_has_work:
444 * @cpu: The vCPU to check.
445 *
446 * Checks whether the CPU has work to do.
447 *
448 * Returns: %true if the CPU has work, %false otherwise.
449 */
450 static inline bool cpu_has_work(CPUState *cpu)
451 {
452 CPUClass *cc = CPU_GET_CLASS(cpu);
453
454 g_assert(cc->has_work);
455 return cc->has_work(cpu);
456 }
457
458 /**
459 * qemu_cpu_is_self:
460 * @cpu: The vCPU to check against.
461 *
462 * Checks whether the caller is executing on the vCPU thread.
463 *
464 * Returns: %true if called from @cpu's thread, %false otherwise.
465 */
466 bool qemu_cpu_is_self(CPUState *cpu);
467
468 /**
469 * qemu_cpu_kick:
470 * @cpu: The vCPU to kick.
471 *
472 * Kicks @cpu's thread.
473 */
474 void qemu_cpu_kick(CPUState *cpu);
475
476 /**
477 * cpu_is_stopped:
478 * @cpu: The CPU to check.
479 *
480 * Checks whether the CPU is stopped.
481 *
482 * Returns: %true if run state is not running or if artificially stopped;
483 * %false otherwise.
484 */
485 bool cpu_is_stopped(CPUState *cpu);
486
487 /**
488 * run_on_cpu:
489 * @cpu: The vCPU to run on.
490 * @func: The function to be executed.
491 * @data: Data to pass to the function.
492 *
493 * Schedules the function @func for execution on the vCPU @cpu.
494 */
495 void run_on_cpu(CPUState *cpu, void (*func)(void *data), void *data);
496
497 /**
498 * async_run_on_cpu:
499 * @cpu: The vCPU to run on.
500 * @func: The function to be executed.
501 * @data: Data to pass to the function.
502 *
503 * Schedules the function @func for execution on the vCPU @cpu asynchronously.
504 */
505 void async_run_on_cpu(CPUState *cpu, void (*func)(void *data), void *data);
506
507 /**
508 * qemu_get_cpu:
509 * @index: The CPUState@cpu_index value of the CPU to obtain.
510 *
511 * Gets a CPU matching @index.
512 *
513 * Returns: The CPU or %NULL if there is no matching CPU.
514 */
515 CPUState *qemu_get_cpu(int index);
516
517 /**
518 * cpu_exists:
519 * @id: Guest-exposed CPU ID to lookup.
520 *
521 * Search for CPU with specified ID.
522 *
523 * Returns: %true - CPU is found, %false - CPU isn't found.
524 */
525 bool cpu_exists(int64_t id);
526
527 #ifndef CONFIG_USER_ONLY
528
529 typedef void (*CPUInterruptHandler)(CPUState *, int);
530
531 extern CPUInterruptHandler cpu_interrupt_handler;
532
533 /**
534 * cpu_interrupt:
535 * @cpu: The CPU to set an interrupt on.
536 * @mask: The interupts to set.
537 *
538 * Invokes the interrupt handler.
539 */
540 static inline void cpu_interrupt(CPUState *cpu, int mask)
541 {
542 cpu_interrupt_handler(cpu, mask);
543 }
544
545 #else /* USER_ONLY */
546
547 void cpu_interrupt(CPUState *cpu, int mask);
548
549 #endif /* USER_ONLY */
550
551 #ifdef CONFIG_SOFTMMU
552 static inline void cpu_unassigned_access(CPUState *cpu, hwaddr addr,
553 bool is_write, bool is_exec,
554 int opaque, unsigned size)
555 {
556 CPUClass *cc = CPU_GET_CLASS(cpu);
557
558 if (cc->do_unassigned_access) {
559 cc->do_unassigned_access(cpu, addr, is_write, is_exec, opaque, size);
560 }
561 }
562
563 static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr,
564 int is_write, int is_user,
565 uintptr_t retaddr)
566 {
567 CPUClass *cc = CPU_GET_CLASS(cpu);
568
569 return cc->do_unaligned_access(cpu, addr, is_write, is_user, retaddr);
570 }
571 #endif
572
573 /**
574 * cpu_reset_interrupt:
575 * @cpu: The CPU to clear the interrupt on.
576 * @mask: The interrupt mask to clear.
577 *
578 * Resets interrupts on the vCPU @cpu.
579 */
580 void cpu_reset_interrupt(CPUState *cpu, int mask);
581
582 /**
583 * cpu_exit:
584 * @cpu: The CPU to exit.
585 *
586 * Requests the CPU @cpu to exit execution.
587 */
588 void cpu_exit(CPUState *cpu);
589
590 /**
591 * cpu_resume:
592 * @cpu: The CPU to resume.
593 *
594 * Resumes CPU, i.e. puts CPU into runnable state.
595 */
596 void cpu_resume(CPUState *cpu);
597
598 /**
599 * qemu_init_vcpu:
600 * @cpu: The vCPU to initialize.
601 *
602 * Initializes a vCPU.
603 */
604 void qemu_init_vcpu(CPUState *cpu);
605
606 #define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */
607 #define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */
608 #define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */
609
610 /**
611 * cpu_single_step:
612 * @cpu: CPU to the flags for.
613 * @enabled: Flags to enable.
614 *
615 * Enables or disables single-stepping for @cpu.
616 */
617 void cpu_single_step(CPUState *cpu, int enabled);
618
619 /* Breakpoint/watchpoint flags */
620 #define BP_MEM_READ 0x01
621 #define BP_MEM_WRITE 0x02
622 #define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE)
623 #define BP_STOP_BEFORE_ACCESS 0x04
624 #define BP_WATCHPOINT_HIT 0x08
625 #define BP_GDB 0x10
626 #define BP_CPU 0x20
627
628 int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
629 CPUBreakpoint **breakpoint);
630 int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags);
631 void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint);
632 void cpu_breakpoint_remove_all(CPUState *cpu, int mask);
633
634 int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
635 int flags, CPUWatchpoint **watchpoint);
636 int cpu_watchpoint_remove(CPUState *cpu, vaddr addr,
637 vaddr len, int flags);
638 void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint);
639 void cpu_watchpoint_remove_all(CPUState *cpu, int mask);
640
641 void QEMU_NORETURN cpu_abort(CPUState *cpu, const char *fmt, ...)
642 GCC_FMT_ATTR(2, 3);
643
644 #ifdef CONFIG_SOFTMMU
645 extern const struct VMStateDescription vmstate_cpu_common;
646 #else
647 #define vmstate_cpu_common vmstate_dummy
648 #endif
649
650 #define VMSTATE_CPU() { \
651 .name = "parent_obj", \
652 .size = sizeof(CPUState), \
653 .vmsd = &vmstate_cpu_common, \
654 .flags = VMS_STRUCT, \
655 .offset = 0, \
656 }
657
658 #endif