exec: Change cpu_breakpoint_{insert,remove{,_by_ref,_all}} argument
[qemu.git] / include / qom / cpu.h
1 /*
2 * QEMU CPU model
3 *
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
19 */
20 #ifndef QEMU_CPU_H
21 #define QEMU_CPU_H
22
23 #include <signal.h>
24 #include <setjmp.h>
25 #include "hw/qdev-core.h"
26 #include "exec/hwaddr.h"
27 #include "qemu/queue.h"
28 #include "qemu/thread.h"
29 #include "qemu/tls.h"
30 #include "qemu/typedefs.h"
31
32 typedef int (*WriteCoreDumpFunction)(const void *buf, size_t size,
33 void *opaque);
34
35 /**
36 * vaddr:
37 * Type wide enough to contain any #target_ulong virtual address.
38 */
39 typedef uint64_t vaddr;
40 #define VADDR_PRId PRId64
41 #define VADDR_PRIu PRIu64
42 #define VADDR_PRIo PRIo64
43 #define VADDR_PRIx PRIx64
44 #define VADDR_PRIX PRIX64
45 #define VADDR_MAX UINT64_MAX
46
47 /**
48 * SECTION:cpu
49 * @section_id: QEMU-cpu
50 * @title: CPU Class
51 * @short_description: Base class for all CPUs
52 */
53
54 #define TYPE_CPU "cpu"
55
56 #define CPU(obj) OBJECT_CHECK(CPUState, (obj), TYPE_CPU)
57 #define CPU_CLASS(class) OBJECT_CLASS_CHECK(CPUClass, (class), TYPE_CPU)
58 #define CPU_GET_CLASS(obj) OBJECT_GET_CLASS(CPUClass, (obj), TYPE_CPU)
59
60 typedef struct CPUState CPUState;
61
62 typedef void (*CPUUnassignedAccess)(CPUState *cpu, hwaddr addr,
63 bool is_write, bool is_exec, int opaque,
64 unsigned size);
65
66 struct TranslationBlock;
67
68 /**
69 * CPUClass:
70 * @class_by_name: Callback to map -cpu command line model name to an
71 * instantiatable CPU type.
72 * @parse_features: Callback to parse command line arguments.
73 * @reset: Callback to reset the #CPUState to its initial state.
74 * @reset_dump_flags: #CPUDumpFlags to use for reset logging.
75 * @has_work: Callback for checking if there is work to do.
76 * @do_interrupt: Callback for interrupt handling.
77 * @do_unassigned_access: Callback for unassigned access handling.
78 * @memory_rw_debug: Callback for GDB memory access.
79 * @dump_state: Callback for dumping state.
80 * @dump_statistics: Callback for dumping statistics.
81 * @get_arch_id: Callback for getting architecture-dependent CPU ID.
82 * @get_paging_enabled: Callback for inquiring whether paging is enabled.
83 * @get_memory_mapping: Callback for obtaining the memory mappings.
84 * @set_pc: Callback for setting the Program Counter register.
85 * @synchronize_from_tb: Callback for synchronizing state from a TCG
86 * #TranslationBlock.
87 * @handle_mmu_fault: Callback for handling an MMU fault.
88 * @get_phys_page_debug: Callback for obtaining a physical address.
89 * @gdb_read_register: Callback for letting GDB read a register.
90 * @gdb_write_register: Callback for letting GDB write a register.
91 * @vmsd: State description for migration.
92 * @gdb_num_core_regs: Number of core registers accessible to GDB.
93 * @gdb_core_xml_file: File name for core registers GDB XML description.
94 *
95 * Represents a CPU family or model.
96 */
97 typedef struct CPUClass {
98 /*< private >*/
99 DeviceClass parent_class;
100 /*< public >*/
101
102 ObjectClass *(*class_by_name)(const char *cpu_model);
103 void (*parse_features)(CPUState *cpu, char *str, Error **errp);
104
105 void (*reset)(CPUState *cpu);
106 int reset_dump_flags;
107 bool (*has_work)(CPUState *cpu);
108 void (*do_interrupt)(CPUState *cpu);
109 CPUUnassignedAccess do_unassigned_access;
110 int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
111 uint8_t *buf, int len, bool is_write);
112 void (*dump_state)(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
113 int flags);
114 void (*dump_statistics)(CPUState *cpu, FILE *f,
115 fprintf_function cpu_fprintf, int flags);
116 int64_t (*get_arch_id)(CPUState *cpu);
117 bool (*get_paging_enabled)(const CPUState *cpu);
118 void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
119 Error **errp);
120 void (*set_pc)(CPUState *cpu, vaddr value);
121 void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb);
122 int (*handle_mmu_fault)(CPUState *cpu, vaddr address, int rw,
123 int mmu_index);
124 hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
125 int (*gdb_read_register)(CPUState *cpu, uint8_t *buf, int reg);
126 int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
127
128 int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu,
129 int cpuid, void *opaque);
130 int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
131 void *opaque);
132 int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu,
133 int cpuid, void *opaque);
134 int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
135 void *opaque);
136
137 const struct VMStateDescription *vmsd;
138 int gdb_num_core_regs;
139 const char *gdb_core_xml_file;
140 } CPUClass;
141
142 #ifdef HOST_WORDS_BIGENDIAN
143 typedef struct icount_decr_u16 {
144 uint16_t high;
145 uint16_t low;
146 } icount_decr_u16;
147 #else
148 typedef struct icount_decr_u16 {
149 uint16_t low;
150 uint16_t high;
151 } icount_decr_u16;
152 #endif
153
154 typedef struct CPUBreakpoint {
155 vaddr pc;
156 int flags; /* BP_* */
157 QTAILQ_ENTRY(CPUBreakpoint) entry;
158 } CPUBreakpoint;
159
160 typedef struct CPUWatchpoint {
161 vaddr vaddr;
162 vaddr len_mask;
163 int flags; /* BP_* */
164 QTAILQ_ENTRY(CPUWatchpoint) entry;
165 } CPUWatchpoint;
166
167 struct KVMState;
168 struct kvm_run;
169
170 #define TB_JMP_CACHE_BITS 12
171 #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
172
173 /**
174 * CPUState:
175 * @cpu_index: CPU index (informative).
176 * @nr_cores: Number of cores within this CPU package.
177 * @nr_threads: Number of threads within this CPU.
178 * @numa_node: NUMA node this CPU is belonging to.
179 * @host_tid: Host thread ID.
180 * @running: #true if CPU is currently running (usermode).
181 * @created: Indicates whether the CPU thread has been successfully created.
182 * @interrupt_request: Indicates a pending interrupt request.
183 * @halted: Nonzero if the CPU is in suspended state.
184 * @stop: Indicates a pending stop request.
185 * @stopped: Indicates the CPU has been artificially stopped.
186 * @tcg_exit_req: Set to force TCG to stop executing linked TBs for this
187 * CPU and return to its top level loop.
188 * @singlestep_enabled: Flags for single-stepping.
189 * @icount_extra: Instructions until next timer event.
190 * @icount_decr: Number of cycles left, with interrupt flag in high bit.
191 * This allows a single read-compare-cbranch-write sequence to test
192 * for both decrementer underflow and exceptions.
193 * @can_do_io: Nonzero if memory-mapped IO is safe.
194 * @env_ptr: Pointer to subclass-specific CPUArchState field.
195 * @current_tb: Currently executing TB.
196 * @gdb_regs: Additional GDB registers.
197 * @gdb_num_regs: Number of total registers accessible to GDB.
198 * @gdb_num_g_regs: Number of registers in GDB 'g' packets.
199 * @next_cpu: Next CPU sharing TB cache.
200 * @opaque: User data.
201 * @mem_io_pc: Host Program Counter at which the memory was accessed.
202 * @mem_io_vaddr: Target virtual address at which the memory was accessed.
203 * @kvm_fd: vCPU file descriptor for KVM.
204 *
205 * State of one CPU core or thread.
206 */
207 struct CPUState {
208 /*< private >*/
209 DeviceState parent_obj;
210 /*< public >*/
211
212 int nr_cores;
213 int nr_threads;
214 int numa_node;
215
216 struct QemuThread *thread;
217 #ifdef _WIN32
218 HANDLE hThread;
219 #endif
220 int thread_id;
221 uint32_t host_tid;
222 bool running;
223 struct QemuCond *halt_cond;
224 struct qemu_work_item *queued_work_first, *queued_work_last;
225 bool thread_kicked;
226 bool created;
227 bool stop;
228 bool stopped;
229 volatile sig_atomic_t exit_request;
230 volatile sig_atomic_t tcg_exit_req;
231 uint32_t interrupt_request;
232 int singlestep_enabled;
233 int64_t icount_extra;
234 sigjmp_buf jmp_env;
235
236 AddressSpace *as;
237 MemoryListener *tcg_as_listener;
238
239 void *env_ptr; /* CPUArchState */
240 struct TranslationBlock *current_tb;
241 struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE];
242 struct GDBRegisterState *gdb_regs;
243 int gdb_num_regs;
244 int gdb_num_g_regs;
245 QTAILQ_ENTRY(CPUState) node;
246
247 /* ice debug support */
248 QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints;
249
250 QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints;
251 CPUWatchpoint *watchpoint_hit;
252
253 void *opaque;
254
255 /* In order to avoid passing too many arguments to the MMIO helpers,
256 * we store some rarely used information in the CPU context.
257 */
258 uintptr_t mem_io_pc;
259 vaddr mem_io_vaddr;
260
261 int kvm_fd;
262 bool kvm_vcpu_dirty;
263 struct KVMState *kvm_state;
264 struct kvm_run *kvm_run;
265
266 /* TODO Move common fields from CPUArchState here. */
267 int cpu_index; /* used by alpha TCG */
268 uint32_t halted; /* used by alpha, cris, ppc TCG */
269 union {
270 uint32_t u32;
271 icount_decr_u16 u16;
272 } icount_decr;
273 uint32_t can_do_io;
274 int32_t exception_index; /* used by m68k TCG */
275 };
276
277 QTAILQ_HEAD(CPUTailQ, CPUState);
278 extern struct CPUTailQ cpus;
279 #define CPU_NEXT(cpu) QTAILQ_NEXT(cpu, node)
280 #define CPU_FOREACH(cpu) QTAILQ_FOREACH(cpu, &cpus, node)
281 #define CPU_FOREACH_SAFE(cpu, next_cpu) \
282 QTAILQ_FOREACH_SAFE(cpu, &cpus, node, next_cpu)
283 #define first_cpu QTAILQ_FIRST(&cpus)
284
285 DECLARE_TLS(CPUState *, current_cpu);
286 #define current_cpu tls_var(current_cpu)
287
288 /**
289 * cpu_paging_enabled:
290 * @cpu: The CPU whose state is to be inspected.
291 *
292 * Returns: %true if paging is enabled, %false otherwise.
293 */
294 bool cpu_paging_enabled(const CPUState *cpu);
295
296 /**
297 * cpu_get_memory_mapping:
298 * @cpu: The CPU whose memory mappings are to be obtained.
299 * @list: Where to write the memory mappings to.
300 * @errp: Pointer for reporting an #Error.
301 */
302 void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
303 Error **errp);
304
305 /**
306 * cpu_write_elf64_note:
307 * @f: pointer to a function that writes memory to a file
308 * @cpu: The CPU whose memory is to be dumped
309 * @cpuid: ID number of the CPU
310 * @opaque: pointer to the CPUState struct
311 */
312 int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
313 int cpuid, void *opaque);
314
315 /**
316 * cpu_write_elf64_qemunote:
317 * @f: pointer to a function that writes memory to a file
318 * @cpu: The CPU whose memory is to be dumped
319 * @cpuid: ID number of the CPU
320 * @opaque: pointer to the CPUState struct
321 */
322 int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
323 void *opaque);
324
325 /**
326 * cpu_write_elf32_note:
327 * @f: pointer to a function that writes memory to a file
328 * @cpu: The CPU whose memory is to be dumped
329 * @cpuid: ID number of the CPU
330 * @opaque: pointer to the CPUState struct
331 */
332 int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
333 int cpuid, void *opaque);
334
335 /**
336 * cpu_write_elf32_qemunote:
337 * @f: pointer to a function that writes memory to a file
338 * @cpu: The CPU whose memory is to be dumped
339 * @cpuid: ID number of the CPU
340 * @opaque: pointer to the CPUState struct
341 */
342 int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
343 void *opaque);
344
345 /**
346 * CPUDumpFlags:
347 * @CPU_DUMP_CODE:
348 * @CPU_DUMP_FPU: dump FPU register state, not just integer
349 * @CPU_DUMP_CCOP: dump info about TCG QEMU's condition code optimization state
350 */
351 enum CPUDumpFlags {
352 CPU_DUMP_CODE = 0x00010000,
353 CPU_DUMP_FPU = 0x00020000,
354 CPU_DUMP_CCOP = 0x00040000,
355 };
356
357 /**
358 * cpu_dump_state:
359 * @cpu: The CPU whose state is to be dumped.
360 * @f: File to dump to.
361 * @cpu_fprintf: Function to dump with.
362 * @flags: Flags what to dump.
363 *
364 * Dumps CPU state.
365 */
366 void cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
367 int flags);
368
369 /**
370 * cpu_dump_statistics:
371 * @cpu: The CPU whose state is to be dumped.
372 * @f: File to dump to.
373 * @cpu_fprintf: Function to dump with.
374 * @flags: Flags what to dump.
375 *
376 * Dumps CPU statistics.
377 */
378 void cpu_dump_statistics(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
379 int flags);
380
381 #ifndef CONFIG_USER_ONLY
382 /**
383 * cpu_get_phys_page_debug:
384 * @cpu: The CPU to obtain the physical page address for.
385 * @addr: The virtual address.
386 *
387 * Obtains the physical page corresponding to a virtual one.
388 * Use it only for debugging because no protection checks are done.
389 *
390 * Returns: Corresponding physical page address or -1 if no page found.
391 */
392 static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
393 {
394 CPUClass *cc = CPU_GET_CLASS(cpu);
395
396 return cc->get_phys_page_debug(cpu, addr);
397 }
398 #endif
399
400 /**
401 * cpu_reset:
402 * @cpu: The CPU whose state is to be reset.
403 */
404 void cpu_reset(CPUState *cpu);
405
406 /**
407 * cpu_class_by_name:
408 * @typename: The CPU base type.
409 * @cpu_model: The model string without any parameters.
410 *
411 * Looks up a CPU #ObjectClass matching name @cpu_model.
412 *
413 * Returns: A #CPUClass or %NULL if not matching class is found.
414 */
415 ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model);
416
417 /**
418 * cpu_generic_init:
419 * @typename: The CPU base type.
420 * @cpu_model: The model string including optional parameters.
421 *
422 * Instantiates a CPU, processes optional parameters and realizes the CPU.
423 *
424 * Returns: A #CPUState or %NULL if an error occurred.
425 */
426 CPUState *cpu_generic_init(const char *typename, const char *cpu_model);
427
428 /**
429 * cpu_has_work:
430 * @cpu: The vCPU to check.
431 *
432 * Checks whether the CPU has work to do.
433 *
434 * Returns: %true if the CPU has work, %false otherwise.
435 */
436 static inline bool cpu_has_work(CPUState *cpu)
437 {
438 CPUClass *cc = CPU_GET_CLASS(cpu);
439
440 g_assert(cc->has_work);
441 return cc->has_work(cpu);
442 }
443
444 /**
445 * qemu_cpu_is_self:
446 * @cpu: The vCPU to check against.
447 *
448 * Checks whether the caller is executing on the vCPU thread.
449 *
450 * Returns: %true if called from @cpu's thread, %false otherwise.
451 */
452 bool qemu_cpu_is_self(CPUState *cpu);
453
454 /**
455 * qemu_cpu_kick:
456 * @cpu: The vCPU to kick.
457 *
458 * Kicks @cpu's thread.
459 */
460 void qemu_cpu_kick(CPUState *cpu);
461
462 /**
463 * cpu_is_stopped:
464 * @cpu: The CPU to check.
465 *
466 * Checks whether the CPU is stopped.
467 *
468 * Returns: %true if run state is not running or if artificially stopped;
469 * %false otherwise.
470 */
471 bool cpu_is_stopped(CPUState *cpu);
472
473 /**
474 * run_on_cpu:
475 * @cpu: The vCPU to run on.
476 * @func: The function to be executed.
477 * @data: Data to pass to the function.
478 *
479 * Schedules the function @func for execution on the vCPU @cpu.
480 */
481 void run_on_cpu(CPUState *cpu, void (*func)(void *data), void *data);
482
483 /**
484 * async_run_on_cpu:
485 * @cpu: The vCPU to run on.
486 * @func: The function to be executed.
487 * @data: Data to pass to the function.
488 *
489 * Schedules the function @func for execution on the vCPU @cpu asynchronously.
490 */
491 void async_run_on_cpu(CPUState *cpu, void (*func)(void *data), void *data);
492
493 /**
494 * qemu_get_cpu:
495 * @index: The CPUState@cpu_index value of the CPU to obtain.
496 *
497 * Gets a CPU matching @index.
498 *
499 * Returns: The CPU or %NULL if there is no matching CPU.
500 */
501 CPUState *qemu_get_cpu(int index);
502
503 /**
504 * cpu_exists:
505 * @id: Guest-exposed CPU ID to lookup.
506 *
507 * Search for CPU with specified ID.
508 *
509 * Returns: %true - CPU is found, %false - CPU isn't found.
510 */
511 bool cpu_exists(int64_t id);
512
513 #ifndef CONFIG_USER_ONLY
514
515 typedef void (*CPUInterruptHandler)(CPUState *, int);
516
517 extern CPUInterruptHandler cpu_interrupt_handler;
518
519 /**
520 * cpu_interrupt:
521 * @cpu: The CPU to set an interrupt on.
522 * @mask: The interupts to set.
523 *
524 * Invokes the interrupt handler.
525 */
526 static inline void cpu_interrupt(CPUState *cpu, int mask)
527 {
528 cpu_interrupt_handler(cpu, mask);
529 }
530
531 #else /* USER_ONLY */
532
533 void cpu_interrupt(CPUState *cpu, int mask);
534
535 #endif /* USER_ONLY */
536
537 #ifndef CONFIG_USER_ONLY
538
539 static inline void cpu_unassigned_access(CPUState *cpu, hwaddr addr,
540 bool is_write, bool is_exec,
541 int opaque, unsigned size)
542 {
543 CPUClass *cc = CPU_GET_CLASS(cpu);
544
545 if (cc->do_unassigned_access) {
546 cc->do_unassigned_access(cpu, addr, is_write, is_exec, opaque, size);
547 }
548 }
549
550 #endif
551
552 /**
553 * cpu_reset_interrupt:
554 * @cpu: The CPU to clear the interrupt on.
555 * @mask: The interrupt mask to clear.
556 *
557 * Resets interrupts on the vCPU @cpu.
558 */
559 void cpu_reset_interrupt(CPUState *cpu, int mask);
560
561 /**
562 * cpu_exit:
563 * @cpu: The CPU to exit.
564 *
565 * Requests the CPU @cpu to exit execution.
566 */
567 void cpu_exit(CPUState *cpu);
568
569 /**
570 * cpu_resume:
571 * @cpu: The CPU to resume.
572 *
573 * Resumes CPU, i.e. puts CPU into runnable state.
574 */
575 void cpu_resume(CPUState *cpu);
576
577 /**
578 * qemu_init_vcpu:
579 * @cpu: The vCPU to initialize.
580 *
581 * Initializes a vCPU.
582 */
583 void qemu_init_vcpu(CPUState *cpu);
584
585 #define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */
586 #define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */
587 #define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */
588
589 /**
590 * cpu_single_step:
591 * @cpu: CPU to the flags for.
592 * @enabled: Flags to enable.
593 *
594 * Enables or disables single-stepping for @cpu.
595 */
596 void cpu_single_step(CPUState *cpu, int enabled);
597
598 /* Breakpoint/watchpoint flags */
599 #define BP_MEM_READ 0x01
600 #define BP_MEM_WRITE 0x02
601 #define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE)
602 #define BP_STOP_BEFORE_ACCESS 0x04
603 #define BP_WATCHPOINT_HIT 0x08
604 #define BP_GDB 0x10
605 #define BP_CPU 0x20
606
607 int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
608 CPUBreakpoint **breakpoint);
609 int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags);
610 void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint);
611 void cpu_breakpoint_remove_all(CPUState *cpu, int mask);
612
613 int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
614 int flags, CPUWatchpoint **watchpoint);
615 int cpu_watchpoint_remove(CPUState *cpu, vaddr addr,
616 vaddr len, int flags);
617 void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint);
618 void cpu_watchpoint_remove_all(CPUState *cpu, int mask);
619
620 #ifdef CONFIG_SOFTMMU
621 extern const struct VMStateDescription vmstate_cpu_common;
622 #else
623 #define vmstate_cpu_common vmstate_dummy
624 #endif
625
626 #define VMSTATE_CPU() { \
627 .name = "parent_obj", \
628 .size = sizeof(CPUState), \
629 .vmsd = &vmstate_cpu_common, \
630 .flags = VMS_STRUCT, \
631 .offset = 0, \
632 }
633
634 #endif