include/qom/cpu.h

   1 /*
   2  * QEMU CPU model
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20 #ifndef QEMU_CPU_H
  21 #define QEMU_CPU_H
  22
  23 #include <signal.h>
  24 #include <setjmp.h>
  25 #include "hw/qdev-core.h"
  26 #include "exec/hwaddr.h"
  27 #include "qemu/queue.h"
  28 #include "qemu/thread.h"
  29 #include "qemu/tls.h"
  30 #include "qemu/typedefs.h"
  31
  32 typedef int (*WriteCoreDumpFunction)(const void *buf, size_t size,
  33                                      void *opaque);
  34
  35 /**
  36  * vaddr:
  37  * Type wide enough to contain any #target_ulong virtual address.
  38  */
  39 typedef uint64_t vaddr;
  40 #define VADDR_PRId PRId64
  41 #define VADDR_PRIu PRIu64
  42 #define VADDR_PRIo PRIo64
  43 #define VADDR_PRIx PRIx64
  44 #define VADDR_PRIX PRIX64
  45 #define VADDR_MAX UINT64_MAX
  46
  47 /**
  48  * SECTION:cpu
  49  * @section_id: QEMU-cpu
  50  * @title: CPU Class
  51  * @short_description: Base class for all CPUs
  52  */
  53
  54 #define TYPE_CPU "cpu"
  55
  56 #define CPU(obj) OBJECT_CHECK(CPUState, (obj), TYPE_CPU)
  57 #define CPU_CLASS(class) OBJECT_CLASS_CHECK(CPUClass, (class), TYPE_CPU)
  58 #define CPU_GET_CLASS(obj) OBJECT_GET_CLASS(CPUClass, (obj), TYPE_CPU)
  59
  60 typedef struct CPUState CPUState;
  61
  62 typedef void (*CPUUnassignedAccess)(CPUState *cpu, hwaddr addr,
  63                                     bool is_write, bool is_exec, int opaque,
  64                                     unsigned size);
  65
  66 struct TranslationBlock;
  67
  68 /**
  69  * CPUClass:
  70  * @class_by_name: Callback to map -cpu command line model name to an
  71  * instantiatable CPU type.
  72  * @parse_features: Callback to parse command line arguments.
  73  * @reset: Callback to reset the #CPUState to its initial state.
  74  * @reset_dump_flags: #CPUDumpFlags to use for reset logging.
  75  * @has_work: Callback for checking if there is work to do.
  76  * @do_interrupt: Callback for interrupt handling.
  77  * @do_unassigned_access: Callback for unassigned access handling.
  78  * @memory_rw_debug: Callback for GDB memory access.
  79  * @dump_state: Callback for dumping state.
  80  * @dump_statistics: Callback for dumping statistics.
  81  * @get_arch_id: Callback for getting architecture-dependent CPU ID.
  82  * @get_paging_enabled: Callback for inquiring whether paging is enabled.
  83  * @get_memory_mapping: Callback for obtaining the memory mappings.
  84  * @set_pc: Callback for setting the Program Counter register.
  85  * @synchronize_from_tb: Callback for synchronizing state from a TCG
  86  * #TranslationBlock.
  87  * @handle_mmu_fault: Callback for handling an MMU fault.
  88  * @get_phys_page_debug: Callback for obtaining a physical address.
  89  * @gdb_read_register: Callback for letting GDB read a register.
  90  * @gdb_write_register: Callback for letting GDB write a register.
  91  * @vmsd: State description for migration.
  92  * @gdb_num_core_regs: Number of core registers accessible to GDB.
  93  * @gdb_core_xml_file: File name for core registers GDB XML description.
  94  *
  95  * Represents a CPU family or model.
  96  */
  97 typedef struct CPUClass {
  98     /*< private >*/
  99     DeviceClass parent_class;
 100     /*< public >*/
 101
 102     ObjectClass *(*class_by_name)(const char *cpu_model);
 103     void (*parse_features)(CPUState *cpu, char *str, Error **errp);
 104
 105     void (*reset)(CPUState *cpu);
 106     int reset_dump_flags;
 107     bool (*has_work)(CPUState *cpu);
 108     void (*do_interrupt)(CPUState *cpu);
 109     CPUUnassignedAccess do_unassigned_access;
 110     int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
 111                            uint8_t *buf, int len, bool is_write);
 112     void (*dump_state)(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
 113                        int flags);
 114     void (*dump_statistics)(CPUState *cpu, FILE *f,
 115                             fprintf_function cpu_fprintf, int flags);
 116     int64_t (*get_arch_id)(CPUState *cpu);
 117     bool (*get_paging_enabled)(const CPUState *cpu);
 118     void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
 119                                Error **errp);
 120     void (*set_pc)(CPUState *cpu, vaddr value);
 121     void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb);
 122     int (*handle_mmu_fault)(CPUState *cpu, vaddr address, int rw,
 123                             int mmu_index);
 124     hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
 125     int (*gdb_read_register)(CPUState *cpu, uint8_t *buf, int reg);
 126     int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
 127
 128     int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu,
 129                             int cpuid, void *opaque);
 130     int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
 131                                 void *opaque);
 132     int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu,
 133                             int cpuid, void *opaque);
 134     int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
 135                                 void *opaque);
 136
 137     const struct VMStateDescription *vmsd;
 138     int gdb_num_core_regs;
 139     const char *gdb_core_xml_file;
 140 } CPUClass;
 141
 142 #ifdef HOST_WORDS_BIGENDIAN
 143 typedef struct icount_decr_u16 {
 144     uint16_t high;
 145     uint16_t low;
 146 } icount_decr_u16;
 147 #else
 148 typedef struct icount_decr_u16 {
 149     uint16_t low;
 150     uint16_t high;
 151 } icount_decr_u16;
 152 #endif
 153
 154 typedef struct CPUWatchpoint {
 155     vaddr vaddr;
 156     vaddr len_mask;
 157     int flags; /* BP_* */
 158     QTAILQ_ENTRY(CPUWatchpoint) entry;
 159 } CPUWatchpoint;
 160
 161 struct KVMState;
 162 struct kvm_run;
 163
 164 #define TB_JMP_CACHE_BITS 12
 165 #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
 166
 167 /**
 168  * CPUState:
 169  * @cpu_index: CPU index (informative).
 170  * @nr_cores: Number of cores within this CPU package.
 171  * @nr_threads: Number of threads within this CPU.
 172  * @numa_node: NUMA node this CPU is belonging to.
 173  * @host_tid: Host thread ID.
 174  * @running: #true if CPU is currently running (usermode).
 175  * @created: Indicates whether the CPU thread has been successfully created.
 176  * @interrupt_request: Indicates a pending interrupt request.
 177  * @halted: Nonzero if the CPU is in suspended state.
 178  * @stop: Indicates a pending stop request.
 179  * @stopped: Indicates the CPU has been artificially stopped.
 180  * @tcg_exit_req: Set to force TCG to stop executing linked TBs for this
 181  *           CPU and return to its top level loop.
 182  * @singlestep_enabled: Flags for single-stepping.
 183  * @icount_extra: Instructions until next timer event.
 184  * @icount_decr: Number of cycles left, with interrupt flag in high bit.
 185  * This allows a single read-compare-cbranch-write sequence to test
 186  * for both decrementer underflow and exceptions.
 187  * @can_do_io: Nonzero if memory-mapped IO is safe.
 188  * @env_ptr: Pointer to subclass-specific CPUArchState field.
 189  * @current_tb: Currently executing TB.
 190  * @gdb_regs: Additional GDB registers.
 191  * @gdb_num_regs: Number of total registers accessible to GDB.
 192  * @gdb_num_g_regs: Number of registers in GDB 'g' packets.
 193  * @next_cpu: Next CPU sharing TB cache.
 194  * @opaque: User data.
 195  * @mem_io_pc: Host Program Counter at which the memory was accessed.
 196  * @mem_io_vaddr: Target virtual address at which the memory was accessed.
 197  * @kvm_fd: vCPU file descriptor for KVM.
 198  *
 199  * State of one CPU core or thread.
 200  */
 201 struct CPUState {
 202     /*< private >*/
 203     DeviceState parent_obj;
 204     /*< public >*/
 205
 206     int nr_cores;
 207     int nr_threads;
 208     int numa_node;
 209
 210     struct QemuThread *thread;
 211 #ifdef _WIN32
 212     HANDLE hThread;
 213 #endif
 214     int thread_id;
 215     uint32_t host_tid;
 216     bool running;
 217     struct QemuCond *halt_cond;
 218     struct qemu_work_item *queued_work_first, *queued_work_last;
 219     bool thread_kicked;
 220     bool created;
 221     bool stop;
 222     bool stopped;
 223     volatile sig_atomic_t exit_request;
 224     volatile sig_atomic_t tcg_exit_req;
 225     uint32_t interrupt_request;
 226     int singlestep_enabled;
 227     int64_t icount_extra;
 228     sigjmp_buf jmp_env;
 229
 230     AddressSpace *as;
 231     MemoryListener *tcg_as_listener;
 232
 233     void *env_ptr; /* CPUArchState */
 234     struct TranslationBlock *current_tb;
 235     struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE];
 236     struct GDBRegisterState *gdb_regs;
 237     int gdb_num_regs;
 238     int gdb_num_g_regs;
 239     QTAILQ_ENTRY(CPUState) node;
 240
 241     QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints;
 242     CPUWatchpoint *watchpoint_hit;
 243
 244     void *opaque;
 245
 246     /* In order to avoid passing too many arguments to the MMIO helpers,
 247      * we store some rarely used information in the CPU context.
 248      */
 249     uintptr_t mem_io_pc;
 250     vaddr mem_io_vaddr;
 251
 252     int kvm_fd;
 253     bool kvm_vcpu_dirty;
 254     struct KVMState *kvm_state;
 255     struct kvm_run *kvm_run;
 256
 257     /* TODO Move common fields from CPUArchState here. */
 258     int cpu_index; /* used by alpha TCG */
 259     uint32_t halted; /* used by alpha, cris, ppc TCG */
 260     union {
 261         uint32_t u32;
 262         icount_decr_u16 u16;
 263     } icount_decr;
 264     uint32_t can_do_io;
 265     int32_t exception_index; /* used by m68k TCG */
 266 };
 267
 268 QTAILQ_HEAD(CPUTailQ, CPUState);
 269 extern struct CPUTailQ cpus;
 270 #define CPU_NEXT(cpu) QTAILQ_NEXT(cpu, node)
 271 #define CPU_FOREACH(cpu) QTAILQ_FOREACH(cpu, &cpus, node)
 272 #define CPU_FOREACH_SAFE(cpu, next_cpu) \
 273     QTAILQ_FOREACH_SAFE(cpu, &cpus, node, next_cpu)
 274 #define first_cpu QTAILQ_FIRST(&cpus)
 275
 276 DECLARE_TLS(CPUState *, current_cpu);
 277 #define current_cpu tls_var(current_cpu)
 278
 279 /**
 280  * cpu_paging_enabled:
 281  * @cpu: The CPU whose state is to be inspected.
 282  *
 283  * Returns: %true if paging is enabled, %false otherwise.
 284  */
 285 bool cpu_paging_enabled(const CPUState *cpu);
 286
 287 /**
 288  * cpu_get_memory_mapping:
 289  * @cpu: The CPU whose memory mappings are to be obtained.
 290  * @list: Where to write the memory mappings to.
 291  * @errp: Pointer for reporting an #Error.
 292  */
 293 void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
 294                             Error **errp);
 295
 296 /**
 297  * cpu_write_elf64_note:
 298  * @f: pointer to a function that writes memory to a file
 299  * @cpu: The CPU whose memory is to be dumped
 300  * @cpuid: ID number of the CPU
 301  * @opaque: pointer to the CPUState struct
 302  */
 303 int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
 304                          int cpuid, void *opaque);
 305
 306 /**
 307  * cpu_write_elf64_qemunote:
 308  * @f: pointer to a function that writes memory to a file
 309  * @cpu: The CPU whose memory is to be dumped
 310  * @cpuid: ID number of the CPU
 311  * @opaque: pointer to the CPUState struct
 312  */
 313 int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
 314                              void *opaque);
 315
 316 /**
 317  * cpu_write_elf32_note:
 318  * @f: pointer to a function that writes memory to a file
 319  * @cpu: The CPU whose memory is to be dumped
 320  * @cpuid: ID number of the CPU
 321  * @opaque: pointer to the CPUState struct
 322  */
 323 int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
 324                          int cpuid, void *opaque);
 325
 326 /**
 327  * cpu_write_elf32_qemunote:
 328  * @f: pointer to a function that writes memory to a file
 329  * @cpu: The CPU whose memory is to be dumped
 330  * @cpuid: ID number of the CPU
 331  * @opaque: pointer to the CPUState struct
 332  */
 333 int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
 334                              void *opaque);
 335
 336 /**
 337  * CPUDumpFlags:
 338  * @CPU_DUMP_CODE:
 339  * @CPU_DUMP_FPU: dump FPU register state, not just integer
 340  * @CPU_DUMP_CCOP: dump info about TCG QEMU's condition code optimization state
 341  */
 342 enum CPUDumpFlags {
 343     CPU_DUMP_CODE = 0x00010000,
 344     CPU_DUMP_FPU  = 0x00020000,
 345     CPU_DUMP_CCOP = 0x00040000,
 346 };
 347
 348 /**
 349  * cpu_dump_state:
 350  * @cpu: The CPU whose state is to be dumped.
 351  * @f: File to dump to.
 352  * @cpu_fprintf: Function to dump with.
 353  * @flags: Flags what to dump.
 354  *
 355  * Dumps CPU state.
 356  */
 357 void cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
 358                     int flags);
 359
 360 /**
 361  * cpu_dump_statistics:
 362  * @cpu: The CPU whose state is to be dumped.
 363  * @f: File to dump to.
 364  * @cpu_fprintf: Function to dump with.
 365  * @flags: Flags what to dump.
 366  *
 367  * Dumps CPU statistics.
 368  */
 369 void cpu_dump_statistics(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
 370                          int flags);
 371
 372 #ifndef CONFIG_USER_ONLY
 373 /**
 374  * cpu_get_phys_page_debug:
 375  * @cpu: The CPU to obtain the physical page address for.
 376  * @addr: The virtual address.
 377  *
 378  * Obtains the physical page corresponding to a virtual one.
 379  * Use it only for debugging because no protection checks are done.
 380  *
 381  * Returns: Corresponding physical page address or -1 if no page found.
 382  */
 383 static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
 384 {
 385     CPUClass *cc = CPU_GET_CLASS(cpu);
 386
 387     return cc->get_phys_page_debug(cpu, addr);
 388 }
 389 #endif
 390
 391 /**
 392  * cpu_reset:
 393  * @cpu: The CPU whose state is to be reset.
 394  */
 395 void cpu_reset(CPUState *cpu);
 396
 397 /**
 398  * cpu_class_by_name:
 399  * @typename: The CPU base type.
 400  * @cpu_model: The model string without any parameters.
 401  *
 402  * Looks up a CPU #ObjectClass matching name @cpu_model.
 403  *
 404  * Returns: A #CPUClass or %NULL if not matching class is found.
 405  */
 406 ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model);
 407
 408 /**
 409  * cpu_generic_init:
 410  * @typename: The CPU base type.
 411  * @cpu_model: The model string including optional parameters.
 412  *
 413  * Instantiates a CPU, processes optional parameters and realizes the CPU.
 414  *
 415  * Returns: A #CPUState or %NULL if an error occurred.
 416  */
 417 CPUState *cpu_generic_init(const char *typename, const char *cpu_model);
 418
 419 /**
 420  * cpu_has_work:
 421  * @cpu: The vCPU to check.
 422  *
 423  * Checks whether the CPU has work to do.
 424  *
 425  * Returns: %true if the CPU has work, %false otherwise.
 426  */
 427 static inline bool cpu_has_work(CPUState *cpu)
 428 {
 429     CPUClass *cc = CPU_GET_CLASS(cpu);
 430
 431     g_assert(cc->has_work);
 432     return cc->has_work(cpu);
 433 }
 434
 435 /**
 436  * qemu_cpu_is_self:
 437  * @cpu: The vCPU to check against.
 438  *
 439  * Checks whether the caller is executing on the vCPU thread.
 440  *
 441  * Returns: %true if called from @cpu's thread, %false otherwise.
 442  */
 443 bool qemu_cpu_is_self(CPUState *cpu);
 444
 445 /**
 446  * qemu_cpu_kick:
 447  * @cpu: The vCPU to kick.
 448  *
 449  * Kicks @cpu's thread.
 450  */
 451 void qemu_cpu_kick(CPUState *cpu);
 452
 453 /**
 454  * cpu_is_stopped:
 455  * @cpu: The CPU to check.
 456  *
 457  * Checks whether the CPU is stopped.
 458  *
 459  * Returns: %true if run state is not running or if artificially stopped;
 460  * %false otherwise.
 461  */
 462 bool cpu_is_stopped(CPUState *cpu);
 463
 464 /**
 465  * run_on_cpu:
 466  * @cpu: The vCPU to run on.
 467  * @func: The function to be executed.
 468  * @data: Data to pass to the function.
 469  *
 470  * Schedules the function @func for execution on the vCPU @cpu.
 471  */
 472 void run_on_cpu(CPUState *cpu, void (*func)(void *data), void *data);
 473
 474 /**
 475  * async_run_on_cpu:
 476  * @cpu: The vCPU to run on.
 477  * @func: The function to be executed.
 478  * @data: Data to pass to the function.
 479  *
 480  * Schedules the function @func for execution on the vCPU @cpu asynchronously.
 481  */
 482 void async_run_on_cpu(CPUState *cpu, void (*func)(void *data), void *data);
 483
 484 /**
 485  * qemu_get_cpu:
 486  * @index: The CPUState@cpu_index value of the CPU to obtain.
 487  *
 488  * Gets a CPU matching @index.
 489  *
 490  * Returns: The CPU or %NULL if there is no matching CPU.
 491  */
 492 CPUState *qemu_get_cpu(int index);
 493
 494 /**
 495  * cpu_exists:
 496  * @id: Guest-exposed CPU ID to lookup.
 497  *
 498  * Search for CPU with specified ID.
 499  *
 500  * Returns: %true - CPU is found, %false - CPU isn't found.
 501  */
 502 bool cpu_exists(int64_t id);
 503
 504 #ifndef CONFIG_USER_ONLY
 505
 506 typedef void (*CPUInterruptHandler)(CPUState *, int);
 507
 508 extern CPUInterruptHandler cpu_interrupt_handler;
 509
 510 /**
 511  * cpu_interrupt:
 512  * @cpu: The CPU to set an interrupt on.
 513  * @mask: The interupts to set.
 514  *
 515  * Invokes the interrupt handler.
 516  */
 517 static inline void cpu_interrupt(CPUState *cpu, int mask)
 518 {
 519     cpu_interrupt_handler(cpu, mask);
 520 }
 521
 522 #else /* USER_ONLY */
 523
 524 void cpu_interrupt(CPUState *cpu, int mask);
 525
 526 #endif /* USER_ONLY */
 527
 528 #ifndef CONFIG_USER_ONLY
 529
 530 static inline void cpu_unassigned_access(CPUState *cpu, hwaddr addr,
 531                                          bool is_write, bool is_exec,
 532                                          int opaque, unsigned size)
 533 {
 534     CPUClass *cc = CPU_GET_CLASS(cpu);
 535
 536     if (cc->do_unassigned_access) {
 537         cc->do_unassigned_access(cpu, addr, is_write, is_exec, opaque, size);
 538     }
 539 }
 540
 541 #endif
 542
 543 /**
 544  * cpu_reset_interrupt:
 545  * @cpu: The CPU to clear the interrupt on.
 546  * @mask: The interrupt mask to clear.
 547  *
 548  * Resets interrupts on the vCPU @cpu.
 549  */
 550 void cpu_reset_interrupt(CPUState *cpu, int mask);
 551
 552 /**
 553  * cpu_exit:
 554  * @cpu: The CPU to exit.
 555  *
 556  * Requests the CPU @cpu to exit execution.
 557  */
 558 void cpu_exit(CPUState *cpu);
 559
 560 /**
 561  * cpu_resume:
 562  * @cpu: The CPU to resume.
 563  *
 564  * Resumes CPU, i.e. puts CPU into runnable state.
 565  */
 566 void cpu_resume(CPUState *cpu);
 567
 568 /**
 569  * qemu_init_vcpu:
 570  * @cpu: The vCPU to initialize.
 571  *
 572  * Initializes a vCPU.
 573  */
 574 void qemu_init_vcpu(CPUState *cpu);
 575
 576 #define SSTEP_ENABLE  0x1  /* Enable simulated HW single stepping */
 577 #define SSTEP_NOIRQ   0x2  /* Do not use IRQ while single stepping */
 578 #define SSTEP_NOTIMER 0x4  /* Do not Timers while single stepping */
 579
 580 /**
 581  * cpu_single_step:
 582  * @cpu: CPU to the flags for.
 583  * @enabled: Flags to enable.
 584  *
 585  * Enables or disables single-stepping for @cpu.
 586  */
 587 void cpu_single_step(CPUState *cpu, int enabled);
 588
 589 #ifdef CONFIG_SOFTMMU
 590 extern const struct VMStateDescription vmstate_cpu_common;
 591 #else
 592 #define vmstate_cpu_common vmstate_dummy
 593 #endif
 594
 595 #define VMSTATE_CPU() {                                                     \
 596     .name = "parent_obj",                                                   \
 597     .size = sizeof(CPUState),                                               \
 598     .vmsd = &vmstate_cpu_common,                                            \
 599     .flags = VMS_STRUCT,                                                    \
 600     .offset = 0,                                                            \
 601 }
 602
 603 #endif