Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-for-5.2-pull-reques...
[qemu.git] / include / standard-headers / drm / drm_fourcc.h
1 /*
2 * Copyright 2011 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #ifndef DRM_FOURCC_H
25 #define DRM_FOURCC_H
26
27
28 #if defined(__cplusplus)
29 extern "C" {
30 #endif
31
32 /**
33 * DOC: overview
34 *
35 * In the DRM subsystem, framebuffer pixel formats are described using the
36 * fourcc codes defined in `include/uapi/drm/drm_fourcc.h`. In addition to the
37 * fourcc code, a Format Modifier may optionally be provided, in order to
38 * further describe the buffer's format - for example tiling or compression.
39 *
40 * Format Modifiers
41 * ----------------
42 *
43 * Format modifiers are used in conjunction with a fourcc code, forming a
44 * unique fourcc:modifier pair. This format:modifier pair must fully define the
45 * format and data layout of the buffer, and should be the only way to describe
46 * that particular buffer.
47 *
48 * Having multiple fourcc:modifier pairs which describe the same layout should
49 * be avoided, as such aliases run the risk of different drivers exposing
50 * different names for the same data format, forcing userspace to understand
51 * that they are aliases.
52 *
53 * Format modifiers may change any property of the buffer, including the number
54 * of planes and/or the required allocation size. Format modifiers are
55 * vendor-namespaced, and as such the relationship between a fourcc code and a
56 * modifier is specific to the modifer being used. For example, some modifiers
57 * may preserve meaning - such as number of planes - from the fourcc code,
58 * whereas others may not.
59 *
60 * Vendors should document their modifier usage in as much detail as
61 * possible, to ensure maximum compatibility across devices, drivers and
62 * applications.
63 *
64 * The authoritative list of format modifier codes is found in
65 * `include/uapi/drm/drm_fourcc.h`
66 */
67
68 #define fourcc_code(a, b, c, d) ((uint32_t)(a) | ((uint32_t)(b) << 8) | \
69 ((uint32_t)(c) << 16) | ((uint32_t)(d) << 24))
70
71 #define DRM_FORMAT_BIG_ENDIAN (1U<<31) /* format is big endian instead of little endian */
72
73 /* Reserve 0 for the invalid format specifier */
74 #define DRM_FORMAT_INVALID 0
75
76 /* color index */
77 #define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
78
79 /* 8 bpp Red */
80 #define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */
81
82 /* 16 bpp Red */
83 #define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */
84
85 /* 16 bpp RG */
86 #define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */
87 #define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */
88
89 /* 32 bpp RG */
90 #define DRM_FORMAT_RG1616 fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */
91 #define DRM_FORMAT_GR1616 fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */
92
93 /* 8 bpp RGB */
94 #define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */
95 #define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */
96
97 /* 16 bpp RGB */
98 #define DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */
99 #define DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */
100 #define DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */
101 #define DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */
102
103 #define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */
104 #define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */
105 #define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */
106 #define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */
107
108 #define DRM_FORMAT_XRGB1555 fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */
109 #define DRM_FORMAT_XBGR1555 fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */
110 #define DRM_FORMAT_RGBX5551 fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */
111 #define DRM_FORMAT_BGRX5551 fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */
112
113 #define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */
114 #define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */
115 #define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */
116 #define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */
117
118 #define DRM_FORMAT_RGB565 fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */
119 #define DRM_FORMAT_BGR565 fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */
120
121 /* 24 bpp RGB */
122 #define DRM_FORMAT_RGB888 fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */
123 #define DRM_FORMAT_BGR888 fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */
124
125 /* 32 bpp RGB */
126 #define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */
127 #define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */
128 #define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */
129 #define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */
130
131 #define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */
132 #define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */
133 #define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */
134 #define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */
135
136 #define DRM_FORMAT_XRGB2101010 fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */
137 #define DRM_FORMAT_XBGR2101010 fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */
138 #define DRM_FORMAT_RGBX1010102 fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */
139 #define DRM_FORMAT_BGRX1010102 fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */
140
141 #define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */
142 #define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */
143 #define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */
144 #define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */
145
146 /*
147 * Floating point 64bpp RGB
148 * IEEE 754-2008 binary16 half-precision float
149 * [15:0] sign:exponent:mantissa 1:5:10
150 */
151 #define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0] x:R:G:B 16:16:16:16 little endian */
152 #define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0] x:B:G:R 16:16:16:16 little endian */
153
154 #define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */
155 #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */
156
157 /* packed YCbCr */
158 #define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */
159 #define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */
160 #define DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */
161 #define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
162
163 #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
164 #define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
165 #define DRM_FORMAT_VUY888 fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y 8:8:8 little endian */
166 #define DRM_FORMAT_VUY101010 fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-linear modifier only */
167
168 /*
169 * packed Y2xx indicate for each component, xx valid data occupy msb
170 * 16-xx padding occupy lsb
171 */
172 #define DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 10:6:10:6:10:6:10:6 little endian per 2 Y pixels */
173 #define DRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 12:4:12:4:12:4:12:4 little endian per 2 Y pixels */
174 #define DRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6') /* [63:0] Cr0:Y1:Cb0:Y0 16:16:16:16 little endian per 2 Y pixels */
175
176 /*
177 * packed Y4xx indicate for each component, xx valid data occupy msb
178 * 16-xx padding occupy lsb except Y410
179 */
180 #define DRM_FORMAT_Y410 fourcc_code('Y', '4', '1', '0') /* [31:0] A:Cr:Y:Cb 2:10:10:10 little endian */
181 #define DRM_FORMAT_Y412 fourcc_code('Y', '4', '1', '2') /* [63:0] A:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */
182 #define DRM_FORMAT_Y416 fourcc_code('Y', '4', '1', '6') /* [63:0] A:Cr:Y:Cb 16:16:16:16 little endian */
183
184 #define DRM_FORMAT_XVYU2101010 fourcc_code('X', 'V', '3', '0') /* [31:0] X:Cr:Y:Cb 2:10:10:10 little endian */
185 #define DRM_FORMAT_XVYU12_16161616 fourcc_code('X', 'V', '3', '6') /* [63:0] X:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */
186 #define DRM_FORMAT_XVYU16161616 fourcc_code('X', 'V', '4', '8') /* [63:0] X:Cr:Y:Cb 16:16:16:16 little endian */
187
188 /*
189 * packed YCbCr420 2x2 tiled formats
190 * first 64 bits will contain Y,Cb,Cr components for a 2x2 tile
191 */
192 /* [63:0] A3:A2:Y3:0:Cr0:0:Y2:0:A1:A0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */
193 #define DRM_FORMAT_Y0L0 fourcc_code('Y', '0', 'L', '0')
194 /* [63:0] X3:X2:Y3:0:Cr0:0:Y2:0:X1:X0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */
195 #define DRM_FORMAT_X0L0 fourcc_code('X', '0', 'L', '0')
196
197 /* [63:0] A3:A2:Y3:Cr0:Y2:A1:A0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */
198 #define DRM_FORMAT_Y0L2 fourcc_code('Y', '0', 'L', '2')
199 /* [63:0] X3:X2:Y3:Cr0:Y2:X1:X0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */
200 #define DRM_FORMAT_X0L2 fourcc_code('X', '0', 'L', '2')
201
202 /*
203 * 1-plane YUV 4:2:0
204 * In these formats, the component ordering is specified (Y, followed by U
205 * then V), but the exact Linear layout is undefined.
206 * These formats can only be used with a non-Linear modifier.
207 */
208 #define DRM_FORMAT_YUV420_8BIT fourcc_code('Y', 'U', '0', '8')
209 #define DRM_FORMAT_YUV420_10BIT fourcc_code('Y', 'U', '1', '0')
210
211 /*
212 * 2 plane RGB + A
213 * index 0 = RGB plane, same format as the corresponding non _A8 format has
214 * index 1 = A plane, [7:0] A
215 */
216 #define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8')
217 #define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8')
218 #define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8')
219 #define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8')
220 #define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8')
221 #define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8')
222 #define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8')
223 #define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8')
224
225 /*
226 * 2 plane YCbCr
227 * index 0 = Y plane, [7:0] Y
228 * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian
229 * or
230 * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian
231 */
232 #define DRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */
233 #define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */
234 #define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */
235 #define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */
236 #define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
237 #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
238
239 /*
240 * 2 plane YCbCr MSB aligned
241 * index 0 = Y plane, [15:0] Y:x [10:6] little endian
242 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
243 */
244 #define DRM_FORMAT_P210 fourcc_code('P', '2', '1', '0') /* 2x1 subsampled Cr:Cb plane, 10 bit per channel */
245
246 /*
247 * 2 plane YCbCr MSB aligned
248 * index 0 = Y plane, [15:0] Y:x [10:6] little endian
249 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
250 */
251 #define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel */
252
253 /*
254 * 2 plane YCbCr MSB aligned
255 * index 0 = Y plane, [15:0] Y:x [12:4] little endian
256 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian
257 */
258 #define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per channel */
259
260 /*
261 * 2 plane YCbCr MSB aligned
262 * index 0 = Y plane, [15:0] Y little endian
263 * index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian
264 */
265 #define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */
266
267 /*
268 * 3 plane YCbCr
269 * index 0: Y plane, [7:0] Y
270 * index 1: Cb plane, [7:0] Cb
271 * index 2: Cr plane, [7:0] Cr
272 * or
273 * index 1: Cr plane, [7:0] Cr
274 * index 2: Cb plane, [7:0] Cb
275 */
276 #define DRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */
277 #define DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */
278 #define DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */
279 #define DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */
280 #define DRM_FORMAT_YUV420 fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */
281 #define DRM_FORMAT_YVU420 fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */
282 #define DRM_FORMAT_YUV422 fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */
283 #define DRM_FORMAT_YVU422 fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */
284 #define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */
285 #define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */
286
287
288 /*
289 * Format Modifiers:
290 *
291 * Format modifiers describe, typically, a re-ordering or modification
292 * of the data in a plane of an FB. This can be used to express tiled/
293 * swizzled formats, or compression, or a combination of the two.
294 *
295 * The upper 8 bits of the format modifier are a vendor-id as assigned
296 * below. The lower 56 bits are assigned as vendor sees fit.
297 */
298
299 /* Vendor Ids: */
300 #define DRM_FORMAT_MOD_NONE 0
301 #define DRM_FORMAT_MOD_VENDOR_NONE 0
302 #define DRM_FORMAT_MOD_VENDOR_INTEL 0x01
303 #define DRM_FORMAT_MOD_VENDOR_AMD 0x02
304 #define DRM_FORMAT_MOD_VENDOR_NVIDIA 0x03
305 #define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04
306 #define DRM_FORMAT_MOD_VENDOR_QCOM 0x05
307 #define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06
308 #define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07
309 #define DRM_FORMAT_MOD_VENDOR_ARM 0x08
310 #define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09
311
312 /* add more to the end as needed */
313
314 #define DRM_FORMAT_RESERVED ((1ULL << 56) - 1)
315
316 #define fourcc_mod_code(vendor, val) \
317 ((((uint64_t)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL))
318
319 /*
320 * Format Modifier tokens:
321 *
322 * When adding a new token please document the layout with a code comment,
323 * similar to the fourcc codes above. drm_fourcc.h is considered the
324 * authoritative source for all of these.
325 */
326
327 /*
328 * Invalid Modifier
329 *
330 * This modifier can be used as a sentinel to terminate the format modifiers
331 * list, or to initialize a variable with an invalid modifier. It might also be
332 * used to report an error back to userspace for certain APIs.
333 */
334 #define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED)
335
336 /*
337 * Linear Layout
338 *
339 * Just plain linear layout. Note that this is different from no specifying any
340 * modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl),
341 * which tells the driver to also take driver-internal information into account
342 * and so might actually result in a tiled framebuffer.
343 */
344 #define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0)
345
346 /* Intel framebuffer modifiers */
347
348 /*
349 * Intel X-tiling layout
350 *
351 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
352 * in row-major layout. Within the tile bytes are laid out row-major, with
353 * a platform-dependent stride. On top of that the memory can apply
354 * platform-depending swizzling of some higher address bits into bit6.
355 *
356 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.
357 * On earlier platforms the is highly platforms specific and not useful for
358 * cross-driver sharing. It exists since on a given platform it does uniquely
359 * identify the layout in a simple way for i915-specific userspace, which
360 * facilitated conversion of userspace to modifiers. Additionally the exact
361 * format on some really old platforms is not known.
362 */
363 #define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1)
364
365 /*
366 * Intel Y-tiling layout
367 *
368 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
369 * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes)
370 * chunks column-major, with a platform-dependent height. On top of that the
371 * memory can apply platform-depending swizzling of some higher address bits
372 * into bit6.
373 *
374 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.
375 * On earlier platforms the is highly platforms specific and not useful for
376 * cross-driver sharing. It exists since on a given platform it does uniquely
377 * identify the layout in a simple way for i915-specific userspace, which
378 * facilitated conversion of userspace to modifiers. Additionally the exact
379 * format on some really old platforms is not known.
380 */
381 #define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2)
382
383 /*
384 * Intel Yf-tiling layout
385 *
386 * This is a tiled layout using 4Kb tiles in row-major layout.
387 * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which
388 * are arranged in four groups (two wide, two high) with column-major layout.
389 * Each group therefore consits out of four 256 byte units, which are also laid
390 * out as 2x2 column-major.
391 * 256 byte units are made out of four 64 byte blocks of pixels, producing
392 * either a square block or a 2:1 unit.
393 * 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width
394 * in pixel depends on the pixel depth.
395 */
396 #define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3)
397
398 /*
399 * Intel color control surface (CCS) for render compression
400 *
401 * The framebuffer format must be one of the 8:8:8:8 RGB formats.
402 * The main surface will be plane index 0 and must be Y/Yf-tiled,
403 * the CCS will be plane index 1.
404 *
405 * Each CCS tile matches a 1024x512 pixel area of the main surface.
406 * To match certain aspects of the 3D hardware the CCS is
407 * considered to be made up of normal 128Bx32 Y tiles, Thus
408 * the CCS pitch must be specified in multiples of 128 bytes.
409 *
410 * In reality the CCS tile appears to be a 64Bx64 Y tile, composed
411 * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks.
412 * But that fact is not relevant unless the memory is accessed
413 * directly.
414 */
415 #define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4)
416 #define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5)
417
418 /*
419 * Intel color control surfaces (CCS) for Gen-12 render compression.
420 *
421 * The main surface is Y-tiled and at plane index 0, the CCS is linear and
422 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
423 * main surface. In other words, 4 bits in CCS map to a main surface cache
424 * line pair. The main surface pitch is required to be a multiple of four
425 * Y-tile widths.
426 */
427 #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
428
429 /*
430 * Intel color control surfaces (CCS) for Gen-12 media compression
431 *
432 * The main surface is Y-tiled and at plane index 0, the CCS is linear and
433 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
434 * main surface. In other words, 4 bits in CCS map to a main surface cache
435 * line pair. The main surface pitch is required to be a multiple of four
436 * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the
437 * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces,
438 * planes 2 and 3 for the respective CCS.
439 */
440 #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
441
442 /*
443 * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
444 *
445 * Macroblocks are laid in a Z-shape, and each pixel data is following the
446 * standard NV12 style.
447 * As for NV12, an image is the result of two frame buffers: one for Y,
448 * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer).
449 * Alignment requirements are (for each buffer):
450 * - multiple of 128 pixels for the width
451 * - multiple of 32 pixels for the height
452 *
453 * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html
454 */
455 #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1)
456
457 /*
458 * Tiled, 16 (pixels) x 16 (lines) - sized macroblocks
459 *
460 * This is a simple tiled layout using tiles of 16x16 pixels in a row-major
461 * layout. For YCbCr formats Cb/Cr components are taken in such a way that
462 * they correspond to their 16x16 luma block.
463 */
464 #define DRM_FORMAT_MOD_SAMSUNG_16_16_TILE fourcc_mod_code(SAMSUNG, 2)
465
466 /*
467 * Qualcomm Compressed Format
468 *
469 * Refers to a compressed variant of the base format that is compressed.
470 * Implementation may be platform and base-format specific.
471 *
472 * Each macrotile consists of m x n (mostly 4 x 4) tiles.
473 * Pixel data pitch/stride is aligned with macrotile width.
474 * Pixel data height is aligned with macrotile height.
475 * Entire pixel data buffer is aligned with 4k(bytes).
476 */
477 #define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1)
478
479 /* Vivante framebuffer modifiers */
480
481 /*
482 * Vivante 4x4 tiling layout
483 *
484 * This is a simple tiled layout using tiles of 4x4 pixels in a row-major
485 * layout.
486 */
487 #define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1)
488
489 /*
490 * Vivante 64x64 super-tiling layout
491 *
492 * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
493 * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row-
494 * major layout.
495 *
496 * For more information: see
497 * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling
498 */
499 #define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2)
500
501 /*
502 * Vivante 4x4 tiling layout for dual-pipe
503 *
504 * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a
505 * different base address. Offsets from the base addresses are therefore halved
506 * compared to the non-split tiled layout.
507 */
508 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3)
509
510 /*
511 * Vivante 64x64 super-tiling layout for dual-pipe
512 *
513 * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile
514 * starts at a different base address. Offsets from the base addresses are
515 * therefore halved compared to the non-split super-tiled layout.
516 */
517 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4)
518
519 /* NVIDIA frame buffer modifiers */
520
521 /*
522 * Tegra Tiled Layout, used by Tegra 2, 3 and 4.
523 *
524 * Pixels are arranged in simple tiles of 16 x 16 bytes.
525 */
526 #define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1)
527
528 /*
529 * Generalized Block Linear layout, used by desktop GPUs starting with NV50/G80,
530 * and Tegra GPUs starting with Tegra K1.
531 *
532 * Pixels are arranged in Groups of Bytes (GOBs). GOB size and layout varies
533 * based on the architecture generation. GOBs themselves are then arranged in
534 * 3D blocks, with the block dimensions (in terms of GOBs) always being a power
535 * of two, and hence expressible as their log2 equivalent (E.g., "2" represents
536 * a block depth or height of "4").
537 *
538 * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
539 * in full detail.
540 *
541 * Macro
542 * Bits Param Description
543 * ---- ----- -----------------------------------------------------------------
544 *
545 * 3:0 h log2(height) of each block, in GOBs. Placed here for
546 * compatibility with the existing
547 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
548 *
549 * 4:4 - Must be 1, to indicate block-linear layout. Necessary for
550 * compatibility with the existing
551 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
552 *
553 * 8:5 - Reserved (To support 3D-surfaces with variable log2(depth) block
554 * size). Must be zero.
555 *
556 * Note there is no log2(width) parameter. Some portions of the
557 * hardware support a block width of two gobs, but it is impractical
558 * to use due to lack of support elsewhere, and has no known
559 * benefits.
560 *
561 * 11:9 - Reserved (To support 2D-array textures with variable array stride
562 * in blocks, specified via log2(tile width in blocks)). Must be
563 * zero.
564 *
565 * 19:12 k Page Kind. This value directly maps to a field in the page
566 * tables of all GPUs >= NV50. It affects the exact layout of bits
567 * in memory and can be derived from the tuple
568 *
569 * (format, GPU model, compression type, samples per pixel)
570 *
571 * Where compression type is defined below. If GPU model were
572 * implied by the format modifier, format, or memory buffer, page
573 * kind would not need to be included in the modifier itself, but
574 * since the modifier should define the layout of the associated
575 * memory buffer independent from any device or other context, it
576 * must be included here.
577 *
578 * 21:20 g GOB Height and Page Kind Generation. The height of a GOB changed
579 * starting with Fermi GPUs. Additionally, the mapping between page
580 * kind and bit layout has changed at various points.
581 *
582 * 0 = Gob Height 8, Fermi - Volta, Tegra K1+ Page Kind mapping
583 * 1 = Gob Height 4, G80 - GT2XX Page Kind mapping
584 * 2 = Gob Height 8, Turing+ Page Kind mapping
585 * 3 = Reserved for future use.
586 *
587 * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further
588 * bit remapping step that occurs at an even lower level than the
589 * page kind and block linear swizzles. This causes the layout of
590 * surfaces mapped in those SOC's GPUs to be incompatible with the
591 * equivalent mapping on other GPUs in the same system.
592 *
593 * 0 = Tegra K1 - Tegra Parker/TX2 Layout.
594 * 1 = Desktop GPU and Tegra Xavier+ Layout
595 *
596 * 25:23 c Lossless Framebuffer Compression type.
597 *
598 * 0 = none
599 * 1 = ROP/3D, layout 1, exact compression format implied by Page
600 * Kind field
601 * 2 = ROP/3D, layout 2, exact compression format implied by Page
602 * Kind field
603 * 3 = CDE horizontal
604 * 4 = CDE vertical
605 * 5 = Reserved for future use
606 * 6 = Reserved for future use
607 * 7 = Reserved for future use
608 *
609 * 55:25 - Reserved for future use. Must be zero.
610 */
611 #define DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(c, s, g, k, h) \
612 fourcc_mod_code(NVIDIA, (0x10 | \
613 ((h) & 0xf) | \
614 (((k) & 0xff) << 12) | \
615 (((g) & 0x3) << 20) | \
616 (((s) & 0x1) << 22) | \
617 (((c) & 0x7) << 23)))
618
619 /* To grandfather in prior block linear format modifiers to the above layout,
620 * the page kind "0", which corresponds to "pitch/linear" and hence is unusable
621 * with block-linear layouts, is remapped within drivers to the value 0xfe,
622 * which corresponds to the "generic" kind used for simple single-sample
623 * uncompressed color formats on Fermi - Volta GPUs.
624 */
625 static inline uint64_t
626 drm_fourcc_canonicalize_nvidia_format_mod(uint64_t modifier)
627 {
628 if (!(modifier & 0x10) || (modifier & (0xff << 12)))
629 return modifier;
630 else
631 return modifier | (0xfe << 12);
632 }
633
634 /*
635 * 16Bx2 Block Linear layout, used by Tegra K1 and later
636 *
637 * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked
638 * vertically by a power of 2 (1 to 32 GOBs) to form a block.
639 *
640 * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape.
641 *
642 * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically.
643 * Valid values are:
644 *
645 * 0 == ONE_GOB
646 * 1 == TWO_GOBS
647 * 2 == FOUR_GOBS
648 * 3 == EIGHT_GOBS
649 * 4 == SIXTEEN_GOBS
650 * 5 == THIRTYTWO_GOBS
651 *
652 * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
653 * in full detail.
654 */
655 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \
656 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 0, 0, 0, (v))
657
658 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \
659 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0)
660 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \
661 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1)
662 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \
663 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2)
664 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \
665 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3)
666 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \
667 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4)
668 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \
669 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5)
670
671 /*
672 * Some Broadcom modifiers take parameters, for example the number of
673 * vertical lines in the image. Reserve the lower 32 bits for modifier
674 * type, and the next 24 bits for parameters. Top 8 bits are the
675 * vendor code.
676 */
677 #define __fourcc_mod_broadcom_param_shift 8
678 #define __fourcc_mod_broadcom_param_bits 48
679 #define fourcc_mod_broadcom_code(val, params) \
680 fourcc_mod_code(BROADCOM, ((((uint64_t)params) << __fourcc_mod_broadcom_param_shift) | val))
681 #define fourcc_mod_broadcom_param(m) \
682 ((int)(((m) >> __fourcc_mod_broadcom_param_shift) & \
683 ((1ULL << __fourcc_mod_broadcom_param_bits) - 1)))
684 #define fourcc_mod_broadcom_mod(m) \
685 ((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) << \
686 __fourcc_mod_broadcom_param_shift))
687
688 /*
689 * Broadcom VC4 "T" format
690 *
691 * This is the primary layout that the V3D GPU can texture from (it
692 * can't do linear). The T format has:
693 *
694 * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4
695 * pixels at 32 bit depth.
696 *
697 * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually
698 * 16x16 pixels).
699 *
700 * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On
701 * even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows
702 * they're (TR, BR, BL, TL), where bottom left is start of memory.
703 *
704 * - an image made of 4k tiles in rows either left-to-right (even rows of 4k
705 * tiles) or right-to-left (odd rows of 4k tiles).
706 */
707 #define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1)
708
709 /*
710 * Broadcom SAND format
711 *
712 * This is the native format that the H.264 codec block uses. For VC4
713 * HVS, it is only valid for H.264 (NV12/21) and RGBA modes.
714 *
715 * The image can be considered to be split into columns, and the
716 * columns are placed consecutively into memory. The width of those
717 * columns can be either 32, 64, 128, or 256 pixels, but in practice
718 * only 128 pixel columns are used.
719 *
720 * The pitch between the start of each column is set to optimally
721 * switch between SDRAM banks. This is passed as the number of lines
722 * of column width in the modifier (we can't use the stride value due
723 * to various core checks that look at it , so you should set the
724 * stride to width*cpp).
725 *
726 * Note that the column height for this format modifier is the same
727 * for all of the planes, assuming that each column contains both Y
728 * and UV. Some SAND-using hardware stores UV in a separate tiled
729 * image from Y to reduce the column height, which is not supported
730 * with these modifiers.
731 */
732
733 #define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \
734 fourcc_mod_broadcom_code(2, v)
735 #define DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(v) \
736 fourcc_mod_broadcom_code(3, v)
737 #define DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(v) \
738 fourcc_mod_broadcom_code(4, v)
739 #define DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(v) \
740 fourcc_mod_broadcom_code(5, v)
741
742 #define DRM_FORMAT_MOD_BROADCOM_SAND32 \
743 DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(0)
744 #define DRM_FORMAT_MOD_BROADCOM_SAND64 \
745 DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(0)
746 #define DRM_FORMAT_MOD_BROADCOM_SAND128 \
747 DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(0)
748 #define DRM_FORMAT_MOD_BROADCOM_SAND256 \
749 DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(0)
750
751 /* Broadcom UIF format
752 *
753 * This is the common format for the current Broadcom multimedia
754 * blocks, including V3D 3.x and newer, newer video codecs, and
755 * displays.
756 *
757 * The image consists of utiles (64b blocks), UIF blocks (2x2 utiles),
758 * and macroblocks (4x4 UIF blocks). Those 4x4 UIF block groups are
759 * stored in columns, with padding between the columns to ensure that
760 * moving from one column to the next doesn't hit the same SDRAM page
761 * bank.
762 *
763 * To calculate the padding, it is assumed that each hardware block
764 * and the software driving it knows the platform's SDRAM page size,
765 * number of banks, and XOR address, and that it's identical between
766 * all blocks using the format. This tiling modifier will use XOR as
767 * necessary to reduce the padding. If a hardware block can't do XOR,
768 * the assumption is that a no-XOR tiling modifier will be created.
769 */
770 #define DRM_FORMAT_MOD_BROADCOM_UIF fourcc_mod_code(BROADCOM, 6)
771
772 /*
773 * Arm Framebuffer Compression (AFBC) modifiers
774 *
775 * AFBC is a proprietary lossless image compression protocol and format.
776 * It provides fine-grained random access and minimizes the amount of data
777 * transferred between IP blocks.
778 *
779 * AFBC has several features which may be supported and/or used, which are
780 * represented using bits in the modifier. Not all combinations are valid,
781 * and different devices or use-cases may support different combinations.
782 *
783 * Further information on the use of AFBC modifiers can be found in
784 * Documentation/gpu/afbc.rst
785 */
786
787 /*
788 * The top 4 bits (out of the 56 bits alloted for specifying vendor specific
789 * modifiers) denote the category for modifiers. Currently we have only two
790 * categories of modifiers ie AFBC and MISC. We can have a maximum of sixteen
791 * different categories.
792 */
793 #define DRM_FORMAT_MOD_ARM_CODE(__type, __val) \
794 fourcc_mod_code(ARM, ((uint64_t)(__type) << 52) | ((__val) & 0x000fffffffffffffULL))
795
796 #define DRM_FORMAT_MOD_ARM_TYPE_AFBC 0x00
797 #define DRM_FORMAT_MOD_ARM_TYPE_MISC 0x01
798
799 #define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) \
800 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFBC, __afbc_mode)
801
802 /*
803 * AFBC superblock size
804 *
805 * Indicates the superblock size(s) used for the AFBC buffer. The buffer
806 * size (in pixels) must be aligned to a multiple of the superblock size.
807 * Four lowest significant bits(LSBs) are reserved for block size.
808 *
809 * Where one superblock size is specified, it applies to all planes of the
810 * buffer (e.g. 16x16, 32x8). When multiple superblock sizes are specified,
811 * the first applies to the Luma plane and the second applies to the Chroma
812 * plane(s). e.g. (32x8_64x4 means 32x8 Luma, with 64x4 Chroma).
813 * Multiple superblock sizes are only valid for multi-plane YCbCr formats.
814 */
815 #define AFBC_FORMAT_MOD_BLOCK_SIZE_MASK 0xf
816 #define AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 (1ULL)
817 #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 (2ULL)
818 #define AFBC_FORMAT_MOD_BLOCK_SIZE_64x4 (3ULL)
819 #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8_64x4 (4ULL)
820
821 /*
822 * AFBC lossless colorspace transform
823 *
824 * Indicates that the buffer makes use of the AFBC lossless colorspace
825 * transform.
826 */
827 #define AFBC_FORMAT_MOD_YTR (1ULL << 4)
828
829 /*
830 * AFBC block-split
831 *
832 * Indicates that the payload of each superblock is split. The second
833 * half of the payload is positioned at a predefined offset from the start
834 * of the superblock payload.
835 */
836 #define AFBC_FORMAT_MOD_SPLIT (1ULL << 5)
837
838 /*
839 * AFBC sparse layout
840 *
841 * This flag indicates that the payload of each superblock must be stored at a
842 * predefined position relative to the other superblocks in the same AFBC
843 * buffer. This order is the same order used by the header buffer. In this mode
844 * each superblock is given the same amount of space as an uncompressed
845 * superblock of the particular format would require, rounding up to the next
846 * multiple of 128 bytes in size.
847 */
848 #define AFBC_FORMAT_MOD_SPARSE (1ULL << 6)
849
850 /*
851 * AFBC copy-block restrict
852 *
853 * Buffers with this flag must obey the copy-block restriction. The restriction
854 * is such that there are no copy-blocks referring across the border of 8x8
855 * blocks. For the subsampled data the 8x8 limitation is also subsampled.
856 */
857 #define AFBC_FORMAT_MOD_CBR (1ULL << 7)
858
859 /*
860 * AFBC tiled layout
861 *
862 * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all
863 * superblocks inside a tile are stored together in memory. 8x8 tiles are used
864 * for pixel formats up to and including 32 bpp while 4x4 tiles are used for
865 * larger bpp formats. The order between the tiles is scan line.
866 * When the tiled layout is used, the buffer size (in pixels) must be aligned
867 * to the tile size.
868 */
869 #define AFBC_FORMAT_MOD_TILED (1ULL << 8)
870
871 /*
872 * AFBC solid color blocks
873 *
874 * Indicates that the buffer makes use of solid-color blocks, whereby bandwidth
875 * can be reduced if a whole superblock is a single color.
876 */
877 #define AFBC_FORMAT_MOD_SC (1ULL << 9)
878
879 /*
880 * AFBC double-buffer
881 *
882 * Indicates that the buffer is allocated in a layout safe for front-buffer
883 * rendering.
884 */
885 #define AFBC_FORMAT_MOD_DB (1ULL << 10)
886
887 /*
888 * AFBC buffer content hints
889 *
890 * Indicates that the buffer includes per-superblock content hints.
891 */
892 #define AFBC_FORMAT_MOD_BCH (1ULL << 11)
893
894 /*
895 * Arm 16x16 Block U-Interleaved modifier
896 *
897 * This is used by Arm Mali Utgard and Midgard GPUs. It divides the image
898 * into 16x16 pixel blocks. Blocks are stored linearly in order, but pixels
899 * in the block are reordered.
900 */
901 #define DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED \
902 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_MISC, 1ULL)
903
904 /*
905 * Allwinner tiled modifier
906 *
907 * This tiling mode is implemented by the VPU found on all Allwinner platforms,
908 * codenamed sunxi. It is associated with a YUV format that uses either 2 or 3
909 * planes.
910 *
911 * With this tiling, the luminance samples are disposed in tiles representing
912 * 32x32 pixels and the chrominance samples in tiles representing 32x64 pixels.
913 * The pixel order in each tile is linear and the tiles are disposed linearly,
914 * both in row-major order.
915 */
916 #define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1)
917
918 #if defined(__cplusplus)
919 }
920 #endif
921
922 #endif /* DRM_FOURCC_H */