python/qemu/console_socket.py: Correct type of recv()
[qemu.git] / linux-headers / asm-arm / kvm.h
1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2 /*
3 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
4 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License, version 2, as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
18 */
19
20 #ifndef __ARM_KVM_H__
21 #define __ARM_KVM_H__
22
23 #include <linux/types.h>
24 #include <linux/psci.h>
25 #include <asm/ptrace.h>
26
27 #define __KVM_HAVE_GUEST_DEBUG
28 #define __KVM_HAVE_IRQ_LINE
29 #define __KVM_HAVE_READONLY_MEM
30 #define __KVM_HAVE_VCPU_EVENTS
31
32 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1
33
34 #define KVM_REG_SIZE(id) \
35 (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
36
37 /* Valid for svc_regs, abt_regs, und_regs, irq_regs in struct kvm_regs */
38 #define KVM_ARM_SVC_sp svc_regs[0]
39 #define KVM_ARM_SVC_lr svc_regs[1]
40 #define KVM_ARM_SVC_spsr svc_regs[2]
41 #define KVM_ARM_ABT_sp abt_regs[0]
42 #define KVM_ARM_ABT_lr abt_regs[1]
43 #define KVM_ARM_ABT_spsr abt_regs[2]
44 #define KVM_ARM_UND_sp und_regs[0]
45 #define KVM_ARM_UND_lr und_regs[1]
46 #define KVM_ARM_UND_spsr und_regs[2]
47 #define KVM_ARM_IRQ_sp irq_regs[0]
48 #define KVM_ARM_IRQ_lr irq_regs[1]
49 #define KVM_ARM_IRQ_spsr irq_regs[2]
50
51 /* Valid only for fiq_regs in struct kvm_regs */
52 #define KVM_ARM_FIQ_r8 fiq_regs[0]
53 #define KVM_ARM_FIQ_r9 fiq_regs[1]
54 #define KVM_ARM_FIQ_r10 fiq_regs[2]
55 #define KVM_ARM_FIQ_fp fiq_regs[3]
56 #define KVM_ARM_FIQ_ip fiq_regs[4]
57 #define KVM_ARM_FIQ_sp fiq_regs[5]
58 #define KVM_ARM_FIQ_lr fiq_regs[6]
59 #define KVM_ARM_FIQ_spsr fiq_regs[7]
60
61 struct kvm_regs {
62 struct pt_regs usr_regs; /* R0_usr - R14_usr, PC, CPSR */
63 unsigned long svc_regs[3]; /* SP_svc, LR_svc, SPSR_svc */
64 unsigned long abt_regs[3]; /* SP_abt, LR_abt, SPSR_abt */
65 unsigned long und_regs[3]; /* SP_und, LR_und, SPSR_und */
66 unsigned long irq_regs[3]; /* SP_irq, LR_irq, SPSR_irq */
67 unsigned long fiq_regs[8]; /* R8_fiq - R14_fiq, SPSR_fiq */
68 };
69
70 /* Supported Processor Types */
71 #define KVM_ARM_TARGET_CORTEX_A15 0
72 #define KVM_ARM_TARGET_CORTEX_A7 1
73 #define KVM_ARM_NUM_TARGETS 2
74
75 /* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */
76 #define KVM_ARM_DEVICE_TYPE_SHIFT 0
77 #define KVM_ARM_DEVICE_TYPE_MASK (0xffff << KVM_ARM_DEVICE_TYPE_SHIFT)
78 #define KVM_ARM_DEVICE_ID_SHIFT 16
79 #define KVM_ARM_DEVICE_ID_MASK (0xffff << KVM_ARM_DEVICE_ID_SHIFT)
80
81 /* Supported device IDs */
82 #define KVM_ARM_DEVICE_VGIC_V2 0
83
84 /* Supported VGIC address types */
85 #define KVM_VGIC_V2_ADDR_TYPE_DIST 0
86 #define KVM_VGIC_V2_ADDR_TYPE_CPU 1
87
88 #define KVM_VGIC_V2_DIST_SIZE 0x1000
89 #define KVM_VGIC_V2_CPU_SIZE 0x2000
90
91 /* Supported VGICv3 address types */
92 #define KVM_VGIC_V3_ADDR_TYPE_DIST 2
93 #define KVM_VGIC_V3_ADDR_TYPE_REDIST 3
94 #define KVM_VGIC_ITS_ADDR_TYPE 4
95 #define KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION 5
96
97 #define KVM_VGIC_V3_DIST_SIZE SZ_64K
98 #define KVM_VGIC_V3_REDIST_SIZE (2 * SZ_64K)
99 #define KVM_VGIC_V3_ITS_SIZE (2 * SZ_64K)
100
101 #define KVM_ARM_VCPU_POWER_OFF 0 /* CPU is started in OFF state */
102 #define KVM_ARM_VCPU_PSCI_0_2 1 /* CPU uses PSCI v0.2 */
103
104 struct kvm_vcpu_init {
105 __u32 target;
106 __u32 features[7];
107 };
108
109 struct kvm_sregs {
110 };
111
112 struct kvm_fpu {
113 };
114
115 struct kvm_guest_debug_arch {
116 };
117
118 struct kvm_debug_exit_arch {
119 };
120
121 struct kvm_sync_regs {
122 /* Used with KVM_CAP_ARM_USER_IRQ */
123 __u64 device_irq_level;
124 };
125
126 struct kvm_arch_memory_slot {
127 };
128
129 /* for KVM_GET/SET_VCPU_EVENTS */
130 struct kvm_vcpu_events {
131 struct {
132 __u8 serror_pending;
133 __u8 serror_has_esr;
134 __u8 ext_dabt_pending;
135 /* Align it to 8 bytes */
136 __u8 pad[5];
137 __u64 serror_esr;
138 } exception;
139 __u32 reserved[12];
140 };
141
142 /* If you need to interpret the index values, here is the key: */
143 #define KVM_REG_ARM_COPROC_MASK 0x000000000FFF0000
144 #define KVM_REG_ARM_COPROC_SHIFT 16
145 #define KVM_REG_ARM_32_OPC2_MASK 0x0000000000000007
146 #define KVM_REG_ARM_32_OPC2_SHIFT 0
147 #define KVM_REG_ARM_OPC1_MASK 0x0000000000000078
148 #define KVM_REG_ARM_OPC1_SHIFT 3
149 #define KVM_REG_ARM_CRM_MASK 0x0000000000000780
150 #define KVM_REG_ARM_CRM_SHIFT 7
151 #define KVM_REG_ARM_32_CRN_MASK 0x0000000000007800
152 #define KVM_REG_ARM_32_CRN_SHIFT 11
153 /*
154 * For KVM currently all guest registers are nonsecure, but we reserve a bit
155 * in the encoding to distinguish secure from nonsecure for AArch32 system
156 * registers that are banked by security. This is 1 for the secure banked
157 * register, and 0 for the nonsecure banked register or if the register is
158 * not banked by security.
159 */
160 #define KVM_REG_ARM_SECURE_MASK 0x0000000010000000
161 #define KVM_REG_ARM_SECURE_SHIFT 28
162
163 #define ARM_CP15_REG_SHIFT_MASK(x,n) \
164 (((x) << KVM_REG_ARM_ ## n ## _SHIFT) & KVM_REG_ARM_ ## n ## _MASK)
165
166 #define __ARM_CP15_REG(op1,crn,crm,op2) \
167 (KVM_REG_ARM | (15 << KVM_REG_ARM_COPROC_SHIFT) | \
168 ARM_CP15_REG_SHIFT_MASK(op1, OPC1) | \
169 ARM_CP15_REG_SHIFT_MASK(crn, 32_CRN) | \
170 ARM_CP15_REG_SHIFT_MASK(crm, CRM) | \
171 ARM_CP15_REG_SHIFT_MASK(op2, 32_OPC2))
172
173 #define ARM_CP15_REG32(...) (__ARM_CP15_REG(__VA_ARGS__) | KVM_REG_SIZE_U32)
174
175 #define __ARM_CP15_REG64(op1,crm) \
176 (__ARM_CP15_REG(op1, 0, crm, 0) | KVM_REG_SIZE_U64)
177 #define ARM_CP15_REG64(...) __ARM_CP15_REG64(__VA_ARGS__)
178
179 /* PL1 Physical Timer Registers */
180 #define KVM_REG_ARM_PTIMER_CTL ARM_CP15_REG32(0, 14, 2, 1)
181 #define KVM_REG_ARM_PTIMER_CNT ARM_CP15_REG64(0, 14)
182 #define KVM_REG_ARM_PTIMER_CVAL ARM_CP15_REG64(2, 14)
183
184 /* Virtual Timer Registers */
185 #define KVM_REG_ARM_TIMER_CTL ARM_CP15_REG32(0, 14, 3, 1)
186 #define KVM_REG_ARM_TIMER_CNT ARM_CP15_REG64(1, 14)
187 #define KVM_REG_ARM_TIMER_CVAL ARM_CP15_REG64(3, 14)
188
189 /* Normal registers are mapped as coprocessor 16. */
190 #define KVM_REG_ARM_CORE (0x0010 << KVM_REG_ARM_COPROC_SHIFT)
191 #define KVM_REG_ARM_CORE_REG(name) (offsetof(struct kvm_regs, name) / 4)
192
193 /* Some registers need more space to represent values. */
194 #define KVM_REG_ARM_DEMUX (0x0011 << KVM_REG_ARM_COPROC_SHIFT)
195 #define KVM_REG_ARM_DEMUX_ID_MASK 0x000000000000FF00
196 #define KVM_REG_ARM_DEMUX_ID_SHIFT 8
197 #define KVM_REG_ARM_DEMUX_ID_CCSIDR (0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT)
198 #define KVM_REG_ARM_DEMUX_VAL_MASK 0x00000000000000FF
199 #define KVM_REG_ARM_DEMUX_VAL_SHIFT 0
200
201 /* VFP registers: we could overload CP10 like ARM does, but that's ugly. */
202 #define KVM_REG_ARM_VFP (0x0012 << KVM_REG_ARM_COPROC_SHIFT)
203 #define KVM_REG_ARM_VFP_MASK 0x000000000000FFFF
204 #define KVM_REG_ARM_VFP_BASE_REG 0x0
205 #define KVM_REG_ARM_VFP_FPSID 0x1000
206 #define KVM_REG_ARM_VFP_FPSCR 0x1001
207 #define KVM_REG_ARM_VFP_MVFR1 0x1006
208 #define KVM_REG_ARM_VFP_MVFR0 0x1007
209 #define KVM_REG_ARM_VFP_FPEXC 0x1008
210 #define KVM_REG_ARM_VFP_FPINST 0x1009
211 #define KVM_REG_ARM_VFP_FPINST2 0x100A
212
213 /* KVM-as-firmware specific pseudo-registers */
214 #define KVM_REG_ARM_FW (0x0014 << KVM_REG_ARM_COPROC_SHIFT)
215 #define KVM_REG_ARM_FW_REG(r) (KVM_REG_ARM | KVM_REG_SIZE_U64 | \
216 KVM_REG_ARM_FW | ((r) & 0xffff))
217 #define KVM_REG_ARM_PSCI_VERSION KVM_REG_ARM_FW_REG(0)
218 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1 KVM_REG_ARM_FW_REG(1)
219 /* Higher values mean better protection. */
220 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_AVAIL 0
221 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_AVAIL 1
222 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_REQUIRED 2
223 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2 KVM_REG_ARM_FW_REG(2)
224 /* Higher values mean better protection. */
225 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_AVAIL 0
226 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_UNKNOWN 1
227 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_AVAIL 2
228 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_REQUIRED 3
229 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_ENABLED (1U << 4)
230
231 /* Device Control API: ARM VGIC */
232 #define KVM_DEV_ARM_VGIC_GRP_ADDR 0
233 #define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1
234 #define KVM_DEV_ARM_VGIC_GRP_CPU_REGS 2
235 #define KVM_DEV_ARM_VGIC_CPUID_SHIFT 32
236 #define KVM_DEV_ARM_VGIC_CPUID_MASK (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)
237 #define KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT 32
238 #define KVM_DEV_ARM_VGIC_V3_MPIDR_MASK \
239 (0xffffffffULL << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT)
240 #define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0
241 #define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
242 #define KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK (0xffff)
243 #define KVM_DEV_ARM_VGIC_GRP_NR_IRQS 3
244 #define KVM_DEV_ARM_VGIC_GRP_CTRL 4
245 #define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5
246 #define KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS 6
247 #define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO 7
248 #define KVM_DEV_ARM_VGIC_GRP_ITS_REGS 8
249 #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT 10
250 #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK \
251 (0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT)
252 #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK 0x3ff
253 #define VGIC_LEVEL_INFO_LINE_LEVEL 0
254
255 /* Device Control API on vcpu fd */
256 #define KVM_ARM_VCPU_PMU_V3_CTRL 0
257 #define KVM_ARM_VCPU_PMU_V3_IRQ 0
258 #define KVM_ARM_VCPU_PMU_V3_INIT 1
259 #define KVM_ARM_VCPU_TIMER_CTRL 1
260 #define KVM_ARM_VCPU_TIMER_IRQ_VTIMER 0
261 #define KVM_ARM_VCPU_TIMER_IRQ_PTIMER 1
262
263 #define KVM_DEV_ARM_VGIC_CTRL_INIT 0
264 #define KVM_DEV_ARM_ITS_SAVE_TABLES 1
265 #define KVM_DEV_ARM_ITS_RESTORE_TABLES 2
266 #define KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES 3
267 #define KVM_DEV_ARM_ITS_CTRL_RESET 4
268
269 /* KVM_IRQ_LINE irq field index values */
270 #define KVM_ARM_IRQ_VCPU2_SHIFT 28
271 #define KVM_ARM_IRQ_VCPU2_MASK 0xf
272 #define KVM_ARM_IRQ_TYPE_SHIFT 24
273 #define KVM_ARM_IRQ_TYPE_MASK 0xf
274 #define KVM_ARM_IRQ_VCPU_SHIFT 16
275 #define KVM_ARM_IRQ_VCPU_MASK 0xff
276 #define KVM_ARM_IRQ_NUM_SHIFT 0
277 #define KVM_ARM_IRQ_NUM_MASK 0xffff
278
279 /* irq_type field */
280 #define KVM_ARM_IRQ_TYPE_CPU 0
281 #define KVM_ARM_IRQ_TYPE_SPI 1
282 #define KVM_ARM_IRQ_TYPE_PPI 2
283
284 /* out-of-kernel GIC cpu interrupt injection irq_number field */
285 #define KVM_ARM_IRQ_CPU_IRQ 0
286 #define KVM_ARM_IRQ_CPU_FIQ 1
287
288 /*
289 * This used to hold the highest supported SPI, but it is now obsolete
290 * and only here to provide source code level compatibility with older
291 * userland. The highest SPI number can be set via KVM_DEV_ARM_VGIC_GRP_NR_IRQS.
292 */
293 #define KVM_ARM_IRQ_GIC_MAX 127
294
295 /* One single KVM irqchip, ie. the VGIC */
296 #define KVM_NR_IRQCHIPS 1
297
298 /* PSCI interface */
299 #define KVM_PSCI_FN_BASE 0x95c1ba5e
300 #define KVM_PSCI_FN(n) (KVM_PSCI_FN_BASE + (n))
301
302 #define KVM_PSCI_FN_CPU_SUSPEND KVM_PSCI_FN(0)
303 #define KVM_PSCI_FN_CPU_OFF KVM_PSCI_FN(1)
304 #define KVM_PSCI_FN_CPU_ON KVM_PSCI_FN(2)
305 #define KVM_PSCI_FN_MIGRATE KVM_PSCI_FN(3)
306
307 #define KVM_PSCI_RET_SUCCESS PSCI_RET_SUCCESS
308 #define KVM_PSCI_RET_NI PSCI_RET_NOT_SUPPORTED
309 #define KVM_PSCI_RET_INVAL PSCI_RET_INVALID_PARAMS
310 #define KVM_PSCI_RET_DENIED PSCI_RET_DENIED
311
312 #endif /* __ARM_KVM_H__ */