Merge remote-tracking branch 'remotes/dgilbert-gitlab/tags/pull-virtiofs-20200221...
[qemu.git] / linux-headers / asm-powerpc / kvm.h
1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2 /*
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License, version 2, as
5 * published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
15 *
16 * Copyright IBM Corp. 2007
17 *
18 * Authors: Hollis Blanchard <hollisb@us.ibm.com>
19 */
20
21 #ifndef __LINUX_KVM_POWERPC_H
22 #define __LINUX_KVM_POWERPC_H
23
24 #include <linux/types.h>
25
26 /* Select powerpc specific features in <linux/kvm.h> */
27 #define __KVM_HAVE_SPAPR_TCE
28 #define __KVM_HAVE_PPC_SMT
29 #define __KVM_HAVE_IRQCHIP
30 #define __KVM_HAVE_IRQ_LINE
31 #define __KVM_HAVE_GUEST_DEBUG
32
33 /* Not always available, but if it is, this is the correct offset. */
34 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1
35
36 struct kvm_regs {
37 __u64 pc;
38 __u64 cr;
39 __u64 ctr;
40 __u64 lr;
41 __u64 xer;
42 __u64 msr;
43 __u64 srr0;
44 __u64 srr1;
45 __u64 pid;
46
47 __u64 sprg0;
48 __u64 sprg1;
49 __u64 sprg2;
50 __u64 sprg3;
51 __u64 sprg4;
52 __u64 sprg5;
53 __u64 sprg6;
54 __u64 sprg7;
55
56 __u64 gpr[32];
57 };
58
59 #define KVM_SREGS_E_IMPL_NONE 0
60 #define KVM_SREGS_E_IMPL_FSL 1
61
62 #define KVM_SREGS_E_FSL_PIDn (1 << 0) /* PID1/PID2 */
63
64 /* flags for kvm_run.flags */
65 #define KVM_RUN_PPC_NMI_DISP_MASK (3 << 0)
66 #define KVM_RUN_PPC_NMI_DISP_FULLY_RECOV (1 << 0)
67 #define KVM_RUN_PPC_NMI_DISP_LIMITED_RECOV (2 << 0)
68 #define KVM_RUN_PPC_NMI_DISP_NOT_RECOV (3 << 0)
69
70 /*
71 * Feature bits indicate which sections of the sregs struct are valid,
72 * both in KVM_GET_SREGS and KVM_SET_SREGS. On KVM_SET_SREGS, registers
73 * corresponding to unset feature bits will not be modified. This allows
74 * restoring a checkpoint made without that feature, while keeping the
75 * default values of the new registers.
76 *
77 * KVM_SREGS_E_BASE contains:
78 * CSRR0/1 (refers to SRR2/3 on 40x)
79 * ESR
80 * DEAR
81 * MCSR
82 * TSR
83 * TCR
84 * DEC
85 * TB
86 * VRSAVE (USPRG0)
87 */
88 #define KVM_SREGS_E_BASE (1 << 0)
89
90 /*
91 * KVM_SREGS_E_ARCH206 contains:
92 *
93 * PIR
94 * MCSRR0/1
95 * DECAR
96 * IVPR
97 */
98 #define KVM_SREGS_E_ARCH206 (1 << 1)
99
100 /*
101 * Contains EPCR, plus the upper half of 64-bit registers
102 * that are 32-bit on 32-bit implementations.
103 */
104 #define KVM_SREGS_E_64 (1 << 2)
105
106 #define KVM_SREGS_E_SPRG8 (1 << 3)
107 #define KVM_SREGS_E_MCIVPR (1 << 4)
108
109 /*
110 * IVORs are used -- contains IVOR0-15, plus additional IVORs
111 * in combination with an appropriate feature bit.
112 */
113 #define KVM_SREGS_E_IVOR (1 << 5)
114
115 /*
116 * Contains MAS0-4, MAS6-7, TLBnCFG, MMUCFG.
117 * Also TLBnPS if MMUCFG[MAVN] = 1.
118 */
119 #define KVM_SREGS_E_ARCH206_MMU (1 << 6)
120
121 /* DBSR, DBCR, IAC, DAC, DVC */
122 #define KVM_SREGS_E_DEBUG (1 << 7)
123
124 /* Enhanced debug -- DSRR0/1, SPRG9 */
125 #define KVM_SREGS_E_ED (1 << 8)
126
127 /* Embedded Floating Point (SPE) -- IVOR32-34 if KVM_SREGS_E_IVOR */
128 #define KVM_SREGS_E_SPE (1 << 9)
129
130 /*
131 * DEPRECATED! USE ONE_REG FOR THIS ONE!
132 * External Proxy (EXP) -- EPR
133 */
134 #define KVM_SREGS_EXP (1 << 10)
135
136 /* External PID (E.PD) -- EPSC/EPLC */
137 #define KVM_SREGS_E_PD (1 << 11)
138
139 /* Processor Control (E.PC) -- IVOR36-37 if KVM_SREGS_E_IVOR */
140 #define KVM_SREGS_E_PC (1 << 12)
141
142 /* Page table (E.PT) -- EPTCFG */
143 #define KVM_SREGS_E_PT (1 << 13)
144
145 /* Embedded Performance Monitor (E.PM) -- IVOR35 if KVM_SREGS_E_IVOR */
146 #define KVM_SREGS_E_PM (1 << 14)
147
148 /*
149 * Special updates:
150 *
151 * Some registers may change even while a vcpu is not running.
152 * To avoid losing these changes, by default these registers are
153 * not updated by KVM_SET_SREGS. To force an update, set the bit
154 * in u.e.update_special corresponding to the register to be updated.
155 *
156 * The update_special field is zero on return from KVM_GET_SREGS.
157 *
158 * When restoring a checkpoint, the caller can set update_special
159 * to 0xffffffff to ensure that everything is restored, even new features
160 * that the caller doesn't know about.
161 */
162 #define KVM_SREGS_E_UPDATE_MCSR (1 << 0)
163 #define KVM_SREGS_E_UPDATE_TSR (1 << 1)
164 #define KVM_SREGS_E_UPDATE_DEC (1 << 2)
165 #define KVM_SREGS_E_UPDATE_DBSR (1 << 3)
166
167 /*
168 * In KVM_SET_SREGS, reserved/pad fields must be left untouched from a
169 * previous KVM_GET_REGS.
170 *
171 * Unless otherwise indicated, setting any register with KVM_SET_SREGS
172 * directly sets its value. It does not trigger any special semantics such
173 * as write-one-to-clear. Calling KVM_SET_SREGS on an unmodified struct
174 * just received from KVM_GET_SREGS is always a no-op.
175 */
176 struct kvm_sregs {
177 __u32 pvr;
178 union {
179 struct {
180 __u64 sdr1;
181 struct {
182 struct {
183 __u64 slbe;
184 __u64 slbv;
185 } slb[64];
186 } ppc64;
187 struct {
188 __u32 sr[16];
189 __u64 ibat[8];
190 __u64 dbat[8];
191 } ppc32;
192 } s;
193 struct {
194 union {
195 struct { /* KVM_SREGS_E_IMPL_FSL */
196 __u32 features; /* KVM_SREGS_E_FSL_ */
197 __u32 svr;
198 __u64 mcar;
199 __u32 hid0;
200
201 /* KVM_SREGS_E_FSL_PIDn */
202 __u32 pid1, pid2;
203 } fsl;
204 __u8 pad[256];
205 } impl;
206
207 __u32 features; /* KVM_SREGS_E_ */
208 __u32 impl_id; /* KVM_SREGS_E_IMPL_ */
209 __u32 update_special; /* KVM_SREGS_E_UPDATE_ */
210 __u32 pir; /* read-only */
211 __u64 sprg8;
212 __u64 sprg9; /* E.ED */
213 __u64 csrr0;
214 __u64 dsrr0; /* E.ED */
215 __u64 mcsrr0;
216 __u32 csrr1;
217 __u32 dsrr1; /* E.ED */
218 __u32 mcsrr1;
219 __u32 esr;
220 __u64 dear;
221 __u64 ivpr;
222 __u64 mcivpr;
223 __u64 mcsr; /* KVM_SREGS_E_UPDATE_MCSR */
224
225 __u32 tsr; /* KVM_SREGS_E_UPDATE_TSR */
226 __u32 tcr;
227 __u32 decar;
228 __u32 dec; /* KVM_SREGS_E_UPDATE_DEC */
229
230 /*
231 * Userspace can read TB directly, but the
232 * value reported here is consistent with "dec".
233 *
234 * Read-only.
235 */
236 __u64 tb;
237
238 __u32 dbsr; /* KVM_SREGS_E_UPDATE_DBSR */
239 __u32 dbcr[3];
240 /*
241 * iac/dac registers are 64bit wide, while this API
242 * interface provides only lower 32 bits on 64 bit
243 * processors. ONE_REG interface is added for 64bit
244 * iac/dac registers.
245 */
246 __u32 iac[4];
247 __u32 dac[2];
248 __u32 dvc[2];
249 __u8 num_iac; /* read-only */
250 __u8 num_dac; /* read-only */
251 __u8 num_dvc; /* read-only */
252 __u8 pad;
253
254 __u32 epr; /* EXP */
255 __u32 vrsave; /* a.k.a. USPRG0 */
256 __u32 epcr; /* KVM_SREGS_E_64 */
257
258 __u32 mas0;
259 __u32 mas1;
260 __u64 mas2;
261 __u64 mas7_3;
262 __u32 mas4;
263 __u32 mas6;
264
265 __u32 ivor_low[16]; /* IVOR0-15 */
266 __u32 ivor_high[18]; /* IVOR32+, plus room to expand */
267
268 __u32 mmucfg; /* read-only */
269 __u32 eptcfg; /* E.PT, read-only */
270 __u32 tlbcfg[4];/* read-only */
271 __u32 tlbps[4]; /* read-only */
272
273 __u32 eplc, epsc; /* E.PD */
274 } e;
275 __u8 pad[1020];
276 } u;
277 };
278
279 struct kvm_fpu {
280 __u64 fpr[32];
281 };
282
283 /*
284 * Defines for h/w breakpoint, watchpoint (read, write or both) and
285 * software breakpoint.
286 * These are used as "type" in KVM_SET_GUEST_DEBUG ioctl and "status"
287 * for KVM_DEBUG_EXIT.
288 */
289 #define KVMPPC_DEBUG_NONE 0x0
290 #define KVMPPC_DEBUG_BREAKPOINT (1UL << 1)
291 #define KVMPPC_DEBUG_WATCH_WRITE (1UL << 2)
292 #define KVMPPC_DEBUG_WATCH_READ (1UL << 3)
293 struct kvm_debug_exit_arch {
294 __u64 address;
295 /*
296 * exiting to userspace because of h/w breakpoint, watchpoint
297 * (read, write or both) and software breakpoint.
298 */
299 __u32 status;
300 __u32 reserved;
301 };
302
303 /* for KVM_SET_GUEST_DEBUG */
304 struct kvm_guest_debug_arch {
305 struct {
306 /* H/W breakpoint/watchpoint address */
307 __u64 addr;
308 /*
309 * Type denotes h/w breakpoint, read watchpoint, write
310 * watchpoint or watchpoint (both read and write).
311 */
312 __u32 type;
313 __u32 reserved;
314 } bp[16];
315 };
316
317 /* Debug related defines */
318 /*
319 * kvm_guest_debug->control is a 32 bit field. The lower 16 bits are generic
320 * and upper 16 bits are architecture specific. Architecture specific defines
321 * that ioctl is for setting hardware breakpoint or software breakpoint.
322 */
323 #define KVM_GUESTDBG_USE_SW_BP 0x00010000
324 #define KVM_GUESTDBG_USE_HW_BP 0x00020000
325
326 /* definition of registers in kvm_run */
327 struct kvm_sync_regs {
328 };
329
330 #define KVM_INTERRUPT_SET -1U
331 #define KVM_INTERRUPT_UNSET -2U
332 #define KVM_INTERRUPT_SET_LEVEL -3U
333
334 #define KVM_CPU_440 1
335 #define KVM_CPU_E500V2 2
336 #define KVM_CPU_3S_32 3
337 #define KVM_CPU_3S_64 4
338 #define KVM_CPU_E500MC 5
339
340 /* for KVM_CAP_SPAPR_TCE */
341 struct kvm_create_spapr_tce {
342 __u64 liobn;
343 __u32 window_size;
344 };
345
346 /* for KVM_CAP_SPAPR_TCE_64 */
347 struct kvm_create_spapr_tce_64 {
348 __u64 liobn;
349 __u32 page_shift;
350 __u32 flags;
351 __u64 offset; /* in pages */
352 __u64 size; /* in pages */
353 };
354
355 /* for KVM_ALLOCATE_RMA */
356 struct kvm_allocate_rma {
357 __u64 rma_size;
358 };
359
360 /* for KVM_CAP_PPC_RTAS */
361 struct kvm_rtas_token_args {
362 char name[120];
363 __u64 token; /* Use a token of 0 to undefine a mapping */
364 };
365
366 struct kvm_book3e_206_tlb_entry {
367 __u32 mas8;
368 __u32 mas1;
369 __u64 mas2;
370 __u64 mas7_3;
371 };
372
373 struct kvm_book3e_206_tlb_params {
374 /*
375 * For mmu types KVM_MMU_FSL_BOOKE_NOHV and KVM_MMU_FSL_BOOKE_HV:
376 *
377 * - The number of ways of TLB0 must be a power of two between 2 and
378 * 16.
379 * - TLB1 must be fully associative.
380 * - The size of TLB0 must be a multiple of the number of ways, and
381 * the number of sets must be a power of two.
382 * - The size of TLB1 may not exceed 64 entries.
383 * - TLB0 supports 4 KiB pages.
384 * - The page sizes supported by TLB1 are as indicated by
385 * TLB1CFG (if MMUCFG[MAVN] = 0) or TLB1PS (if MMUCFG[MAVN] = 1)
386 * as returned by KVM_GET_SREGS.
387 * - TLB2 and TLB3 are reserved, and their entries in tlb_sizes[]
388 * and tlb_ways[] must be zero.
389 *
390 * tlb_ways[n] = tlb_sizes[n] means the array is fully associative.
391 *
392 * KVM will adjust TLBnCFG based on the sizes configured here,
393 * though arrays greater than 2048 entries will have TLBnCFG[NENTRY]
394 * set to zero.
395 */
396 __u32 tlb_sizes[4];
397 __u32 tlb_ways[4];
398 __u32 reserved[8];
399 };
400
401 /* For KVM_PPC_GET_HTAB_FD */
402 struct kvm_get_htab_fd {
403 __u64 flags;
404 __u64 start_index;
405 __u64 reserved[2];
406 };
407
408 /* Values for kvm_get_htab_fd.flags */
409 #define KVM_GET_HTAB_BOLTED_ONLY ((__u64)0x1)
410 #define KVM_GET_HTAB_WRITE ((__u64)0x2)
411
412 /*
413 * Data read on the file descriptor is formatted as a series of
414 * records, each consisting of a header followed by a series of
415 * `n_valid' HPTEs (16 bytes each), which are all valid. Following
416 * those valid HPTEs there are `n_invalid' invalid HPTEs, which
417 * are not represented explicitly in the stream. The same format
418 * is used for writing.
419 */
420 struct kvm_get_htab_header {
421 __u32 index;
422 __u16 n_valid;
423 __u16 n_invalid;
424 };
425
426 /* For KVM_PPC_CONFIGURE_V3_MMU */
427 struct kvm_ppc_mmuv3_cfg {
428 __u64 flags;
429 __u64 process_table; /* second doubleword of partition table entry */
430 };
431
432 /* Flag values for KVM_PPC_CONFIGURE_V3_MMU */
433 #define KVM_PPC_MMUV3_RADIX 1 /* 1 = radix mode, 0 = HPT */
434 #define KVM_PPC_MMUV3_GTSE 2 /* global translation shootdown enb. */
435
436 /* For KVM_PPC_GET_RMMU_INFO */
437 struct kvm_ppc_rmmu_info {
438 struct kvm_ppc_radix_geom {
439 __u8 page_shift;
440 __u8 level_bits[4];
441 __u8 pad[3];
442 } geometries[8];
443 __u32 ap_encodings[8];
444 };
445
446 /* For KVM_PPC_GET_CPU_CHAR */
447 struct kvm_ppc_cpu_char {
448 __u64 character; /* characteristics of the CPU */
449 __u64 behaviour; /* recommended software behaviour */
450 __u64 character_mask; /* valid bits in character */
451 __u64 behaviour_mask; /* valid bits in behaviour */
452 };
453
454 /*
455 * Values for character and character_mask.
456 * These are identical to the values used by H_GET_CPU_CHARACTERISTICS.
457 */
458 #define KVM_PPC_CPU_CHAR_SPEC_BAR_ORI31 (1ULL << 63)
459 #define KVM_PPC_CPU_CHAR_BCCTRL_SERIALISED (1ULL << 62)
460 #define KVM_PPC_CPU_CHAR_L1D_FLUSH_ORI30 (1ULL << 61)
461 #define KVM_PPC_CPU_CHAR_L1D_FLUSH_TRIG2 (1ULL << 60)
462 #define KVM_PPC_CPU_CHAR_L1D_THREAD_PRIV (1ULL << 59)
463 #define KVM_PPC_CPU_CHAR_BR_HINT_HONOURED (1ULL << 58)
464 #define KVM_PPC_CPU_CHAR_MTTRIG_THR_RECONF (1ULL << 57)
465 #define KVM_PPC_CPU_CHAR_COUNT_CACHE_DIS (1ULL << 56)
466 #define KVM_PPC_CPU_CHAR_BCCTR_FLUSH_ASSIST (1ull << 54)
467
468 #define KVM_PPC_CPU_BEHAV_FAVOUR_SECURITY (1ULL << 63)
469 #define KVM_PPC_CPU_BEHAV_L1D_FLUSH_PR (1ULL << 62)
470 #define KVM_PPC_CPU_BEHAV_BNDS_CHK_SPEC_BAR (1ULL << 61)
471 #define KVM_PPC_CPU_BEHAV_FLUSH_COUNT_CACHE (1ull << 58)
472
473 /* Per-vcpu XICS interrupt controller state */
474 #define KVM_REG_PPC_ICP_STATE (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8c)
475
476 #define KVM_REG_PPC_ICP_CPPR_SHIFT 56 /* current proc priority */
477 #define KVM_REG_PPC_ICP_CPPR_MASK 0xff
478 #define KVM_REG_PPC_ICP_XISR_SHIFT 32 /* interrupt status field */
479 #define KVM_REG_PPC_ICP_XISR_MASK 0xffffff
480 #define KVM_REG_PPC_ICP_MFRR_SHIFT 24 /* pending IPI priority */
481 #define KVM_REG_PPC_ICP_MFRR_MASK 0xff
482 #define KVM_REG_PPC_ICP_PPRI_SHIFT 16 /* pending irq priority */
483 #define KVM_REG_PPC_ICP_PPRI_MASK 0xff
484
485 #define KVM_REG_PPC_VP_STATE (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x8d)
486
487 /* Device control API: PPC-specific devices */
488 #define KVM_DEV_MPIC_GRP_MISC 1
489 #define KVM_DEV_MPIC_BASE_ADDR 0 /* 64-bit */
490
491 #define KVM_DEV_MPIC_GRP_REGISTER 2 /* 32-bit */
492 #define KVM_DEV_MPIC_GRP_IRQ_ACTIVE 3 /* 32-bit */
493
494 /* One-Reg API: PPC-specific registers */
495 #define KVM_REG_PPC_HIOR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x1)
496 #define KVM_REG_PPC_IAC1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x2)
497 #define KVM_REG_PPC_IAC2 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x3)
498 #define KVM_REG_PPC_IAC3 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x4)
499 #define KVM_REG_PPC_IAC4 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x5)
500 #define KVM_REG_PPC_DAC1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x6)
501 #define KVM_REG_PPC_DAC2 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x7)
502 #define KVM_REG_PPC_DABR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8)
503 #define KVM_REG_PPC_DSCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x9)
504 #define KVM_REG_PPC_PURR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa)
505 #define KVM_REG_PPC_SPURR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb)
506 #define KVM_REG_PPC_DAR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc)
507 #define KVM_REG_PPC_DSISR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xd)
508 #define KVM_REG_PPC_AMR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xe)
509 #define KVM_REG_PPC_UAMOR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xf)
510
511 #define KVM_REG_PPC_MMCR0 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x10)
512 #define KVM_REG_PPC_MMCR1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x11)
513 #define KVM_REG_PPC_MMCRA (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x12)
514 #define KVM_REG_PPC_MMCR2 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x13)
515 #define KVM_REG_PPC_MMCRS (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x14)
516 #define KVM_REG_PPC_SIAR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x15)
517 #define KVM_REG_PPC_SDAR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x16)
518 #define KVM_REG_PPC_SIER (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x17)
519
520 #define KVM_REG_PPC_PMC1 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x18)
521 #define KVM_REG_PPC_PMC2 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x19)
522 #define KVM_REG_PPC_PMC3 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1a)
523 #define KVM_REG_PPC_PMC4 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1b)
524 #define KVM_REG_PPC_PMC5 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1c)
525 #define KVM_REG_PPC_PMC6 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1d)
526 #define KVM_REG_PPC_PMC7 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1e)
527 #define KVM_REG_PPC_PMC8 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1f)
528
529 /* 32 floating-point registers */
530 #define KVM_REG_PPC_FPR0 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x20)
531 #define KVM_REG_PPC_FPR(n) (KVM_REG_PPC_FPR0 + (n))
532 #define KVM_REG_PPC_FPR31 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x3f)
533
534 /* 32 VMX/Altivec vector registers */
535 #define KVM_REG_PPC_VR0 (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x40)
536 #define KVM_REG_PPC_VR(n) (KVM_REG_PPC_VR0 + (n))
537 #define KVM_REG_PPC_VR31 (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x5f)
538
539 /* 32 double-width FP registers for VSX */
540 /* High-order halves overlap with FP regs */
541 #define KVM_REG_PPC_VSR0 (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x60)
542 #define KVM_REG_PPC_VSR(n) (KVM_REG_PPC_VSR0 + (n))
543 #define KVM_REG_PPC_VSR31 (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x7f)
544
545 /* FP and vector status/control registers */
546 #define KVM_REG_PPC_FPSCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x80)
547 /*
548 * VSCR register is documented as a 32-bit register in the ISA, but it can
549 * only be accesses via a vector register. Expose VSCR as a 32-bit register
550 * even though the kernel represents it as a 128-bit vector.
551 */
552 #define KVM_REG_PPC_VSCR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x81)
553
554 /* Virtual processor areas */
555 /* For SLB & DTL, address in high (first) half, length in low half */
556 #define KVM_REG_PPC_VPA_ADDR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x82)
557 #define KVM_REG_PPC_VPA_SLB (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x83)
558 #define KVM_REG_PPC_VPA_DTL (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x84)
559
560 #define KVM_REG_PPC_EPCR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x85)
561 #define KVM_REG_PPC_EPR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x86)
562
563 /* Timer Status Register OR/CLEAR interface */
564 #define KVM_REG_PPC_OR_TSR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x87)
565 #define KVM_REG_PPC_CLEAR_TSR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x88)
566 #define KVM_REG_PPC_TCR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x89)
567 #define KVM_REG_PPC_TSR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x8a)
568
569 /* Debugging: Special instruction for software breakpoint */
570 #define KVM_REG_PPC_DEBUG_INST (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x8b)
571
572 /* MMU registers */
573 #define KVM_REG_PPC_MAS0 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x8c)
574 #define KVM_REG_PPC_MAS1 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x8d)
575 #define KVM_REG_PPC_MAS2 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8e)
576 #define KVM_REG_PPC_MAS7_3 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8f)
577 #define KVM_REG_PPC_MAS4 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x90)
578 #define KVM_REG_PPC_MAS6 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x91)
579 #define KVM_REG_PPC_MMUCFG (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x92)
580 /*
581 * TLBnCFG fields TLBnCFG_N_ENTRY and TLBnCFG_ASSOC can be changed only using
582 * KVM_CAP_SW_TLB ioctl
583 */
584 #define KVM_REG_PPC_TLB0CFG (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x93)
585 #define KVM_REG_PPC_TLB1CFG (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x94)
586 #define KVM_REG_PPC_TLB2CFG (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x95)
587 #define KVM_REG_PPC_TLB3CFG (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x96)
588 #define KVM_REG_PPC_TLB0PS (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x97)
589 #define KVM_REG_PPC_TLB1PS (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x98)
590 #define KVM_REG_PPC_TLB2PS (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x99)
591 #define KVM_REG_PPC_TLB3PS (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x9a)
592 #define KVM_REG_PPC_EPTCFG (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x9b)
593
594 /* Timebase offset */
595 #define KVM_REG_PPC_TB_OFFSET (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x9c)
596
597 /* POWER8 registers */
598 #define KVM_REG_PPC_SPMC1 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x9d)
599 #define KVM_REG_PPC_SPMC2 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x9e)
600 #define KVM_REG_PPC_IAMR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x9f)
601 #define KVM_REG_PPC_TFHAR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa0)
602 #define KVM_REG_PPC_TFIAR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa1)
603 #define KVM_REG_PPC_TEXASR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa2)
604 #define KVM_REG_PPC_FSCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa3)
605 #define KVM_REG_PPC_PSPB (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xa4)
606 #define KVM_REG_PPC_EBBHR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa5)
607 #define KVM_REG_PPC_EBBRR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa6)
608 #define KVM_REG_PPC_BESCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa7)
609 #define KVM_REG_PPC_TAR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa8)
610 #define KVM_REG_PPC_DPDES (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa9)
611 #define KVM_REG_PPC_DAWR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xaa)
612 #define KVM_REG_PPC_DAWRX (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xab)
613 #define KVM_REG_PPC_CIABR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xac)
614 #define KVM_REG_PPC_IC (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xad)
615 #define KVM_REG_PPC_VTB (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xae)
616 #define KVM_REG_PPC_CSIGR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xaf)
617 #define KVM_REG_PPC_TACR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb0)
618 #define KVM_REG_PPC_TCSCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb1)
619 #define KVM_REG_PPC_PID (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb2)
620 #define KVM_REG_PPC_ACOP (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb3)
621
622 #define KVM_REG_PPC_VRSAVE (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xb4)
623 #define KVM_REG_PPC_LPCR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xb5)
624 #define KVM_REG_PPC_LPCR_64 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb5)
625 #define KVM_REG_PPC_PPR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb6)
626
627 /* Architecture compatibility level */
628 #define KVM_REG_PPC_ARCH_COMPAT (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xb7)
629
630 #define KVM_REG_PPC_DABRX (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xb8)
631 #define KVM_REG_PPC_WORT (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb9)
632 #define KVM_REG_PPC_SPRG9 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xba)
633 #define KVM_REG_PPC_DBSR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xbb)
634
635 /* POWER9 registers */
636 #define KVM_REG_PPC_TIDR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xbc)
637 #define KVM_REG_PPC_PSSCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xbd)
638
639 #define KVM_REG_PPC_DEC_EXPIRY (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xbe)
640 #define KVM_REG_PPC_ONLINE (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xbf)
641 #define KVM_REG_PPC_PTCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc0)
642
643 /* Transactional Memory checkpointed state:
644 * This is all GPRs, all VSX regs and a subset of SPRs
645 */
646 #define KVM_REG_PPC_TM (KVM_REG_PPC | 0x80000000)
647 /* TM GPRs */
648 #define KVM_REG_PPC_TM_GPR0 (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0)
649 #define KVM_REG_PPC_TM_GPR(n) (KVM_REG_PPC_TM_GPR0 + (n))
650 #define KVM_REG_PPC_TM_GPR31 (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x1f)
651 /* TM VSX */
652 #define KVM_REG_PPC_TM_VSR0 (KVM_REG_PPC_TM | KVM_REG_SIZE_U128 | 0x20)
653 #define KVM_REG_PPC_TM_VSR(n) (KVM_REG_PPC_TM_VSR0 + (n))
654 #define KVM_REG_PPC_TM_VSR63 (KVM_REG_PPC_TM | KVM_REG_SIZE_U128 | 0x5f)
655 /* TM SPRS */
656 #define KVM_REG_PPC_TM_CR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x60)
657 #define KVM_REG_PPC_TM_LR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x61)
658 #define KVM_REG_PPC_TM_CTR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x62)
659 #define KVM_REG_PPC_TM_FPSCR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x63)
660 #define KVM_REG_PPC_TM_AMR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x64)
661 #define KVM_REG_PPC_TM_PPR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x65)
662 #define KVM_REG_PPC_TM_VRSAVE (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x66)
663 #define KVM_REG_PPC_TM_VSCR (KVM_REG_PPC_TM | KVM_REG_SIZE_U32 | 0x67)
664 #define KVM_REG_PPC_TM_DSCR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x68)
665 #define KVM_REG_PPC_TM_TAR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x69)
666 #define KVM_REG_PPC_TM_XER (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x6a)
667
668 /* PPC64 eXternal Interrupt Controller Specification */
669 #define KVM_DEV_XICS_GRP_SOURCES 1 /* 64-bit source attributes */
670 #define KVM_DEV_XICS_GRP_CTRL 2
671 #define KVM_DEV_XICS_NR_SERVERS 1
672
673 /* Layout of 64-bit source attribute values */
674 #define KVM_XICS_DESTINATION_SHIFT 0
675 #define KVM_XICS_DESTINATION_MASK 0xffffffffULL
676 #define KVM_XICS_PRIORITY_SHIFT 32
677 #define KVM_XICS_PRIORITY_MASK 0xff
678 #define KVM_XICS_LEVEL_SENSITIVE (1ULL << 40)
679 #define KVM_XICS_MASKED (1ULL << 41)
680 #define KVM_XICS_PENDING (1ULL << 42)
681 #define KVM_XICS_PRESENTED (1ULL << 43)
682 #define KVM_XICS_QUEUED (1ULL << 44)
683
684 /* POWER9 XIVE Native Interrupt Controller */
685 #define KVM_DEV_XIVE_GRP_CTRL 1
686 #define KVM_DEV_XIVE_RESET 1
687 #define KVM_DEV_XIVE_EQ_SYNC 2
688 #define KVM_DEV_XIVE_NR_SERVERS 3
689 #define KVM_DEV_XIVE_GRP_SOURCE 2 /* 64-bit source identifier */
690 #define KVM_DEV_XIVE_GRP_SOURCE_CONFIG 3 /* 64-bit source identifier */
691 #define KVM_DEV_XIVE_GRP_EQ_CONFIG 4 /* 64-bit EQ identifier */
692 #define KVM_DEV_XIVE_GRP_SOURCE_SYNC 5 /* 64-bit source identifier */
693
694 /* Layout of 64-bit XIVE source attribute values */
695 #define KVM_XIVE_LEVEL_SENSITIVE (1ULL << 0)
696 #define KVM_XIVE_LEVEL_ASSERTED (1ULL << 1)
697
698 /* Layout of 64-bit XIVE source configuration attribute values */
699 #define KVM_XIVE_SOURCE_PRIORITY_SHIFT 0
700 #define KVM_XIVE_SOURCE_PRIORITY_MASK 0x7
701 #define KVM_XIVE_SOURCE_SERVER_SHIFT 3
702 #define KVM_XIVE_SOURCE_SERVER_MASK 0xfffffff8ULL
703 #define KVM_XIVE_SOURCE_MASKED_SHIFT 32
704 #define KVM_XIVE_SOURCE_MASKED_MASK 0x100000000ULL
705 #define KVM_XIVE_SOURCE_EISN_SHIFT 33
706 #define KVM_XIVE_SOURCE_EISN_MASK 0xfffffffe00000000ULL
707
708 /* Layout of 64-bit EQ identifier */
709 #define KVM_XIVE_EQ_PRIORITY_SHIFT 0
710 #define KVM_XIVE_EQ_PRIORITY_MASK 0x7
711 #define KVM_XIVE_EQ_SERVER_SHIFT 3
712 #define KVM_XIVE_EQ_SERVER_MASK 0xfffffff8ULL
713
714 /* Layout of EQ configuration values (64 bytes) */
715 struct kvm_ppc_xive_eq {
716 __u32 flags;
717 __u32 qshift;
718 __u64 qaddr;
719 __u32 qtoggle;
720 __u32 qindex;
721 __u8 pad[40];
722 };
723
724 #define KVM_XIVE_EQ_ALWAYS_NOTIFY 0x00000001
725
726 #define KVM_XIVE_TIMA_PAGE_OFFSET 0
727 #define KVM_XIVE_ESB_PAGE_OFFSET 4
728
729 #endif /* __LINUX_KVM_POWERPC_H */