Update VERSION for v7.2.0-rc3
[qemu.git] / linux-headers / asm-riscv / kvm.h
1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2 /*
3 * Copyright (C) 2019 Western Digital Corporation or its affiliates.
4 *
5 * Authors:
6 * Anup Patel <anup.patel@wdc.com>
7 */
8
9 #ifndef __LINUX_KVM_RISCV_H
10 #define __LINUX_KVM_RISCV_H
11
12 #ifndef __ASSEMBLY__
13
14 #include <linux/types.h>
15 #include <asm/ptrace.h>
16
17 #define __KVM_HAVE_READONLY_MEM
18
19 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1
20
21 #define KVM_INTERRUPT_SET -1U
22 #define KVM_INTERRUPT_UNSET -2U
23
24 /* for KVM_GET_REGS and KVM_SET_REGS */
25 struct kvm_regs {
26 };
27
28 /* for KVM_GET_FPU and KVM_SET_FPU */
29 struct kvm_fpu {
30 };
31
32 /* KVM Debug exit structure */
33 struct kvm_debug_exit_arch {
34 };
35
36 /* for KVM_SET_GUEST_DEBUG */
37 struct kvm_guest_debug_arch {
38 };
39
40 /* definition of registers in kvm_run */
41 struct kvm_sync_regs {
42 };
43
44 /* for KVM_GET_SREGS and KVM_SET_SREGS */
45 struct kvm_sregs {
46 };
47
48 /* CONFIG registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
49 struct kvm_riscv_config {
50 unsigned long isa;
51 };
52
53 /* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
54 struct kvm_riscv_core {
55 struct user_regs_struct regs;
56 unsigned long mode;
57 };
58
59 /* Possible privilege modes for kvm_riscv_core */
60 #define KVM_RISCV_MODE_S 1
61 #define KVM_RISCV_MODE_U 0
62
63 /* CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
64 struct kvm_riscv_csr {
65 unsigned long sstatus;
66 unsigned long sie;
67 unsigned long stvec;
68 unsigned long sscratch;
69 unsigned long sepc;
70 unsigned long scause;
71 unsigned long stval;
72 unsigned long sip;
73 unsigned long satp;
74 unsigned long scounteren;
75 };
76
77 /* TIMER registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
78 struct kvm_riscv_timer {
79 __u64 frequency;
80 __u64 time;
81 __u64 compare;
82 __u64 state;
83 };
84
85 /* Possible states for kvm_riscv_timer */
86 #define KVM_RISCV_TIMER_STATE_OFF 0
87 #define KVM_RISCV_TIMER_STATE_ON 1
88
89 #define KVM_REG_SIZE(id) \
90 (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
91
92 /* If you need to interpret the index values, here is the key: */
93 #define KVM_REG_RISCV_TYPE_MASK 0x00000000FF000000
94 #define KVM_REG_RISCV_TYPE_SHIFT 24
95
96 /* Config registers are mapped as type 1 */
97 #define KVM_REG_RISCV_CONFIG (0x01 << KVM_REG_RISCV_TYPE_SHIFT)
98 #define KVM_REG_RISCV_CONFIG_REG(name) \
99 (offsetof(struct kvm_riscv_config, name) / sizeof(unsigned long))
100
101 /* Core registers are mapped as type 2 */
102 #define KVM_REG_RISCV_CORE (0x02 << KVM_REG_RISCV_TYPE_SHIFT)
103 #define KVM_REG_RISCV_CORE_REG(name) \
104 (offsetof(struct kvm_riscv_core, name) / sizeof(unsigned long))
105
106 /* Control and status registers are mapped as type 3 */
107 #define KVM_REG_RISCV_CSR (0x03 << KVM_REG_RISCV_TYPE_SHIFT)
108 #define KVM_REG_RISCV_CSR_REG(name) \
109 (offsetof(struct kvm_riscv_csr, name) / sizeof(unsigned long))
110
111 /* Timer registers are mapped as type 4 */
112 #define KVM_REG_RISCV_TIMER (0x04 << KVM_REG_RISCV_TYPE_SHIFT)
113 #define KVM_REG_RISCV_TIMER_REG(name) \
114 (offsetof(struct kvm_riscv_timer, name) / sizeof(__u64))
115
116 /* F extension registers are mapped as type 5 */
117 #define KVM_REG_RISCV_FP_F (0x05 << KVM_REG_RISCV_TYPE_SHIFT)
118 #define KVM_REG_RISCV_FP_F_REG(name) \
119 (offsetof(struct __riscv_f_ext_state, name) / sizeof(__u32))
120
121 /* D extension registers are mapped as type 6 */
122 #define KVM_REG_RISCV_FP_D (0x06 << KVM_REG_RISCV_TYPE_SHIFT)
123 #define KVM_REG_RISCV_FP_D_REG(name) \
124 (offsetof(struct __riscv_d_ext_state, name) / sizeof(__u64))
125
126 #endif
127
128 #endif /* __LINUX_KVM_RISCV_H */