qdev: remove baked in notion of aliases (v2)
[qemu.git] / linux-headers / asm-x86 / kvm.h
1 #ifndef _ASM_X86_KVM_H
2 #define _ASM_X86_KVM_H
3
4 /*
5 * KVM x86 specific structures and definitions
6 *
7 */
8
9 #include <linux/types.h>
10 #include <linux/ioctl.h>
11
12 /* Select x86 specific features in <linux/kvm.h> */
13 #define __KVM_HAVE_PIT
14 #define __KVM_HAVE_IOAPIC
15 #define __KVM_HAVE_DEVICE_ASSIGNMENT
16 #define __KVM_HAVE_MSI
17 #define __KVM_HAVE_USER_NMI
18 #define __KVM_HAVE_GUEST_DEBUG
19 #define __KVM_HAVE_MSIX
20 #define __KVM_HAVE_MCE
21 #define __KVM_HAVE_PIT_STATE2
22 #define __KVM_HAVE_XEN_HVM
23 #define __KVM_HAVE_VCPU_EVENTS
24 #define __KVM_HAVE_DEBUGREGS
25 #define __KVM_HAVE_XSAVE
26 #define __KVM_HAVE_XCRS
27
28 /* Architectural interrupt line count. */
29 #define KVM_NR_INTERRUPTS 256
30
31 struct kvm_memory_alias {
32 __u32 slot; /* this has a different namespace than memory slots */
33 __u32 flags;
34 __u64 guest_phys_addr;
35 __u64 memory_size;
36 __u64 target_phys_addr;
37 };
38
39 /* for KVM_GET_IRQCHIP and KVM_SET_IRQCHIP */
40 struct kvm_pic_state {
41 __u8 last_irr; /* edge detection */
42 __u8 irr; /* interrupt request register */
43 __u8 imr; /* interrupt mask register */
44 __u8 isr; /* interrupt service register */
45 __u8 priority_add; /* highest irq priority */
46 __u8 irq_base;
47 __u8 read_reg_select;
48 __u8 poll;
49 __u8 special_mask;
50 __u8 init_state;
51 __u8 auto_eoi;
52 __u8 rotate_on_auto_eoi;
53 __u8 special_fully_nested_mode;
54 __u8 init4; /* true if 4 byte init */
55 __u8 elcr; /* PIIX edge/trigger selection */
56 __u8 elcr_mask;
57 };
58
59 #define KVM_IOAPIC_NUM_PINS 24
60 struct kvm_ioapic_state {
61 __u64 base_address;
62 __u32 ioregsel;
63 __u32 id;
64 __u32 irr;
65 __u32 pad;
66 union {
67 __u64 bits;
68 struct {
69 __u8 vector;
70 __u8 delivery_mode:3;
71 __u8 dest_mode:1;
72 __u8 delivery_status:1;
73 __u8 polarity:1;
74 __u8 remote_irr:1;
75 __u8 trig_mode:1;
76 __u8 mask:1;
77 __u8 reserve:7;
78 __u8 reserved[4];
79 __u8 dest_id;
80 } fields;
81 } redirtbl[KVM_IOAPIC_NUM_PINS];
82 };
83
84 #define KVM_IRQCHIP_PIC_MASTER 0
85 #define KVM_IRQCHIP_PIC_SLAVE 1
86 #define KVM_IRQCHIP_IOAPIC 2
87 #define KVM_NR_IRQCHIPS 3
88
89 /* for KVM_GET_REGS and KVM_SET_REGS */
90 struct kvm_regs {
91 /* out (KVM_GET_REGS) / in (KVM_SET_REGS) */
92 __u64 rax, rbx, rcx, rdx;
93 __u64 rsi, rdi, rsp, rbp;
94 __u64 r8, r9, r10, r11;
95 __u64 r12, r13, r14, r15;
96 __u64 rip, rflags;
97 };
98
99 /* for KVM_GET_LAPIC and KVM_SET_LAPIC */
100 #define KVM_APIC_REG_SIZE 0x400
101 struct kvm_lapic_state {
102 char regs[KVM_APIC_REG_SIZE];
103 };
104
105 struct kvm_segment {
106 __u64 base;
107 __u32 limit;
108 __u16 selector;
109 __u8 type;
110 __u8 present, dpl, db, s, l, g, avl;
111 __u8 unusable;
112 __u8 padding;
113 };
114
115 struct kvm_dtable {
116 __u64 base;
117 __u16 limit;
118 __u16 padding[3];
119 };
120
121
122 /* for KVM_GET_SREGS and KVM_SET_SREGS */
123 struct kvm_sregs {
124 /* out (KVM_GET_SREGS) / in (KVM_SET_SREGS) */
125 struct kvm_segment cs, ds, es, fs, gs, ss;
126 struct kvm_segment tr, ldt;
127 struct kvm_dtable gdt, idt;
128 __u64 cr0, cr2, cr3, cr4, cr8;
129 __u64 efer;
130 __u64 apic_base;
131 __u64 interrupt_bitmap[(KVM_NR_INTERRUPTS + 63) / 64];
132 };
133
134 /* for KVM_GET_FPU and KVM_SET_FPU */
135 struct kvm_fpu {
136 __u8 fpr[8][16];
137 __u16 fcw;
138 __u16 fsw;
139 __u8 ftwx; /* in fxsave format */
140 __u8 pad1;
141 __u16 last_opcode;
142 __u64 last_ip;
143 __u64 last_dp;
144 __u8 xmm[16][16];
145 __u32 mxcsr;
146 __u32 pad2;
147 };
148
149 struct kvm_msr_entry {
150 __u32 index;
151 __u32 reserved;
152 __u64 data;
153 };
154
155 /* for KVM_GET_MSRS and KVM_SET_MSRS */
156 struct kvm_msrs {
157 __u32 nmsrs; /* number of msrs in entries */
158 __u32 pad;
159
160 struct kvm_msr_entry entries[0];
161 };
162
163 /* for KVM_GET_MSR_INDEX_LIST */
164 struct kvm_msr_list {
165 __u32 nmsrs; /* number of msrs in entries */
166 __u32 indices[0];
167 };
168
169
170 struct kvm_cpuid_entry {
171 __u32 function;
172 __u32 eax;
173 __u32 ebx;
174 __u32 ecx;
175 __u32 edx;
176 __u32 padding;
177 };
178
179 /* for KVM_SET_CPUID */
180 struct kvm_cpuid {
181 __u32 nent;
182 __u32 padding;
183 struct kvm_cpuid_entry entries[0];
184 };
185
186 struct kvm_cpuid_entry2 {
187 __u32 function;
188 __u32 index;
189 __u32 flags;
190 __u32 eax;
191 __u32 ebx;
192 __u32 ecx;
193 __u32 edx;
194 __u32 padding[3];
195 };
196
197 #define KVM_CPUID_FLAG_SIGNIFCANT_INDEX 1
198 #define KVM_CPUID_FLAG_STATEFUL_FUNC 2
199 #define KVM_CPUID_FLAG_STATE_READ_NEXT 4
200
201 /* for KVM_SET_CPUID2 */
202 struct kvm_cpuid2 {
203 __u32 nent;
204 __u32 padding;
205 struct kvm_cpuid_entry2 entries[0];
206 };
207
208 /* for KVM_GET_PIT and KVM_SET_PIT */
209 struct kvm_pit_channel_state {
210 __u32 count; /* can be 65536 */
211 __u16 latched_count;
212 __u8 count_latched;
213 __u8 status_latched;
214 __u8 status;
215 __u8 read_state;
216 __u8 write_state;
217 __u8 write_latch;
218 __u8 rw_mode;
219 __u8 mode;
220 __u8 bcd;
221 __u8 gate;
222 __s64 count_load_time;
223 };
224
225 struct kvm_debug_exit_arch {
226 __u32 exception;
227 __u32 pad;
228 __u64 pc;
229 __u64 dr6;
230 __u64 dr7;
231 };
232
233 #define KVM_GUESTDBG_USE_SW_BP 0x00010000
234 #define KVM_GUESTDBG_USE_HW_BP 0x00020000
235 #define KVM_GUESTDBG_INJECT_DB 0x00040000
236 #define KVM_GUESTDBG_INJECT_BP 0x00080000
237
238 /* for KVM_SET_GUEST_DEBUG */
239 struct kvm_guest_debug_arch {
240 __u64 debugreg[8];
241 };
242
243 struct kvm_pit_state {
244 struct kvm_pit_channel_state channels[3];
245 };
246
247 #define KVM_PIT_FLAGS_HPET_LEGACY 0x00000001
248
249 struct kvm_pit_state2 {
250 struct kvm_pit_channel_state channels[3];
251 __u32 flags;
252 __u32 reserved[9];
253 };
254
255 struct kvm_reinject_control {
256 __u8 pit_reinject;
257 __u8 reserved[31];
258 };
259
260 /* When set in flags, include corresponding fields on KVM_SET_VCPU_EVENTS */
261 #define KVM_VCPUEVENT_VALID_NMI_PENDING 0x00000001
262 #define KVM_VCPUEVENT_VALID_SIPI_VECTOR 0x00000002
263 #define KVM_VCPUEVENT_VALID_SHADOW 0x00000004
264
265 /* Interrupt shadow states */
266 #define KVM_X86_SHADOW_INT_MOV_SS 0x01
267 #define KVM_X86_SHADOW_INT_STI 0x02
268
269 /* for KVM_GET/SET_VCPU_EVENTS */
270 struct kvm_vcpu_events {
271 struct {
272 __u8 injected;
273 __u8 nr;
274 __u8 has_error_code;
275 __u8 pad;
276 __u32 error_code;
277 } exception;
278 struct {
279 __u8 injected;
280 __u8 nr;
281 __u8 soft;
282 __u8 shadow;
283 } interrupt;
284 struct {
285 __u8 injected;
286 __u8 pending;
287 __u8 masked;
288 __u8 pad;
289 } nmi;
290 __u32 sipi_vector;
291 __u32 flags;
292 __u32 reserved[10];
293 };
294
295 /* for KVM_GET/SET_DEBUGREGS */
296 struct kvm_debugregs {
297 __u64 db[4];
298 __u64 dr6;
299 __u64 dr7;
300 __u64 flags;
301 __u64 reserved[9];
302 };
303
304 /* for KVM_CAP_XSAVE */
305 struct kvm_xsave {
306 __u32 region[1024];
307 };
308
309 #define KVM_MAX_XCRS 16
310
311 struct kvm_xcr {
312 __u32 xcr;
313 __u32 reserved;
314 __u64 value;
315 };
316
317 struct kvm_xcrs {
318 __u32 nr_xcrs;
319 __u32 flags;
320 struct kvm_xcr xcrs[KVM_MAX_XCRS];
321 __u64 padding[16];
322 };
323
324 #endif /* _ASM_X86_KVM_H */