block: User BdrvChild callback for device name
[qemu.git] / linux-user / main.c
1 /*
2 * qemu user main
3 *
4 * Copyright (c) 2003-2008 Fabrice Bellard
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "qemu/osdep.h"
20 #include <sys/mman.h>
21 #include <sys/syscall.h>
22 #include <sys/resource.h>
23
24 #include "qemu.h"
25 #include "qemu/path.h"
26 #include "qemu/cutils.h"
27 #include "qemu/help_option.h"
28 #include "cpu.h"
29 #include "tcg.h"
30 #include "qemu/timer.h"
31 #include "qemu/envlist.h"
32 #include "elf.h"
33 #include "exec/log.h"
34
35 char *exec_path;
36
37 int singlestep;
38 static const char *filename;
39 static const char *argv0;
40 static int gdbstub_port;
41 static envlist_t *envlist;
42 static const char *cpu_model;
43 unsigned long mmap_min_addr;
44 unsigned long guest_base;
45 int have_guest_base;
46
47 #define EXCP_DUMP(env, fmt, ...) \
48 do { \
49 CPUState *cs = ENV_GET_CPU(env); \
50 fprintf(stderr, fmt , ## __VA_ARGS__); \
51 cpu_dump_state(cs, stderr, fprintf, 0); \
52 if (qemu_log_separate()) { \
53 qemu_log(fmt, ## __VA_ARGS__); \
54 log_cpu_state(cs, 0); \
55 } \
56 } while (0)
57
58 #if (TARGET_LONG_BITS == 32) && (HOST_LONG_BITS == 64)
59 /*
60 * When running 32-on-64 we should make sure we can fit all of the possible
61 * guest address space into a contiguous chunk of virtual host memory.
62 *
63 * This way we will never overlap with our own libraries or binaries or stack
64 * or anything else that QEMU maps.
65 */
66 # ifdef TARGET_MIPS
67 /* MIPS only supports 31 bits of virtual address space for user space */
68 unsigned long reserved_va = 0x77000000;
69 # else
70 unsigned long reserved_va = 0xf7000000;
71 # endif
72 #else
73 unsigned long reserved_va;
74 #endif
75
76 static void usage(int exitcode);
77
78 static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX;
79 const char *qemu_uname_release;
80
81 /* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so
82 we allocate a bigger stack. Need a better solution, for example
83 by remapping the process stack directly at the right place */
84 unsigned long guest_stack_size = 8 * 1024 * 1024UL;
85
86 void gemu_log(const char *fmt, ...)
87 {
88 va_list ap;
89
90 va_start(ap, fmt);
91 vfprintf(stderr, fmt, ap);
92 va_end(ap);
93 }
94
95 #if defined(TARGET_I386)
96 int cpu_get_pic_interrupt(CPUX86State *env)
97 {
98 return -1;
99 }
100 #endif
101
102 /***********************************************************/
103 /* Helper routines for implementing atomic operations. */
104
105 /* To implement exclusive operations we force all cpus to syncronise.
106 We don't require a full sync, only that no cpus are executing guest code.
107 The alternative is to map target atomic ops onto host equivalents,
108 which requires quite a lot of per host/target work. */
109 static pthread_mutex_t cpu_list_mutex = PTHREAD_MUTEX_INITIALIZER;
110 static pthread_mutex_t exclusive_lock = PTHREAD_MUTEX_INITIALIZER;
111 static pthread_cond_t exclusive_cond = PTHREAD_COND_INITIALIZER;
112 static pthread_cond_t exclusive_resume = PTHREAD_COND_INITIALIZER;
113 static int pending_cpus;
114
115 /* Make sure everything is in a consistent state for calling fork(). */
116 void fork_start(void)
117 {
118 qemu_mutex_lock(&tcg_ctx.tb_ctx.tb_lock);
119 pthread_mutex_lock(&exclusive_lock);
120 mmap_fork_start();
121 }
122
123 void fork_end(int child)
124 {
125 mmap_fork_end(child);
126 if (child) {
127 CPUState *cpu, *next_cpu;
128 /* Child processes created by fork() only have a single thread.
129 Discard information about the parent threads. */
130 CPU_FOREACH_SAFE(cpu, next_cpu) {
131 if (cpu != thread_cpu) {
132 QTAILQ_REMOVE(&cpus, thread_cpu, node);
133 }
134 }
135 pending_cpus = 0;
136 pthread_mutex_init(&exclusive_lock, NULL);
137 pthread_mutex_init(&cpu_list_mutex, NULL);
138 pthread_cond_init(&exclusive_cond, NULL);
139 pthread_cond_init(&exclusive_resume, NULL);
140 qemu_mutex_init(&tcg_ctx.tb_ctx.tb_lock);
141 gdbserver_fork(thread_cpu);
142 } else {
143 pthread_mutex_unlock(&exclusive_lock);
144 qemu_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock);
145 }
146 }
147
148 /* Wait for pending exclusive operations to complete. The exclusive lock
149 must be held. */
150 static inline void exclusive_idle(void)
151 {
152 while (pending_cpus) {
153 pthread_cond_wait(&exclusive_resume, &exclusive_lock);
154 }
155 }
156
157 /* Start an exclusive operation.
158 Must only be called from outside cpu_arm_exec. */
159 static inline void start_exclusive(void)
160 {
161 CPUState *other_cpu;
162
163 pthread_mutex_lock(&exclusive_lock);
164 exclusive_idle();
165
166 pending_cpus = 1;
167 /* Make all other cpus stop executing. */
168 CPU_FOREACH(other_cpu) {
169 if (other_cpu->running) {
170 pending_cpus++;
171 cpu_exit(other_cpu);
172 }
173 }
174 if (pending_cpus > 1) {
175 pthread_cond_wait(&exclusive_cond, &exclusive_lock);
176 }
177 }
178
179 /* Finish an exclusive operation. */
180 static inline void __attribute__((unused)) end_exclusive(void)
181 {
182 pending_cpus = 0;
183 pthread_cond_broadcast(&exclusive_resume);
184 pthread_mutex_unlock(&exclusive_lock);
185 }
186
187 /* Wait for exclusive ops to finish, and begin cpu execution. */
188 static inline void cpu_exec_start(CPUState *cpu)
189 {
190 pthread_mutex_lock(&exclusive_lock);
191 exclusive_idle();
192 cpu->running = true;
193 pthread_mutex_unlock(&exclusive_lock);
194 }
195
196 /* Mark cpu as not executing, and release pending exclusive ops. */
197 static inline void cpu_exec_end(CPUState *cpu)
198 {
199 pthread_mutex_lock(&exclusive_lock);
200 cpu->running = false;
201 if (pending_cpus > 1) {
202 pending_cpus--;
203 if (pending_cpus == 1) {
204 pthread_cond_signal(&exclusive_cond);
205 }
206 }
207 exclusive_idle();
208 pthread_mutex_unlock(&exclusive_lock);
209 }
210
211 void cpu_list_lock(void)
212 {
213 pthread_mutex_lock(&cpu_list_mutex);
214 }
215
216 void cpu_list_unlock(void)
217 {
218 pthread_mutex_unlock(&cpu_list_mutex);
219 }
220
221
222 #ifdef TARGET_I386
223 /***********************************************************/
224 /* CPUX86 core interface */
225
226 uint64_t cpu_get_tsc(CPUX86State *env)
227 {
228 return cpu_get_host_ticks();
229 }
230
231 static void write_dt(void *ptr, unsigned long addr, unsigned long limit,
232 int flags)
233 {
234 unsigned int e1, e2;
235 uint32_t *p;
236 e1 = (addr << 16) | (limit & 0xffff);
237 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000);
238 e2 |= flags;
239 p = ptr;
240 p[0] = tswap32(e1);
241 p[1] = tswap32(e2);
242 }
243
244 static uint64_t *idt_table;
245 #ifdef TARGET_X86_64
246 static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,
247 uint64_t addr, unsigned int sel)
248 {
249 uint32_t *p, e1, e2;
250 e1 = (addr & 0xffff) | (sel << 16);
251 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
252 p = ptr;
253 p[0] = tswap32(e1);
254 p[1] = tswap32(e2);
255 p[2] = tswap32(addr >> 32);
256 p[3] = 0;
257 }
258 /* only dpl matters as we do only user space emulation */
259 static void set_idt(int n, unsigned int dpl)
260 {
261 set_gate64(idt_table + n * 2, 0, dpl, 0, 0);
262 }
263 #else
264 static void set_gate(void *ptr, unsigned int type, unsigned int dpl,
265 uint32_t addr, unsigned int sel)
266 {
267 uint32_t *p, e1, e2;
268 e1 = (addr & 0xffff) | (sel << 16);
269 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
270 p = ptr;
271 p[0] = tswap32(e1);
272 p[1] = tswap32(e2);
273 }
274
275 /* only dpl matters as we do only user space emulation */
276 static void set_idt(int n, unsigned int dpl)
277 {
278 set_gate(idt_table + n, 0, dpl, 0, 0);
279 }
280 #endif
281
282 void cpu_loop(CPUX86State *env)
283 {
284 CPUState *cs = CPU(x86_env_get_cpu(env));
285 int trapnr;
286 abi_ulong pc;
287 target_siginfo_t info;
288
289 for(;;) {
290 cpu_exec_start(cs);
291 trapnr = cpu_x86_exec(cs);
292 cpu_exec_end(cs);
293 switch(trapnr) {
294 case 0x80:
295 /* linux syscall from int $0x80 */
296 env->regs[R_EAX] = do_syscall(env,
297 env->regs[R_EAX],
298 env->regs[R_EBX],
299 env->regs[R_ECX],
300 env->regs[R_EDX],
301 env->regs[R_ESI],
302 env->regs[R_EDI],
303 env->regs[R_EBP],
304 0, 0);
305 break;
306 #ifndef TARGET_ABI32
307 case EXCP_SYSCALL:
308 /* linux syscall from syscall instruction */
309 env->regs[R_EAX] = do_syscall(env,
310 env->regs[R_EAX],
311 env->regs[R_EDI],
312 env->regs[R_ESI],
313 env->regs[R_EDX],
314 env->regs[10],
315 env->regs[8],
316 env->regs[9],
317 0, 0);
318 break;
319 #endif
320 case EXCP0B_NOSEG:
321 case EXCP0C_STACK:
322 info.si_signo = TARGET_SIGBUS;
323 info.si_errno = 0;
324 info.si_code = TARGET_SI_KERNEL;
325 info._sifields._sigfault._addr = 0;
326 queue_signal(env, info.si_signo, &info);
327 break;
328 case EXCP0D_GPF:
329 /* XXX: potential problem if ABI32 */
330 #ifndef TARGET_X86_64
331 if (env->eflags & VM_MASK) {
332 handle_vm86_fault(env);
333 } else
334 #endif
335 {
336 info.si_signo = TARGET_SIGSEGV;
337 info.si_errno = 0;
338 info.si_code = TARGET_SI_KERNEL;
339 info._sifields._sigfault._addr = 0;
340 queue_signal(env, info.si_signo, &info);
341 }
342 break;
343 case EXCP0E_PAGE:
344 info.si_signo = TARGET_SIGSEGV;
345 info.si_errno = 0;
346 if (!(env->error_code & 1))
347 info.si_code = TARGET_SEGV_MAPERR;
348 else
349 info.si_code = TARGET_SEGV_ACCERR;
350 info._sifields._sigfault._addr = env->cr[2];
351 queue_signal(env, info.si_signo, &info);
352 break;
353 case EXCP00_DIVZ:
354 #ifndef TARGET_X86_64
355 if (env->eflags & VM_MASK) {
356 handle_vm86_trap(env, trapnr);
357 } else
358 #endif
359 {
360 /* division by zero */
361 info.si_signo = TARGET_SIGFPE;
362 info.si_errno = 0;
363 info.si_code = TARGET_FPE_INTDIV;
364 info._sifields._sigfault._addr = env->eip;
365 queue_signal(env, info.si_signo, &info);
366 }
367 break;
368 case EXCP01_DB:
369 case EXCP03_INT3:
370 #ifndef TARGET_X86_64
371 if (env->eflags & VM_MASK) {
372 handle_vm86_trap(env, trapnr);
373 } else
374 #endif
375 {
376 info.si_signo = TARGET_SIGTRAP;
377 info.si_errno = 0;
378 if (trapnr == EXCP01_DB) {
379 info.si_code = TARGET_TRAP_BRKPT;
380 info._sifields._sigfault._addr = env->eip;
381 } else {
382 info.si_code = TARGET_SI_KERNEL;
383 info._sifields._sigfault._addr = 0;
384 }
385 queue_signal(env, info.si_signo, &info);
386 }
387 break;
388 case EXCP04_INTO:
389 case EXCP05_BOUND:
390 #ifndef TARGET_X86_64
391 if (env->eflags & VM_MASK) {
392 handle_vm86_trap(env, trapnr);
393 } else
394 #endif
395 {
396 info.si_signo = TARGET_SIGSEGV;
397 info.si_errno = 0;
398 info.si_code = TARGET_SI_KERNEL;
399 info._sifields._sigfault._addr = 0;
400 queue_signal(env, info.si_signo, &info);
401 }
402 break;
403 case EXCP06_ILLOP:
404 info.si_signo = TARGET_SIGILL;
405 info.si_errno = 0;
406 info.si_code = TARGET_ILL_ILLOPN;
407 info._sifields._sigfault._addr = env->eip;
408 queue_signal(env, info.si_signo, &info);
409 break;
410 case EXCP_INTERRUPT:
411 /* just indicate that signals should be handled asap */
412 break;
413 case EXCP_DEBUG:
414 {
415 int sig;
416
417 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
418 if (sig)
419 {
420 info.si_signo = sig;
421 info.si_errno = 0;
422 info.si_code = TARGET_TRAP_BRKPT;
423 queue_signal(env, info.si_signo, &info);
424 }
425 }
426 break;
427 default:
428 pc = env->segs[R_CS].base + env->eip;
429 EXCP_DUMP(env, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
430 (long)pc, trapnr);
431 abort();
432 }
433 process_pending_signals(env);
434 }
435 }
436 #endif
437
438 #ifdef TARGET_ARM
439
440 #define get_user_code_u32(x, gaddr, env) \
441 ({ abi_long __r = get_user_u32((x), (gaddr)); \
442 if (!__r && bswap_code(arm_sctlr_b(env))) { \
443 (x) = bswap32(x); \
444 } \
445 __r; \
446 })
447
448 #define get_user_code_u16(x, gaddr, env) \
449 ({ abi_long __r = get_user_u16((x), (gaddr)); \
450 if (!__r && bswap_code(arm_sctlr_b(env))) { \
451 (x) = bswap16(x); \
452 } \
453 __r; \
454 })
455
456 #define get_user_data_u32(x, gaddr, env) \
457 ({ abi_long __r = get_user_u32((x), (gaddr)); \
458 if (!__r && arm_cpu_bswap_data(env)) { \
459 (x) = bswap32(x); \
460 } \
461 __r; \
462 })
463
464 #define get_user_data_u16(x, gaddr, env) \
465 ({ abi_long __r = get_user_u16((x), (gaddr)); \
466 if (!__r && arm_cpu_bswap_data(env)) { \
467 (x) = bswap16(x); \
468 } \
469 __r; \
470 })
471
472 #define put_user_data_u32(x, gaddr, env) \
473 ({ typeof(x) __x = (x); \
474 if (arm_cpu_bswap_data(env)) { \
475 __x = bswap32(__x); \
476 } \
477 put_user_u32(__x, (gaddr)); \
478 })
479
480 #define put_user_data_u16(x, gaddr, env) \
481 ({ typeof(x) __x = (x); \
482 if (arm_cpu_bswap_data(env)) { \
483 __x = bswap16(__x); \
484 } \
485 put_user_u16(__x, (gaddr)); \
486 })
487
488 #ifdef TARGET_ABI32
489 /* Commpage handling -- there is no commpage for AArch64 */
490
491 /*
492 * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt
493 * Input:
494 * r0 = pointer to oldval
495 * r1 = pointer to newval
496 * r2 = pointer to target value
497 *
498 * Output:
499 * r0 = 0 if *ptr was changed, non-0 if no exchange happened
500 * C set if *ptr was changed, clear if no exchange happened
501 *
502 * Note segv's in kernel helpers are a bit tricky, we can set the
503 * data address sensibly but the PC address is just the entry point.
504 */
505 static void arm_kernel_cmpxchg64_helper(CPUARMState *env)
506 {
507 uint64_t oldval, newval, val;
508 uint32_t addr, cpsr;
509 target_siginfo_t info;
510
511 /* Based on the 32 bit code in do_kernel_trap */
512
513 /* XXX: This only works between threads, not between processes.
514 It's probably possible to implement this with native host
515 operations. However things like ldrex/strex are much harder so
516 there's not much point trying. */
517 start_exclusive();
518 cpsr = cpsr_read(env);
519 addr = env->regs[2];
520
521 if (get_user_u64(oldval, env->regs[0])) {
522 env->exception.vaddress = env->regs[0];
523 goto segv;
524 };
525
526 if (get_user_u64(newval, env->regs[1])) {
527 env->exception.vaddress = env->regs[1];
528 goto segv;
529 };
530
531 if (get_user_u64(val, addr)) {
532 env->exception.vaddress = addr;
533 goto segv;
534 }
535
536 if (val == oldval) {
537 val = newval;
538
539 if (put_user_u64(val, addr)) {
540 env->exception.vaddress = addr;
541 goto segv;
542 };
543
544 env->regs[0] = 0;
545 cpsr |= CPSR_C;
546 } else {
547 env->regs[0] = -1;
548 cpsr &= ~CPSR_C;
549 }
550 cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr);
551 end_exclusive();
552 return;
553
554 segv:
555 end_exclusive();
556 /* We get the PC of the entry address - which is as good as anything,
557 on a real kernel what you get depends on which mode it uses. */
558 info.si_signo = TARGET_SIGSEGV;
559 info.si_errno = 0;
560 /* XXX: check env->error_code */
561 info.si_code = TARGET_SEGV_MAPERR;
562 info._sifields._sigfault._addr = env->exception.vaddress;
563 queue_signal(env, info.si_signo, &info);
564 }
565
566 /* Handle a jump to the kernel code page. */
567 static int
568 do_kernel_trap(CPUARMState *env)
569 {
570 uint32_t addr;
571 uint32_t cpsr;
572 uint32_t val;
573
574 switch (env->regs[15]) {
575 case 0xffff0fa0: /* __kernel_memory_barrier */
576 /* ??? No-op. Will need to do better for SMP. */
577 break;
578 case 0xffff0fc0: /* __kernel_cmpxchg */
579 /* XXX: This only works between threads, not between processes.
580 It's probably possible to implement this with native host
581 operations. However things like ldrex/strex are much harder so
582 there's not much point trying. */
583 start_exclusive();
584 cpsr = cpsr_read(env);
585 addr = env->regs[2];
586 /* FIXME: This should SEGV if the access fails. */
587 if (get_user_u32(val, addr))
588 val = ~env->regs[0];
589 if (val == env->regs[0]) {
590 val = env->regs[1];
591 /* FIXME: Check for segfaults. */
592 put_user_u32(val, addr);
593 env->regs[0] = 0;
594 cpsr |= CPSR_C;
595 } else {
596 env->regs[0] = -1;
597 cpsr &= ~CPSR_C;
598 }
599 cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr);
600 end_exclusive();
601 break;
602 case 0xffff0fe0: /* __kernel_get_tls */
603 env->regs[0] = cpu_get_tls(env);
604 break;
605 case 0xffff0f60: /* __kernel_cmpxchg64 */
606 arm_kernel_cmpxchg64_helper(env);
607 break;
608
609 default:
610 return 1;
611 }
612 /* Jump back to the caller. */
613 addr = env->regs[14];
614 if (addr & 1) {
615 env->thumb = 1;
616 addr &= ~1;
617 }
618 env->regs[15] = addr;
619
620 return 0;
621 }
622
623 /* Store exclusive handling for AArch32 */
624 static int do_strex(CPUARMState *env)
625 {
626 uint64_t val;
627 int size;
628 int rc = 1;
629 int segv = 0;
630 uint32_t addr;
631 start_exclusive();
632 if (env->exclusive_addr != env->exclusive_test) {
633 goto fail;
634 }
635 /* We know we're always AArch32 so the address is in uint32_t range
636 * unless it was the -1 exclusive-monitor-lost value (which won't
637 * match exclusive_test above).
638 */
639 assert(extract64(env->exclusive_addr, 32, 32) == 0);
640 addr = env->exclusive_addr;
641 size = env->exclusive_info & 0xf;
642 switch (size) {
643 case 0:
644 segv = get_user_u8(val, addr);
645 break;
646 case 1:
647 segv = get_user_data_u16(val, addr, env);
648 break;
649 case 2:
650 case 3:
651 segv = get_user_data_u32(val, addr, env);
652 break;
653 default:
654 abort();
655 }
656 if (segv) {
657 env->exception.vaddress = addr;
658 goto done;
659 }
660 if (size == 3) {
661 uint32_t valhi;
662 segv = get_user_data_u32(valhi, addr + 4, env);
663 if (segv) {
664 env->exception.vaddress = addr + 4;
665 goto done;
666 }
667 if (arm_cpu_bswap_data(env)) {
668 val = deposit64((uint64_t)valhi, 32, 32, val);
669 } else {
670 val = deposit64(val, 32, 32, valhi);
671 }
672 }
673 if (val != env->exclusive_val) {
674 goto fail;
675 }
676
677 val = env->regs[(env->exclusive_info >> 8) & 0xf];
678 switch (size) {
679 case 0:
680 segv = put_user_u8(val, addr);
681 break;
682 case 1:
683 segv = put_user_data_u16(val, addr, env);
684 break;
685 case 2:
686 case 3:
687 segv = put_user_data_u32(val, addr, env);
688 break;
689 }
690 if (segv) {
691 env->exception.vaddress = addr;
692 goto done;
693 }
694 if (size == 3) {
695 val = env->regs[(env->exclusive_info >> 12) & 0xf];
696 segv = put_user_data_u32(val, addr + 4, env);
697 if (segv) {
698 env->exception.vaddress = addr + 4;
699 goto done;
700 }
701 }
702 rc = 0;
703 fail:
704 env->regs[15] += 4;
705 env->regs[(env->exclusive_info >> 4) & 0xf] = rc;
706 done:
707 end_exclusive();
708 return segv;
709 }
710
711 void cpu_loop(CPUARMState *env)
712 {
713 CPUState *cs = CPU(arm_env_get_cpu(env));
714 int trapnr;
715 unsigned int n, insn;
716 target_siginfo_t info;
717 uint32_t addr;
718
719 for(;;) {
720 cpu_exec_start(cs);
721 trapnr = cpu_arm_exec(cs);
722 cpu_exec_end(cs);
723 switch(trapnr) {
724 case EXCP_UDEF:
725 {
726 TaskState *ts = cs->opaque;
727 uint32_t opcode;
728 int rc;
729
730 /* we handle the FPU emulation here, as Linux */
731 /* we get the opcode */
732 /* FIXME - what to do if get_user() fails? */
733 get_user_code_u32(opcode, env->regs[15], env);
734
735 rc = EmulateAll(opcode, &ts->fpa, env);
736 if (rc == 0) { /* illegal instruction */
737 info.si_signo = TARGET_SIGILL;
738 info.si_errno = 0;
739 info.si_code = TARGET_ILL_ILLOPN;
740 info._sifields._sigfault._addr = env->regs[15];
741 queue_signal(env, info.si_signo, &info);
742 } else if (rc < 0) { /* FP exception */
743 int arm_fpe=0;
744
745 /* translate softfloat flags to FPSR flags */
746 if (-rc & float_flag_invalid)
747 arm_fpe |= BIT_IOC;
748 if (-rc & float_flag_divbyzero)
749 arm_fpe |= BIT_DZC;
750 if (-rc & float_flag_overflow)
751 arm_fpe |= BIT_OFC;
752 if (-rc & float_flag_underflow)
753 arm_fpe |= BIT_UFC;
754 if (-rc & float_flag_inexact)
755 arm_fpe |= BIT_IXC;
756
757 FPSR fpsr = ts->fpa.fpsr;
758 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);
759
760 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */
761 info.si_signo = TARGET_SIGFPE;
762 info.si_errno = 0;
763
764 /* ordered by priority, least first */
765 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES;
766 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND;
767 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF;
768 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV;
769 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV;
770
771 info._sifields._sigfault._addr = env->regs[15];
772 queue_signal(env, info.si_signo, &info);
773 } else {
774 env->regs[15] += 4;
775 }
776
777 /* accumulate unenabled exceptions */
778 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC))
779 fpsr |= BIT_IXC;
780 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC))
781 fpsr |= BIT_UFC;
782 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC))
783 fpsr |= BIT_OFC;
784 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC))
785 fpsr |= BIT_DZC;
786 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC))
787 fpsr |= BIT_IOC;
788 ts->fpa.fpsr=fpsr;
789 } else { /* everything OK */
790 /* increment PC */
791 env->regs[15] += 4;
792 }
793 }
794 break;
795 case EXCP_SWI:
796 case EXCP_BKPT:
797 {
798 env->eabi = 1;
799 /* system call */
800 if (trapnr == EXCP_BKPT) {
801 if (env->thumb) {
802 /* FIXME - what to do if get_user() fails? */
803 get_user_code_u16(insn, env->regs[15], env);
804 n = insn & 0xff;
805 env->regs[15] += 2;
806 } else {
807 /* FIXME - what to do if get_user() fails? */
808 get_user_code_u32(insn, env->regs[15], env);
809 n = (insn & 0xf) | ((insn >> 4) & 0xff0);
810 env->regs[15] += 4;
811 }
812 } else {
813 if (env->thumb) {
814 /* FIXME - what to do if get_user() fails? */
815 get_user_code_u16(insn, env->regs[15] - 2, env);
816 n = insn & 0xff;
817 } else {
818 /* FIXME - what to do if get_user() fails? */
819 get_user_code_u32(insn, env->regs[15] - 4, env);
820 n = insn & 0xffffff;
821 }
822 }
823
824 if (n == ARM_NR_cacheflush) {
825 /* nop */
826 } else if (n == ARM_NR_semihosting
827 || n == ARM_NR_thumb_semihosting) {
828 env->regs[0] = do_arm_semihosting (env);
829 } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) {
830 /* linux syscall */
831 if (env->thumb || n == 0) {
832 n = env->regs[7];
833 } else {
834 n -= ARM_SYSCALL_BASE;
835 env->eabi = 0;
836 }
837 if ( n > ARM_NR_BASE) {
838 switch (n) {
839 case ARM_NR_cacheflush:
840 /* nop */
841 break;
842 case ARM_NR_set_tls:
843 cpu_set_tls(env, env->regs[0]);
844 env->regs[0] = 0;
845 break;
846 case ARM_NR_breakpoint:
847 env->regs[15] -= env->thumb ? 2 : 4;
848 goto excp_debug;
849 default:
850 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n",
851 n);
852 env->regs[0] = -TARGET_ENOSYS;
853 break;
854 }
855 } else {
856 env->regs[0] = do_syscall(env,
857 n,
858 env->regs[0],
859 env->regs[1],
860 env->regs[2],
861 env->regs[3],
862 env->regs[4],
863 env->regs[5],
864 0, 0);
865 }
866 } else {
867 goto error;
868 }
869 }
870 break;
871 case EXCP_INTERRUPT:
872 /* just indicate that signals should be handled asap */
873 break;
874 case EXCP_STREX:
875 if (!do_strex(env)) {
876 break;
877 }
878 /* fall through for segv */
879 case EXCP_PREFETCH_ABORT:
880 case EXCP_DATA_ABORT:
881 addr = env->exception.vaddress;
882 {
883 info.si_signo = TARGET_SIGSEGV;
884 info.si_errno = 0;
885 /* XXX: check env->error_code */
886 info.si_code = TARGET_SEGV_MAPERR;
887 info._sifields._sigfault._addr = addr;
888 queue_signal(env, info.si_signo, &info);
889 }
890 break;
891 case EXCP_DEBUG:
892 excp_debug:
893 {
894 int sig;
895
896 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
897 if (sig)
898 {
899 info.si_signo = sig;
900 info.si_errno = 0;
901 info.si_code = TARGET_TRAP_BRKPT;
902 queue_signal(env, info.si_signo, &info);
903 }
904 }
905 break;
906 case EXCP_KERNEL_TRAP:
907 if (do_kernel_trap(env))
908 goto error;
909 break;
910 case EXCP_YIELD:
911 /* nothing to do here for user-mode, just resume guest code */
912 break;
913 default:
914 error:
915 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
916 abort();
917 }
918 process_pending_signals(env);
919 }
920 }
921
922 #else
923
924 /*
925 * Handle AArch64 store-release exclusive
926 *
927 * rs = gets the status result of store exclusive
928 * rt = is the register that is stored
929 * rt2 = is the second register store (in STP)
930 *
931 */
932 static int do_strex_a64(CPUARMState *env)
933 {
934 uint64_t val;
935 int size;
936 bool is_pair;
937 int rc = 1;
938 int segv = 0;
939 uint64_t addr;
940 int rs, rt, rt2;
941
942 start_exclusive();
943 /* size | is_pair << 2 | (rs << 4) | (rt << 9) | (rt2 << 14)); */
944 size = extract32(env->exclusive_info, 0, 2);
945 is_pair = extract32(env->exclusive_info, 2, 1);
946 rs = extract32(env->exclusive_info, 4, 5);
947 rt = extract32(env->exclusive_info, 9, 5);
948 rt2 = extract32(env->exclusive_info, 14, 5);
949
950 addr = env->exclusive_addr;
951
952 if (addr != env->exclusive_test) {
953 goto finish;
954 }
955
956 switch (size) {
957 case 0:
958 segv = get_user_u8(val, addr);
959 break;
960 case 1:
961 segv = get_user_u16(val, addr);
962 break;
963 case 2:
964 segv = get_user_u32(val, addr);
965 break;
966 case 3:
967 segv = get_user_u64(val, addr);
968 break;
969 default:
970 abort();
971 }
972 if (segv) {
973 env->exception.vaddress = addr;
974 goto error;
975 }
976 if (val != env->exclusive_val) {
977 goto finish;
978 }
979 if (is_pair) {
980 if (size == 2) {
981 segv = get_user_u32(val, addr + 4);
982 } else {
983 segv = get_user_u64(val, addr + 8);
984 }
985 if (segv) {
986 env->exception.vaddress = addr + (size == 2 ? 4 : 8);
987 goto error;
988 }
989 if (val != env->exclusive_high) {
990 goto finish;
991 }
992 }
993 /* handle the zero register */
994 val = rt == 31 ? 0 : env->xregs[rt];
995 switch (size) {
996 case 0:
997 segv = put_user_u8(val, addr);
998 break;
999 case 1:
1000 segv = put_user_u16(val, addr);
1001 break;
1002 case 2:
1003 segv = put_user_u32(val, addr);
1004 break;
1005 case 3:
1006 segv = put_user_u64(val, addr);
1007 break;
1008 }
1009 if (segv) {
1010 goto error;
1011 }
1012 if (is_pair) {
1013 /* handle the zero register */
1014 val = rt2 == 31 ? 0 : env->xregs[rt2];
1015 if (size == 2) {
1016 segv = put_user_u32(val, addr + 4);
1017 } else {
1018 segv = put_user_u64(val, addr + 8);
1019 }
1020 if (segv) {
1021 env->exception.vaddress = addr + (size == 2 ? 4 : 8);
1022 goto error;
1023 }
1024 }
1025 rc = 0;
1026 finish:
1027 env->pc += 4;
1028 /* rs == 31 encodes a write to the ZR, thus throwing away
1029 * the status return. This is rather silly but valid.
1030 */
1031 if (rs < 31) {
1032 env->xregs[rs] = rc;
1033 }
1034 error:
1035 /* instruction faulted, PC does not advance */
1036 /* either way a strex releases any exclusive lock we have */
1037 env->exclusive_addr = -1;
1038 end_exclusive();
1039 return segv;
1040 }
1041
1042 /* AArch64 main loop */
1043 void cpu_loop(CPUARMState *env)
1044 {
1045 CPUState *cs = CPU(arm_env_get_cpu(env));
1046 int trapnr, sig;
1047 target_siginfo_t info;
1048
1049 for (;;) {
1050 cpu_exec_start(cs);
1051 trapnr = cpu_arm_exec(cs);
1052 cpu_exec_end(cs);
1053
1054 switch (trapnr) {
1055 case EXCP_SWI:
1056 env->xregs[0] = do_syscall(env,
1057 env->xregs[8],
1058 env->xregs[0],
1059 env->xregs[1],
1060 env->xregs[2],
1061 env->xregs[3],
1062 env->xregs[4],
1063 env->xregs[5],
1064 0, 0);
1065 break;
1066 case EXCP_INTERRUPT:
1067 /* just indicate that signals should be handled asap */
1068 break;
1069 case EXCP_UDEF:
1070 info.si_signo = TARGET_SIGILL;
1071 info.si_errno = 0;
1072 info.si_code = TARGET_ILL_ILLOPN;
1073 info._sifields._sigfault._addr = env->pc;
1074 queue_signal(env, info.si_signo, &info);
1075 break;
1076 case EXCP_STREX:
1077 if (!do_strex_a64(env)) {
1078 break;
1079 }
1080 /* fall through for segv */
1081 case EXCP_PREFETCH_ABORT:
1082 case EXCP_DATA_ABORT:
1083 info.si_signo = TARGET_SIGSEGV;
1084 info.si_errno = 0;
1085 /* XXX: check env->error_code */
1086 info.si_code = TARGET_SEGV_MAPERR;
1087 info._sifields._sigfault._addr = env->exception.vaddress;
1088 queue_signal(env, info.si_signo, &info);
1089 break;
1090 case EXCP_DEBUG:
1091 case EXCP_BKPT:
1092 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1093 if (sig) {
1094 info.si_signo = sig;
1095 info.si_errno = 0;
1096 info.si_code = TARGET_TRAP_BRKPT;
1097 queue_signal(env, info.si_signo, &info);
1098 }
1099 break;
1100 case EXCP_SEMIHOST:
1101 env->xregs[0] = do_arm_semihosting(env);
1102 break;
1103 case EXCP_YIELD:
1104 /* nothing to do here for user-mode, just resume guest code */
1105 break;
1106 default:
1107 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
1108 abort();
1109 }
1110 process_pending_signals(env);
1111 /* Exception return on AArch64 always clears the exclusive monitor,
1112 * so any return to running guest code implies this.
1113 * A strex (successful or otherwise) also clears the monitor, so
1114 * we don't need to specialcase EXCP_STREX.
1115 */
1116 env->exclusive_addr = -1;
1117 }
1118 }
1119 #endif /* ndef TARGET_ABI32 */
1120
1121 #endif
1122
1123 #ifdef TARGET_UNICORE32
1124
1125 void cpu_loop(CPUUniCore32State *env)
1126 {
1127 CPUState *cs = CPU(uc32_env_get_cpu(env));
1128 int trapnr;
1129 unsigned int n, insn;
1130 target_siginfo_t info;
1131
1132 for (;;) {
1133 cpu_exec_start(cs);
1134 trapnr = uc32_cpu_exec(cs);
1135 cpu_exec_end(cs);
1136 switch (trapnr) {
1137 case UC32_EXCP_PRIV:
1138 {
1139 /* system call */
1140 get_user_u32(insn, env->regs[31] - 4);
1141 n = insn & 0xffffff;
1142
1143 if (n >= UC32_SYSCALL_BASE) {
1144 /* linux syscall */
1145 n -= UC32_SYSCALL_BASE;
1146 if (n == UC32_SYSCALL_NR_set_tls) {
1147 cpu_set_tls(env, env->regs[0]);
1148 env->regs[0] = 0;
1149 } else {
1150 env->regs[0] = do_syscall(env,
1151 n,
1152 env->regs[0],
1153 env->regs[1],
1154 env->regs[2],
1155 env->regs[3],
1156 env->regs[4],
1157 env->regs[5],
1158 0, 0);
1159 }
1160 } else {
1161 goto error;
1162 }
1163 }
1164 break;
1165 case UC32_EXCP_DTRAP:
1166 case UC32_EXCP_ITRAP:
1167 info.si_signo = TARGET_SIGSEGV;
1168 info.si_errno = 0;
1169 /* XXX: check env->error_code */
1170 info.si_code = TARGET_SEGV_MAPERR;
1171 info._sifields._sigfault._addr = env->cp0.c4_faultaddr;
1172 queue_signal(env, info.si_signo, &info);
1173 break;
1174 case EXCP_INTERRUPT:
1175 /* just indicate that signals should be handled asap */
1176 break;
1177 case EXCP_DEBUG:
1178 {
1179 int sig;
1180
1181 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1182 if (sig) {
1183 info.si_signo = sig;
1184 info.si_errno = 0;
1185 info.si_code = TARGET_TRAP_BRKPT;
1186 queue_signal(env, info.si_signo, &info);
1187 }
1188 }
1189 break;
1190 default:
1191 goto error;
1192 }
1193 process_pending_signals(env);
1194 }
1195
1196 error:
1197 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
1198 abort();
1199 }
1200 #endif
1201
1202 #ifdef TARGET_SPARC
1203 #define SPARC64_STACK_BIAS 2047
1204
1205 //#define DEBUG_WIN
1206
1207 /* WARNING: dealing with register windows _is_ complicated. More info
1208 can be found at http://www.sics.se/~psm/sparcstack.html */
1209 static inline int get_reg_index(CPUSPARCState *env, int cwp, int index)
1210 {
1211 index = (index + cwp * 16) % (16 * env->nwindows);
1212 /* wrap handling : if cwp is on the last window, then we use the
1213 registers 'after' the end */
1214 if (index < 8 && env->cwp == env->nwindows - 1)
1215 index += 16 * env->nwindows;
1216 return index;
1217 }
1218
1219 /* save the register window 'cwp1' */
1220 static inline void save_window_offset(CPUSPARCState *env, int cwp1)
1221 {
1222 unsigned int i;
1223 abi_ulong sp_ptr;
1224
1225 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
1226 #ifdef TARGET_SPARC64
1227 if (sp_ptr & 3)
1228 sp_ptr += SPARC64_STACK_BIAS;
1229 #endif
1230 #if defined(DEBUG_WIN)
1231 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n",
1232 sp_ptr, cwp1);
1233 #endif
1234 for(i = 0; i < 16; i++) {
1235 /* FIXME - what to do if put_user() fails? */
1236 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
1237 sp_ptr += sizeof(abi_ulong);
1238 }
1239 }
1240
1241 static void save_window(CPUSPARCState *env)
1242 {
1243 #ifndef TARGET_SPARC64
1244 unsigned int new_wim;
1245 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) &
1246 ((1LL << env->nwindows) - 1);
1247 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
1248 env->wim = new_wim;
1249 #else
1250 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
1251 env->cansave++;
1252 env->canrestore--;
1253 #endif
1254 }
1255
1256 static void restore_window(CPUSPARCState *env)
1257 {
1258 #ifndef TARGET_SPARC64
1259 unsigned int new_wim;
1260 #endif
1261 unsigned int i, cwp1;
1262 abi_ulong sp_ptr;
1263
1264 #ifndef TARGET_SPARC64
1265 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) &
1266 ((1LL << env->nwindows) - 1);
1267 #endif
1268
1269 /* restore the invalid window */
1270 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
1271 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
1272 #ifdef TARGET_SPARC64
1273 if (sp_ptr & 3)
1274 sp_ptr += SPARC64_STACK_BIAS;
1275 #endif
1276 #if defined(DEBUG_WIN)
1277 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n",
1278 sp_ptr, cwp1);
1279 #endif
1280 for(i = 0; i < 16; i++) {
1281 /* FIXME - what to do if get_user() fails? */
1282 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
1283 sp_ptr += sizeof(abi_ulong);
1284 }
1285 #ifdef TARGET_SPARC64
1286 env->canrestore++;
1287 if (env->cleanwin < env->nwindows - 1)
1288 env->cleanwin++;
1289 env->cansave--;
1290 #else
1291 env->wim = new_wim;
1292 #endif
1293 }
1294
1295 static void flush_windows(CPUSPARCState *env)
1296 {
1297 int offset, cwp1;
1298
1299 offset = 1;
1300 for(;;) {
1301 /* if restore would invoke restore_window(), then we can stop */
1302 cwp1 = cpu_cwp_inc(env, env->cwp + offset);
1303 #ifndef TARGET_SPARC64
1304 if (env->wim & (1 << cwp1))
1305 break;
1306 #else
1307 if (env->canrestore == 0)
1308 break;
1309 env->cansave++;
1310 env->canrestore--;
1311 #endif
1312 save_window_offset(env, cwp1);
1313 offset++;
1314 }
1315 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
1316 #ifndef TARGET_SPARC64
1317 /* set wim so that restore will reload the registers */
1318 env->wim = 1 << cwp1;
1319 #endif
1320 #if defined(DEBUG_WIN)
1321 printf("flush_windows: nb=%d\n", offset - 1);
1322 #endif
1323 }
1324
1325 void cpu_loop (CPUSPARCState *env)
1326 {
1327 CPUState *cs = CPU(sparc_env_get_cpu(env));
1328 int trapnr;
1329 abi_long ret;
1330 target_siginfo_t info;
1331
1332 while (1) {
1333 cpu_exec_start(cs);
1334 trapnr = cpu_sparc_exec(cs);
1335 cpu_exec_end(cs);
1336
1337 /* Compute PSR before exposing state. */
1338 if (env->cc_op != CC_OP_FLAGS) {
1339 cpu_get_psr(env);
1340 }
1341
1342 switch (trapnr) {
1343 #ifndef TARGET_SPARC64
1344 case 0x88:
1345 case 0x90:
1346 #else
1347 case 0x110:
1348 case 0x16d:
1349 #endif
1350 ret = do_syscall (env, env->gregs[1],
1351 env->regwptr[0], env->regwptr[1],
1352 env->regwptr[2], env->regwptr[3],
1353 env->regwptr[4], env->regwptr[5],
1354 0, 0);
1355 if ((abi_ulong)ret >= (abi_ulong)(-515)) {
1356 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
1357 env->xcc |= PSR_CARRY;
1358 #else
1359 env->psr |= PSR_CARRY;
1360 #endif
1361 ret = -ret;
1362 } else {
1363 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
1364 env->xcc &= ~PSR_CARRY;
1365 #else
1366 env->psr &= ~PSR_CARRY;
1367 #endif
1368 }
1369 env->regwptr[0] = ret;
1370 /* next instruction */
1371 env->pc = env->npc;
1372 env->npc = env->npc + 4;
1373 break;
1374 case 0x83: /* flush windows */
1375 #ifdef TARGET_ABI32
1376 case 0x103:
1377 #endif
1378 flush_windows(env);
1379 /* next instruction */
1380 env->pc = env->npc;
1381 env->npc = env->npc + 4;
1382 break;
1383 #ifndef TARGET_SPARC64
1384 case TT_WIN_OVF: /* window overflow */
1385 save_window(env);
1386 break;
1387 case TT_WIN_UNF: /* window underflow */
1388 restore_window(env);
1389 break;
1390 case TT_TFAULT:
1391 case TT_DFAULT:
1392 {
1393 info.si_signo = TARGET_SIGSEGV;
1394 info.si_errno = 0;
1395 /* XXX: check env->error_code */
1396 info.si_code = TARGET_SEGV_MAPERR;
1397 info._sifields._sigfault._addr = env->mmuregs[4];
1398 queue_signal(env, info.si_signo, &info);
1399 }
1400 break;
1401 #else
1402 case TT_SPILL: /* window overflow */
1403 save_window(env);
1404 break;
1405 case TT_FILL: /* window underflow */
1406 restore_window(env);
1407 break;
1408 case TT_TFAULT:
1409 case TT_DFAULT:
1410 {
1411 info.si_signo = TARGET_SIGSEGV;
1412 info.si_errno = 0;
1413 /* XXX: check env->error_code */
1414 info.si_code = TARGET_SEGV_MAPERR;
1415 if (trapnr == TT_DFAULT)
1416 info._sifields._sigfault._addr = env->dmmuregs[4];
1417 else
1418 info._sifields._sigfault._addr = cpu_tsptr(env)->tpc;
1419 queue_signal(env, info.si_signo, &info);
1420 }
1421 break;
1422 #ifndef TARGET_ABI32
1423 case 0x16e:
1424 flush_windows(env);
1425 sparc64_get_context(env);
1426 break;
1427 case 0x16f:
1428 flush_windows(env);
1429 sparc64_set_context(env);
1430 break;
1431 #endif
1432 #endif
1433 case EXCP_INTERRUPT:
1434 /* just indicate that signals should be handled asap */
1435 break;
1436 case TT_ILL_INSN:
1437 {
1438 info.si_signo = TARGET_SIGILL;
1439 info.si_errno = 0;
1440 info.si_code = TARGET_ILL_ILLOPC;
1441 info._sifields._sigfault._addr = env->pc;
1442 queue_signal(env, info.si_signo, &info);
1443 }
1444 break;
1445 case EXCP_DEBUG:
1446 {
1447 int sig;
1448
1449 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1450 if (sig)
1451 {
1452 info.si_signo = sig;
1453 info.si_errno = 0;
1454 info.si_code = TARGET_TRAP_BRKPT;
1455 queue_signal(env, info.si_signo, &info);
1456 }
1457 }
1458 break;
1459 default:
1460 printf ("Unhandled trap: 0x%x\n", trapnr);
1461 cpu_dump_state(cs, stderr, fprintf, 0);
1462 exit(EXIT_FAILURE);
1463 }
1464 process_pending_signals (env);
1465 }
1466 }
1467
1468 #endif
1469
1470 #ifdef TARGET_PPC
1471 static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env)
1472 {
1473 return cpu_get_host_ticks();
1474 }
1475
1476 uint64_t cpu_ppc_load_tbl(CPUPPCState *env)
1477 {
1478 return cpu_ppc_get_tb(env);
1479 }
1480
1481 uint32_t cpu_ppc_load_tbu(CPUPPCState *env)
1482 {
1483 return cpu_ppc_get_tb(env) >> 32;
1484 }
1485
1486 uint64_t cpu_ppc_load_atbl(CPUPPCState *env)
1487 {
1488 return cpu_ppc_get_tb(env);
1489 }
1490
1491 uint32_t cpu_ppc_load_atbu(CPUPPCState *env)
1492 {
1493 return cpu_ppc_get_tb(env) >> 32;
1494 }
1495
1496 uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env)
1497 __attribute__ (( alias ("cpu_ppc_load_tbu") ));
1498
1499 uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env)
1500 {
1501 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
1502 }
1503
1504 /* XXX: to be fixed */
1505 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
1506 {
1507 return -1;
1508 }
1509
1510 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
1511 {
1512 return -1;
1513 }
1514
1515 static int do_store_exclusive(CPUPPCState *env)
1516 {
1517 target_ulong addr;
1518 target_ulong page_addr;
1519 target_ulong val, val2 __attribute__((unused)) = 0;
1520 int flags;
1521 int segv = 0;
1522
1523 addr = env->reserve_ea;
1524 page_addr = addr & TARGET_PAGE_MASK;
1525 start_exclusive();
1526 mmap_lock();
1527 flags = page_get_flags(page_addr);
1528 if ((flags & PAGE_READ) == 0) {
1529 segv = 1;
1530 } else {
1531 int reg = env->reserve_info & 0x1f;
1532 int size = env->reserve_info >> 5;
1533 int stored = 0;
1534
1535 if (addr == env->reserve_addr) {
1536 switch (size) {
1537 case 1: segv = get_user_u8(val, addr); break;
1538 case 2: segv = get_user_u16(val, addr); break;
1539 case 4: segv = get_user_u32(val, addr); break;
1540 #if defined(TARGET_PPC64)
1541 case 8: segv = get_user_u64(val, addr); break;
1542 case 16: {
1543 segv = get_user_u64(val, addr);
1544 if (!segv) {
1545 segv = get_user_u64(val2, addr + 8);
1546 }
1547 break;
1548 }
1549 #endif
1550 default: abort();
1551 }
1552 if (!segv && val == env->reserve_val) {
1553 val = env->gpr[reg];
1554 switch (size) {
1555 case 1: segv = put_user_u8(val, addr); break;
1556 case 2: segv = put_user_u16(val, addr); break;
1557 case 4: segv = put_user_u32(val, addr); break;
1558 #if defined(TARGET_PPC64)
1559 case 8: segv = put_user_u64(val, addr); break;
1560 case 16: {
1561 if (val2 == env->reserve_val2) {
1562 if (msr_le) {
1563 val2 = val;
1564 val = env->gpr[reg+1];
1565 } else {
1566 val2 = env->gpr[reg+1];
1567 }
1568 segv = put_user_u64(val, addr);
1569 if (!segv) {
1570 segv = put_user_u64(val2, addr + 8);
1571 }
1572 }
1573 break;
1574 }
1575 #endif
1576 default: abort();
1577 }
1578 if (!segv) {
1579 stored = 1;
1580 }
1581 }
1582 }
1583 env->crf[0] = (stored << 1) | xer_so;
1584 env->reserve_addr = (target_ulong)-1;
1585 }
1586 if (!segv) {
1587 env->nip += 4;
1588 }
1589 mmap_unlock();
1590 end_exclusive();
1591 return segv;
1592 }
1593
1594 void cpu_loop(CPUPPCState *env)
1595 {
1596 CPUState *cs = CPU(ppc_env_get_cpu(env));
1597 target_siginfo_t info;
1598 int trapnr;
1599 target_ulong ret;
1600
1601 for(;;) {
1602 cpu_exec_start(cs);
1603 trapnr = cpu_ppc_exec(cs);
1604 cpu_exec_end(cs);
1605 switch(trapnr) {
1606 case POWERPC_EXCP_NONE:
1607 /* Just go on */
1608 break;
1609 case POWERPC_EXCP_CRITICAL: /* Critical input */
1610 cpu_abort(cs, "Critical interrupt while in user mode. "
1611 "Aborting\n");
1612 break;
1613 case POWERPC_EXCP_MCHECK: /* Machine check exception */
1614 cpu_abort(cs, "Machine check exception while in user mode. "
1615 "Aborting\n");
1616 break;
1617 case POWERPC_EXCP_DSI: /* Data storage exception */
1618 EXCP_DUMP(env, "Invalid data memory access: 0x" TARGET_FMT_lx "\n",
1619 env->spr[SPR_DAR]);
1620 /* XXX: check this. Seems bugged */
1621 switch (env->error_code & 0xFF000000) {
1622 case 0x40000000:
1623 info.si_signo = TARGET_SIGSEGV;
1624 info.si_errno = 0;
1625 info.si_code = TARGET_SEGV_MAPERR;
1626 break;
1627 case 0x04000000:
1628 info.si_signo = TARGET_SIGILL;
1629 info.si_errno = 0;
1630 info.si_code = TARGET_ILL_ILLADR;
1631 break;
1632 case 0x08000000:
1633 info.si_signo = TARGET_SIGSEGV;
1634 info.si_errno = 0;
1635 info.si_code = TARGET_SEGV_ACCERR;
1636 break;
1637 default:
1638 /* Let's send a regular segfault... */
1639 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1640 env->error_code);
1641 info.si_signo = TARGET_SIGSEGV;
1642 info.si_errno = 0;
1643 info.si_code = TARGET_SEGV_MAPERR;
1644 break;
1645 }
1646 info._sifields._sigfault._addr = env->nip;
1647 queue_signal(env, info.si_signo, &info);
1648 break;
1649 case POWERPC_EXCP_ISI: /* Instruction storage exception */
1650 EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" TARGET_FMT_lx
1651 "\n", env->spr[SPR_SRR0]);
1652 /* XXX: check this */
1653 switch (env->error_code & 0xFF000000) {
1654 case 0x40000000:
1655 info.si_signo = TARGET_SIGSEGV;
1656 info.si_errno = 0;
1657 info.si_code = TARGET_SEGV_MAPERR;
1658 break;
1659 case 0x10000000:
1660 case 0x08000000:
1661 info.si_signo = TARGET_SIGSEGV;
1662 info.si_errno = 0;
1663 info.si_code = TARGET_SEGV_ACCERR;
1664 break;
1665 default:
1666 /* Let's send a regular segfault... */
1667 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1668 env->error_code);
1669 info.si_signo = TARGET_SIGSEGV;
1670 info.si_errno = 0;
1671 info.si_code = TARGET_SEGV_MAPERR;
1672 break;
1673 }
1674 info._sifields._sigfault._addr = env->nip - 4;
1675 queue_signal(env, info.si_signo, &info);
1676 break;
1677 case POWERPC_EXCP_EXTERNAL: /* External input */
1678 cpu_abort(cs, "External interrupt while in user mode. "
1679 "Aborting\n");
1680 break;
1681 case POWERPC_EXCP_ALIGN: /* Alignment exception */
1682 EXCP_DUMP(env, "Unaligned memory access\n");
1683 /* XXX: check this */
1684 info.si_signo = TARGET_SIGBUS;
1685 info.si_errno = 0;
1686 info.si_code = TARGET_BUS_ADRALN;
1687 info._sifields._sigfault._addr = env->nip;
1688 queue_signal(env, info.si_signo, &info);
1689 break;
1690 case POWERPC_EXCP_PROGRAM: /* Program exception */
1691 /* XXX: check this */
1692 switch (env->error_code & ~0xF) {
1693 case POWERPC_EXCP_FP:
1694 EXCP_DUMP(env, "Floating point program exception\n");
1695 info.si_signo = TARGET_SIGFPE;
1696 info.si_errno = 0;
1697 switch (env->error_code & 0xF) {
1698 case POWERPC_EXCP_FP_OX:
1699 info.si_code = TARGET_FPE_FLTOVF;
1700 break;
1701 case POWERPC_EXCP_FP_UX:
1702 info.si_code = TARGET_FPE_FLTUND;
1703 break;
1704 case POWERPC_EXCP_FP_ZX:
1705 case POWERPC_EXCP_FP_VXZDZ:
1706 info.si_code = TARGET_FPE_FLTDIV;
1707 break;
1708 case POWERPC_EXCP_FP_XX:
1709 info.si_code = TARGET_FPE_FLTRES;
1710 break;
1711 case POWERPC_EXCP_FP_VXSOFT:
1712 info.si_code = TARGET_FPE_FLTINV;
1713 break;
1714 case POWERPC_EXCP_FP_VXSNAN:
1715 case POWERPC_EXCP_FP_VXISI:
1716 case POWERPC_EXCP_FP_VXIDI:
1717 case POWERPC_EXCP_FP_VXIMZ:
1718 case POWERPC_EXCP_FP_VXVC:
1719 case POWERPC_EXCP_FP_VXSQRT:
1720 case POWERPC_EXCP_FP_VXCVI:
1721 info.si_code = TARGET_FPE_FLTSUB;
1722 break;
1723 default:
1724 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n",
1725 env->error_code);
1726 break;
1727 }
1728 break;
1729 case POWERPC_EXCP_INVAL:
1730 EXCP_DUMP(env, "Invalid instruction\n");
1731 info.si_signo = TARGET_SIGILL;
1732 info.si_errno = 0;
1733 switch (env->error_code & 0xF) {
1734 case POWERPC_EXCP_INVAL_INVAL:
1735 info.si_code = TARGET_ILL_ILLOPC;
1736 break;
1737 case POWERPC_EXCP_INVAL_LSWX:
1738 info.si_code = TARGET_ILL_ILLOPN;
1739 break;
1740 case POWERPC_EXCP_INVAL_SPR:
1741 info.si_code = TARGET_ILL_PRVREG;
1742 break;
1743 case POWERPC_EXCP_INVAL_FP:
1744 info.si_code = TARGET_ILL_COPROC;
1745 break;
1746 default:
1747 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n",
1748 env->error_code & 0xF);
1749 info.si_code = TARGET_ILL_ILLADR;
1750 break;
1751 }
1752 break;
1753 case POWERPC_EXCP_PRIV:
1754 EXCP_DUMP(env, "Privilege violation\n");
1755 info.si_signo = TARGET_SIGILL;
1756 info.si_errno = 0;
1757 switch (env->error_code & 0xF) {
1758 case POWERPC_EXCP_PRIV_OPC:
1759 info.si_code = TARGET_ILL_PRVOPC;
1760 break;
1761 case POWERPC_EXCP_PRIV_REG:
1762 info.si_code = TARGET_ILL_PRVREG;
1763 break;
1764 default:
1765 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n",
1766 env->error_code & 0xF);
1767 info.si_code = TARGET_ILL_PRVOPC;
1768 break;
1769 }
1770 break;
1771 case POWERPC_EXCP_TRAP:
1772 cpu_abort(cs, "Tried to call a TRAP\n");
1773 break;
1774 default:
1775 /* Should not happen ! */
1776 cpu_abort(cs, "Unknown program exception (%02x)\n",
1777 env->error_code);
1778 break;
1779 }
1780 info._sifields._sigfault._addr = env->nip - 4;
1781 queue_signal(env, info.si_signo, &info);
1782 break;
1783 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
1784 EXCP_DUMP(env, "No floating point allowed\n");
1785 info.si_signo = TARGET_SIGILL;
1786 info.si_errno = 0;
1787 info.si_code = TARGET_ILL_COPROC;
1788 info._sifields._sigfault._addr = env->nip - 4;
1789 queue_signal(env, info.si_signo, &info);
1790 break;
1791 case POWERPC_EXCP_SYSCALL: /* System call exception */
1792 cpu_abort(cs, "Syscall exception while in user mode. "
1793 "Aborting\n");
1794 break;
1795 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
1796 EXCP_DUMP(env, "No APU instruction allowed\n");
1797 info.si_signo = TARGET_SIGILL;
1798 info.si_errno = 0;
1799 info.si_code = TARGET_ILL_COPROC;
1800 info._sifields._sigfault._addr = env->nip - 4;
1801 queue_signal(env, info.si_signo, &info);
1802 break;
1803 case POWERPC_EXCP_DECR: /* Decrementer exception */
1804 cpu_abort(cs, "Decrementer interrupt while in user mode. "
1805 "Aborting\n");
1806 break;
1807 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
1808 cpu_abort(cs, "Fix interval timer interrupt while in user mode. "
1809 "Aborting\n");
1810 break;
1811 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
1812 cpu_abort(cs, "Watchdog timer interrupt while in user mode. "
1813 "Aborting\n");
1814 break;
1815 case POWERPC_EXCP_DTLB: /* Data TLB error */
1816 cpu_abort(cs, "Data TLB exception while in user mode. "
1817 "Aborting\n");
1818 break;
1819 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
1820 cpu_abort(cs, "Instruction TLB exception while in user mode. "
1821 "Aborting\n");
1822 break;
1823 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */
1824 EXCP_DUMP(env, "No SPE/floating-point instruction allowed\n");
1825 info.si_signo = TARGET_SIGILL;
1826 info.si_errno = 0;
1827 info.si_code = TARGET_ILL_COPROC;
1828 info._sifields._sigfault._addr = env->nip - 4;
1829 queue_signal(env, info.si_signo, &info);
1830 break;
1831 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */
1832 cpu_abort(cs, "Embedded floating-point data IRQ not handled\n");
1833 break;
1834 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */
1835 cpu_abort(cs, "Embedded floating-point round IRQ not handled\n");
1836 break;
1837 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */
1838 cpu_abort(cs, "Performance monitor exception not handled\n");
1839 break;
1840 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
1841 cpu_abort(cs, "Doorbell interrupt while in user mode. "
1842 "Aborting\n");
1843 break;
1844 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
1845 cpu_abort(cs, "Doorbell critical interrupt while in user mode. "
1846 "Aborting\n");
1847 break;
1848 case POWERPC_EXCP_RESET: /* System reset exception */
1849 cpu_abort(cs, "Reset interrupt while in user mode. "
1850 "Aborting\n");
1851 break;
1852 case POWERPC_EXCP_DSEG: /* Data segment exception */
1853 cpu_abort(cs, "Data segment exception while in user mode. "
1854 "Aborting\n");
1855 break;
1856 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
1857 cpu_abort(cs, "Instruction segment exception "
1858 "while in user mode. Aborting\n");
1859 break;
1860 /* PowerPC 64 with hypervisor mode support */
1861 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
1862 cpu_abort(cs, "Hypervisor decrementer interrupt "
1863 "while in user mode. Aborting\n");
1864 break;
1865 case POWERPC_EXCP_TRACE: /* Trace exception */
1866 /* Nothing to do:
1867 * we use this exception to emulate step-by-step execution mode.
1868 */
1869 break;
1870 /* PowerPC 64 with hypervisor mode support */
1871 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
1872 cpu_abort(cs, "Hypervisor data storage exception "
1873 "while in user mode. Aborting\n");
1874 break;
1875 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */
1876 cpu_abort(cs, "Hypervisor instruction storage exception "
1877 "while in user mode. Aborting\n");
1878 break;
1879 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
1880 cpu_abort(cs, "Hypervisor data segment exception "
1881 "while in user mode. Aborting\n");
1882 break;
1883 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */
1884 cpu_abort(cs, "Hypervisor instruction segment exception "
1885 "while in user mode. Aborting\n");
1886 break;
1887 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
1888 EXCP_DUMP(env, "No Altivec instructions allowed\n");
1889 info.si_signo = TARGET_SIGILL;
1890 info.si_errno = 0;
1891 info.si_code = TARGET_ILL_COPROC;
1892 info._sifields._sigfault._addr = env->nip - 4;
1893 queue_signal(env, info.si_signo, &info);
1894 break;
1895 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */
1896 cpu_abort(cs, "Programmable interval timer interrupt "
1897 "while in user mode. Aborting\n");
1898 break;
1899 case POWERPC_EXCP_IO: /* IO error exception */
1900 cpu_abort(cs, "IO error exception while in user mode. "
1901 "Aborting\n");
1902 break;
1903 case POWERPC_EXCP_RUNM: /* Run mode exception */
1904 cpu_abort(cs, "Run mode exception while in user mode. "
1905 "Aborting\n");
1906 break;
1907 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
1908 cpu_abort(cs, "Emulation trap exception not handled\n");
1909 break;
1910 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
1911 cpu_abort(cs, "Instruction fetch TLB exception "
1912 "while in user-mode. Aborting");
1913 break;
1914 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
1915 cpu_abort(cs, "Data load TLB exception while in user-mode. "
1916 "Aborting");
1917 break;
1918 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
1919 cpu_abort(cs, "Data store TLB exception while in user-mode. "
1920 "Aborting");
1921 break;
1922 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
1923 cpu_abort(cs, "Floating-point assist exception not handled\n");
1924 break;
1925 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
1926 cpu_abort(cs, "Instruction address breakpoint exception "
1927 "not handled\n");
1928 break;
1929 case POWERPC_EXCP_SMI: /* System management interrupt */
1930 cpu_abort(cs, "System management interrupt while in user mode. "
1931 "Aborting\n");
1932 break;
1933 case POWERPC_EXCP_THERM: /* Thermal interrupt */
1934 cpu_abort(cs, "Thermal interrupt interrupt while in user mode. "
1935 "Aborting\n");
1936 break;
1937 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */
1938 cpu_abort(cs, "Performance monitor exception not handled\n");
1939 break;
1940 case POWERPC_EXCP_VPUA: /* Vector assist exception */
1941 cpu_abort(cs, "Vector assist exception not handled\n");
1942 break;
1943 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
1944 cpu_abort(cs, "Soft patch exception not handled\n");
1945 break;
1946 case POWERPC_EXCP_MAINT: /* Maintenance exception */
1947 cpu_abort(cs, "Maintenance exception while in user mode. "
1948 "Aborting\n");
1949 break;
1950 case POWERPC_EXCP_STOP: /* stop translation */
1951 /* We did invalidate the instruction cache. Go on */
1952 break;
1953 case POWERPC_EXCP_BRANCH: /* branch instruction: */
1954 /* We just stopped because of a branch. Go on */
1955 break;
1956 case POWERPC_EXCP_SYSCALL_USER:
1957 /* system call in user-mode emulation */
1958 /* WARNING:
1959 * PPC ABI uses overflow flag in cr0 to signal an error
1960 * in syscalls.
1961 */
1962 env->crf[0] &= ~0x1;
1963 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4],
1964 env->gpr[5], env->gpr[6], env->gpr[7],
1965 env->gpr[8], 0, 0);
1966 if (ret == (target_ulong)(-TARGET_QEMU_ESIGRETURN)) {
1967 /* Returning from a successful sigreturn syscall.
1968 Avoid corrupting register state. */
1969 break;
1970 }
1971 if (ret > (target_ulong)(-515)) {
1972 env->crf[0] |= 0x1;
1973 ret = -ret;
1974 }
1975 env->gpr[3] = ret;
1976 break;
1977 case POWERPC_EXCP_STCX:
1978 if (do_store_exclusive(env)) {
1979 info.si_signo = TARGET_SIGSEGV;
1980 info.si_errno = 0;
1981 info.si_code = TARGET_SEGV_MAPERR;
1982 info._sifields._sigfault._addr = env->nip;
1983 queue_signal(env, info.si_signo, &info);
1984 }
1985 break;
1986 case EXCP_DEBUG:
1987 {
1988 int sig;
1989
1990 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1991 if (sig) {
1992 info.si_signo = sig;
1993 info.si_errno = 0;
1994 info.si_code = TARGET_TRAP_BRKPT;
1995 queue_signal(env, info.si_signo, &info);
1996 }
1997 }
1998 break;
1999 case EXCP_INTERRUPT:
2000 /* just indicate that signals should be handled asap */
2001 break;
2002 default:
2003 cpu_abort(cs, "Unknown exception 0x%d. Aborting\n", trapnr);
2004 break;
2005 }
2006 process_pending_signals(env);
2007 }
2008 }
2009 #endif
2010
2011 #ifdef TARGET_MIPS
2012
2013 # ifdef TARGET_ABI_MIPSO32
2014 # define MIPS_SYS(name, args) args,
2015 static const uint8_t mips_syscall_args[] = {
2016 MIPS_SYS(sys_syscall , 8) /* 4000 */
2017 MIPS_SYS(sys_exit , 1)
2018 MIPS_SYS(sys_fork , 0)
2019 MIPS_SYS(sys_read , 3)
2020 MIPS_SYS(sys_write , 3)
2021 MIPS_SYS(sys_open , 3) /* 4005 */
2022 MIPS_SYS(sys_close , 1)
2023 MIPS_SYS(sys_waitpid , 3)
2024 MIPS_SYS(sys_creat , 2)
2025 MIPS_SYS(sys_link , 2)
2026 MIPS_SYS(sys_unlink , 1) /* 4010 */
2027 MIPS_SYS(sys_execve , 0)
2028 MIPS_SYS(sys_chdir , 1)
2029 MIPS_SYS(sys_time , 1)
2030 MIPS_SYS(sys_mknod , 3)
2031 MIPS_SYS(sys_chmod , 2) /* 4015 */
2032 MIPS_SYS(sys_lchown , 3)
2033 MIPS_SYS(sys_ni_syscall , 0)
2034 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */
2035 MIPS_SYS(sys_lseek , 3)
2036 MIPS_SYS(sys_getpid , 0) /* 4020 */
2037 MIPS_SYS(sys_mount , 5)
2038 MIPS_SYS(sys_umount , 1)
2039 MIPS_SYS(sys_setuid , 1)
2040 MIPS_SYS(sys_getuid , 0)
2041 MIPS_SYS(sys_stime , 1) /* 4025 */
2042 MIPS_SYS(sys_ptrace , 4)
2043 MIPS_SYS(sys_alarm , 1)
2044 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */
2045 MIPS_SYS(sys_pause , 0)
2046 MIPS_SYS(sys_utime , 2) /* 4030 */
2047 MIPS_SYS(sys_ni_syscall , 0)
2048 MIPS_SYS(sys_ni_syscall , 0)
2049 MIPS_SYS(sys_access , 2)
2050 MIPS_SYS(sys_nice , 1)
2051 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */
2052 MIPS_SYS(sys_sync , 0)
2053 MIPS_SYS(sys_kill , 2)
2054 MIPS_SYS(sys_rename , 2)
2055 MIPS_SYS(sys_mkdir , 2)
2056 MIPS_SYS(sys_rmdir , 1) /* 4040 */
2057 MIPS_SYS(sys_dup , 1)
2058 MIPS_SYS(sys_pipe , 0)
2059 MIPS_SYS(sys_times , 1)
2060 MIPS_SYS(sys_ni_syscall , 0)
2061 MIPS_SYS(sys_brk , 1) /* 4045 */
2062 MIPS_SYS(sys_setgid , 1)
2063 MIPS_SYS(sys_getgid , 0)
2064 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */
2065 MIPS_SYS(sys_geteuid , 0)
2066 MIPS_SYS(sys_getegid , 0) /* 4050 */
2067 MIPS_SYS(sys_acct , 0)
2068 MIPS_SYS(sys_umount2 , 2)
2069 MIPS_SYS(sys_ni_syscall , 0)
2070 MIPS_SYS(sys_ioctl , 3)
2071 MIPS_SYS(sys_fcntl , 3) /* 4055 */
2072 MIPS_SYS(sys_ni_syscall , 2)
2073 MIPS_SYS(sys_setpgid , 2)
2074 MIPS_SYS(sys_ni_syscall , 0)
2075 MIPS_SYS(sys_olduname , 1)
2076 MIPS_SYS(sys_umask , 1) /* 4060 */
2077 MIPS_SYS(sys_chroot , 1)
2078 MIPS_SYS(sys_ustat , 2)
2079 MIPS_SYS(sys_dup2 , 2)
2080 MIPS_SYS(sys_getppid , 0)
2081 MIPS_SYS(sys_getpgrp , 0) /* 4065 */
2082 MIPS_SYS(sys_setsid , 0)
2083 MIPS_SYS(sys_sigaction , 3)
2084 MIPS_SYS(sys_sgetmask , 0)
2085 MIPS_SYS(sys_ssetmask , 1)
2086 MIPS_SYS(sys_setreuid , 2) /* 4070 */
2087 MIPS_SYS(sys_setregid , 2)
2088 MIPS_SYS(sys_sigsuspend , 0)
2089 MIPS_SYS(sys_sigpending , 1)
2090 MIPS_SYS(sys_sethostname , 2)
2091 MIPS_SYS(sys_setrlimit , 2) /* 4075 */
2092 MIPS_SYS(sys_getrlimit , 2)
2093 MIPS_SYS(sys_getrusage , 2)
2094 MIPS_SYS(sys_gettimeofday, 2)
2095 MIPS_SYS(sys_settimeofday, 2)
2096 MIPS_SYS(sys_getgroups , 2) /* 4080 */
2097 MIPS_SYS(sys_setgroups , 2)
2098 MIPS_SYS(sys_ni_syscall , 0) /* old_select */
2099 MIPS_SYS(sys_symlink , 2)
2100 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */
2101 MIPS_SYS(sys_readlink , 3) /* 4085 */
2102 MIPS_SYS(sys_uselib , 1)
2103 MIPS_SYS(sys_swapon , 2)
2104 MIPS_SYS(sys_reboot , 3)
2105 MIPS_SYS(old_readdir , 3)
2106 MIPS_SYS(old_mmap , 6) /* 4090 */
2107 MIPS_SYS(sys_munmap , 2)
2108 MIPS_SYS(sys_truncate , 2)
2109 MIPS_SYS(sys_ftruncate , 2)
2110 MIPS_SYS(sys_fchmod , 2)
2111 MIPS_SYS(sys_fchown , 3) /* 4095 */
2112 MIPS_SYS(sys_getpriority , 2)
2113 MIPS_SYS(sys_setpriority , 3)
2114 MIPS_SYS(sys_ni_syscall , 0)
2115 MIPS_SYS(sys_statfs , 2)
2116 MIPS_SYS(sys_fstatfs , 2) /* 4100 */
2117 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */
2118 MIPS_SYS(sys_socketcall , 2)
2119 MIPS_SYS(sys_syslog , 3)
2120 MIPS_SYS(sys_setitimer , 3)
2121 MIPS_SYS(sys_getitimer , 2) /* 4105 */
2122 MIPS_SYS(sys_newstat , 2)
2123 MIPS_SYS(sys_newlstat , 2)
2124 MIPS_SYS(sys_newfstat , 2)
2125 MIPS_SYS(sys_uname , 1)
2126 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */
2127 MIPS_SYS(sys_vhangup , 0)
2128 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */
2129 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */
2130 MIPS_SYS(sys_wait4 , 4)
2131 MIPS_SYS(sys_swapoff , 1) /* 4115 */
2132 MIPS_SYS(sys_sysinfo , 1)
2133 MIPS_SYS(sys_ipc , 6)
2134 MIPS_SYS(sys_fsync , 1)
2135 MIPS_SYS(sys_sigreturn , 0)
2136 MIPS_SYS(sys_clone , 6) /* 4120 */
2137 MIPS_SYS(sys_setdomainname, 2)
2138 MIPS_SYS(sys_newuname , 1)
2139 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */
2140 MIPS_SYS(sys_adjtimex , 1)
2141 MIPS_SYS(sys_mprotect , 3) /* 4125 */
2142 MIPS_SYS(sys_sigprocmask , 3)
2143 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */
2144 MIPS_SYS(sys_init_module , 5)
2145 MIPS_SYS(sys_delete_module, 1)
2146 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */
2147 MIPS_SYS(sys_quotactl , 0)
2148 MIPS_SYS(sys_getpgid , 1)
2149 MIPS_SYS(sys_fchdir , 1)
2150 MIPS_SYS(sys_bdflush , 2)
2151 MIPS_SYS(sys_sysfs , 3) /* 4135 */
2152 MIPS_SYS(sys_personality , 1)
2153 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */
2154 MIPS_SYS(sys_setfsuid , 1)
2155 MIPS_SYS(sys_setfsgid , 1)
2156 MIPS_SYS(sys_llseek , 5) /* 4140 */
2157 MIPS_SYS(sys_getdents , 3)
2158 MIPS_SYS(sys_select , 5)
2159 MIPS_SYS(sys_flock , 2)
2160 MIPS_SYS(sys_msync , 3)
2161 MIPS_SYS(sys_readv , 3) /* 4145 */
2162 MIPS_SYS(sys_writev , 3)
2163 MIPS_SYS(sys_cacheflush , 3)
2164 MIPS_SYS(sys_cachectl , 3)
2165 MIPS_SYS(sys_sysmips , 4)
2166 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */
2167 MIPS_SYS(sys_getsid , 1)
2168 MIPS_SYS(sys_fdatasync , 0)
2169 MIPS_SYS(sys_sysctl , 1)
2170 MIPS_SYS(sys_mlock , 2)
2171 MIPS_SYS(sys_munlock , 2) /* 4155 */
2172 MIPS_SYS(sys_mlockall , 1)
2173 MIPS_SYS(sys_munlockall , 0)
2174 MIPS_SYS(sys_sched_setparam, 2)
2175 MIPS_SYS(sys_sched_getparam, 2)
2176 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */
2177 MIPS_SYS(sys_sched_getscheduler, 1)
2178 MIPS_SYS(sys_sched_yield , 0)
2179 MIPS_SYS(sys_sched_get_priority_max, 1)
2180 MIPS_SYS(sys_sched_get_priority_min, 1)
2181 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */
2182 MIPS_SYS(sys_nanosleep, 2)
2183 MIPS_SYS(sys_mremap , 5)
2184 MIPS_SYS(sys_accept , 3)
2185 MIPS_SYS(sys_bind , 3)
2186 MIPS_SYS(sys_connect , 3) /* 4170 */
2187 MIPS_SYS(sys_getpeername , 3)
2188 MIPS_SYS(sys_getsockname , 3)
2189 MIPS_SYS(sys_getsockopt , 5)
2190 MIPS_SYS(sys_listen , 2)
2191 MIPS_SYS(sys_recv , 4) /* 4175 */
2192 MIPS_SYS(sys_recvfrom , 6)
2193 MIPS_SYS(sys_recvmsg , 3)
2194 MIPS_SYS(sys_send , 4)
2195 MIPS_SYS(sys_sendmsg , 3)
2196 MIPS_SYS(sys_sendto , 6) /* 4180 */
2197 MIPS_SYS(sys_setsockopt , 5)
2198 MIPS_SYS(sys_shutdown , 2)
2199 MIPS_SYS(sys_socket , 3)
2200 MIPS_SYS(sys_socketpair , 4)
2201 MIPS_SYS(sys_setresuid , 3) /* 4185 */
2202 MIPS_SYS(sys_getresuid , 3)
2203 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */
2204 MIPS_SYS(sys_poll , 3)
2205 MIPS_SYS(sys_nfsservctl , 3)
2206 MIPS_SYS(sys_setresgid , 3) /* 4190 */
2207 MIPS_SYS(sys_getresgid , 3)
2208 MIPS_SYS(sys_prctl , 5)
2209 MIPS_SYS(sys_rt_sigreturn, 0)
2210 MIPS_SYS(sys_rt_sigaction, 4)
2211 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */
2212 MIPS_SYS(sys_rt_sigpending, 2)
2213 MIPS_SYS(sys_rt_sigtimedwait, 4)
2214 MIPS_SYS(sys_rt_sigqueueinfo, 3)
2215 MIPS_SYS(sys_rt_sigsuspend, 0)
2216 MIPS_SYS(sys_pread64 , 6) /* 4200 */
2217 MIPS_SYS(sys_pwrite64 , 6)
2218 MIPS_SYS(sys_chown , 3)
2219 MIPS_SYS(sys_getcwd , 2)
2220 MIPS_SYS(sys_capget , 2)
2221 MIPS_SYS(sys_capset , 2) /* 4205 */
2222 MIPS_SYS(sys_sigaltstack , 2)
2223 MIPS_SYS(sys_sendfile , 4)
2224 MIPS_SYS(sys_ni_syscall , 0)
2225 MIPS_SYS(sys_ni_syscall , 0)
2226 MIPS_SYS(sys_mmap2 , 6) /* 4210 */
2227 MIPS_SYS(sys_truncate64 , 4)
2228 MIPS_SYS(sys_ftruncate64 , 4)
2229 MIPS_SYS(sys_stat64 , 2)
2230 MIPS_SYS(sys_lstat64 , 2)
2231 MIPS_SYS(sys_fstat64 , 2) /* 4215 */
2232 MIPS_SYS(sys_pivot_root , 2)
2233 MIPS_SYS(sys_mincore , 3)
2234 MIPS_SYS(sys_madvise , 3)
2235 MIPS_SYS(sys_getdents64 , 3)
2236 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */
2237 MIPS_SYS(sys_ni_syscall , 0)
2238 MIPS_SYS(sys_gettid , 0)
2239 MIPS_SYS(sys_readahead , 5)
2240 MIPS_SYS(sys_setxattr , 5)
2241 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */
2242 MIPS_SYS(sys_fsetxattr , 5)
2243 MIPS_SYS(sys_getxattr , 4)
2244 MIPS_SYS(sys_lgetxattr , 4)
2245 MIPS_SYS(sys_fgetxattr , 4)
2246 MIPS_SYS(sys_listxattr , 3) /* 4230 */
2247 MIPS_SYS(sys_llistxattr , 3)
2248 MIPS_SYS(sys_flistxattr , 3)
2249 MIPS_SYS(sys_removexattr , 2)
2250 MIPS_SYS(sys_lremovexattr, 2)
2251 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */
2252 MIPS_SYS(sys_tkill , 2)
2253 MIPS_SYS(sys_sendfile64 , 5)
2254 MIPS_SYS(sys_futex , 6)
2255 MIPS_SYS(sys_sched_setaffinity, 3)
2256 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */
2257 MIPS_SYS(sys_io_setup , 2)
2258 MIPS_SYS(sys_io_destroy , 1)
2259 MIPS_SYS(sys_io_getevents, 5)
2260 MIPS_SYS(sys_io_submit , 3)
2261 MIPS_SYS(sys_io_cancel , 3) /* 4245 */
2262 MIPS_SYS(sys_exit_group , 1)
2263 MIPS_SYS(sys_lookup_dcookie, 3)
2264 MIPS_SYS(sys_epoll_create, 1)
2265 MIPS_SYS(sys_epoll_ctl , 4)
2266 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */
2267 MIPS_SYS(sys_remap_file_pages, 5)
2268 MIPS_SYS(sys_set_tid_address, 1)
2269 MIPS_SYS(sys_restart_syscall, 0)
2270 MIPS_SYS(sys_fadvise64_64, 7)
2271 MIPS_SYS(sys_statfs64 , 3) /* 4255 */
2272 MIPS_SYS(sys_fstatfs64 , 2)
2273 MIPS_SYS(sys_timer_create, 3)
2274 MIPS_SYS(sys_timer_settime, 4)
2275 MIPS_SYS(sys_timer_gettime, 2)
2276 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */
2277 MIPS_SYS(sys_timer_delete, 1)
2278 MIPS_SYS(sys_clock_settime, 2)
2279 MIPS_SYS(sys_clock_gettime, 2)
2280 MIPS_SYS(sys_clock_getres, 2)
2281 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */
2282 MIPS_SYS(sys_tgkill , 3)
2283 MIPS_SYS(sys_utimes , 2)
2284 MIPS_SYS(sys_mbind , 4)
2285 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */
2286 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */
2287 MIPS_SYS(sys_mq_open , 4)
2288 MIPS_SYS(sys_mq_unlink , 1)
2289 MIPS_SYS(sys_mq_timedsend, 5)
2290 MIPS_SYS(sys_mq_timedreceive, 5)
2291 MIPS_SYS(sys_mq_notify , 2) /* 4275 */
2292 MIPS_SYS(sys_mq_getsetattr, 3)
2293 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */
2294 MIPS_SYS(sys_waitid , 4)
2295 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */
2296 MIPS_SYS(sys_add_key , 5)
2297 MIPS_SYS(sys_request_key, 4)
2298 MIPS_SYS(sys_keyctl , 5)
2299 MIPS_SYS(sys_set_thread_area, 1)
2300 MIPS_SYS(sys_inotify_init, 0)
2301 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */
2302 MIPS_SYS(sys_inotify_rm_watch, 2)
2303 MIPS_SYS(sys_migrate_pages, 4)
2304 MIPS_SYS(sys_openat, 4)
2305 MIPS_SYS(sys_mkdirat, 3)
2306 MIPS_SYS(sys_mknodat, 4) /* 4290 */
2307 MIPS_SYS(sys_fchownat, 5)
2308 MIPS_SYS(sys_futimesat, 3)
2309 MIPS_SYS(sys_fstatat64, 4)
2310 MIPS_SYS(sys_unlinkat, 3)
2311 MIPS_SYS(sys_renameat, 4) /* 4295 */
2312 MIPS_SYS(sys_linkat, 5)
2313 MIPS_SYS(sys_symlinkat, 3)
2314 MIPS_SYS(sys_readlinkat, 4)
2315 MIPS_SYS(sys_fchmodat, 3)
2316 MIPS_SYS(sys_faccessat, 3) /* 4300 */
2317 MIPS_SYS(sys_pselect6, 6)
2318 MIPS_SYS(sys_ppoll, 5)
2319 MIPS_SYS(sys_unshare, 1)
2320 MIPS_SYS(sys_splice, 6)
2321 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */
2322 MIPS_SYS(sys_tee, 4)
2323 MIPS_SYS(sys_vmsplice, 4)
2324 MIPS_SYS(sys_move_pages, 6)
2325 MIPS_SYS(sys_set_robust_list, 2)
2326 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */
2327 MIPS_SYS(sys_kexec_load, 4)
2328 MIPS_SYS(sys_getcpu, 3)
2329 MIPS_SYS(sys_epoll_pwait, 6)
2330 MIPS_SYS(sys_ioprio_set, 3)
2331 MIPS_SYS(sys_ioprio_get, 2)
2332 MIPS_SYS(sys_utimensat, 4)
2333 MIPS_SYS(sys_signalfd, 3)
2334 MIPS_SYS(sys_ni_syscall, 0) /* was timerfd */
2335 MIPS_SYS(sys_eventfd, 1)
2336 MIPS_SYS(sys_fallocate, 6) /* 4320 */
2337 MIPS_SYS(sys_timerfd_create, 2)
2338 MIPS_SYS(sys_timerfd_gettime, 2)
2339 MIPS_SYS(sys_timerfd_settime, 4)
2340 MIPS_SYS(sys_signalfd4, 4)
2341 MIPS_SYS(sys_eventfd2, 2) /* 4325 */
2342 MIPS_SYS(sys_epoll_create1, 1)
2343 MIPS_SYS(sys_dup3, 3)
2344 MIPS_SYS(sys_pipe2, 2)
2345 MIPS_SYS(sys_inotify_init1, 1)
2346 MIPS_SYS(sys_preadv, 6) /* 4330 */
2347 MIPS_SYS(sys_pwritev, 6)
2348 MIPS_SYS(sys_rt_tgsigqueueinfo, 4)
2349 MIPS_SYS(sys_perf_event_open, 5)
2350 MIPS_SYS(sys_accept4, 4)
2351 MIPS_SYS(sys_recvmmsg, 5) /* 4335 */
2352 MIPS_SYS(sys_fanotify_init, 2)
2353 MIPS_SYS(sys_fanotify_mark, 6)
2354 MIPS_SYS(sys_prlimit64, 4)
2355 MIPS_SYS(sys_name_to_handle_at, 5)
2356 MIPS_SYS(sys_open_by_handle_at, 3) /* 4340 */
2357 MIPS_SYS(sys_clock_adjtime, 2)
2358 MIPS_SYS(sys_syncfs, 1)
2359 };
2360 # undef MIPS_SYS
2361 # endif /* O32 */
2362
2363 static int do_store_exclusive(CPUMIPSState *env)
2364 {
2365 target_ulong addr;
2366 target_ulong page_addr;
2367 target_ulong val;
2368 int flags;
2369 int segv = 0;
2370 int reg;
2371 int d;
2372
2373 addr = env->lladdr;
2374 page_addr = addr & TARGET_PAGE_MASK;
2375 start_exclusive();
2376 mmap_lock();
2377 flags = page_get_flags(page_addr);
2378 if ((flags & PAGE_READ) == 0) {
2379 segv = 1;
2380 } else {
2381 reg = env->llreg & 0x1f;
2382 d = (env->llreg & 0x20) != 0;
2383 if (d) {
2384 segv = get_user_s64(val, addr);
2385 } else {
2386 segv = get_user_s32(val, addr);
2387 }
2388 if (!segv) {
2389 if (val != env->llval) {
2390 env->active_tc.gpr[reg] = 0;
2391 } else {
2392 if (d) {
2393 segv = put_user_u64(env->llnewval, addr);
2394 } else {
2395 segv = put_user_u32(env->llnewval, addr);
2396 }
2397 if (!segv) {
2398 env->active_tc.gpr[reg] = 1;
2399 }
2400 }
2401 }
2402 }
2403 env->lladdr = -1;
2404 if (!segv) {
2405 env->active_tc.PC += 4;
2406 }
2407 mmap_unlock();
2408 end_exclusive();
2409 return segv;
2410 }
2411
2412 /* Break codes */
2413 enum {
2414 BRK_OVERFLOW = 6,
2415 BRK_DIVZERO = 7
2416 };
2417
2418 static int do_break(CPUMIPSState *env, target_siginfo_t *info,
2419 unsigned int code)
2420 {
2421 int ret = -1;
2422
2423 switch (code) {
2424 case BRK_OVERFLOW:
2425 case BRK_DIVZERO:
2426 info->si_signo = TARGET_SIGFPE;
2427 info->si_errno = 0;
2428 info->si_code = (code == BRK_OVERFLOW) ? FPE_INTOVF : FPE_INTDIV;
2429 queue_signal(env, info->si_signo, &*info);
2430 ret = 0;
2431 break;
2432 default:
2433 info->si_signo = TARGET_SIGTRAP;
2434 info->si_errno = 0;
2435 queue_signal(env, info->si_signo, &*info);
2436 ret = 0;
2437 break;
2438 }
2439
2440 return ret;
2441 }
2442
2443 void cpu_loop(CPUMIPSState *env)
2444 {
2445 CPUState *cs = CPU(mips_env_get_cpu(env));
2446 target_siginfo_t info;
2447 int trapnr;
2448 abi_long ret;
2449 # ifdef TARGET_ABI_MIPSO32
2450 unsigned int syscall_num;
2451 # endif
2452
2453 for(;;) {
2454 cpu_exec_start(cs);
2455 trapnr = cpu_mips_exec(cs);
2456 cpu_exec_end(cs);
2457 switch(trapnr) {
2458 case EXCP_SYSCALL:
2459 env->active_tc.PC += 4;
2460 # ifdef TARGET_ABI_MIPSO32
2461 syscall_num = env->active_tc.gpr[2] - 4000;
2462 if (syscall_num >= sizeof(mips_syscall_args)) {
2463 ret = -TARGET_ENOSYS;
2464 } else {
2465 int nb_args;
2466 abi_ulong sp_reg;
2467 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;
2468
2469 nb_args = mips_syscall_args[syscall_num];
2470 sp_reg = env->active_tc.gpr[29];
2471 switch (nb_args) {
2472 /* these arguments are taken from the stack */
2473 case 8:
2474 if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) {
2475 goto done_syscall;
2476 }
2477 case 7:
2478 if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) {
2479 goto done_syscall;
2480 }
2481 case 6:
2482 if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) {
2483 goto done_syscall;
2484 }
2485 case 5:
2486 if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) {
2487 goto done_syscall;
2488 }
2489 default:
2490 break;
2491 }
2492 ret = do_syscall(env, env->active_tc.gpr[2],
2493 env->active_tc.gpr[4],
2494 env->active_tc.gpr[5],
2495 env->active_tc.gpr[6],
2496 env->active_tc.gpr[7],
2497 arg5, arg6, arg7, arg8);
2498 }
2499 done_syscall:
2500 # else
2501 ret = do_syscall(env, env->active_tc.gpr[2],
2502 env->active_tc.gpr[4], env->active_tc.gpr[5],
2503 env->active_tc.gpr[6], env->active_tc.gpr[7],
2504 env->active_tc.gpr[8], env->active_tc.gpr[9],
2505 env->active_tc.gpr[10], env->active_tc.gpr[11]);
2506 # endif /* O32 */
2507 if (ret == -TARGET_QEMU_ESIGRETURN) {
2508 /* Returning from a successful sigreturn syscall.
2509 Avoid clobbering register state. */
2510 break;
2511 }
2512 if ((abi_ulong)ret >= (abi_ulong)-1133) {
2513 env->active_tc.gpr[7] = 1; /* error flag */
2514 ret = -ret;
2515 } else {
2516 env->active_tc.gpr[7] = 0; /* error flag */
2517 }
2518 env->active_tc.gpr[2] = ret;
2519 break;
2520 case EXCP_TLBL:
2521 case EXCP_TLBS:
2522 case EXCP_AdEL:
2523 case EXCP_AdES:
2524 info.si_signo = TARGET_SIGSEGV;
2525 info.si_errno = 0;
2526 /* XXX: check env->error_code */
2527 info.si_code = TARGET_SEGV_MAPERR;
2528 info._sifields._sigfault._addr = env->CP0_BadVAddr;
2529 queue_signal(env, info.si_signo, &info);
2530 break;
2531 case EXCP_CpU:
2532 case EXCP_RI:
2533 info.si_signo = TARGET_SIGILL;
2534 info.si_errno = 0;
2535 info.si_code = 0;
2536 queue_signal(env, info.si_signo, &info);
2537 break;
2538 case EXCP_INTERRUPT:
2539 /* just indicate that signals should be handled asap */
2540 break;
2541 case EXCP_DEBUG:
2542 {
2543 int sig;
2544
2545 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2546 if (sig)
2547 {
2548 info.si_signo = sig;
2549 info.si_errno = 0;
2550 info.si_code = TARGET_TRAP_BRKPT;
2551 queue_signal(env, info.si_signo, &info);
2552 }
2553 }
2554 break;
2555 case EXCP_SC:
2556 if (do_store_exclusive(env)) {
2557 info.si_signo = TARGET_SIGSEGV;
2558 info.si_errno = 0;
2559 info.si_code = TARGET_SEGV_MAPERR;
2560 info._sifields._sigfault._addr = env->active_tc.PC;
2561 queue_signal(env, info.si_signo, &info);
2562 }
2563 break;
2564 case EXCP_DSPDIS:
2565 info.si_signo = TARGET_SIGILL;
2566 info.si_errno = 0;
2567 info.si_code = TARGET_ILL_ILLOPC;
2568 queue_signal(env, info.si_signo, &info);
2569 break;
2570 /* The code below was inspired by the MIPS Linux kernel trap
2571 * handling code in arch/mips/kernel/traps.c.
2572 */
2573 case EXCP_BREAK:
2574 {
2575 abi_ulong trap_instr;
2576 unsigned int code;
2577
2578 if (env->hflags & MIPS_HFLAG_M16) {
2579 if (env->insn_flags & ASE_MICROMIPS) {
2580 /* microMIPS mode */
2581 ret = get_user_u16(trap_instr, env->active_tc.PC);
2582 if (ret != 0) {
2583 goto error;
2584 }
2585
2586 if ((trap_instr >> 10) == 0x11) {
2587 /* 16-bit instruction */
2588 code = trap_instr & 0xf;
2589 } else {
2590 /* 32-bit instruction */
2591 abi_ulong instr_lo;
2592
2593 ret = get_user_u16(instr_lo,
2594 env->active_tc.PC + 2);
2595 if (ret != 0) {
2596 goto error;
2597 }
2598 trap_instr = (trap_instr << 16) | instr_lo;
2599 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2600 /* Unfortunately, microMIPS also suffers from
2601 the old assembler bug... */
2602 if (code >= (1 << 10)) {
2603 code >>= 10;
2604 }
2605 }
2606 } else {
2607 /* MIPS16e mode */
2608 ret = get_user_u16(trap_instr, env->active_tc.PC);
2609 if (ret != 0) {
2610 goto error;
2611 }
2612 code = (trap_instr >> 6) & 0x3f;
2613 }
2614 } else {
2615 ret = get_user_u32(trap_instr, env->active_tc.PC);
2616 if (ret != 0) {
2617 goto error;
2618 }
2619
2620 /* As described in the original Linux kernel code, the
2621 * below checks on 'code' are to work around an old
2622 * assembly bug.
2623 */
2624 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2625 if (code >= (1 << 10)) {
2626 code >>= 10;
2627 }
2628 }
2629
2630 if (do_break(env, &info, code) != 0) {
2631 goto error;
2632 }
2633 }
2634 break;
2635 case EXCP_TRAP:
2636 {
2637 abi_ulong trap_instr;
2638 unsigned int code = 0;
2639
2640 if (env->hflags & MIPS_HFLAG_M16) {
2641 /* microMIPS mode */
2642 abi_ulong instr[2];
2643
2644 ret = get_user_u16(instr[0], env->active_tc.PC) ||
2645 get_user_u16(instr[1], env->active_tc.PC + 2);
2646
2647 trap_instr = (instr[0] << 16) | instr[1];
2648 } else {
2649 ret = get_user_u32(trap_instr, env->active_tc.PC);
2650 }
2651
2652 if (ret != 0) {
2653 goto error;
2654 }
2655
2656 /* The immediate versions don't provide a code. */
2657 if (!(trap_instr & 0xFC000000)) {
2658 if (env->hflags & MIPS_HFLAG_M16) {
2659 /* microMIPS mode */
2660 code = ((trap_instr >> 12) & ((1 << 4) - 1));
2661 } else {
2662 code = ((trap_instr >> 6) & ((1 << 10) - 1));
2663 }
2664 }
2665
2666 if (do_break(env, &info, code) != 0) {
2667 goto error;
2668 }
2669 }
2670 break;
2671 default:
2672 error:
2673 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
2674 abort();
2675 }
2676 process_pending_signals(env);
2677 }
2678 }
2679 #endif
2680
2681 #ifdef TARGET_OPENRISC
2682
2683 void cpu_loop(CPUOpenRISCState *env)
2684 {
2685 CPUState *cs = CPU(openrisc_env_get_cpu(env));
2686 int trapnr, gdbsig;
2687
2688 for (;;) {
2689 cpu_exec_start(cs);
2690 trapnr = cpu_openrisc_exec(cs);
2691 cpu_exec_end(cs);
2692 gdbsig = 0;
2693
2694 switch (trapnr) {
2695 case EXCP_RESET:
2696 qemu_log_mask(CPU_LOG_INT, "\nReset request, exit, pc is %#x\n", env->pc);
2697 exit(EXIT_FAILURE);
2698 break;
2699 case EXCP_BUSERR:
2700 qemu_log_mask(CPU_LOG_INT, "\nBus error, exit, pc is %#x\n", env->pc);
2701 gdbsig = TARGET_SIGBUS;
2702 break;
2703 case EXCP_DPF:
2704 case EXCP_IPF:
2705 cpu_dump_state(cs, stderr, fprintf, 0);
2706 gdbsig = TARGET_SIGSEGV;
2707 break;
2708 case EXCP_TICK:
2709 qemu_log_mask(CPU_LOG_INT, "\nTick time interrupt pc is %#x\n", env->pc);
2710 break;
2711 case EXCP_ALIGN:
2712 qemu_log_mask(CPU_LOG_INT, "\nAlignment pc is %#x\n", env->pc);
2713 gdbsig = TARGET_SIGBUS;
2714 break;
2715 case EXCP_ILLEGAL:
2716 qemu_log_mask(CPU_LOG_INT, "\nIllegal instructionpc is %#x\n", env->pc);
2717 gdbsig = TARGET_SIGILL;
2718 break;
2719 case EXCP_INT:
2720 qemu_log_mask(CPU_LOG_INT, "\nExternal interruptpc is %#x\n", env->pc);
2721 break;
2722 case EXCP_DTLBMISS:
2723 case EXCP_ITLBMISS:
2724 qemu_log_mask(CPU_LOG_INT, "\nTLB miss\n");
2725 break;
2726 case EXCP_RANGE:
2727 qemu_log_mask(CPU_LOG_INT, "\nRange\n");
2728 gdbsig = TARGET_SIGSEGV;
2729 break;
2730 case EXCP_SYSCALL:
2731 env->pc += 4; /* 0xc00; */
2732 env->gpr[11] = do_syscall(env,
2733 env->gpr[11], /* return value */
2734 env->gpr[3], /* r3 - r7 are params */
2735 env->gpr[4],
2736 env->gpr[5],
2737 env->gpr[6],
2738 env->gpr[7],
2739 env->gpr[8], 0, 0);
2740 break;
2741 case EXCP_FPE:
2742 qemu_log_mask(CPU_LOG_INT, "\nFloating point error\n");
2743 break;
2744 case EXCP_TRAP:
2745 qemu_log_mask(CPU_LOG_INT, "\nTrap\n");
2746 gdbsig = TARGET_SIGTRAP;
2747 break;
2748 case EXCP_NR:
2749 qemu_log_mask(CPU_LOG_INT, "\nNR\n");
2750 break;
2751 default:
2752 EXCP_DUMP(env, "\nqemu: unhandled CPU exception %#x - aborting\n",
2753 trapnr);
2754 gdbsig = TARGET_SIGILL;
2755 break;
2756 }
2757 if (gdbsig) {
2758 gdb_handlesig(cs, gdbsig);
2759 if (gdbsig != TARGET_SIGTRAP) {
2760 exit(EXIT_FAILURE);
2761 }
2762 }
2763
2764 process_pending_signals(env);
2765 }
2766 }
2767
2768 #endif /* TARGET_OPENRISC */
2769
2770 #ifdef TARGET_SH4
2771 void cpu_loop(CPUSH4State *env)
2772 {
2773 CPUState *cs = CPU(sh_env_get_cpu(env));
2774 int trapnr, ret;
2775 target_siginfo_t info;
2776
2777 while (1) {
2778 cpu_exec_start(cs);
2779 trapnr = cpu_sh4_exec(cs);
2780 cpu_exec_end(cs);
2781
2782 switch (trapnr) {
2783 case 0x160:
2784 env->pc += 2;
2785 ret = do_syscall(env,
2786 env->gregs[3],
2787 env->gregs[4],
2788 env->gregs[5],
2789 env->gregs[6],
2790 env->gregs[7],
2791 env->gregs[0],
2792 env->gregs[1],
2793 0, 0);
2794 env->gregs[0] = ret;
2795 break;
2796 case EXCP_INTERRUPT:
2797 /* just indicate that signals should be handled asap */
2798 break;
2799 case EXCP_DEBUG:
2800 {
2801 int sig;
2802
2803 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2804 if (sig)
2805 {
2806 info.si_signo = sig;
2807 info.si_errno = 0;
2808 info.si_code = TARGET_TRAP_BRKPT;
2809 queue_signal(env, info.si_signo, &info);
2810 }
2811 }
2812 break;
2813 case 0xa0:
2814 case 0xc0:
2815 info.si_signo = TARGET_SIGSEGV;
2816 info.si_errno = 0;
2817 info.si_code = TARGET_SEGV_MAPERR;
2818 info._sifields._sigfault._addr = env->tea;
2819 queue_signal(env, info.si_signo, &info);
2820 break;
2821
2822 default:
2823 printf ("Unhandled trap: 0x%x\n", trapnr);
2824 cpu_dump_state(cs, stderr, fprintf, 0);
2825 exit(EXIT_FAILURE);
2826 }
2827 process_pending_signals (env);
2828 }
2829 }
2830 #endif
2831
2832 #ifdef TARGET_CRIS
2833 void cpu_loop(CPUCRISState *env)
2834 {
2835 CPUState *cs = CPU(cris_env_get_cpu(env));
2836 int trapnr, ret;
2837 target_siginfo_t info;
2838
2839 while (1) {
2840 cpu_exec_start(cs);
2841 trapnr = cpu_cris_exec(cs);
2842 cpu_exec_end(cs);
2843 switch (trapnr) {
2844 case 0xaa:
2845 {
2846 info.si_signo = TARGET_SIGSEGV;
2847 info.si_errno = 0;
2848 /* XXX: check env->error_code */
2849 info.si_code = TARGET_SEGV_MAPERR;
2850 info._sifields._sigfault._addr = env->pregs[PR_EDA];
2851 queue_signal(env, info.si_signo, &info);
2852 }
2853 break;
2854 case EXCP_INTERRUPT:
2855 /* just indicate that signals should be handled asap */
2856 break;
2857 case EXCP_BREAK:
2858 ret = do_syscall(env,
2859 env->regs[9],
2860 env->regs[10],
2861 env->regs[11],
2862 env->regs[12],
2863 env->regs[13],
2864 env->pregs[7],
2865 env->pregs[11],
2866 0, 0);
2867 env->regs[10] = ret;
2868 break;
2869 case EXCP_DEBUG:
2870 {
2871 int sig;
2872
2873 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2874 if (sig)
2875 {
2876 info.si_signo = sig;
2877 info.si_errno = 0;
2878 info.si_code = TARGET_TRAP_BRKPT;
2879 queue_signal(env, info.si_signo, &info);
2880 }
2881 }
2882 break;
2883 default:
2884 printf ("Unhandled trap: 0x%x\n", trapnr);
2885 cpu_dump_state(cs, stderr, fprintf, 0);
2886 exit(EXIT_FAILURE);
2887 }
2888 process_pending_signals (env);
2889 }
2890 }
2891 #endif
2892
2893 #ifdef TARGET_MICROBLAZE
2894 void cpu_loop(CPUMBState *env)
2895 {
2896 CPUState *cs = CPU(mb_env_get_cpu(env));
2897 int trapnr, ret;
2898 target_siginfo_t info;
2899
2900 while (1) {
2901 cpu_exec_start(cs);
2902 trapnr = cpu_mb_exec(cs);
2903 cpu_exec_end(cs);
2904 switch (trapnr) {
2905 case 0xaa:
2906 {
2907 info.si_signo = TARGET_SIGSEGV;
2908 info.si_errno = 0;
2909 /* XXX: check env->error_code */
2910 info.si_code = TARGET_SEGV_MAPERR;
2911 info._sifields._sigfault._addr = 0;
2912 queue_signal(env, info.si_signo, &info);
2913 }
2914 break;
2915 case EXCP_INTERRUPT:
2916 /* just indicate that signals should be handled asap */
2917 break;
2918 case EXCP_BREAK:
2919 /* Return address is 4 bytes after the call. */
2920 env->regs[14] += 4;
2921 env->sregs[SR_PC] = env->regs[14];
2922 ret = do_syscall(env,
2923 env->regs[12],
2924 env->regs[5],
2925 env->regs[6],
2926 env->regs[7],
2927 env->regs[8],
2928 env->regs[9],
2929 env->regs[10],
2930 0, 0);
2931 env->regs[3] = ret;
2932 break;
2933 case EXCP_HW_EXCP:
2934 env->regs[17] = env->sregs[SR_PC] + 4;
2935 if (env->iflags & D_FLAG) {
2936 env->sregs[SR_ESR] |= 1 << 12;
2937 env->sregs[SR_PC] -= 4;
2938 /* FIXME: if branch was immed, replay the imm as well. */
2939 }
2940
2941 env->iflags &= ~(IMM_FLAG | D_FLAG);
2942
2943 switch (env->sregs[SR_ESR] & 31) {
2944 case ESR_EC_DIVZERO:
2945 info.si_signo = TARGET_SIGFPE;
2946 info.si_errno = 0;
2947 info.si_code = TARGET_FPE_FLTDIV;
2948 info._sifields._sigfault._addr = 0;
2949 queue_signal(env, info.si_signo, &info);
2950 break;
2951 case ESR_EC_FPU:
2952 info.si_signo = TARGET_SIGFPE;
2953 info.si_errno = 0;
2954 if (env->sregs[SR_FSR] & FSR_IO) {
2955 info.si_code = TARGET_FPE_FLTINV;
2956 }
2957 if (env->sregs[SR_FSR] & FSR_DZ) {
2958 info.si_code = TARGET_FPE_FLTDIV;
2959 }
2960 info._sifields._sigfault._addr = 0;
2961 queue_signal(env, info.si_signo, &info);
2962 break;
2963 default:
2964 printf ("Unhandled hw-exception: 0x%x\n",
2965 env->sregs[SR_ESR] & ESR_EC_MASK);
2966 cpu_dump_state(cs, stderr, fprintf, 0);
2967 exit(EXIT_FAILURE);
2968 break;
2969 }
2970 break;
2971 case EXCP_DEBUG:
2972 {
2973 int sig;
2974
2975 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2976 if (sig)
2977 {
2978 info.si_signo = sig;
2979 info.si_errno = 0;
2980 info.si_code = TARGET_TRAP_BRKPT;
2981 queue_signal(env, info.si_signo, &info);
2982 }
2983 }
2984 break;
2985 default:
2986 printf ("Unhandled trap: 0x%x\n", trapnr);
2987 cpu_dump_state(cs, stderr, fprintf, 0);
2988 exit(EXIT_FAILURE);
2989 }
2990 process_pending_signals (env);
2991 }
2992 }
2993 #endif
2994
2995 #ifdef TARGET_M68K
2996
2997 void cpu_loop(CPUM68KState *env)
2998 {
2999 CPUState *cs = CPU(m68k_env_get_cpu(env));
3000 int trapnr;
3001 unsigned int n;
3002 target_siginfo_t info;
3003 TaskState *ts = cs->opaque;
3004
3005 for(;;) {
3006 cpu_exec_start(cs);
3007 trapnr = cpu_m68k_exec(cs);
3008 cpu_exec_end(cs);
3009 switch(trapnr) {
3010 case EXCP_ILLEGAL:
3011 {
3012 if (ts->sim_syscalls) {
3013 uint16_t nr;
3014 get_user_u16(nr, env->pc + 2);
3015 env->pc += 4;
3016 do_m68k_simcall(env, nr);
3017 } else {
3018 goto do_sigill;
3019 }
3020 }
3021 break;
3022 case EXCP_HALT_INSN:
3023 /* Semihosing syscall. */
3024 env->pc += 4;
3025 do_m68k_semihosting(env, env->dregs[0]);
3026 break;
3027 case EXCP_LINEA:
3028 case EXCP_LINEF:
3029 case EXCP_UNSUPPORTED:
3030 do_sigill:
3031 info.si_signo = TARGET_SIGILL;
3032 info.si_errno = 0;
3033 info.si_code = TARGET_ILL_ILLOPN;
3034 info._sifields._sigfault._addr = env->pc;
3035 queue_signal(env, info.si_signo, &info);
3036 break;
3037 case EXCP_TRAP0:
3038 {
3039 ts->sim_syscalls = 0;
3040 n = env->dregs[0];
3041 env->pc += 2;
3042 env->dregs[0] = do_syscall(env,
3043 n,
3044 env->dregs[1],
3045 env->dregs[2],
3046 env->dregs[3],
3047 env->dregs[4],
3048 env->dregs[5],
3049 env->aregs[0],
3050 0, 0);
3051 }
3052 break;
3053 case EXCP_INTERRUPT:
3054 /* just indicate that signals should be handled asap */
3055 break;
3056 case EXCP_ACCESS:
3057 {
3058 info.si_signo = TARGET_SIGSEGV;
3059 info.si_errno = 0;
3060 /* XXX: check env->error_code */
3061 info.si_code = TARGET_SEGV_MAPERR;
3062 info._sifields._sigfault._addr = env->mmu.ar;
3063 queue_signal(env, info.si_signo, &info);
3064 }
3065 break;
3066 case EXCP_DEBUG:
3067 {
3068 int sig;
3069
3070 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
3071 if (sig)
3072 {
3073 info.si_signo = sig;
3074 info.si_errno = 0;
3075 info.si_code = TARGET_TRAP_BRKPT;
3076 queue_signal(env, info.si_signo, &info);
3077 }
3078 }
3079 break;
3080 default:
3081 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
3082 abort();
3083 }
3084 process_pending_signals(env);
3085 }
3086 }
3087 #endif /* TARGET_M68K */
3088
3089 #ifdef TARGET_ALPHA
3090 static void do_store_exclusive(CPUAlphaState *env, int reg, int quad)
3091 {
3092 target_ulong addr, val, tmp;
3093 target_siginfo_t info;
3094 int ret = 0;
3095
3096 addr = env->lock_addr;
3097 tmp = env->lock_st_addr;
3098 env->lock_addr = -1;
3099 env->lock_st_addr = 0;
3100
3101 start_exclusive();
3102 mmap_lock();
3103
3104 if (addr == tmp) {
3105 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3106 goto do_sigsegv;
3107 }
3108
3109 if (val == env->lock_value) {
3110 tmp = env->ir[reg];
3111 if (quad ? put_user_u64(tmp, addr) : put_user_u32(tmp, addr)) {
3112 goto do_sigsegv;
3113 }
3114 ret = 1;
3115 }
3116 }
3117 env->ir[reg] = ret;
3118 env->pc += 4;
3119
3120 mmap_unlock();
3121 end_exclusive();
3122 return;
3123
3124 do_sigsegv:
3125 mmap_unlock();
3126 end_exclusive();
3127
3128 info.si_signo = TARGET_SIGSEGV;
3129 info.si_errno = 0;
3130 info.si_code = TARGET_SEGV_MAPERR;
3131 info._sifields._sigfault._addr = addr;
3132 queue_signal(env, TARGET_SIGSEGV, &info);
3133 }
3134
3135 void cpu_loop(CPUAlphaState *env)
3136 {
3137 CPUState *cs = CPU(alpha_env_get_cpu(env));
3138 int trapnr;
3139 target_siginfo_t info;
3140 abi_long sysret;
3141
3142 while (1) {
3143 cpu_exec_start(cs);
3144 trapnr = cpu_alpha_exec(cs);
3145 cpu_exec_end(cs);
3146
3147 /* All of the traps imply a transition through PALcode, which
3148 implies an REI instruction has been executed. Which means
3149 that the intr_flag should be cleared. */
3150 env->intr_flag = 0;
3151
3152 switch (trapnr) {
3153 case EXCP_RESET:
3154 fprintf(stderr, "Reset requested. Exit\n");
3155 exit(EXIT_FAILURE);
3156 break;
3157 case EXCP_MCHK:
3158 fprintf(stderr, "Machine check exception. Exit\n");
3159 exit(EXIT_FAILURE);
3160 break;
3161 case EXCP_SMP_INTERRUPT:
3162 case EXCP_CLK_INTERRUPT:
3163 case EXCP_DEV_INTERRUPT:
3164 fprintf(stderr, "External interrupt. Exit\n");
3165 exit(EXIT_FAILURE);
3166 break;
3167 case EXCP_MMFAULT:
3168 env->lock_addr = -1;
3169 info.si_signo = TARGET_SIGSEGV;
3170 info.si_errno = 0;
3171 info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID
3172 ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR);
3173 info._sifields._sigfault._addr = env->trap_arg0;
3174 queue_signal(env, info.si_signo, &info);
3175 break;
3176 case EXCP_UNALIGN:
3177 env->lock_addr = -1;
3178 info.si_signo = TARGET_SIGBUS;
3179 info.si_errno = 0;
3180 info.si_code = TARGET_BUS_ADRALN;
3181 info._sifields._sigfault._addr = env->trap_arg0;
3182 queue_signal(env, info.si_signo, &info);
3183 break;
3184 case EXCP_OPCDEC:
3185 do_sigill:
3186 env->lock_addr = -1;
3187 info.si_signo = TARGET_SIGILL;
3188 info.si_errno = 0;
3189 info.si_code = TARGET_ILL_ILLOPC;
3190 info._sifields._sigfault._addr = env->pc;
3191 queue_signal(env, info.si_signo, &info);
3192 break;
3193 case EXCP_ARITH:
3194 env->lock_addr = -1;
3195 info.si_signo = TARGET_SIGFPE;
3196 info.si_errno = 0;
3197 info.si_code = TARGET_FPE_FLTINV;
3198 info._sifields._sigfault._addr = env->pc;
3199 queue_signal(env, info.si_signo, &info);
3200 break;
3201 case EXCP_FEN:
3202 /* No-op. Linux simply re-enables the FPU. */
3203 break;
3204 case EXCP_CALL_PAL:
3205 env->lock_addr = -1;
3206 switch (env->error_code) {
3207 case 0x80:
3208 /* BPT */
3209 info.si_signo = TARGET_SIGTRAP;
3210 info.si_errno = 0;
3211 info.si_code = TARGET_TRAP_BRKPT;
3212 info._sifields._sigfault._addr = env->pc;
3213 queue_signal(env, info.si_signo, &info);
3214 break;
3215 case 0x81:
3