linux-user: Support for restarting system calls for MIPS targets
[qemu.git] / linux-user / main.c
1 /*
2 * qemu user main
3 *
4 * Copyright (c) 2003-2008 Fabrice Bellard
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "qemu/osdep.h"
20 #include <sys/mman.h>
21 #include <sys/syscall.h>
22 #include <sys/resource.h>
23
24 #include "qemu.h"
25 #include "qemu/path.h"
26 #include "qemu/cutils.h"
27 #include "qemu/help_option.h"
28 #include "cpu.h"
29 #include "exec/exec-all.h"
30 #include "tcg.h"
31 #include "qemu/timer.h"
32 #include "qemu/envlist.h"
33 #include "elf.h"
34 #include "exec/log.h"
35
36 char *exec_path;
37
38 int singlestep;
39 static const char *filename;
40 static const char *argv0;
41 static int gdbstub_port;
42 static envlist_t *envlist;
43 static const char *cpu_model;
44 unsigned long mmap_min_addr;
45 unsigned long guest_base;
46 int have_guest_base;
47
48 #define EXCP_DUMP(env, fmt, ...) \
49 do { \
50 CPUState *cs = ENV_GET_CPU(env); \
51 fprintf(stderr, fmt , ## __VA_ARGS__); \
52 cpu_dump_state(cs, stderr, fprintf, 0); \
53 if (qemu_log_separate()) { \
54 qemu_log(fmt, ## __VA_ARGS__); \
55 log_cpu_state(cs, 0); \
56 } \
57 } while (0)
58
59 #if (TARGET_LONG_BITS == 32) && (HOST_LONG_BITS == 64)
60 /*
61 * When running 32-on-64 we should make sure we can fit all of the possible
62 * guest address space into a contiguous chunk of virtual host memory.
63 *
64 * This way we will never overlap with our own libraries or binaries or stack
65 * or anything else that QEMU maps.
66 */
67 # ifdef TARGET_MIPS
68 /* MIPS only supports 31 bits of virtual address space for user space */
69 unsigned long reserved_va = 0x77000000;
70 # else
71 unsigned long reserved_va = 0xf7000000;
72 # endif
73 #else
74 unsigned long reserved_va;
75 #endif
76
77 static void usage(int exitcode);
78
79 static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX;
80 const char *qemu_uname_release;
81
82 /* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so
83 we allocate a bigger stack. Need a better solution, for example
84 by remapping the process stack directly at the right place */
85 unsigned long guest_stack_size = 8 * 1024 * 1024UL;
86
87 void gemu_log(const char *fmt, ...)
88 {
89 va_list ap;
90
91 va_start(ap, fmt);
92 vfprintf(stderr, fmt, ap);
93 va_end(ap);
94 }
95
96 #if defined(TARGET_I386)
97 int cpu_get_pic_interrupt(CPUX86State *env)
98 {
99 return -1;
100 }
101 #endif
102
103 /***********************************************************/
104 /* Helper routines for implementing atomic operations. */
105
106 /* To implement exclusive operations we force all cpus to syncronise.
107 We don't require a full sync, only that no cpus are executing guest code.
108 The alternative is to map target atomic ops onto host equivalents,
109 which requires quite a lot of per host/target work. */
110 static pthread_mutex_t cpu_list_mutex = PTHREAD_MUTEX_INITIALIZER;
111 static pthread_mutex_t exclusive_lock = PTHREAD_MUTEX_INITIALIZER;
112 static pthread_cond_t exclusive_cond = PTHREAD_COND_INITIALIZER;
113 static pthread_cond_t exclusive_resume = PTHREAD_COND_INITIALIZER;
114 static int pending_cpus;
115
116 /* Make sure everything is in a consistent state for calling fork(). */
117 void fork_start(void)
118 {
119 qemu_mutex_lock(&tcg_ctx.tb_ctx.tb_lock);
120 pthread_mutex_lock(&exclusive_lock);
121 mmap_fork_start();
122 }
123
124 void fork_end(int child)
125 {
126 mmap_fork_end(child);
127 if (child) {
128 CPUState *cpu, *next_cpu;
129 /* Child processes created by fork() only have a single thread.
130 Discard information about the parent threads. */
131 CPU_FOREACH_SAFE(cpu, next_cpu) {
132 if (cpu != thread_cpu) {
133 QTAILQ_REMOVE(&cpus, thread_cpu, node);
134 }
135 }
136 pending_cpus = 0;
137 pthread_mutex_init(&exclusive_lock, NULL);
138 pthread_mutex_init(&cpu_list_mutex, NULL);
139 pthread_cond_init(&exclusive_cond, NULL);
140 pthread_cond_init(&exclusive_resume, NULL);
141 qemu_mutex_init(&tcg_ctx.tb_ctx.tb_lock);
142 gdbserver_fork(thread_cpu);
143 } else {
144 pthread_mutex_unlock(&exclusive_lock);
145 qemu_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock);
146 }
147 }
148
149 /* Wait for pending exclusive operations to complete. The exclusive lock
150 must be held. */
151 static inline void exclusive_idle(void)
152 {
153 while (pending_cpus) {
154 pthread_cond_wait(&exclusive_resume, &exclusive_lock);
155 }
156 }
157
158 /* Start an exclusive operation.
159 Must only be called from outside cpu_arm_exec. */
160 static inline void start_exclusive(void)
161 {
162 CPUState *other_cpu;
163
164 pthread_mutex_lock(&exclusive_lock);
165 exclusive_idle();
166
167 pending_cpus = 1;
168 /* Make all other cpus stop executing. */
169 CPU_FOREACH(other_cpu) {
170 if (other_cpu->running) {
171 pending_cpus++;
172 cpu_exit(other_cpu);
173 }
174 }
175 if (pending_cpus > 1) {
176 pthread_cond_wait(&exclusive_cond, &exclusive_lock);
177 }
178 }
179
180 /* Finish an exclusive operation. */
181 static inline void __attribute__((unused)) end_exclusive(void)
182 {
183 pending_cpus = 0;
184 pthread_cond_broadcast(&exclusive_resume);
185 pthread_mutex_unlock(&exclusive_lock);
186 }
187
188 /* Wait for exclusive ops to finish, and begin cpu execution. */
189 static inline void cpu_exec_start(CPUState *cpu)
190 {
191 pthread_mutex_lock(&exclusive_lock);
192 exclusive_idle();
193 cpu->running = true;
194 pthread_mutex_unlock(&exclusive_lock);
195 }
196
197 /* Mark cpu as not executing, and release pending exclusive ops. */
198 static inline void cpu_exec_end(CPUState *cpu)
199 {
200 pthread_mutex_lock(&exclusive_lock);
201 cpu->running = false;
202 if (pending_cpus > 1) {
203 pending_cpus--;
204 if (pending_cpus == 1) {
205 pthread_cond_signal(&exclusive_cond);
206 }
207 }
208 exclusive_idle();
209 pthread_mutex_unlock(&exclusive_lock);
210 }
211
212 void cpu_list_lock(void)
213 {
214 pthread_mutex_lock(&cpu_list_mutex);
215 }
216
217 void cpu_list_unlock(void)
218 {
219 pthread_mutex_unlock(&cpu_list_mutex);
220 }
221
222
223 #ifdef TARGET_I386
224 /***********************************************************/
225 /* CPUX86 core interface */
226
227 uint64_t cpu_get_tsc(CPUX86State *env)
228 {
229 return cpu_get_host_ticks();
230 }
231
232 static void write_dt(void *ptr, unsigned long addr, unsigned long limit,
233 int flags)
234 {
235 unsigned int e1, e2;
236 uint32_t *p;
237 e1 = (addr << 16) | (limit & 0xffff);
238 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000);
239 e2 |= flags;
240 p = ptr;
241 p[0] = tswap32(e1);
242 p[1] = tswap32(e2);
243 }
244
245 static uint64_t *idt_table;
246 #ifdef TARGET_X86_64
247 static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,
248 uint64_t addr, unsigned int sel)
249 {
250 uint32_t *p, e1, e2;
251 e1 = (addr & 0xffff) | (sel << 16);
252 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
253 p = ptr;
254 p[0] = tswap32(e1);
255 p[1] = tswap32(e2);
256 p[2] = tswap32(addr >> 32);
257 p[3] = 0;
258 }
259 /* only dpl matters as we do only user space emulation */
260 static void set_idt(int n, unsigned int dpl)
261 {
262 set_gate64(idt_table + n * 2, 0, dpl, 0, 0);
263 }
264 #else
265 static void set_gate(void *ptr, unsigned int type, unsigned int dpl,
266 uint32_t addr, unsigned int sel)
267 {
268 uint32_t *p, e1, e2;
269 e1 = (addr & 0xffff) | (sel << 16);
270 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
271 p = ptr;
272 p[0] = tswap32(e1);
273 p[1] = tswap32(e2);
274 }
275
276 /* only dpl matters as we do only user space emulation */
277 static void set_idt(int n, unsigned int dpl)
278 {
279 set_gate(idt_table + n, 0, dpl, 0, 0);
280 }
281 #endif
282
283 void cpu_loop(CPUX86State *env)
284 {
285 CPUState *cs = CPU(x86_env_get_cpu(env));
286 int trapnr;
287 abi_ulong pc;
288 abi_ulong ret;
289 target_siginfo_t info;
290
291 for(;;) {
292 cpu_exec_start(cs);
293 trapnr = cpu_x86_exec(cs);
294 cpu_exec_end(cs);
295 switch(trapnr) {
296 case 0x80:
297 /* linux syscall from int $0x80 */
298 ret = do_syscall(env,
299 env->regs[R_EAX],
300 env->regs[R_EBX],
301 env->regs[R_ECX],
302 env->regs[R_EDX],
303 env->regs[R_ESI],
304 env->regs[R_EDI],
305 env->regs[R_EBP],
306 0, 0);
307 if (ret == -TARGET_ERESTARTSYS) {
308 env->eip -= 2;
309 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
310 env->regs[R_EAX] = ret;
311 }
312 break;
313 #ifndef TARGET_ABI32
314 case EXCP_SYSCALL:
315 /* linux syscall from syscall instruction */
316 ret = do_syscall(env,
317 env->regs[R_EAX],
318 env->regs[R_EDI],
319 env->regs[R_ESI],
320 env->regs[R_EDX],
321 env->regs[10],
322 env->regs[8],
323 env->regs[9],
324 0, 0);
325 if (ret == -TARGET_ERESTARTSYS) {
326 env->eip -= 2;
327 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
328 env->regs[R_EAX] = ret;
329 }
330 break;
331 #endif
332 case EXCP0B_NOSEG:
333 case EXCP0C_STACK:
334 info.si_signo = TARGET_SIGBUS;
335 info.si_errno = 0;
336 info.si_code = TARGET_SI_KERNEL;
337 info._sifields._sigfault._addr = 0;
338 queue_signal(env, info.si_signo, &info);
339 break;
340 case EXCP0D_GPF:
341 /* XXX: potential problem if ABI32 */
342 #ifndef TARGET_X86_64
343 if (env->eflags & VM_MASK) {
344 handle_vm86_fault(env);
345 } else
346 #endif
347 {
348 info.si_signo = TARGET_SIGSEGV;
349 info.si_errno = 0;
350 info.si_code = TARGET_SI_KERNEL;
351 info._sifields._sigfault._addr = 0;
352 queue_signal(env, info.si_signo, &info);
353 }
354 break;
355 case EXCP0E_PAGE:
356 info.si_signo = TARGET_SIGSEGV;
357 info.si_errno = 0;
358 if (!(env->error_code & 1))
359 info.si_code = TARGET_SEGV_MAPERR;
360 else
361 info.si_code = TARGET_SEGV_ACCERR;
362 info._sifields._sigfault._addr = env->cr[2];
363 queue_signal(env, info.si_signo, &info);
364 break;
365 case EXCP00_DIVZ:
366 #ifndef TARGET_X86_64
367 if (env->eflags & VM_MASK) {
368 handle_vm86_trap(env, trapnr);
369 } else
370 #endif
371 {
372 /* division by zero */
373 info.si_signo = TARGET_SIGFPE;
374 info.si_errno = 0;
375 info.si_code = TARGET_FPE_INTDIV;
376 info._sifields._sigfault._addr = env->eip;
377 queue_signal(env, info.si_signo, &info);
378 }
379 break;
380 case EXCP01_DB:
381 case EXCP03_INT3:
382 #ifndef TARGET_X86_64
383 if (env->eflags & VM_MASK) {
384 handle_vm86_trap(env, trapnr);
385 } else
386 #endif
387 {
388 info.si_signo = TARGET_SIGTRAP;
389 info.si_errno = 0;
390 if (trapnr == EXCP01_DB) {
391 info.si_code = TARGET_TRAP_BRKPT;
392 info._sifields._sigfault._addr = env->eip;
393 } else {
394 info.si_code = TARGET_SI_KERNEL;
395 info._sifields._sigfault._addr = 0;
396 }
397 queue_signal(env, info.si_signo, &info);
398 }
399 break;
400 case EXCP04_INTO:
401 case EXCP05_BOUND:
402 #ifndef TARGET_X86_64
403 if (env->eflags & VM_MASK) {
404 handle_vm86_trap(env, trapnr);
405 } else
406 #endif
407 {
408 info.si_signo = TARGET_SIGSEGV;
409 info.si_errno = 0;
410 info.si_code = TARGET_SI_KERNEL;
411 info._sifields._sigfault._addr = 0;
412 queue_signal(env, info.si_signo, &info);
413 }
414 break;
415 case EXCP06_ILLOP:
416 info.si_signo = TARGET_SIGILL;
417 info.si_errno = 0;
418 info.si_code = TARGET_ILL_ILLOPN;
419 info._sifields._sigfault._addr = env->eip;
420 queue_signal(env, info.si_signo, &info);
421 break;
422 case EXCP_INTERRUPT:
423 /* just indicate that signals should be handled asap */
424 break;
425 case EXCP_DEBUG:
426 {
427 int sig;
428
429 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
430 if (sig)
431 {
432 info.si_signo = sig;
433 info.si_errno = 0;
434 info.si_code = TARGET_TRAP_BRKPT;
435 queue_signal(env, info.si_signo, &info);
436 }
437 }
438 break;
439 default:
440 pc = env->segs[R_CS].base + env->eip;
441 EXCP_DUMP(env, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
442 (long)pc, trapnr);
443 abort();
444 }
445 process_pending_signals(env);
446 }
447 }
448 #endif
449
450 #ifdef TARGET_ARM
451
452 #define get_user_code_u32(x, gaddr, env) \
453 ({ abi_long __r = get_user_u32((x), (gaddr)); \
454 if (!__r && bswap_code(arm_sctlr_b(env))) { \
455 (x) = bswap32(x); \
456 } \
457 __r; \
458 })
459
460 #define get_user_code_u16(x, gaddr, env) \
461 ({ abi_long __r = get_user_u16((x), (gaddr)); \
462 if (!__r && bswap_code(arm_sctlr_b(env))) { \
463 (x) = bswap16(x); \
464 } \
465 __r; \
466 })
467
468 #define get_user_data_u32(x, gaddr, env) \
469 ({ abi_long __r = get_user_u32((x), (gaddr)); \
470 if (!__r && arm_cpu_bswap_data(env)) { \
471 (x) = bswap32(x); \
472 } \
473 __r; \
474 })
475
476 #define get_user_data_u16(x, gaddr, env) \
477 ({ abi_long __r = get_user_u16((x), (gaddr)); \
478 if (!__r && arm_cpu_bswap_data(env)) { \
479 (x) = bswap16(x); \
480 } \
481 __r; \
482 })
483
484 #define put_user_data_u32(x, gaddr, env) \
485 ({ typeof(x) __x = (x); \
486 if (arm_cpu_bswap_data(env)) { \
487 __x = bswap32(__x); \
488 } \
489 put_user_u32(__x, (gaddr)); \
490 })
491
492 #define put_user_data_u16(x, gaddr, env) \
493 ({ typeof(x) __x = (x); \
494 if (arm_cpu_bswap_data(env)) { \
495 __x = bswap16(__x); \
496 } \
497 put_user_u16(__x, (gaddr)); \
498 })
499
500 #ifdef TARGET_ABI32
501 /* Commpage handling -- there is no commpage for AArch64 */
502
503 /*
504 * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt
505 * Input:
506 * r0 = pointer to oldval
507 * r1 = pointer to newval
508 * r2 = pointer to target value
509 *
510 * Output:
511 * r0 = 0 if *ptr was changed, non-0 if no exchange happened
512 * C set if *ptr was changed, clear if no exchange happened
513 *
514 * Note segv's in kernel helpers are a bit tricky, we can set the
515 * data address sensibly but the PC address is just the entry point.
516 */
517 static void arm_kernel_cmpxchg64_helper(CPUARMState *env)
518 {
519 uint64_t oldval, newval, val;
520 uint32_t addr, cpsr;
521 target_siginfo_t info;
522
523 /* Based on the 32 bit code in do_kernel_trap */
524
525 /* XXX: This only works between threads, not between processes.
526 It's probably possible to implement this with native host
527 operations. However things like ldrex/strex are much harder so
528 there's not much point trying. */
529 start_exclusive();
530 cpsr = cpsr_read(env);
531 addr = env->regs[2];
532
533 if (get_user_u64(oldval, env->regs[0])) {
534 env->exception.vaddress = env->regs[0];
535 goto segv;
536 };
537
538 if (get_user_u64(newval, env->regs[1])) {
539 env->exception.vaddress = env->regs[1];
540 goto segv;
541 };
542
543 if (get_user_u64(val, addr)) {
544 env->exception.vaddress = addr;
545 goto segv;
546 }
547
548 if (val == oldval) {
549 val = newval;
550
551 if (put_user_u64(val, addr)) {
552 env->exception.vaddress = addr;
553 goto segv;
554 };
555
556 env->regs[0] = 0;
557 cpsr |= CPSR_C;
558 } else {
559 env->regs[0] = -1;
560 cpsr &= ~CPSR_C;
561 }
562 cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr);
563 end_exclusive();
564 return;
565
566 segv:
567 end_exclusive();
568 /* We get the PC of the entry address - which is as good as anything,
569 on a real kernel what you get depends on which mode it uses. */
570 info.si_signo = TARGET_SIGSEGV;
571 info.si_errno = 0;
572 /* XXX: check env->error_code */
573 info.si_code = TARGET_SEGV_MAPERR;
574 info._sifields._sigfault._addr = env->exception.vaddress;
575 queue_signal(env, info.si_signo, &info);
576 }
577
578 /* Handle a jump to the kernel code page. */
579 static int
580 do_kernel_trap(CPUARMState *env)
581 {
582 uint32_t addr;
583 uint32_t cpsr;
584 uint32_t val;
585
586 switch (env->regs[15]) {
587 case 0xffff0fa0: /* __kernel_memory_barrier */
588 /* ??? No-op. Will need to do better for SMP. */
589 break;
590 case 0xffff0fc0: /* __kernel_cmpxchg */
591 /* XXX: This only works between threads, not between processes.
592 It's probably possible to implement this with native host
593 operations. However things like ldrex/strex are much harder so
594 there's not much point trying. */
595 start_exclusive();
596 cpsr = cpsr_read(env);
597 addr = env->regs[2];
598 /* FIXME: This should SEGV if the access fails. */
599 if (get_user_u32(val, addr))
600 val = ~env->regs[0];
601 if (val == env->regs[0]) {
602 val = env->regs[1];
603 /* FIXME: Check for segfaults. */
604 put_user_u32(val, addr);
605 env->regs[0] = 0;
606 cpsr |= CPSR_C;
607 } else {
608 env->regs[0] = -1;
609 cpsr &= ~CPSR_C;
610 }
611 cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr);
612 end_exclusive();
613 break;
614 case 0xffff0fe0: /* __kernel_get_tls */
615 env->regs[0] = cpu_get_tls(env);
616 break;
617 case 0xffff0f60: /* __kernel_cmpxchg64 */
618 arm_kernel_cmpxchg64_helper(env);
619 break;
620
621 default:
622 return 1;
623 }
624 /* Jump back to the caller. */
625 addr = env->regs[14];
626 if (addr & 1) {
627 env->thumb = 1;
628 addr &= ~1;
629 }
630 env->regs[15] = addr;
631
632 return 0;
633 }
634
635 /* Store exclusive handling for AArch32 */
636 static int do_strex(CPUARMState *env)
637 {
638 uint64_t val;
639 int size;
640 int rc = 1;
641 int segv = 0;
642 uint32_t addr;
643 start_exclusive();
644 if (env->exclusive_addr != env->exclusive_test) {
645 goto fail;
646 }
647 /* We know we're always AArch32 so the address is in uint32_t range
648 * unless it was the -1 exclusive-monitor-lost value (which won't
649 * match exclusive_test above).
650 */
651 assert(extract64(env->exclusive_addr, 32, 32) == 0);
652 addr = env->exclusive_addr;
653 size = env->exclusive_info & 0xf;
654 switch (size) {
655 case 0:
656 segv = get_user_u8(val, addr);
657 break;
658 case 1:
659 segv = get_user_data_u16(val, addr, env);
660 break;
661 case 2:
662 case 3:
663 segv = get_user_data_u32(val, addr, env);
664 break;
665 default:
666 abort();
667 }
668 if (segv) {
669 env->exception.vaddress = addr;
670 goto done;
671 }
672 if (size == 3) {
673 uint32_t valhi;
674 segv = get_user_data_u32(valhi, addr + 4, env);
675 if (segv) {
676 env->exception.vaddress = addr + 4;
677 goto done;
678 }
679 if (arm_cpu_bswap_data(env)) {
680 val = deposit64((uint64_t)valhi, 32, 32, val);
681 } else {
682 val = deposit64(val, 32, 32, valhi);
683 }
684 }
685 if (val != env->exclusive_val) {
686 goto fail;
687 }
688
689 val = env->regs[(env->exclusive_info >> 8) & 0xf];
690 switch (size) {
691 case 0:
692 segv = put_user_u8(val, addr);
693 break;
694 case 1:
695 segv = put_user_data_u16(val, addr, env);
696 break;
697 case 2:
698 case 3:
699 segv = put_user_data_u32(val, addr, env);
700 break;
701 }
702 if (segv) {
703 env->exception.vaddress = addr;
704 goto done;
705 }
706 if (size == 3) {
707 val = env->regs[(env->exclusive_info >> 12) & 0xf];
708 segv = put_user_data_u32(val, addr + 4, env);
709 if (segv) {
710 env->exception.vaddress = addr + 4;
711 goto done;
712 }
713 }
714 rc = 0;
715 fail:
716 env->regs[15] += 4;
717 env->regs[(env->exclusive_info >> 4) & 0xf] = rc;
718 done:
719 end_exclusive();
720 return segv;
721 }
722
723 void cpu_loop(CPUARMState *env)
724 {
725 CPUState *cs = CPU(arm_env_get_cpu(env));
726 int trapnr;
727 unsigned int n, insn;
728 target_siginfo_t info;
729 uint32_t addr;
730 abi_ulong ret;
731
732 for(;;) {
733 cpu_exec_start(cs);
734 trapnr = cpu_arm_exec(cs);
735 cpu_exec_end(cs);
736 switch(trapnr) {
737 case EXCP_UDEF:
738 {
739 TaskState *ts = cs->opaque;
740 uint32_t opcode;
741 int rc;
742
743 /* we handle the FPU emulation here, as Linux */
744 /* we get the opcode */
745 /* FIXME - what to do if get_user() fails? */
746 get_user_code_u32(opcode, env->regs[15], env);
747
748 rc = EmulateAll(opcode, &ts->fpa, env);
749 if (rc == 0) { /* illegal instruction */
750 info.si_signo = TARGET_SIGILL;
751 info.si_errno = 0;
752 info.si_code = TARGET_ILL_ILLOPN;
753 info._sifields._sigfault._addr = env->regs[15];
754 queue_signal(env, info.si_signo, &info);
755 } else if (rc < 0) { /* FP exception */
756 int arm_fpe=0;
757
758 /* translate softfloat flags to FPSR flags */
759 if (-rc & float_flag_invalid)
760 arm_fpe |= BIT_IOC;
761 if (-rc & float_flag_divbyzero)
762 arm_fpe |= BIT_DZC;
763 if (-rc & float_flag_overflow)
764 arm_fpe |= BIT_OFC;
765 if (-rc & float_flag_underflow)
766 arm_fpe |= BIT_UFC;
767 if (-rc & float_flag_inexact)
768 arm_fpe |= BIT_IXC;
769
770 FPSR fpsr = ts->fpa.fpsr;
771 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);
772
773 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */
774 info.si_signo = TARGET_SIGFPE;
775 info.si_errno = 0;
776
777 /* ordered by priority, least first */
778 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES;
779 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND;
780 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF;
781 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV;
782 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV;
783
784 info._sifields._sigfault._addr = env->regs[15];
785 queue_signal(env, info.si_signo, &info);
786 } else {
787 env->regs[15] += 4;
788 }
789
790 /* accumulate unenabled exceptions */
791 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC))
792 fpsr |= BIT_IXC;
793 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC))
794 fpsr |= BIT_UFC;
795 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC))
796 fpsr |= BIT_OFC;
797 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC))
798 fpsr |= BIT_DZC;
799 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC))
800 fpsr |= BIT_IOC;
801 ts->fpa.fpsr=fpsr;
802 } else { /* everything OK */
803 /* increment PC */
804 env->regs[15] += 4;
805 }
806 }
807 break;
808 case EXCP_SWI:
809 case EXCP_BKPT:
810 {
811 env->eabi = 1;
812 /* system call */
813 if (trapnr == EXCP_BKPT) {
814 if (env->thumb) {
815 /* FIXME - what to do if get_user() fails? */
816 get_user_code_u16(insn, env->regs[15], env);
817 n = insn & 0xff;
818 env->regs[15] += 2;
819 } else {
820 /* FIXME - what to do if get_user() fails? */
821 get_user_code_u32(insn, env->regs[15], env);
822 n = (insn & 0xf) | ((insn >> 4) & 0xff0);
823 env->regs[15] += 4;
824 }
825 } else {
826 if (env->thumb) {
827 /* FIXME - what to do if get_user() fails? */
828 get_user_code_u16(insn, env->regs[15] - 2, env);
829 n = insn & 0xff;
830 } else {
831 /* FIXME - what to do if get_user() fails? */
832 get_user_code_u32(insn, env->regs[15] - 4, env);
833 n = insn & 0xffffff;
834 }
835 }
836
837 if (n == ARM_NR_cacheflush) {
838 /* nop */
839 } else if (n == ARM_NR_semihosting
840 || n == ARM_NR_thumb_semihosting) {
841 env->regs[0] = do_arm_semihosting (env);
842 } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) {
843 /* linux syscall */
844 if (env->thumb || n == 0) {
845 n = env->regs[7];
846 } else {
847 n -= ARM_SYSCALL_BASE;
848 env->eabi = 0;
849 }
850 if ( n > ARM_NR_BASE) {
851 switch (n) {
852 case ARM_NR_cacheflush:
853 /* nop */
854 break;
855 case ARM_NR_set_tls:
856 cpu_set_tls(env, env->regs[0]);
857 env->regs[0] = 0;
858 break;
859 case ARM_NR_breakpoint:
860 env->regs[15] -= env->thumb ? 2 : 4;
861 goto excp_debug;
862 default:
863 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n",
864 n);
865 env->regs[0] = -TARGET_ENOSYS;
866 break;
867 }
868 } else {
869 ret = do_syscall(env,
870 n,
871 env->regs[0],
872 env->regs[1],
873 env->regs[2],
874 env->regs[3],
875 env->regs[4],
876 env->regs[5],
877 0, 0);
878 if (ret == -TARGET_ERESTARTSYS) {
879 env->regs[15] -= env->thumb ? 2 : 4;
880 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
881 env->regs[0] = ret;
882 }
883 }
884 } else {
885 goto error;
886 }
887 }
888 break;
889 case EXCP_INTERRUPT:
890 /* just indicate that signals should be handled asap */
891 break;
892 case EXCP_STREX:
893 if (!do_strex(env)) {
894 break;
895 }
896 /* fall through for segv */
897 case EXCP_PREFETCH_ABORT:
898 case EXCP_DATA_ABORT:
899 addr = env->exception.vaddress;
900 {
901 info.si_signo = TARGET_SIGSEGV;
902 info.si_errno = 0;
903 /* XXX: check env->error_code */
904 info.si_code = TARGET_SEGV_MAPERR;
905 info._sifields._sigfault._addr = addr;
906 queue_signal(env, info.si_signo, &info);
907 }
908 break;
909 case EXCP_DEBUG:
910 excp_debug:
911 {
912 int sig;
913
914 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
915 if (sig)
916 {
917 info.si_signo = sig;
918 info.si_errno = 0;
919 info.si_code = TARGET_TRAP_BRKPT;
920 queue_signal(env, info.si_signo, &info);
921 }
922 }
923 break;
924 case EXCP_KERNEL_TRAP:
925 if (do_kernel_trap(env))
926 goto error;
927 break;
928 case EXCP_YIELD:
929 /* nothing to do here for user-mode, just resume guest code */
930 break;
931 default:
932 error:
933 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
934 abort();
935 }
936 process_pending_signals(env);
937 }
938 }
939
940 #else
941
942 /*
943 * Handle AArch64 store-release exclusive
944 *
945 * rs = gets the status result of store exclusive
946 * rt = is the register that is stored
947 * rt2 = is the second register store (in STP)
948 *
949 */
950 static int do_strex_a64(CPUARMState *env)
951 {
952 uint64_t val;
953 int size;
954 bool is_pair;
955 int rc = 1;
956 int segv = 0;
957 uint64_t addr;
958 int rs, rt, rt2;
959
960 start_exclusive();
961 /* size | is_pair << 2 | (rs << 4) | (rt << 9) | (rt2 << 14)); */
962 size = extract32(env->exclusive_info, 0, 2);
963 is_pair = extract32(env->exclusive_info, 2, 1);
964 rs = extract32(env->exclusive_info, 4, 5);
965 rt = extract32(env->exclusive_info, 9, 5);
966 rt2 = extract32(env->exclusive_info, 14, 5);
967
968 addr = env->exclusive_addr;
969
970 if (addr != env->exclusive_test) {
971 goto finish;
972 }
973
974 switch (size) {
975 case 0:
976 segv = get_user_u8(val, addr);
977 break;
978 case 1:
979 segv = get_user_u16(val, addr);
980 break;
981 case 2:
982 segv = get_user_u32(val, addr);
983 break;
984 case 3:
985 segv = get_user_u64(val, addr);
986 break;
987 default:
988 abort();
989 }
990 if (segv) {
991 env->exception.vaddress = addr;
992 goto error;
993 }
994 if (val != env->exclusive_val) {
995 goto finish;
996 }
997 if (is_pair) {
998 if (size == 2) {
999 segv = get_user_u32(val, addr + 4);
1000 } else {
1001 segv = get_user_u64(val, addr + 8);
1002 }
1003 if (segv) {
1004 env->exception.vaddress = addr + (size == 2 ? 4 : 8);
1005 goto error;
1006 }
1007 if (val != env->exclusive_high) {
1008 goto finish;
1009 }
1010 }
1011 /* handle the zero register */
1012 val = rt == 31 ? 0 : env->xregs[rt];
1013 switch (size) {
1014 case 0:
1015 segv = put_user_u8(val, addr);
1016 break;
1017 case 1:
1018 segv = put_user_u16(val, addr);
1019 break;
1020 case 2:
1021 segv = put_user_u32(val, addr);
1022 break;
1023 case 3:
1024 segv = put_user_u64(val, addr);
1025 break;
1026 }
1027 if (segv) {
1028 goto error;
1029 }
1030 if (is_pair) {
1031 /* handle the zero register */
1032 val = rt2 == 31 ? 0 : env->xregs[rt2];
1033 if (size == 2) {
1034 segv = put_user_u32(val, addr + 4);
1035 } else {
1036 segv = put_user_u64(val, addr + 8);
1037 }
1038 if (segv) {
1039 env->exception.vaddress = addr + (size == 2 ? 4 : 8);
1040 goto error;
1041 }
1042 }
1043 rc = 0;
1044 finish:
1045 env->pc += 4;
1046 /* rs == 31 encodes a write to the ZR, thus throwing away
1047 * the status return. This is rather silly but valid.
1048 */
1049 if (rs < 31) {
1050 env->xregs[rs] = rc;
1051 }
1052 error:
1053 /* instruction faulted, PC does not advance */
1054 /* either way a strex releases any exclusive lock we have */
1055 env->exclusive_addr = -1;
1056 end_exclusive();
1057 return segv;
1058 }
1059
1060 /* AArch64 main loop */
1061 void cpu_loop(CPUARMState *env)
1062 {
1063 CPUState *cs = CPU(arm_env_get_cpu(env));
1064 int trapnr, sig;
1065 abi_long ret;
1066 target_siginfo_t info;
1067
1068 for (;;) {
1069 cpu_exec_start(cs);
1070 trapnr = cpu_arm_exec(cs);
1071 cpu_exec_end(cs);
1072
1073 switch (trapnr) {
1074 case EXCP_SWI:
1075 ret = do_syscall(env,
1076 env->xregs[8],
1077 env->xregs[0],
1078 env->xregs[1],
1079 env->xregs[2],
1080 env->xregs[3],
1081 env->xregs[4],
1082 env->xregs[5],
1083 0, 0);
1084 if (ret == -TARGET_ERESTARTSYS) {
1085 env->pc -= 4;
1086 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
1087 env->xregs[0] = ret;
1088 }
1089 break;
1090 case EXCP_INTERRUPT:
1091 /* just indicate that signals should be handled asap */
1092 break;
1093 case EXCP_UDEF:
1094 info.si_signo = TARGET_SIGILL;
1095 info.si_errno = 0;
1096 info.si_code = TARGET_ILL_ILLOPN;
1097 info._sifields._sigfault._addr = env->pc;
1098 queue_signal(env, info.si_signo, &info);
1099 break;
1100 case EXCP_STREX:
1101 if (!do_strex_a64(env)) {
1102 break;
1103 }
1104 /* fall through for segv */
1105 case EXCP_PREFETCH_ABORT:
1106 case EXCP_DATA_ABORT:
1107 info.si_signo = TARGET_SIGSEGV;
1108 info.si_errno = 0;
1109 /* XXX: check env->error_code */
1110 info.si_code = TARGET_SEGV_MAPERR;
1111 info._sifields._sigfault._addr = env->exception.vaddress;
1112 queue_signal(env, info.si_signo, &info);
1113 break;
1114 case EXCP_DEBUG:
1115 case EXCP_BKPT:
1116 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1117 if (sig) {
1118 info.si_signo = sig;
1119 info.si_errno = 0;
1120 info.si_code = TARGET_TRAP_BRKPT;
1121 queue_signal(env, info.si_signo, &info);
1122 }
1123 break;
1124 case EXCP_SEMIHOST:
1125 env->xregs[0] = do_arm_semihosting(env);
1126 break;
1127 case EXCP_YIELD:
1128 /* nothing to do here for user-mode, just resume guest code */
1129 break;
1130 default:
1131 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
1132 abort();
1133 }
1134 process_pending_signals(env);
1135 /* Exception return on AArch64 always clears the exclusive monitor,
1136 * so any return to running guest code implies this.
1137 * A strex (successful or otherwise) also clears the monitor, so
1138 * we don't need to specialcase EXCP_STREX.
1139 */
1140 env->exclusive_addr = -1;
1141 }
1142 }
1143 #endif /* ndef TARGET_ABI32 */
1144
1145 #endif
1146
1147 #ifdef TARGET_UNICORE32
1148
1149 void cpu_loop(CPUUniCore32State *env)
1150 {
1151 CPUState *cs = CPU(uc32_env_get_cpu(env));
1152 int trapnr;
1153 unsigned int n, insn;
1154 target_siginfo_t info;
1155
1156 for (;;) {
1157 cpu_exec_start(cs);
1158 trapnr = uc32_cpu_exec(cs);
1159 cpu_exec_end(cs);
1160 switch (trapnr) {
1161 case UC32_EXCP_PRIV:
1162 {
1163 /* system call */
1164 get_user_u32(insn, env->regs[31] - 4);
1165 n = insn & 0xffffff;
1166
1167 if (n >= UC32_SYSCALL_BASE) {
1168 /* linux syscall */
1169 n -= UC32_SYSCALL_BASE;
1170 if (n == UC32_SYSCALL_NR_set_tls) {
1171 cpu_set_tls(env, env->regs[0]);
1172 env->regs[0] = 0;
1173 } else {
1174 env->regs[0] = do_syscall(env,
1175 n,
1176 env->regs[0],
1177 env->regs[1],
1178 env->regs[2],
1179 env->regs[3],
1180 env->regs[4],
1181 env->regs[5],
1182 0, 0);
1183 }
1184 } else {
1185 goto error;
1186 }
1187 }
1188 break;
1189 case UC32_EXCP_DTRAP:
1190 case UC32_EXCP_ITRAP:
1191 info.si_signo = TARGET_SIGSEGV;
1192 info.si_errno = 0;
1193 /* XXX: check env->error_code */
1194 info.si_code = TARGET_SEGV_MAPERR;
1195 info._sifields._sigfault._addr = env->cp0.c4_faultaddr;
1196 queue_signal(env, info.si_signo, &info);
1197 break;
1198 case EXCP_INTERRUPT:
1199 /* just indicate that signals should be handled asap */
1200 break;
1201 case EXCP_DEBUG:
1202 {
1203 int sig;
1204
1205 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1206 if (sig) {
1207 info.si_signo = sig;
1208 info.si_errno = 0;
1209 info.si_code = TARGET_TRAP_BRKPT;
1210 queue_signal(env, info.si_signo, &info);
1211 }
1212 }
1213 break;
1214 default:
1215 goto error;
1216 }
1217 process_pending_signals(env);
1218 }
1219
1220 error:
1221 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
1222 abort();
1223 }
1224 #endif
1225
1226 #ifdef TARGET_SPARC
1227 #define SPARC64_STACK_BIAS 2047
1228
1229 //#define DEBUG_WIN
1230
1231 /* WARNING: dealing with register windows _is_ complicated. More info
1232 can be found at http://www.sics.se/~psm/sparcstack.html */
1233 static inline int get_reg_index(CPUSPARCState *env, int cwp, int index)
1234 {
1235 index = (index + cwp * 16) % (16 * env->nwindows);
1236 /* wrap handling : if cwp is on the last window, then we use the
1237 registers 'after' the end */
1238 if (index < 8 && env->cwp == env->nwindows - 1)
1239 index += 16 * env->nwindows;
1240 return index;
1241 }
1242
1243 /* save the register window 'cwp1' */
1244 static inline void save_window_offset(CPUSPARCState *env, int cwp1)
1245 {
1246 unsigned int i;
1247 abi_ulong sp_ptr;
1248
1249 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
1250 #ifdef TARGET_SPARC64
1251 if (sp_ptr & 3)
1252 sp_ptr += SPARC64_STACK_BIAS;
1253 #endif
1254 #if defined(DEBUG_WIN)
1255 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n",
1256 sp_ptr, cwp1);
1257 #endif
1258 for(i = 0; i < 16; i++) {
1259 /* FIXME - what to do if put_user() fails? */
1260 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
1261 sp_ptr += sizeof(abi_ulong);
1262 }
1263 }
1264
1265 static void save_window(CPUSPARCState *env)
1266 {
1267 #ifndef TARGET_SPARC64
1268 unsigned int new_wim;
1269 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) &
1270 ((1LL << env->nwindows) - 1);
1271 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
1272 env->wim = new_wim;
1273 #else
1274 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
1275 env->cansave++;
1276 env->canrestore--;
1277 #endif
1278 }
1279
1280 static void restore_window(CPUSPARCState *env)
1281 {
1282 #ifndef TARGET_SPARC64
1283 unsigned int new_wim;
1284 #endif
1285 unsigned int i, cwp1;
1286 abi_ulong sp_ptr;
1287
1288 #ifndef TARGET_SPARC64
1289 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) &
1290 ((1LL << env->nwindows) - 1);
1291 #endif
1292
1293 /* restore the invalid window */
1294 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
1295 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
1296 #ifdef TARGET_SPARC64
1297 if (sp_ptr & 3)
1298 sp_ptr += SPARC64_STACK_BIAS;
1299 #endif
1300 #if defined(DEBUG_WIN)
1301 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n",
1302 sp_ptr, cwp1);
1303 #endif
1304 for(i = 0; i < 16; i++) {
1305 /* FIXME - what to do if get_user() fails? */
1306 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
1307 sp_ptr += sizeof(abi_ulong);
1308 }
1309 #ifdef TARGET_SPARC64
1310 env->canrestore++;
1311 if (env->cleanwin < env->nwindows - 1)
1312 env->cleanwin++;
1313 env->cansave--;
1314 #else
1315 env->wim = new_wim;
1316 #endif
1317 }
1318
1319 static void flush_windows(CPUSPARCState *env)
1320 {
1321 int offset, cwp1;
1322
1323 offset = 1;
1324 for(;;) {
1325 /* if restore would invoke restore_window(), then we can stop */
1326 cwp1 = cpu_cwp_inc(env, env->cwp + offset);
1327 #ifndef TARGET_SPARC64
1328 if (env->wim & (1 << cwp1))
1329 break;
1330 #else
1331 if (env->canrestore == 0)
1332 break;
1333 env->cansave++;
1334 env->canrestore--;
1335 #endif
1336 save_window_offset(env, cwp1);
1337 offset++;
1338 }
1339 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
1340 #ifndef TARGET_SPARC64
1341 /* set wim so that restore will reload the registers */
1342 env->wim = 1 << cwp1;
1343 #endif
1344 #if defined(DEBUG_WIN)
1345 printf("flush_windows: nb=%d\n", offset - 1);
1346 #endif
1347 }
1348
1349 void cpu_loop (CPUSPARCState *env)
1350 {
1351 CPUState *cs = CPU(sparc_env_get_cpu(env));
1352 int trapnr;
1353 abi_long ret;
1354 target_siginfo_t info;
1355
1356 while (1) {
1357 cpu_exec_start(cs);
1358 trapnr = cpu_sparc_exec(cs);
1359 cpu_exec_end(cs);
1360
1361 /* Compute PSR before exposing state. */
1362 if (env->cc_op != CC_OP_FLAGS) {
1363 cpu_get_psr(env);
1364 }
1365
1366 switch (trapnr) {
1367 #ifndef TARGET_SPARC64
1368 case 0x88:
1369 case 0x90:
1370 #else
1371 case 0x110:
1372 case 0x16d:
1373 #endif
1374 ret = do_syscall (env, env->gregs[1],
1375 env->regwptr[0], env->regwptr[1],
1376 env->regwptr[2], env->regwptr[3],
1377 env->regwptr[4], env->regwptr[5],
1378 0, 0);
1379 if ((abi_ulong)ret >= (abi_ulong)(-515)) {
1380 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
1381 env->xcc |= PSR_CARRY;
1382 #else
1383 env->psr |= PSR_CARRY;
1384 #endif
1385 ret = -ret;
1386 } else {
1387 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
1388 env->xcc &= ~PSR_CARRY;
1389 #else
1390 env->psr &= ~PSR_CARRY;
1391 #endif
1392 }
1393 env->regwptr[0] = ret;
1394 /* next instruction */
1395 env->pc = env->npc;
1396 env->npc = env->npc + 4;
1397 break;
1398 case 0x83: /* flush windows */
1399 #ifdef TARGET_ABI32
1400 case 0x103:
1401 #endif
1402 flush_windows(env);
1403 /* next instruction */
1404 env->pc = env->npc;
1405 env->npc = env->npc + 4;
1406 break;
1407 #ifndef TARGET_SPARC64
1408 case TT_WIN_OVF: /* window overflow */
1409 save_window(env);
1410 break;
1411 case TT_WIN_UNF: /* window underflow */
1412 restore_window(env);
1413 break;
1414 case TT_TFAULT:
1415 case TT_DFAULT:
1416 {
1417 info.si_signo = TARGET_SIGSEGV;
1418 info.si_errno = 0;
1419 /* XXX: check env->error_code */
1420 info.si_code = TARGET_SEGV_MAPERR;
1421 info._sifields._sigfault._addr = env->mmuregs[4];
1422 queue_signal(env, info.si_signo, &info);
1423 }
1424 break;
1425 #else
1426 case TT_SPILL: /* window overflow */
1427 save_window(env);
1428 break;
1429 case TT_FILL: /* window underflow */
1430 restore_window(env);
1431 break;
1432 case TT_TFAULT:
1433 case TT_DFAULT:
1434 {
1435 info.si_signo = TARGET_SIGSEGV;
1436 info.si_errno = 0;
1437 /* XXX: check env->error_code */
1438 info.si_code = TARGET_SEGV_MAPERR;
1439 if (trapnr == TT_DFAULT)
1440 info._sifields._sigfault._addr = env->dmmuregs[4];
1441 else
1442 info._sifields._sigfault._addr = cpu_tsptr(env)->tpc;
1443 queue_signal(env, info.si_signo, &info);
1444 }
1445 break;
1446 #ifndef TARGET_ABI32
1447 case 0x16e:
1448 flush_windows(env);
1449 sparc64_get_context(env);
1450 break;
1451 case 0x16f:
1452 flush_windows(env);
1453 sparc64_set_context(env);
1454 break;
1455 #endif
1456 #endif
1457 case EXCP_INTERRUPT:
1458 /* just indicate that signals should be handled asap */
1459 break;
1460 case TT_ILL_INSN:
1461 {
1462 info.si_signo = TARGET_SIGILL;
1463 info.si_errno = 0;
1464 info.si_code = TARGET_ILL_ILLOPC;
1465 info._sifields._sigfault._addr = env->pc;
1466 queue_signal(env, info.si_signo, &info);
1467 }
1468 break;
1469 case EXCP_DEBUG:
1470 {
1471 int sig;
1472
1473 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1474 if (sig)
1475 {
1476 info.si_signo = sig;
1477 info.si_errno = 0;
1478 info.si_code = TARGET_TRAP_BRKPT;
1479 queue_signal(env, info.si_signo, &info);
1480 }
1481 }
1482 break;
1483 default:
1484 printf ("Unhandled trap: 0x%x\n", trapnr);
1485 cpu_dump_state(cs, stderr, fprintf, 0);
1486 exit(EXIT_FAILURE);
1487 }
1488 process_pending_signals (env);
1489 }
1490 }
1491
1492 #endif
1493
1494 #ifdef TARGET_PPC
1495 static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env)
1496 {
1497 return cpu_get_host_ticks();
1498 }
1499
1500 uint64_t cpu_ppc_load_tbl(CPUPPCState *env)
1501 {
1502 return cpu_ppc_get_tb(env);
1503 }
1504
1505 uint32_t cpu_ppc_load_tbu(CPUPPCState *env)
1506 {
1507 return cpu_ppc_get_tb(env) >> 32;
1508 }
1509
1510 uint64_t cpu_ppc_load_atbl(CPUPPCState *env)
1511 {
1512 return cpu_ppc_get_tb(env);
1513 }
1514
1515 uint32_t cpu_ppc_load_atbu(CPUPPCState *env)
1516 {
1517 return cpu_ppc_get_tb(env) >> 32;
1518 }
1519
1520 uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env)
1521 __attribute__ (( alias ("cpu_ppc_load_tbu") ));
1522
1523 uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env)
1524 {
1525 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
1526 }
1527
1528 /* XXX: to be fixed */
1529 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
1530 {
1531 return -1;
1532 }
1533
1534 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
1535 {
1536 return -1;
1537 }
1538
1539 static int do_store_exclusive(CPUPPCState *env)
1540 {
1541 target_ulong addr;
1542 target_ulong page_addr;
1543 target_ulong val, val2 __attribute__((unused)) = 0;
1544 int flags;
1545 int segv = 0;
1546
1547 addr = env->reserve_ea;
1548 page_addr = addr & TARGET_PAGE_MASK;
1549 start_exclusive();
1550 mmap_lock();
1551 flags = page_get_flags(page_addr);
1552 if ((flags & PAGE_READ) == 0) {
1553 segv = 1;
1554 } else {
1555 int reg = env->reserve_info & 0x1f;
1556 int size = env->reserve_info >> 5;
1557 int stored = 0;
1558
1559 if (addr == env->reserve_addr) {
1560 switch (size) {
1561 case 1: segv = get_user_u8(val, addr); break;
1562 case 2: segv = get_user_u16(val, addr); break;
1563 case 4: segv = get_user_u32(val, addr); break;
1564 #if defined(TARGET_PPC64)
1565 case 8: segv = get_user_u64(val, addr); break;
1566 case 16: {
1567 segv = get_user_u64(val, addr);
1568 if (!segv) {
1569 segv = get_user_u64(val2, addr + 8);
1570 }
1571 break;
1572 }
1573 #endif
1574 default: abort();
1575 }
1576 if (!segv && val == env->reserve_val) {
1577 val = env->gpr[reg];
1578 switch (size) {
1579 case 1: segv = put_user_u8(val, addr); break;
1580 case 2: segv = put_user_u16(val, addr); break;
1581 case 4: segv = put_user_u32(val, addr); break;
1582 #if defined(TARGET_PPC64)
1583 case 8: segv = put_user_u64(val, addr); break;
1584 case 16: {
1585 if (val2 == env->reserve_val2) {
1586 if (msr_le) {
1587 val2 = val;
1588 val = env->gpr[reg+1];
1589 } else {
1590 val2 = env->gpr[reg+1];
1591 }
1592 segv = put_user_u64(val, addr);
1593 if (!segv) {
1594 segv = put_user_u64(val2, addr + 8);
1595 }
1596 }
1597 break;
1598 }
1599 #endif
1600 default: abort();
1601 }
1602 if (!segv) {
1603 stored = 1;
1604 }
1605 }
1606 }
1607 env->crf[0] = (stored << 1) | xer_so;
1608 env->reserve_addr = (target_ulong)-1;
1609 }
1610 if (!segv) {
1611 env->nip += 4;
1612 }
1613 mmap_unlock();
1614 end_exclusive();
1615 return segv;
1616 }
1617
1618 void cpu_loop(CPUPPCState *env)
1619 {
1620 CPUState *cs = CPU(ppc_env_get_cpu(env));
1621 target_siginfo_t info;
1622 int trapnr;
1623 target_ulong ret;
1624
1625 for(;;) {
1626 cpu_exec_start(cs);
1627 trapnr = cpu_ppc_exec(cs);
1628 cpu_exec_end(cs);
1629 switch(trapnr) {
1630 case POWERPC_EXCP_NONE:
1631 /* Just go on */
1632 break;
1633 case POWERPC_EXCP_CRITICAL: /* Critical input */
1634 cpu_abort(cs, "Critical interrupt while in user mode. "
1635 "Aborting\n");
1636 break;
1637 case POWERPC_EXCP_MCHECK: /* Machine check exception */
1638 cpu_abort(cs, "Machine check exception while in user mode. "
1639 "Aborting\n");
1640 break;
1641 case POWERPC_EXCP_DSI: /* Data storage exception */
1642 EXCP_DUMP(env, "Invalid data memory access: 0x" TARGET_FMT_lx "\n",
1643 env->spr[SPR_DAR]);
1644 /* XXX: check this. Seems bugged */
1645 switch (env->error_code & 0xFF000000) {
1646 case 0x40000000:
1647 info.si_signo = TARGET_SIGSEGV;
1648 info.si_errno = 0;
1649 info.si_code = TARGET_SEGV_MAPERR;
1650 break;
1651 case 0x04000000:
1652 info.si_signo = TARGET_SIGILL;
1653 info.si_errno = 0;
1654 info.si_code = TARGET_ILL_ILLADR;
1655 break;
1656 case 0x08000000:
1657 info.si_signo = TARGET_SIGSEGV;
1658 info.si_errno = 0;
1659 info.si_code = TARGET_SEGV_ACCERR;
1660 break;
1661 default:
1662 /* Let's send a regular segfault... */
1663 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1664 env->error_code);
1665 info.si_signo = TARGET_SIGSEGV;
1666 info.si_errno = 0;
1667 info.si_code = TARGET_SEGV_MAPERR;
1668 break;
1669 }
1670 info._sifields._sigfault._addr = env->nip;
1671 queue_signal(env, info.si_signo, &info);
1672 break;
1673 case POWERPC_EXCP_ISI: /* Instruction storage exception */
1674 EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" TARGET_FMT_lx
1675 "\n", env->spr[SPR_SRR0]);
1676 /* XXX: check this */
1677 switch (env->error_code & 0xFF000000) {
1678 case 0x40000000:
1679 info.si_signo = TARGET_SIGSEGV;
1680 info.si_errno = 0;
1681 info.si_code = TARGET_SEGV_MAPERR;
1682 break;
1683 case 0x10000000:
1684 case 0x08000000:
1685 info.si_signo = TARGET_SIGSEGV;
1686 info.si_errno = 0;
1687 info.si_code = TARGET_SEGV_ACCERR;
1688 break;
1689 default:
1690 /* Let's send a regular segfault... */
1691 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1692 env->error_code);
1693 info.si_signo = TARGET_SIGSEGV;
1694 info.si_errno = 0;
1695 info.si_code = TARGET_SEGV_MAPERR;
1696 break;
1697 }
1698 info._sifields._sigfault._addr = env->nip - 4;
1699 queue_signal(env, info.si_signo, &info);
1700 break;
1701 case POWERPC_EXCP_EXTERNAL: /* External input */
1702 cpu_abort(cs, "External interrupt while in user mode. "
1703 "Aborting\n");
1704 break;
1705 case POWERPC_EXCP_ALIGN: /* Alignment exception */
1706 EXCP_DUMP(env, "Unaligned memory access\n");
1707 /* XXX: check this */
1708 info.si_signo = TARGET_SIGBUS;
1709 info.si_errno = 0;
1710 info.si_code = TARGET_BUS_ADRALN;
1711 info._sifields._sigfault._addr = env->nip;
1712 queue_signal(env, info.si_signo, &info);
1713 break;
1714 case POWERPC_EXCP_PROGRAM: /* Program exception */
1715 /* XXX: check this */
1716 switch (env->error_code & ~0xF) {
1717 case POWERPC_EXCP_FP:
1718 EXCP_DUMP(env, "Floating point program exception\n");
1719 info.si_signo = TARGET_SIGFPE;
1720 info.si_errno = 0;
1721 switch (env->error_code & 0xF) {
1722 case POWERPC_EXCP_FP_OX:
1723 info.si_code = TARGET_FPE_FLTOVF;
1724 break;
1725 case POWERPC_EXCP_FP_UX:
1726 info.si_code = TARGET_FPE_FLTUND;
1727 break;
1728 case POWERPC_EXCP_FP_ZX:
1729 case POWERPC_EXCP_FP_VXZDZ:
1730 info.si_code = TARGET_FPE_FLTDIV;
1731 break;
1732 case POWERPC_EXCP_FP_XX:
1733 info.si_code = TARGET_FPE_FLTRES;
1734 break;
1735 case POWERPC_EXCP_FP_VXSOFT:
1736 info.si_code = TARGET_FPE_FLTINV;
1737 break;
1738 case POWERPC_EXCP_FP_VXSNAN:
1739 case POWERPC_EXCP_FP_VXISI:
1740 case POWERPC_EXCP_FP_VXIDI:
1741 case POWERPC_EXCP_FP_VXIMZ:
1742 case POWERPC_EXCP_FP_VXVC:
1743 case POWERPC_EXCP_FP_VXSQRT:
1744 case POWERPC_EXCP_FP_VXCVI:
1745 info.si_code = TARGET_FPE_FLTSUB;
1746 break;
1747 default:
1748 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n",
1749 env->error_code);
1750 break;
1751 }
1752 break;
1753 case POWERPC_EXCP_INVAL:
1754 EXCP_DUMP(env, "Invalid instruction\n");
1755 info.si_signo = TARGET_SIGILL;
1756 info.si_errno = 0;
1757 switch (env->error_code & 0xF) {
1758 case POWERPC_EXCP_INVAL_INVAL:
1759 info.si_code = TARGET_ILL_ILLOPC;
1760 break;
1761 case POWERPC_EXCP_INVAL_LSWX:
1762 info.si_code = TARGET_ILL_ILLOPN;
1763 break;
1764 case POWERPC_EXCP_INVAL_SPR:
1765 info.si_code = TARGET_ILL_PRVREG;
1766 break;
1767 case POWERPC_EXCP_INVAL_FP:
1768 info.si_code = TARGET_ILL_COPROC;
1769 break;
1770 default:
1771 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n",
1772 env->error_code & 0xF);
1773 info.si_code = TARGET_ILL_ILLADR;
1774 break;
1775 }
1776 break;
1777 case POWERPC_EXCP_PRIV:
1778 EXCP_DUMP(env, "Privilege violation\n");
1779 info.si_signo = TARGET_SIGILL;
1780 info.si_errno = 0;
1781 switch (env->error_code & 0xF) {
1782 case POWERPC_EXCP_PRIV_OPC:
1783 info.si_code = TARGET_ILL_PRVOPC;
1784 break;
1785 case POWERPC_EXCP_PRIV_REG:
1786 info.si_code = TARGET_ILL_PRVREG;
1787 break;
1788 default:
1789 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n",
1790 env->error_code & 0xF);
1791 info.si_code = TARGET_ILL_PRVOPC;
1792 break;
1793 }
1794 break;
1795 case POWERPC_EXCP_TRAP:
1796 cpu_abort(cs, "Tried to call a TRAP\n");
1797 break;
1798 default:
1799 /* Should not happen ! */
1800 cpu_abort(cs, "Unknown program exception (%02x)\n",
1801 env->error_code);
1802 break;
1803 }
1804 info._sifields._sigfault._addr = env->nip - 4;
1805 queue_signal(env, info.si_signo, &info);
1806 break;
1807 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
1808 EXCP_DUMP(env, "No floating point allowed\n");
1809 info.si_signo = TARGET_SIGILL;
1810 info.si_errno = 0;
1811 info.si_code = TARGET_ILL_COPROC;
1812 info._sifields._sigfault._addr = env->nip - 4;
1813 queue_signal(env, info.si_signo, &info);
1814 break;
1815 case POWERPC_EXCP_SYSCALL: /* System call exception */
1816 cpu_abort(cs, "Syscall exception while in user mode. "
1817 "Aborting\n");
1818 break;
1819 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
1820 EXCP_DUMP(env, "No APU instruction allowed\n");
1821 info.si_signo = TARGET_SIGILL;
1822 info.si_errno = 0;
1823 info.si_code = TARGET_ILL_COPROC;
1824 info._sifields._sigfault._addr = env->nip - 4;
1825 queue_signal(env, info.si_signo, &info);
1826 break;
1827 case POWERPC_EXCP_DECR: /* Decrementer exception */
1828 cpu_abort(cs, "Decrementer interrupt while in user mode. "
1829 "Aborting\n");
1830 break;
1831 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
1832 cpu_abort(cs, "Fix interval timer interrupt while in user mode. "
1833 "Aborting\n");
1834 break;
1835 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
1836 cpu_abort(cs, "Watchdog timer interrupt while in user mode. "
1837 "Aborting\n");
1838 break;
1839 case POWERPC_EXCP_DTLB: /* Data TLB error */
1840 cpu_abort(cs, "Data TLB exception while in user mode. "
1841 "Aborting\n");
1842 break;
1843 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
1844 cpu_abort(cs, "Instruction TLB exception while in user mode. "
1845 "Aborting\n");
1846 break;
1847 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */
1848 EXCP_DUMP(env, "No SPE/floating-point instruction allowed\n");
1849 info.si_signo = TARGET_SIGILL;
1850 info.si_errno = 0;
1851 info.si_code = TARGET_ILL_COPROC;
1852 info._sifields._sigfault._addr = env->nip - 4;
1853 queue_signal(env, info.si_signo, &info);
1854 break;
1855 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */
1856 cpu_abort(cs, "Embedded floating-point data IRQ not handled\n");
1857 break;
1858 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */
1859 cpu_abort(cs, "Embedded floating-point round IRQ not handled\n");
1860 break;
1861 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */
1862 cpu_abort(cs, "Performance monitor exception not handled\n");
1863 break;
1864 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
1865 cpu_abort(cs, "Doorbell interrupt while in user mode. "
1866 "Aborting\n");
1867 break;
1868 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
1869 cpu_abort(cs, "Doorbell critical interrupt while in user mode. "
1870 "Aborting\n");
1871 break;
1872 case POWERPC_EXCP_RESET: /* System reset exception */
1873 cpu_abort(cs, "Reset interrupt while in user mode. "
1874 "Aborting\n");
1875 break;
1876 case POWERPC_EXCP_DSEG: /* Data segment exception */
1877 cpu_abort(cs, "Data segment exception while in user mode. "
1878 "Aborting\n");
1879 break;
1880 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
1881 cpu_abort(cs, "Instruction segment exception "
1882 "while in user mode. Aborting\n");
1883 break;
1884 /* PowerPC 64 with hypervisor mode support */
1885 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
1886 cpu_abort(cs, "Hypervisor decrementer interrupt "
1887 "while in user mode. Aborting\n");
1888 break;
1889 case POWERPC_EXCP_TRACE: /* Trace exception */
1890 /* Nothing to do:
1891 * we use this exception to emulate step-by-step execution mode.
1892 */
1893 break;
1894 /* PowerPC 64 with hypervisor mode support */
1895 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
1896 cpu_abort(cs, "Hypervisor data storage exception "
1897 "while in user mode. Aborting\n");
1898 break;
1899 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */
1900 cpu_abort(cs, "Hypervisor instruction storage exception "
1901 "while in user mode. Aborting\n");
1902 break;
1903 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
1904 cpu_abort(cs, "Hypervisor data segment exception "
1905 "while in user mode. Aborting\n");
1906 break;
1907 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */
1908 cpu_abort(cs, "Hypervisor instruction segment exception "
1909 "while in user mode. Aborting\n");
1910 break;
1911 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
1912 EXCP_DUMP(env, "No Altivec instructions allowed\n");
1913 info.si_signo = TARGET_SIGILL;
1914 info.si_errno = 0;
1915 info.si_code = TARGET_ILL_COPROC;
1916 info._sifields._sigfault._addr = env->nip - 4;
1917 queue_signal(env, info.si_signo, &info);
1918 break;
1919 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */
1920 cpu_abort(cs, "Programmable interval timer interrupt "
1921 "while in user mode. Aborting\n");
1922 break;
1923 case POWERPC_EXCP_IO: /* IO error exception */
1924 cpu_abort(cs, "IO error exception while in user mode. "
1925 "Aborting\n");
1926 break;
1927 case POWERPC_EXCP_RUNM: /* Run mode exception */
1928 cpu_abort(cs, "Run mode exception while in user mode. "
1929 "Aborting\n");
1930 break;
1931 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
1932 cpu_abort(cs, "Emulation trap exception not handled\n");
1933 break;
1934 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
1935 cpu_abort(cs, "Instruction fetch TLB exception "
1936 "while in user-mode. Aborting");
1937 break;
1938 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
1939 cpu_abort(cs, "Data load TLB exception while in user-mode. "
1940 "Aborting");
1941 break;
1942 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
1943 cpu_abort(cs, "Data store TLB exception while in user-mode. "
1944 "Aborting");
1945 break;
1946 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
1947 cpu_abort(cs, "Floating-point assist exception not handled\n");
1948 break;
1949 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
1950 cpu_abort(cs, "Instruction address breakpoint exception "
1951 "not handled\n");
1952 break;
1953 case POWERPC_EXCP_SMI: /* System management interrupt */
1954 cpu_abort(cs, "System management interrupt while in user mode. "
1955 "Aborting\n");
1956 break;
1957 case POWERPC_EXCP_THERM: /* Thermal interrupt */
1958 cpu_abort(cs, "Thermal interrupt interrupt while in user mode. "
1959 "Aborting\n");
1960 break;
1961 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */
1962 cpu_abort(cs, "Performance monitor exception not handled\n");
1963 break;
1964 case POWERPC_EXCP_VPUA: /* Vector assist exception */
1965 cpu_abort(cs, "Vector assist exception not handled\n");
1966 break;
1967 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
1968 cpu_abort(cs, "Soft patch exception not handled\n");
1969 break;
1970 case POWERPC_EXCP_MAINT: /* Maintenance exception */
1971 cpu_abort(cs, "Maintenance exception while in user mode. "
1972 "Aborting\n");
1973 break;
1974 case POWERPC_EXCP_STOP: /* stop translation */
1975 /* We did invalidate the instruction cache. Go on */
1976 break;
1977 case POWERPC_EXCP_BRANCH: /* branch instruction: */
1978 /* We just stopped because of a branch. Go on */
1979 break;
1980 case POWERPC_EXCP_SYSCALL_USER:
1981 /* system call in user-mode emulation */
1982 /* WARNING:
1983 * PPC ABI uses overflow flag in cr0 to signal an error
1984 * in syscalls.
1985 */
1986 env->crf[0] &= ~0x1;
1987 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4],
1988 env->gpr[5], env->gpr[6], env->gpr[7],
1989 env->gpr[8], 0, 0);
1990 if (ret == (target_ulong)(-TARGET_QEMU_ESIGRETURN)) {
1991 /* Returning from a successful sigreturn syscall.
1992 Avoid corrupting register state. */
1993 break;
1994 }
1995 if (ret > (target_ulong)(-515)) {
1996 env->crf[0] |= 0x1;
1997 ret = -ret;
1998 }
1999 env->gpr[3] = ret;
2000 break;
2001 case POWERPC_EXCP_STCX:
2002 if (do_store_exclusive(env)) {
2003 info.si_signo = TARGET_SIGSEGV;
2004 info.si_errno = 0;
2005 info.si_code = TARGET_SEGV_MAPERR;
2006 info._sifields._sigfault._addr = env->nip;
2007 queue_signal(env, info.si_signo, &info);
2008 }
2009 break;
2010 case EXCP_DEBUG:
2011 {
2012 int sig;
2013
2014 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2015 if (sig) {
2016 info.si_signo = sig;
2017 info.si_errno = 0;
2018 info.si_code = TARGET_TRAP_BRKPT;
2019 queue_signal(env, info.si_signo, &info);
2020 }
2021 }
2022 break;
2023 case EXCP_INTERRUPT:
2024 /* just indicate that signals should be handled asap */
2025 break;
2026 default:
2027 cpu_abort(cs, "Unknown exception 0x%d. Aborting\n", trapnr);
2028 break;
2029 }
2030 process_pending_signals(env);
2031 }
2032 }
2033 #endif
2034
2035 #ifdef TARGET_MIPS
2036
2037 # ifdef TARGET_ABI_MIPSO32
2038 # define MIPS_SYS(name, args) args,
2039 static const uint8_t mips_syscall_args[] = {
2040 MIPS_SYS(sys_syscall , 8) /* 4000 */
2041 MIPS_SYS(sys_exit , 1)
2042 MIPS_SYS(sys_fork , 0)
2043 MIPS_SYS(sys_read , 3)
2044 MIPS_SYS(sys_write , 3)
2045 MIPS_SYS(sys_open , 3) /* 4005 */
2046 MIPS_SYS(sys_close , 1)
2047 MIPS_SYS(sys_waitpid , 3)
2048 MIPS_SYS(sys_creat , 2)
2049 MIPS_SYS(sys_link , 2)
2050 MIPS_SYS(sys_unlink , 1) /* 4010 */
2051 MIPS_SYS(sys_execve , 0)
2052 MIPS_SYS(sys_chdir , 1)
2053 MIPS_SYS(sys_time , 1)
2054 MIPS_SYS(sys_mknod , 3)
2055 MIPS_SYS(sys_chmod , 2) /* 4015 */
2056 MIPS_SYS(sys_lchown , 3)
2057 MIPS_SYS(sys_ni_syscall , 0)
2058 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */
2059 MIPS_SYS(sys_lseek , 3)
2060 MIPS_SYS(sys_getpid , 0) /* 4020 */
2061 MIPS_SYS(sys_mount , 5)
2062 MIPS_SYS(sys_umount , 1)
2063 MIPS_SYS(sys_setuid , 1)
2064 MIPS_SYS(sys_getuid , 0)
2065 MIPS_SYS(sys_stime , 1) /* 4025 */
2066 MIPS_SYS(sys_ptrace , 4)
2067 MIPS_SYS(sys_alarm , 1)
2068 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */
2069 MIPS_SYS(sys_pause , 0)
2070 MIPS_SYS(sys_utime , 2) /* 4030 */
2071 MIPS_SYS(sys_ni_syscall , 0)
2072 MIPS_SYS(sys_ni_syscall , 0)
2073 MIPS_SYS(sys_access , 2)
2074 MIPS_SYS(sys_nice , 1)
2075 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */
2076 MIPS_SYS(sys_sync , 0)
2077 MIPS_SYS(sys_kill , 2)
2078 MIPS_SYS(sys_rename , 2)
2079 MIPS_SYS(sys_mkdir , 2)
2080 MIPS_SYS(sys_rmdir , 1) /* 4040 */
2081 MIPS_SYS(sys_dup , 1)
2082 MIPS_SYS(sys_pipe , 0)
2083 MIPS_SYS(sys_times , 1)
2084 MIPS_SYS(sys_ni_syscall , 0)
2085 MIPS_SYS(sys_brk , 1) /* 4045 */
2086 MIPS_SYS(sys_setgid , 1)
2087 MIPS_SYS(sys_getgid , 0)
2088 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */
2089 MIPS_SYS(sys_geteuid , 0)
2090 MIPS_SYS(sys_getegid , 0) /* 4050 */
2091 MIPS_SYS(sys_acct , 0)
2092 MIPS_SYS(sys_umount2 , 2)
2093 MIPS_SYS(sys_ni_syscall , 0)
2094 MIPS_SYS(sys_ioctl , 3)
2095 MIPS_SYS(sys_fcntl , 3) /* 4055 */
2096 MIPS_SYS(sys_ni_syscall , 2)
2097 MIPS_SYS(sys_setpgid , 2)
2098 MIPS_SYS(sys_ni_syscall , 0)
2099 MIPS_SYS(sys_olduname , 1)
2100 MIPS_SYS(sys_umask , 1) /* 4060 */
2101 MIPS_SYS(sys_chroot , 1)
2102 MIPS_SYS(sys_ustat , 2)
2103 MIPS_SYS(sys_dup2 , 2)
2104 MIPS_SYS(sys_getppid , 0)
2105 MIPS_SYS(sys_getpgrp , 0) /* 4065 */
2106 MIPS_SYS(sys_setsid , 0)
2107 MIPS_SYS(sys_sigaction , 3)
2108 MIPS_SYS(sys_sgetmask , 0)
2109 MIPS_SYS(sys_ssetmask , 1)
2110 MIPS_SYS(sys_setreuid , 2) /* 4070 */
2111 MIPS_SYS(sys_setregid , 2)
2112 MIPS_SYS(sys_sigsuspend , 0)
2113 MIPS_SYS(sys_sigpending , 1)
2114 MIPS_SYS(sys_sethostname , 2)
2115 MIPS_SYS(sys_setrlimit , 2) /* 4075 */
2116 MIPS_SYS(sys_getrlimit , 2)
2117 MIPS_SYS(sys_getrusage , 2)
2118 MIPS_SYS(sys_gettimeofday, 2)
2119 MIPS_SYS(sys_settimeofday, 2)
2120 MIPS_SYS(sys_getgroups , 2) /* 4080 */
2121 MIPS_SYS(sys_setgroups , 2)
2122 MIPS_SYS(sys_ni_syscall , 0) /* old_select */
2123 MIPS_SYS(sys_symlink , 2)
2124 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */
2125 MIPS_SYS(sys_readlink , 3) /* 4085 */
2126 MIPS_SYS(sys_uselib , 1)
2127 MIPS_SYS(sys_swapon , 2)
2128 MIPS_SYS(sys_reboot , 3)
2129 MIPS_SYS(old_readdir , 3)
2130 MIPS_SYS(old_mmap , 6) /* 4090 */
2131 MIPS_SYS(sys_munmap , 2)
2132 MIPS_SYS(sys_truncate , 2)
2133 MIPS_SYS(sys_ftruncate , 2)
2134 MIPS_SYS(sys_fchmod , 2)
2135 MIPS_SYS(sys_fchown , 3) /* 4095 */
2136 MIPS_SYS(sys_getpriority , 2)
2137 MIPS_SYS(sys_setpriority , 3)
2138 MIPS_SYS(sys_ni_syscall , 0)
2139 MIPS_SYS(sys_statfs , 2)
2140 MIPS_SYS(sys_fstatfs , 2) /* 4100 */
2141 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */
2142 MIPS_SYS(sys_socketcall , 2)
2143 MIPS_SYS(sys_syslog , 3)
2144 MIPS_SYS(sys_setitimer , 3)
2145 MIPS_SYS(sys_getitimer , 2) /* 4105 */
2146 MIPS_SYS(sys_newstat , 2)
2147 MIPS_SYS(sys_newlstat , 2)
2148 MIPS_SYS(sys_newfstat , 2)
2149 MIPS_SYS(sys_uname , 1)
2150 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */
2151 MIPS_SYS(sys_vhangup , 0)
2152 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */
2153 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */
2154 MIPS_SYS(sys_wait4 , 4)
2155 MIPS_SYS(sys_swapoff , 1) /* 4115 */
2156 MIPS_SYS(sys_sysinfo , 1)
2157 MIPS_SYS(sys_ipc , 6)
2158 MIPS_SYS(sys_fsync , 1)
2159 MIPS_SYS(sys_sigreturn , 0)
2160 MIPS_SYS(sys_clone , 6) /* 4120 */
2161 MIPS_SYS(sys_setdomainname, 2)
2162 MIPS_SYS(sys_newuname , 1)
2163 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */
2164 MIPS_SYS(sys_adjtimex , 1)
2165 MIPS_SYS(sys_mprotect , 3) /* 4125 */
2166 MIPS_SYS(sys_sigprocmask , 3)
2167 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */
2168 MIPS_SYS(sys_init_module , 5)
2169 MIPS_SYS(sys_delete_module, 1)
2170 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */
2171 MIPS_SYS(sys_quotactl , 0)
2172 MIPS_SYS(sys_getpgid , 1)
2173 MIPS_SYS(sys_fchdir , 1)
2174 MIPS_SYS(sys_bdflush , 2)
2175 MIPS_SYS(sys_sysfs , 3) /* 4135 */
2176 MIPS_SYS(sys_personality , 1)
2177 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */
2178 MIPS_SYS(sys_setfsuid , 1)
2179 MIPS_SYS(sys_setfsgid , 1)
2180 MIPS_SYS(sys_llseek , 5) /* 4140 */
2181 MIPS_SYS(sys_getdents , 3)
2182 MIPS_SYS(sys_select , 5)
2183 MIPS_SYS(sys_flock , 2)
2184 MIPS_SYS(sys_msync , 3)
2185 MIPS_SYS(sys_readv , 3) /* 4145 */
2186 MIPS_SYS(sys_writev , 3)
2187 MIPS_SYS(sys_cacheflush , 3)
2188 MIPS_SYS(sys_cachectl , 3)
2189 MIPS_SYS(sys_sysmips , 4)
2190 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */
2191 MIPS_SYS(sys_getsid , 1)
2192 MIPS_SYS(sys_fdatasync , 0)
2193 MIPS_SYS(sys_sysctl , 1)
2194 MIPS_SYS(sys_mlock , 2)
2195 MIPS_SYS(sys_munlock , 2) /* 4155 */
2196 MIPS_SYS(sys_mlockall , 1)
2197 MIPS_SYS(sys_munlockall , 0)
2198 MIPS_SYS(sys_sched_setparam, 2)
2199 MIPS_SYS(sys_sched_getparam, 2)
2200 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */
2201 MIPS_SYS(sys_sched_getscheduler, 1)
2202 MIPS_SYS(sys_sched_yield , 0)
2203 MIPS_SYS(sys_sched_get_priority_max, 1)
2204 MIPS_SYS(sys_sched_get_priority_min, 1)
2205 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */
2206 MIPS_SYS(sys_nanosleep, 2)
2207 MIPS_SYS(sys_mremap , 5)
2208 MIPS_SYS(sys_accept , 3)
2209 MIPS_SYS(sys_bind , 3)
2210 MIPS_SYS(sys_connect , 3) /* 4170 */
2211 MIPS_SYS(sys_getpeername , 3)
2212 MIPS_SYS(sys_getsockname , 3)
2213 MIPS_SYS(sys_getsockopt , 5)
2214 MIPS_SYS(sys_listen , 2)
2215 MIPS_SYS(sys_recv , 4) /* 4175 */
2216 MIPS_SYS(sys_recvfrom , 6)
2217 MIPS_SYS(sys_recvmsg , 3)
2218 MIPS_SYS(sys_send , 4)
2219 MIPS_SYS(sys_sendmsg , 3)
2220 MIPS_SYS(sys_sendto , 6) /* 4180 */
2221 MIPS_SYS(sys_setsockopt , 5)
2222 MIPS_SYS(sys_shutdown , 2)
2223 MIPS_SYS(sys_socket , 3)
2224 MIPS_SYS(sys_socketpair , 4)
2225 MIPS_SYS(sys_setresuid , 3) /* 4185 */
2226 MIPS_SYS(sys_getresuid , 3)
2227 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */
2228 MIPS_SYS(sys_poll , 3)
2229 MIPS_SYS(sys_nfsservctl , 3)
2230 MIPS_SYS(sys_setresgid , 3) /* 4190 */
2231 MIPS_SYS(sys_getresgid , 3)
2232 MIPS_SYS(sys_prctl , 5)
2233 MIPS_SYS(sys_rt_sigreturn, 0)
2234 MIPS_SYS(sys_rt_sigaction, 4)
2235 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */
2236 MIPS_SYS(sys_rt_sigpending, 2)
2237 MIPS_SYS(sys_rt_sigtimedwait, 4)
2238 MIPS_SYS(sys_rt_sigqueueinfo, 3)
2239 MIPS_SYS(sys_rt_sigsuspend, 0)
2240 MIPS_SYS(sys_pread64 , 6) /* 4200 */
2241 MIPS_SYS(sys_pwrite64 , 6)
2242 MIPS_SYS(sys_chown , 3)
2243 MIPS_SYS(sys_getcwd , 2)
2244 MIPS_SYS(sys_capget , 2)
2245 MIPS_SYS(sys_capset , 2) /* 4205 */
2246 MIPS_SYS(sys_sigaltstack , 2)
2247 MIPS_SYS(sys_sendfile , 4)
2248 MIPS_SYS(sys_ni_syscall , 0)
2249 MIPS_SYS(sys_ni_syscall , 0)
2250 MIPS_SYS(sys_mmap2 , 6) /* 4210 */
2251 MIPS_SYS(sys_truncate64 , 4)
2252 MIPS_SYS(sys_ftruncate64 , 4)
2253 MIPS_SYS(sys_stat64 , 2)
2254 MIPS_SYS(sys_lstat64 , 2)
2255 MIPS_SYS(sys_fstat64 , 2) /* 4215 */
2256 MIPS_SYS(sys_pivot_root , 2)
2257 MIPS_SYS(sys_mincore , 3)
2258 MIPS_SYS(sys_madvise , 3)
2259 MIPS_SYS(sys_getdents64 , 3)
2260 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */
2261 MIPS_SYS(sys_ni_syscall , 0)
2262 MIPS_SYS(sys_gettid , 0)
2263 MIPS_SYS(sys_readahead , 5)
2264 MIPS_SYS(sys_setxattr , 5)
2265 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */
2266 MIPS_SYS(sys_fsetxattr , 5)
2267 MIPS_SYS(sys_getxattr , 4)
2268 MIPS_SYS(sys_lgetxattr , 4)
2269 MIPS_SYS(sys_fgetxattr , 4)
2270 MIPS_SYS(sys_listxattr , 3) /* 4230 */
2271 MIPS_SYS(sys_llistxattr , 3)
2272 MIPS_SYS(sys_flistxattr , 3)
2273 MIPS_SYS(sys_removexattr , 2)
2274 MIPS_SYS(sys_lremovexattr, 2)
2275 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */
2276 MIPS_SYS(sys_tkill , 2)
2277 MIPS_SYS(sys_sendfile64 , 5)
2278 MIPS_SYS(sys_futex , 6)
2279 MIPS_SYS(sys_sched_setaffinity, 3)
2280 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */
2281 MIPS_SYS(sys_io_setup , 2)
2282 MIPS_SYS(sys_io_destroy , 1)
2283 MIPS_SYS(sys_io_getevents, 5)
2284 MIPS_SYS(sys_io_submit , 3)
2285 MIPS_SYS(sys_io_cancel , 3) /* 4245 */
2286 MIPS_SYS(sys_exit_group , 1)
2287 MIPS_SYS(sys_lookup_dcookie, 3)
2288 MIPS_SYS(sys_epoll_create, 1)
2289 MIPS_SYS(sys_epoll_ctl , 4)
2290 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */
2291 MIPS_SYS(sys_remap_file_pages, 5)
2292 MIPS_SYS(sys_set_tid_address, 1)
2293 MIPS_SYS(sys_restart_syscall, 0)
2294 MIPS_SYS(sys_fadvise64_64, 7)
2295 MIPS_SYS(sys_statfs64 , 3) /* 4255 */
2296 MIPS_SYS(sys_fstatfs64 , 2)
2297 MIPS_SYS(sys_timer_create, 3)
2298 MIPS_SYS(sys_timer_settime, 4)
2299 MIPS_SYS(sys_timer_gettime, 2)
2300 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */
2301 MIPS_SYS(sys_timer_delete, 1)
2302 MIPS_SYS(sys_clock_settime, 2)
2303 MIPS_SYS(sys_clock_gettime, 2)
2304 MIPS_SYS(sys_clock_getres, 2)
2305 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */
2306 MIPS_SYS(sys_tgkill , 3)
2307 MIPS_SYS(sys_utimes , 2)
2308 MIPS_SYS(sys_mbind , 4)
2309 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */
2310 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */
2311 MIPS_SYS(sys_mq_open , 4)
2312 MIPS_SYS(sys_mq_unlink , 1)
2313 MIPS_SYS(sys_mq_timedsend, 5)
2314 MIPS_SYS(sys_mq_timedreceive, 5)
2315 MIPS_SYS(sys_mq_notify , 2) /* 4275 */
2316 MIPS_SYS(sys_mq_getsetattr, 3)
2317 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */
2318 MIPS_SYS(sys_waitid , 4)
2319 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */
2320 MIPS_SYS(sys_add_key , 5)
2321 MIPS_SYS(sys_request_key, 4)
2322 MIPS_SYS(sys_keyctl , 5)
2323 MIPS_SYS(sys_set_thread_area, 1)
2324 MIPS_SYS(sys_inotify_init, 0)
2325 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */
2326 MIPS_SYS(sys_inotify_rm_watch, 2)
2327 MIPS_SYS(sys_migrate_pages, 4)
2328 MIPS_SYS(sys_openat, 4)
2329 MIPS_SYS(sys_mkdirat, 3)
2330 MIPS_SYS(sys_mknodat, 4) /* 4290 */
2331 MIPS_SYS(sys_fchownat, 5)
2332 MIPS_SYS(sys_futimesat, 3)
2333 MIPS_SYS(sys_fstatat64, 4)
2334 MIPS_SYS(sys_unlinkat, 3)
2335 MIPS_SYS(sys_renameat, 4) /* 4295 */
2336 MIPS_SYS(sys_linkat, 5)
2337 MIPS_SYS(sys_symlinkat, 3)
2338 MIPS_SYS(sys_readlinkat, 4)
2339 MIPS_SYS(sys_fchmodat, 3)
2340 MIPS_SYS(sys_faccessat, 3) /* 4300 */
2341 MIPS_SYS(sys_pselect6, 6)
2342 MIPS_SYS(sys_ppoll, 5)
2343 MIPS_SYS(sys_unshare, 1)
2344 MIPS_SYS(sys_splice, 6)
2345 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */
2346 MIPS_SYS(sys_tee, 4)
2347 MIPS_SYS(sys_vmsplice, 4)
2348 MIPS_SYS(sys_move_pages, 6)
2349 MIPS_SYS(sys_set_robust_list, 2)
2350 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */
2351 MIPS_SYS(sys_kexec_load, 4)
2352 MIPS_SYS(sys_getcpu, 3)
2353 MIPS_SYS(sys_epoll_pwait, 6)
2354 MIPS_SYS(sys_ioprio_set, 3)
2355 MIPS_SYS(sys_ioprio_get, 2)
2356 MIPS_SYS(sys_utimensat, 4)
2357 MIPS_SYS(sys_signalfd, 3)
2358 MIPS_SYS(sys_ni_syscall, 0) /* was timerfd */
2359 MIPS_SYS(sys_eventfd, 1)
2360 MIPS_SYS(sys_fallocate, 6) /* 4320 */
2361 MIPS_SYS(sys_timerfd_create, 2)
2362 MIPS_SYS(sys_timerfd_gettime, 2)
2363 MIPS_SYS(sys_timerfd_settime, 4)
2364 MIPS_SYS(sys_signalfd4, 4)
2365 MIPS_SYS(sys_eventfd2, 2) /* 4325 */
2366 MIPS_SYS(sys_epoll_create1, 1)
2367 MIPS_SYS(sys_dup3, 3)
2368 MIPS_SYS(sys_pipe2, 2)
2369 MIPS_SYS(sys_inotify_init1, 1)
2370 MIPS_SYS(sys_preadv, 6) /* 4330 */
2371 MIPS_SYS(sys_pwritev, 6)
2372 MIPS_SYS(sys_rt_tgsigqueueinfo, 4)
2373 MIPS_SYS(sys_perf_event_open, 5)
2374 MIPS_SYS(sys_accept4, 4)
2375 MIPS_SYS(sys_recvmmsg, 5) /* 4335 */
2376 MIPS_SYS(sys_fanotify_init, 2)
2377 MIPS_SYS(sys_fanotify_mark, 6)
2378 MIPS_SYS(sys_prlimit64, 4)
2379 MIPS_SYS(sys_name_to_handle_at, 5)
2380 MIPS_SYS(sys_open_by_handle_at, 3) /* 4340 */
2381 MIPS_SYS(sys_clock_adjtime, 2)
2382 MIPS_SYS(sys_syncfs, 1)
2383 };
2384 # undef MIPS_SYS
2385 # endif /* O32 */
2386
2387 static int do_store_exclusive(CPUMIPSState *env)
2388 {
2389 target_ulong addr;
2390 target_ulong page_addr;
2391 target_ulong val;
2392 int flags;
2393 int segv = 0;
2394 int reg;
2395 int d;
2396
2397 addr = env->lladdr;
2398 page_addr = addr & TARGET_PAGE_MASK;
2399 start_exclusive();
2400 mmap_lock();
2401 flags = page_get_flags(page_addr);
2402 if ((flags & PAGE_READ) == 0) {
2403 segv = 1;
2404 } else {
2405 reg = env->llreg & 0x1f;
2406 d = (env->llreg & 0x20) != 0;
2407 if (d) {
2408 segv = get_user_s64(val, addr);
2409 } else {
2410 segv = get_user_s32(val, addr);
2411 }
2412 if (!segv) {
2413 if (val != env->llval) {
2414 env->active_tc.gpr[reg] = 0;
2415 } else {
2416 if (d) {
2417 segv = put_user_u64(env->llnewval, addr);
2418 } else {
2419 segv = put_user_u32(env->llnewval, addr);
2420 }
2421 if (!segv) {
2422 env->active_tc.gpr[reg] = 1;
2423 }
2424 }
2425 }
2426 }
2427 env->lladdr = -1;
2428 if (!segv) {
2429 env->active_tc.PC += 4;
2430 }
2431 mmap_unlock();
2432 end_exclusive();
2433 return segv;
2434 }
2435
2436 /* Break codes */
2437 enum {
2438 BRK_OVERFLOW = 6,
2439 BRK_DIVZERO = 7
2440 };
2441
2442 static int do_break(CPUMIPSState *env, target_siginfo_t *info,
2443 unsigned int code)
2444 {
2445 int ret = -1;
2446
2447 switch (code) {
2448 case BRK_OVERFLOW:
2449 case BRK_DIVZERO:
2450 info->si_signo = TARGET_SIGFPE;
2451 info->si_errno = 0;
2452 info->si_code = (code == BRK_OVERFLOW) ? FPE_INTOVF : FPE_INTDIV;
2453 queue_signal(env, info->si_signo, &*info);
2454 ret = 0;
2455 break;
2456 default:
2457 info->si_signo = TARGET_SIGTRAP;
2458 info->si_errno = 0;
2459 queue_signal(env, info->si_signo, &*info);
2460 ret = 0;
2461 break;
2462 }
2463
2464 return ret;
2465 }
2466
2467 void cpu_loop(CPUMIPSState *env)
2468 {
2469 CPUState *cs = CPU(mips_env_get_cpu(env));
2470 target_siginfo_t info;
2471 int trapnr;
2472 abi_long ret;
2473 # ifdef TARGET_ABI_MIPSO32
2474 unsigned int syscall_num;
2475 # endif
2476
2477 for(;;) {
2478 cpu_exec_start(cs);
2479 trapnr = cpu_mips_exec(cs);
2480 cpu_exec_end(cs);
2481 switch(trapnr) {
2482 case EXCP_SYSCALL:
2483 env->active_tc.PC += 4;
2484 # ifdef TARGET_ABI_MIPSO32
2485 syscall_num = env->active_tc.gpr[2] - 4000;
2486 if (syscall_num >= sizeof(mips_syscall_args)) {
2487 ret = -TARGET_ENOSYS;
2488 } else {
2489 int nb_args;
2490 abi_ulong sp_reg;
2491 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;
2492
2493 nb_args = mips_syscall_args[syscall_num];
2494 sp_reg = env->active_tc.gpr[29];
2495 switch (nb_args) {
2496 /* these arguments are taken from the stack */
2497 case 8:
2498 if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) {
2499 goto done_syscall;
2500 }
2501 case 7:
2502 if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) {
2503 goto done_syscall;
2504 }
2505 case 6:
2506 if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) {
2507 goto done_syscall;
2508 }
2509 case 5:
2510 if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) {
2511 goto done_syscall;
2512 }
2513 default:
2514 break;
2515 }
2516 ret = do_syscall(env, env->active_tc.gpr[2],
2517 env->active_tc.gpr[4],
2518 env->active_tc.gpr[5],
2519 env->active_tc.gpr[6],
2520 env->active_tc.gpr[7],
2521 arg5, arg6, arg7, arg8);
2522 }
2523 done_syscall:
2524 # else
2525 ret = do_syscall(env, env->active_tc.gpr[2],
2526 env->active_tc.gpr[4], env->active_tc.gpr[5],
2527 env->active_tc.gpr[6], env->active_tc.gpr[7],
2528 env->active_tc.gpr[8], env->active_tc.gpr[9],
2529 env->active_tc.gpr[10], env->active_tc.gpr[11]);
2530 # endif /* O32 */
2531 if (ret == -TARGET_ERESTARTSYS) {
2532 env->active_tc.PC -= 4;
2533 break;
2534 }
2535 if (ret == -TARGET_QEMU_ESIGRETURN) {
2536 /* Returning from a successful sigreturn syscall.
2537 Avoid clobbering register state. */
2538 break;
2539 }
2540 if ((abi_ulong)ret >= (abi_ulong)-1133) {
2541 env->active_tc.gpr[7] = 1; /* error flag */
2542 ret = -ret;
2543 } else {
2544 env->active_tc.gpr[7] = 0; /* error flag */
2545 }
2546 env->active_tc.gpr[2] = ret;
2547 break;
2548 case EXCP_TLBL:
2549 case EXCP_TLBS:
2550 case EXCP_AdEL:
2551 case EXCP_AdES:
2552 info.si_signo = TARGET_SIGSEGV;
2553 info.si_errno = 0;
2554 /* XXX: check env->error_code */
2555 info.si_code = TARGET_SEGV_MAPERR;
2556 info._sifields._sigfault._addr = env->CP0_BadVAddr;
2557 queue_signal(env, info.si_signo, &info);
2558 break;
2559 case EXCP_CpU:
2560 case EXCP_RI:
2561 info.si_signo = TARGET_SIGILL;
2562 info.si_errno = 0;
2563 info.si_code = 0;
2564 queue_signal(env, info.si_signo, &info);
2565 break;
2566 case EXCP_INTERRUPT:
2567 /* just indicate that signals should be handled asap */
2568 break;
2569 case EXCP_DEBUG:
2570 {
2571 int sig;
2572
2573 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2574 if (sig)
2575 {
2576 info.si_signo = sig;
2577 info.si_errno = 0;
2578 info.si_code = TARGET_TRAP_BRKPT;
2579 queue_signal(env, info.si_signo, &info);
2580 }
2581 }
2582 break;
2583 case EXCP_SC:
2584 if (do_store_exclusive(env)) {
2585 info.si_signo = TARGET_SIGSEGV;
2586 info.si_errno = 0;
2587 info.si_code = TARGET_SEGV_MAPERR;
2588 info._sifields._sigfault._addr = env->active_tc.PC;
2589 queue_signal(env, info.si_signo, &info);
2590 }
2591 break;
2592 case EXCP_DSPDIS:
2593 info.si_signo = TARGET_SIGILL;
2594 info.si_errno = 0;
2595 info.si_code = TARGET_ILL_ILLOPC;
2596 queue_signal(env, info.si_signo, &info);
2597 break;
2598 /* The code below was inspired by the MIPS Linux kernel trap
2599 * handling code in arch/mips/kernel/traps.c.
2600 */
2601 case EXCP_BREAK:
2602 {
2603 abi_ulong trap_instr;
2604 unsigned int code;
2605
2606 if (env->hflags & MIPS_HFLAG_M16) {
2607 if (env->insn_flags & ASE_MICROMIPS) {
2608 /* microMIPS mode */
2609 ret = get_user_u16(trap_instr, env->active_tc.PC);
2610 if (ret != 0) {
2611 goto error;
2612 }
2613
2614 if ((trap_instr >> 10) == 0x11) {
2615 /* 16-bit instruction */
2616 code = trap_instr & 0xf;
2617 } else {
2618 /* 32-bit instruction */
2619 abi_ulong instr_lo;
2620
2621 ret = get_user_u16(instr_lo,
2622 env->active_tc.PC + 2);
2623 if (ret != 0) {
2624 goto error;
2625 }
2626 trap_instr = (trap_instr << 16) | instr_lo;
2627 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2628 /* Unfortunately, microMIPS also suffers from
2629 the old assembler bug... */
2630 if (code >= (1 << 10)) {
2631 code >>= 10;
2632 }
2633 }
2634 } else {
2635 /* MIPS16e mode */
2636 ret = get_user_u16(trap_instr, env->active_tc.PC);
2637 if (ret != 0) {
2638 goto error;
2639 }
2640 code = (trap_instr >> 6) & 0x3f;
2641 }
2642 } else {
2643 ret = get_user_u32(trap_instr, env->active_tc.PC);
2644 if (ret != 0) {
2645 goto error;
2646 }
2647
2648 /* As described in the original Linux kernel code, the
2649 * below checks on 'code' are to work around an old
2650 * assembly bug.
2651 */
2652 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2653 if (code >= (1 << 10)) {
2654 code >>= 10;
2655 }
2656 }
2657
2658 if (do_break(env, &info, code) != 0) {
2659 goto error;
2660 }
2661 }
2662 break;
2663 case EXCP_TRAP:
2664 {
2665 abi_ulong trap_instr;
2666 unsigned int code = 0;
2667
2668 if (env->hflags & MIPS_HFLAG_M16) {
2669 /* microMIPS mode */
2670 abi_ulong instr[2];
2671
2672 ret = get_user_u16(instr[0], env->active_tc.PC) ||
2673 get_user_u16(instr[1], env->active_tc.PC + 2);
2674
2675 trap_instr = (instr[0] << 16) | instr[1];
2676 } else {
2677 ret = get_user_u32(trap_instr, env->active_tc.PC);
2678 }
2679
2680 if (ret != 0) {
2681 goto error;
2682 }
2683
2684 /* The immediate versions don't provide a code. */
2685 if (!(trap_instr & 0xFC000000)) {
2686 if (env->hflags & MIPS_HFLAG_M16) {
2687 /* microMIPS mode */
2688 code = ((trap_instr >> 12) & ((1 << 4) - 1));
2689 } else {
2690 code = ((trap_instr >> 6) & ((1 << 10) - 1));
2691 }
2692 }
2693
2694 if (do_break(env, &info, code) != 0) {
2695 goto error;
2696 }
2697 }
2698 break;
2699 default:
2700 error:
2701 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
2702 abort();
2703 }
2704 process_pending_signals(env);
2705 }
2706 }
2707 #endif
2708
2709 #ifdef TARGET_OPENRISC
2710
2711 void cpu_loop(CPUOpenRISCState *env)
2712 {
2713 CPUState *cs = CPU(openrisc_env_get_cpu(env));
2714 int trapnr, gdbsig;
2715
2716 for (;;) {
2717 cpu_exec_start(cs);
2718 trapnr = cpu_openrisc_exec(cs);
2719 cpu_exec_end(cs);
2720 gdbsig = 0;
2721
2722 switch (trapnr) {
2723 case EXCP_RESET:
2724 qemu_log_mask(CPU_LOG_INT, "\nReset request, exit, pc is %#x\n", env->pc);
2725 exit(EXIT_FAILURE);
2726 break;
2727 case EXCP_BUSERR:
2728 qemu_log_mask(CPU_LOG_INT, "\nBus error, exit, pc is %#x\n", env->pc);
2729 gdbsig = TARGET_SIGBUS;
2730 break;
2731 case EXCP_DPF:
2732 case EXCP_IPF:
2733 cpu_dump_state(cs, stderr, fprintf, 0);
2734 gdbsig = TARGET_SIGSEGV;
2735 break;
2736 case EXCP_TICK:
2737 qemu_log_mask(CPU_LOG_INT, "\nTick time interrupt pc is %#x\n", env->pc);
2738 break;
2739 case EXCP_ALIGN:
2740 qemu_log_mask(CPU_LOG_INT, "\nAlignment pc is %#x\n", env->pc);
2741 gdbsig = TARGET_SIGBUS;
2742 break;
2743 case EXCP_ILLEGAL:
2744 qemu_log_mask(CPU_LOG_INT, "\nIllegal instructionpc is %#x\n", env->pc);
2745 gdbsig = TARGET_SIGILL;
2746 break;
2747 case EXCP_INT:
2748 qemu_log_mask(CPU_LOG_INT, "\nExternal interruptpc is %#x\n", env->pc);
2749 break;
2750 case EXCP_DTLBMISS:
2751 case EXCP_ITLBMISS:
2752 qemu_log_mask(CPU_LOG_INT, "\nTLB miss\n");
2753 break;
2754 case EXCP_RANGE:
2755 qemu_log_mask(CPU_LOG_INT, "\nRange\n");
2756 gdbsig = TARGET_SIGSEGV;
2757 break;
2758 case EXCP_SYSCALL:
2759 env->pc += 4; /* 0xc00; */
2760 env->gpr[11] = do_syscall(env,
2761 env->gpr[11], /* return value */
2762 env->gpr[3], /* r3 - r7 are params */
2763 env->gpr[4],
2764 env->gpr[5],
2765 env->gpr[6],
2766 env->gpr[7],
2767 env->gpr[8], 0, 0);
2768 break;
2769 case EXCP_FPE:
2770 qemu_log_mask(CPU_LOG_INT, "\nFloating point error\n");
2771 break;
2772 case EXCP_TRAP:
2773 qemu_log_mask(CPU_LOG_INT, "\nTrap\n");
2774 gdbsig = TARGET_SIGTRAP;
2775 break;
2776 case EXCP_NR:
2777 qemu_log_mask(CPU_LOG_INT, "\nNR\n");
2778 break;
2779 default:
2780 EXCP_DUMP(env, "\nqemu: unhandled CPU exception %#x - aborting\n",
2781 trapnr);
2782 gdbsig = TARGET_SIGILL;
2783 break;
2784 }
2785 if (gdbsig) {
2786 gdb_handlesig(cs, gdbsig);
2787 if (gdbsig != TARGET_SIGTRAP) {
2788 exit(EXIT_FAILURE);
2789 }
2790 }
2791
2792 process_pending_signals(env);
2793 }
2794 }
2795
2796 #endif /* TARGET_OPENRISC */
2797
2798 #ifdef TARGET_SH4
2799 void cpu_loop(CPUSH4State *env)
2800 {
2801 CPUState *cs = CPU(sh_env_get_cpu(env));
2802 int trapnr, ret;
2803 target_siginfo_t info;
2804
2805 while (1) {
2806 cpu_exec_start(cs);
2807 trapnr = cpu_sh4_exec(cs);
2808 cpu_exec_end(cs);
2809
2810 switch (trapnr) {
2811 case 0x160:
2812 env->pc += 2;
2813 ret = do_syscall(env,
2814 env->gregs[3],
2815 env->gregs[4],
2816 env->gregs[5],
2817 env->gregs[6],
2818 env->gregs[7],
2819 env->gregs[0],
2820 env->gregs[1],
2821 0, 0);
2822 env->gregs[0] = ret;
2823 break;
2824 case EXCP_INTERRUPT:
2825 /* just indicate that signals should be handled asap */
2826 break;
2827 case EXCP_DEBUG:
2828 {
2829 int sig;
2830
2831 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2832 if (sig)
2833 {
2834 info.si_signo = sig;
2835 info.si_errno = 0;
2836 info.si_code = TARGET_TRAP_BRKPT;
2837 queue_signal(env, info.si_signo, &info);
2838 }
2839 }
2840 break;
2841 case 0xa0:
2842 case 0xc0:
2843 info.si_signo = TARGET_SIGSEGV;
2844 info.si_errno = 0;
2845 info.si_code = TARGET_SEGV_MAPERR;
2846 info._sifields._sigfault._addr = env->tea;
2847 queue_signal(env, info.si_signo, &info);
2848 break;
2849
2850 default:
2851 printf ("Unhandled trap: 0x%x\n", trapnr);
2852 cpu_dump_state(cs, stderr, fprintf, 0);
2853 exit(EXIT_FAILURE);
2854 }
2855 process_pending_signals (env);
2856 }
2857 }
2858 #endif
2859
2860 #ifdef TARGET_CRIS
2861 void cpu_loop(CPUCRISState *env)
2862 {
2863 CPUState *cs = CPU(cris_env_get_cpu(env));
2864 int trapnr, ret;
2865 target_siginfo_t info;
2866
2867 while (1) {
2868 cpu_exec_start(cs);
2869 trapnr = cpu_cris_exec(cs);
2870 cpu_exec_end(cs);
2871 switch (trapnr) {
2872 case 0xaa:
2873 {
2874 info.si_signo = TARGET_SIGSEGV;
2875 info.si_errno = 0;
2876 /* XXX: check env->error_code */
2877 info.si_code = TARGET_SEGV_MAPERR;
2878 info._sifields._sigfault._addr = env->pregs[PR_EDA];
2879 queue_signal(env, info.si_signo, &info);
2880 }
2881 break;
2882 case EXCP_INTERRUPT:
2883 /* just indicate that signals should be handled asap */
2884 break;
2885 case EXCP_BREAK:
2886 ret = do_syscall(env,
2887 env->regs[9],
2888 env->regs[10],
2889 env->regs[11],
2890 env->regs[12],
2891 env->regs[13],
2892 env->pregs[7],
2893 env->pregs[11],
2894 0, 0);
2895 env->regs[10] = ret;
2896 break;
2897 case EXCP_DEBUG:
2898 {
2899 int sig;
2900
2901 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2902 if (sig)
2903 {
2904 info.si_signo = sig;
2905 info.si_errno = 0;
2906 info.si_code = TARGET_TRAP_BRKPT;
2907 queue_signal(env, info.si_signo, &info);
2908 }
2909 }
2910 break;
2911 default:
2912 printf ("Unhandled trap: 0x%x\n", trapnr);
2913 cpu_dump_state(cs, stderr, fprintf, 0);
2914 exit(EXIT_FAILURE);
2915 }
2916 process_pending_signals (env);
2917 }
2918 }
2919 #endif
2920
2921 #ifdef TARGET_MICROBLAZE
2922 void cpu_loop(CPUMBState *env)
2923 {
2924 CPUState *cs = CPU(mb_env_get_cpu(env));
2925 int trapnr, ret;
2926 target_siginfo_t info;
2927
2928 while (1) {
2929 cpu_exec_start(cs);
2930 trapnr = cpu_mb_exec(cs);
2931 cpu_exec_end(cs);
2932 switch (trapnr) {
2933 case 0xaa:
2934 {
2935 info.si_signo = TARGET_SIGSEGV;
2936 info.si_errno = 0;
2937 /* XXX: check env->error_code */
2938 info.si_code = TARGET_SEGV_MAPERR;
2939 info._sifields._sigfault._addr = 0;
2940 queue_signal(env, info.si_signo, &info);
2941 }
2942 break;
2943 case EXCP_INTERRUPT:
2944 /* just indicate that signals should be handled asap */
2945 break;
2946 case EXCP_BREAK:
2947 /* Return address is 4 bytes after the call. */
2948 env->regs[14] += 4;
2949 env->sregs[SR_PC] = env->regs[14];
2950 ret = do_syscall(env,
2951 env->regs[12],
2952 env->regs[5],
2953 env->regs[6],
2954 env->regs[7],
2955 env->regs[8],
2956 env->regs[9],
2957 env->regs[10],
2958 0, 0);
2959 env->regs[3] = ret;
2960 break;
2961 case EXCP_HW_EXCP:
2962 env->regs[17] = env->sregs[SR_PC] + 4;
2963 if (env->iflags & D_FLAG) {
2964 env->sregs[SR_ESR] |= 1 << 12;
2965 env->sregs[SR_PC] -= 4;
2966 /* FIXME: if branch was immed, replay the imm as well. */
2967 }
2968
2969 env->iflags &= ~(IMM_FLAG | D_FLAG);
2970
2971 switch (env->sregs[SR_ESR] & 31) {
2972 case ESR_EC_DIVZERO:
2973 info.si_signo = TARGET_SIGFPE;
2974 info.si_errno = 0;
2975 info.si_code = TARGET_FPE_FLTDIV;
2976 info._sifields._sigfault._addr = 0;
2977 queue_signal(env, info.si_signo, &info);
2978 break;
2979 case ESR_EC_FPU:
2980 info.si_signo = TARGET_SIGFPE;
2981 info.si_errno = 0;
2982 if (env->sregs[SR_FSR] & FSR_IO) {
2983 info.si_code = TARGET_FPE_FLTINV;
2984 }
2985 if (env->sregs[SR_FSR] & FSR_DZ) {
2986 info.si_code = TARGET_FPE_FLTDIV;
2987 }
2988 info._sifields._sigfault._addr = 0;
2989 queue_signal(env, info.si_signo, &info);
2990 break;
2991 default:
2992 printf ("Unhandled hw-exception: 0x%x\n",
2993 env->sregs[SR_ESR] & ESR_EC_MASK);
2994 cpu_dump_state(cs, stderr, fprintf, 0);
2995 exit(EXIT_FAILURE);
2996 break;
2997 }
2998 break;
2999 case EXCP_DEBUG:
3000 {
3001 int sig;
3002
3003 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
3004 if (sig)
3005 {
3006 info.si_signo = sig;
3007 info.si_errno = 0;
3008 info.si_code = TARGET_TRAP_BRKPT;
3009 queue_signal(env, info.si_signo, &info);
3010 }
3011 }
3012 break;
3013 default:
3014 printf ("Unhandled trap: 0x%x\n", trapnr);
3015 cpu_dump_state(cs, stderr, fprintf, 0);
3016 exit(EXIT_FAILURE);
3017 }
3018 process_pending_signals (env);
3019 }
3020 }
3021 #endif
3022
3023 #ifdef TARGET_M68K
3024
3025 void cpu_loop(CPUM68KState *env)
3026 {
3027 CPUState *cs = CPU(m68k_env_get_cpu(env));
3028 int trapnr;
3029 unsigned int n;
3030 target_siginfo_t info;
3031 TaskState *ts = cs->opaque;
3032
3033 for(;;) {
3034 cpu_exec_start(cs);
3035 trapnr = cpu_m68k_exec(cs);
3036 cpu_exec_end(cs);
3037 switch(trapnr) {
3038 case EXCP_ILLEGAL:
3039 {
3040 if (ts->sim_syscalls) {
3041 uint16_t nr;
3042 get_user_u16(nr, env->pc + 2);
3043 env->pc += 4;
3044 do_m68k_simcall(env, nr);
3045 } else {
3046 goto do_sigill;
3047 }
3048 }
3049 break;
3050 case EXCP_HALT_INSN:
3051 /* Semihosing syscall. */
3052 env->pc += 4;
3053 do_m68k_semihosting(env, env->dregs[0]);
3054 break;
3055 case EXCP_LINEA:
3056 case EXCP_LINEF:
3057 case EXCP_UNSUPPORTED:
3058 do_sigill:
3059 info.si_signo = TARGET_SIGILL;
3060 info.si_errno = 0;
3061 info.si_code = TARGET_ILL_ILLOPN;
3062 info._sifields._sigfault._addr = env->pc;
3063 queue_signal(env, info.si_signo, &info);
3064 break;
3065 case EXCP_TRAP0:
3066 {
3067 ts->sim_syscalls = 0;
3068 n = env->dregs[0];
3069 env->pc += 2;
3070 env->dregs[0] = do_syscall(env,
3071 n,
3072 env->dregs[1],
3073 env->dregs[2],
3074 env->dregs[3],
3075 env->dregs[4],
3076 env->dregs[5],
3077 env->aregs[0],
3078 0, 0);
3079 }
3080 break;
3081 case EXCP_INTERRUPT:
3082 /* just indicate that signals should be handled asap */
3083 break;
3084 case EXCP_ACCESS:
3085 {
3086 info.si_signo = TARGET_SIGSEGV;
3087 info.si_errno = 0;
3088 /* XXX: check env->error_code */
3089 info.si_code = TARGET_SEGV_MAPERR;
3090 info._sifields._sigfault._addr = env->mmu.ar;
3091 queue_signal(env, info.si_signo, &info);
3092 }
3093 break;
3094 case EXCP_DEBUG:
3095 {
3096 int sig;
3097
3098 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
3099 if (sig)
3100 {
3101 info.si_signo = sig;
3102 info.si_errno = 0;
3103 info.si_code = TARGET_TRAP_BRKPT;
3104 queue_signal(env, info.si_signo, &info);
3105 }
3106 }
3107 break;
3108 default:
3109 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
3110 abort();
3111 }
3112 process_pending_signals(env);
3113 }
3114 }
3115 #endif /* TARGET_M68K */
3116
3117 #ifdef TARGET_ALPHA
3118 static void do_store_exclusive(CPUAlphaState *env, int reg, int quad)
3119 {
3120 target_ulong addr, val, tmp;
3121 target_siginfo_t info;
3122 int ret = 0;
3123
3124 addr = env->lock_addr;
3125 tmp = env->lock_st_addr;
3126 env->lock_addr = -1;
3127 env->lock_st_addr = 0;
3128
3129 start_exclusive();
3130 mmap_lock();
3131
3132 if (addr == tmp) {
3133 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3134 goto do_sigsegv;
3135 }
3136
3137 if (val == env->lock_value) {
3138 tmp = env->ir[reg];
3139 if (quad ? put_user_u64(tmp, addr) : put_user_u32(tmp, addr)) {
3140 goto do_sigsegv;
3141 }
3142 ret = 1;
3143 }
3144 }
3145 env->ir[reg] = ret;
3146 env->pc += 4;
3147
3148 mmap_unlock();
3149 end_exclusive();
3150 return;
3151
3152 do_sigsegv:
3153 mmap_unlock();
3154 end_exclusive();
3155
3156 info.si_signo = TARGET_SIGSEGV;
3157 info.si_errno = 0;
3158 info.si_code = TARGET_SEGV_MAPERR;
3159 info._sifields._sigfault._addr = addr;
3160 queue_signal(env, TARGET_SIGSEGV, &info);
3161 }
3162
3163 void cpu_loop(CPUAlphaState *env)
3164 {
3165 CPUState *cs = CPU(alpha_env_get_cpu(env));
3166 int trapnr;
3167 target_siginfo_t info;
3168 abi_long sysret;
3169
3170 while (1) {
3171 cpu_exec_start(cs);
3172 trapnr = cpu_alpha_exec(cs);
3173 cpu_exec_end(cs);
3174
3175 /* All of the traps imply a transition through PALcode, which
3176 implies an REI instruction has been executed. Which means
3177 that the intr_flag should be cleared. */
3178 env->intr_flag = 0;
3179
3180 switch (trapnr) {
3181 case EXCP_RESET:
3182 fprintf(stderr, "Reset requested. Exit\n");
3183 exit(EXIT_FAILURE);
3184 break;
3185 case EXCP_MCHK:
3186 fprintf(stderr, "Machine check exception. Exit\n");
3187 exit(EXIT_FAILURE);
3188 break;
3189 case EXCP_SMP_INTERRUPT:
3190 case EXCP_CLK_INTERRUPT:
3191 case EXCP_DEV_INTERRUPT:
3192 fprintf(stderr, "External interrupt. Exit\n");
3193 exit(EXIT_FAILURE);
3194 break;
3195 case EXCP_MMFAULT:
3196 env->lock_addr = -1;
3197 info.si_signo = TARGET_SIGSEGV;
3198 info.si_errno = 0;
3199 info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID
3200 ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR);
3201 info._sifields._sigfault._addr = env->trap_arg0;
3202 queue_signal(env, info.si_signo, &info);
3203 break;
3204 case EXCP_UNALIGN:
3205 env->lock_addr = -1;
3206 info.si_signo = TARGET_SIGBUS;
3207 info.si_errno = 0;
3208 info.si_code = TARGET_BUS_ADRALN;
3209 info._sifields._sigfault._addr = env->trap_arg0;
3210 queue_signal(env, info.si_signo, &info);
3211 break;
3212 case EXCP_OPCDEC:
3213 do_sigill:
3214 env->lock_addr = -1;
3215 info.si_signo = TARGET_SIGILL;
3216 info.si_errno = 0;
3217 info.si_code = TARGET_ILL_ILLOPC;
3218