linux-user: Add default configs for mips64[el]
[qemu.git] / m68k-dis.c
1 /* This file is composed of several different files from the upstream
2 sourceware.org CVS. Original file boundaries marked with **** */
3
4 #include <string.h>
5 #include <math.h>
6 #include <stdio.h>
7
8 #include "dis-asm.h"
9
10 /* **** floatformat.h from sourceware.org CVS 2005-08-14. */
11 /* IEEE floating point support declarations, for GDB, the GNU Debugger.
12 Copyright 1991, 1994, 1995, 1997, 2000, 2003 Free Software Foundation, Inc.
13
14 This file is part of GDB.
15
16 This program is free software; you can redistribute it and/or modify
17 it under the terms of the GNU General Public License as published by
18 the Free Software Foundation; either version 2 of the License, or
19 (at your option) any later version.
20
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
25
26 You should have received a copy of the GNU General Public License
27 along with this program; if not, see <http://www.gnu.org/licenses/>. */
28
29 #if !defined (FLOATFORMAT_H)
30 #define FLOATFORMAT_H 1
31
32 /*#include "ansidecl.h" */
33
34 /* A floatformat consists of a sign bit, an exponent and a mantissa. Once the
35 bytes are concatenated according to the byteorder flag, then each of those
36 fields is contiguous. We number the bits with 0 being the most significant
37 (i.e. BITS_BIG_ENDIAN type numbering), and specify which bits each field
38 contains with the *_start and *_len fields. */
39
40 /* What is the order of the bytes. */
41
42 enum floatformat_byteorders {
43
44 /* Standard little endian byte order.
45 EX: 1.2345678e10 => 00 00 80 c5 e0 fe 06 42 */
46
47 floatformat_little,
48
49 /* Standard big endian byte order.
50 EX: 1.2345678e10 => 42 06 fe e0 c5 80 00 00 */
51
52 floatformat_big,
53
54 /* Little endian byte order but big endian word order.
55 EX: 1.2345678e10 => e0 fe 06 42 00 00 80 c5 */
56
57 floatformat_littlebyte_bigword
58
59 };
60
61 enum floatformat_intbit { floatformat_intbit_yes, floatformat_intbit_no };
62
63 struct floatformat
64 {
65 enum floatformat_byteorders byteorder;
66 unsigned int totalsize; /* Total size of number in bits */
67
68 /* Sign bit is always one bit long. 1 means negative, 0 means positive. */
69 unsigned int sign_start;
70
71 unsigned int exp_start;
72 unsigned int exp_len;
73 /* Bias added to a "true" exponent to form the biased exponent. It
74 is intentionally signed as, otherwize, -exp_bias can turn into a
75 very large number (e.g., given the exp_bias of 0x3fff and a 64
76 bit long, the equation (long)(1 - exp_bias) evaluates to
77 4294950914) instead of -16382). */
78 int exp_bias;
79 /* Exponent value which indicates NaN. This is the actual value stored in
80 the float, not adjusted by the exp_bias. This usually consists of all
81 one bits. */
82 unsigned int exp_nan;
83
84 unsigned int man_start;
85 unsigned int man_len;
86
87 /* Is the integer bit explicit or implicit? */
88 enum floatformat_intbit intbit;
89
90 /* Internal name for debugging. */
91 const char *name;
92
93 /* Validator method. */
94 int (*is_valid) (const struct floatformat *fmt, const char *from);
95 };
96
97 /* floatformats for IEEE single and double, big and little endian. */
98
99 extern const struct floatformat floatformat_ieee_single_big;
100 extern const struct floatformat floatformat_ieee_single_little;
101 extern const struct floatformat floatformat_ieee_double_big;
102 extern const struct floatformat floatformat_ieee_double_little;
103
104 /* floatformat for ARM IEEE double, little endian bytes and big endian words */
105
106 extern const struct floatformat floatformat_ieee_double_littlebyte_bigword;
107
108 /* floatformats for various extendeds. */
109
110 extern const struct floatformat floatformat_i387_ext;
111 extern const struct floatformat floatformat_m68881_ext;
112 extern const struct floatformat floatformat_i960_ext;
113 extern const struct floatformat floatformat_m88110_ext;
114 extern const struct floatformat floatformat_m88110_harris_ext;
115 extern const struct floatformat floatformat_arm_ext_big;
116 extern const struct floatformat floatformat_arm_ext_littlebyte_bigword;
117 /* IA-64 Floating Point register spilt into memory. */
118 extern const struct floatformat floatformat_ia64_spill_big;
119 extern const struct floatformat floatformat_ia64_spill_little;
120 extern const struct floatformat floatformat_ia64_quad_big;
121 extern const struct floatformat floatformat_ia64_quad_little;
122
123 /* Convert from FMT to a double.
124 FROM is the address of the extended float.
125 Store the double in *TO. */
126
127 extern void
128 floatformat_to_double (const struct floatformat *, const char *, double *);
129
130 /* The converse: convert the double *FROM to FMT
131 and store where TO points. */
132
133 extern void
134 floatformat_from_double (const struct floatformat *, const double *, char *);
135
136 /* Return non-zero iff the data at FROM is a valid number in format FMT. */
137
138 extern int
139 floatformat_is_valid (const struct floatformat *fmt, const char *from);
140
141 #endif /* defined (FLOATFORMAT_H) */
142 /* **** End of floatformat.h */
143 /* **** m68k-dis.h from sourceware.org CVS 2005-08-14. */
144 /* Opcode table header for m680[01234]0/m6888[12]/m68851.
145 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1999, 2001,
146 2003, 2004 Free Software Foundation, Inc.
147
148 This file is part of GDB, GAS, and the GNU binutils.
149
150 GDB, GAS, and the GNU binutils are free software; you can redistribute
151 them and/or modify them under the terms of the GNU General Public
152 License as published by the Free Software Foundation; either version
153 1, or (at your option) any later version.
154
155 GDB, GAS, and the GNU binutils are distributed in the hope that they
156 will be useful, but WITHOUT ANY WARRANTY; without even the implied
157 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
158 the GNU General Public License for more details.
159
160 You should have received a copy of the GNU General Public License
161 along with this file; see the file COPYING. If not,
162 see <http://www.gnu.org/licenses/>. */
163
164 /* These are used as bit flags for the arch field in the m68k_opcode
165 structure. */
166 #define _m68k_undef 0
167 #define m68000 0x001
168 #define m68008 m68000 /* Synonym for -m68000. otherwise unused. */
169 #define m68010 0x002
170 #define m68020 0x004
171 #define m68030 0x008
172 #define m68ec030 m68030 /* Similar enough to -m68030 to ignore differences;
173 gas will deal with the few differences. */
174 #define m68040 0x010
175 /* There is no 68050. */
176 #define m68060 0x020
177 #define m68881 0x040
178 #define m68882 m68881 /* Synonym for -m68881. otherwise unused. */
179 #define m68851 0x080
180 #define cpu32 0x100 /* e.g., 68332 */
181
182 #define mcfmac 0x200 /* ColdFire MAC. */
183 #define mcfemac 0x400 /* ColdFire EMAC. */
184 #define cfloat 0x800 /* ColdFire FPU. */
185 #define mcfhwdiv 0x1000 /* ColdFire hardware divide. */
186
187 #define mcfisa_a 0x2000 /* ColdFire ISA_A. */
188 #define mcfisa_aa 0x4000 /* ColdFire ISA_A+. */
189 #define mcfisa_b 0x8000 /* ColdFire ISA_B. */
190 #define mcfusp 0x10000 /* ColdFire USP instructions. */
191
192 #define mcf5200 0x20000
193 #define mcf5206e 0x40000
194 #define mcf521x 0x80000
195 #define mcf5249 0x100000
196 #define mcf528x 0x200000
197 #define mcf5307 0x400000
198 #define mcf5407 0x800000
199 #define mcf5470 0x1000000
200 #define mcf5480 0x2000000
201
202 /* Handy aliases. */
203 #define m68040up (m68040 | m68060)
204 #define m68030up (m68030 | m68040up)
205 #define m68020up (m68020 | m68030up)
206 #define m68010up (m68010 | cpu32 | m68020up)
207 #define m68000up (m68000 | m68010up)
208
209 #define mfloat (m68881 | m68882 | m68040 | m68060)
210 #define mmmu (m68851 | m68030 | m68040 | m68060)
211
212 /* The structure used to hold information for an opcode. */
213
214 struct m68k_opcode
215 {
216 /* The opcode name. */
217 const char *name;
218 /* The pseudo-size of the instruction(in bytes). Used to determine
219 number of bytes necessary to disassemble the instruction. */
220 unsigned int size;
221 /* The opcode itself. */
222 unsigned long opcode;
223 /* The mask used by the disassembler. */
224 unsigned long match;
225 /* The arguments. */
226 const char *args;
227 /* The architectures which support this opcode. */
228 unsigned int arch;
229 };
230
231 /* The structure used to hold information for an opcode alias. */
232
233 struct m68k_opcode_alias
234 {
235 /* The alias name. */
236 const char *alias;
237 /* The instruction for which this is an alias. */
238 const char *primary;
239 };
240
241 /* We store four bytes of opcode for all opcodes because that is the
242 most any of them need. The actual length of an instruction is
243 always at least 2 bytes, and is as much longer as necessary to hold
244 the operands it has.
245
246 The match field is a mask saying which bits must match particular
247 opcode in order for an instruction to be an instance of that
248 opcode.
249
250 The args field is a string containing two characters for each
251 operand of the instruction. The first specifies the kind of
252 operand; the second, the place it is stored. */
253
254 /* Kinds of operands:
255 Characters used: AaBbCcDdEeFfGgHIiJkLlMmnOopQqRrSsTtU VvWwXxYyZz01234|*~%;@!&$?/<>#^+-
256
257 D data register only. Stored as 3 bits.
258 A address register only. Stored as 3 bits.
259 a address register indirect only. Stored as 3 bits.
260 R either kind of register. Stored as 4 bits.
261 r either kind of register indirect only. Stored as 4 bits.
262 At the moment, used only for cas2 instruction.
263 F floating point coprocessor register only. Stored as 3 bits.
264 O an offset (or width): immediate data 0-31 or data register.
265 Stored as 6 bits in special format for BF... insns.
266 + autoincrement only. Stored as 3 bits (number of the address register).
267 - autodecrement only. Stored as 3 bits (number of the address register).
268 Q quick immediate data. Stored as 3 bits.
269 This matches an immediate operand only when value is in range 1 .. 8.
270 M moveq immediate data. Stored as 8 bits.
271 This matches an immediate operand only when value is in range -128..127
272 T trap vector immediate data. Stored as 4 bits.
273
274 k K-factor for fmove.p instruction. Stored as a 7-bit constant or
275 a three bit register offset, depending on the field type.
276
277 # immediate data. Stored in special places (b, w or l)
278 which say how many bits to store.
279 ^ immediate data for floating point instructions. Special places
280 are offset by 2 bytes from '#'...
281 B pc-relative address, converted to an offset
282 that is treated as immediate data.
283 d displacement and register. Stores the register as 3 bits
284 and stores the displacement in the entire second word.
285
286 C the CCR. No need to store it; this is just for filtering validity.
287 S the SR. No need to store, just as with CCR.
288 U the USP. No need to store, just as with CCR.
289 E the MAC ACC. No need to store, just as with CCR.
290 e the EMAC ACC[0123].
291 G the MAC/EMAC MACSR. No need to store, just as with CCR.
292 g the EMAC ACCEXT{01,23}.
293 H the MASK. No need to store, just as with CCR.
294 i the MAC/EMAC scale factor.
295
296 I Coprocessor ID. Not printed if 1. The Coprocessor ID is always
297 extracted from the 'd' field of word one, which means that an extended
298 coprocessor opcode can be skipped using the 'i' place, if needed.
299
300 s System Control register for the floating point coprocessor.
301
302 J Misc register for movec instruction, stored in 'j' format.
303 Possible values:
304 0x000 SFC Source Function Code reg [60, 40, 30, 20, 10]
305 0x001 DFC Data Function Code reg [60, 40, 30, 20, 10]
306 0x002 CACR Cache Control Register [60, 40, 30, 20, mcf]
307 0x003 TC MMU Translation Control [60, 40]
308 0x004 ITT0 Instruction Transparent
309 Translation reg 0 [60, 40]
310 0x005 ITT1 Instruction Transparent
311 Translation reg 1 [60, 40]
312 0x006 DTT0 Data Transparent
313 Translation reg 0 [60, 40]
314 0x007 DTT1 Data Transparent
315 Translation reg 1 [60, 40]
316 0x008 BUSCR Bus Control Register [60]
317 0x800 USP User Stack Pointer [60, 40, 30, 20, 10]
318 0x801 VBR Vector Base reg [60, 40, 30, 20, 10, mcf]
319 0x802 CAAR Cache Address Register [ 30, 20]
320 0x803 MSP Master Stack Pointer [ 40, 30, 20]
321 0x804 ISP Interrupt Stack Pointer [ 40, 30, 20]
322 0x805 MMUSR MMU Status reg [ 40]
323 0x806 URP User Root Pointer [60, 40]
324 0x807 SRP Supervisor Root Pointer [60, 40]
325 0x808 PCR Processor Configuration reg [60]
326 0xC00 ROMBAR ROM Base Address Register [520X]
327 0xC04 RAMBAR0 RAM Base Address Register 0 [520X]
328 0xC05 RAMBAR1 RAM Base Address Register 0 [520X]
329 0xC0F MBAR0 RAM Base Address Register 0 [520X]
330 0xC04 FLASHBAR FLASH Base Address Register [mcf528x]
331 0xC05 RAMBAR Static RAM Base Address Register [mcf528x]
332
333 L Register list of the type d0-d7/a0-a7 etc.
334 (New! Improved! Can also hold fp0-fp7, as well!)
335 The assembler tries to see if the registers match the insn by
336 looking at where the insn wants them stored.
337
338 l Register list like L, but with all the bits reversed.
339 Used for going the other way. . .
340
341 c cache identifier which may be "nc" for no cache, "ic"
342 for instruction cache, "dc" for data cache, or "bc"
343 for both caches. Used in cinv and cpush. Always
344 stored in position "d".
345
346 u Any register, with ``upper'' or ``lower'' specification. Used
347 in the mac instructions with size word.
348
349 The remainder are all stored as 6 bits using an address mode and a
350 register number; they differ in which addressing modes they match.
351
352 * all (modes 0-6,7.0-4)
353 ~ alterable memory (modes 2-6,7.0,7.1)
354 (not 0,1,7.2-4)
355 % alterable (modes 0-6,7.0,7.1)
356 (not 7.2-4)
357 ; data (modes 0,2-6,7.0-4)
358 (not 1)
359 @ data, but not immediate (modes 0,2-6,7.0-3)
360 (not 1,7.4)
361 ! control (modes 2,5,6,7.0-3)
362 (not 0,1,3,4,7.4)
363 & alterable control (modes 2,5,6,7.0,7.1)
364 (not 0,1,3,4,7.2-4)
365 $ alterable data (modes 0,2-6,7.0,7.1)
366 (not 1,7.2-4)
367 ? alterable control, or data register (modes 0,2,5,6,7.0,7.1)
368 (not 1,3,4,7.2-4)
369 / control, or data register (modes 0,2,5,6,7.0-3)
370 (not 1,3,4,7.4)
371 > *save operands (modes 2,4,5,6,7.0,7.1)
372 (not 0,1,3,7.2-4)
373 < *restore operands (modes 2,3,5,6,7.0-3)
374 (not 0,1,4,7.4)
375
376 coldfire move operands:
377 m (modes 0-4)
378 n (modes 5,7.2)
379 o (modes 6,7.0,7.1,7.3,7.4)
380 p (modes 0-5)
381
382 coldfire bset/bclr/btst/mulsl/mulul operands:
383 q (modes 0,2-5)
384 v (modes 0,2-5,7.0,7.1)
385 b (modes 0,2-5,7.2)
386 w (modes 2-5,7.2)
387 y (modes 2,5)
388 z (modes 2,5,7.2)
389 x mov3q immediate operand.
390 4 (modes 2,3,4,5)
391 */
392
393 /* For the 68851: */
394 /* I didn't use much imagination in choosing the
395 following codes, so many of them aren't very
396 mnemonic. -rab
397
398 0 32 bit pmmu register
399 Possible values:
400 000 TC Translation Control Register (68030, 68851)
401
402 1 16 bit pmmu register
403 111 AC Access Control (68851)
404
405 2 8 bit pmmu register
406 100 CAL Current Access Level (68851)
407 101 VAL Validate Access Level (68851)
408 110 SCC Stack Change Control (68851)
409
410 3 68030-only pmmu registers (32 bit)
411 010 TT0 Transparent Translation reg 0
412 (aka Access Control reg 0 -- AC0 -- on 68ec030)
413 011 TT1 Transparent Translation reg 1
414 (aka Access Control reg 1 -- AC1 -- on 68ec030)
415
416 W wide pmmu registers
417 Possible values:
418 001 DRP Dma Root Pointer (68851)
419 010 SRP Supervisor Root Pointer (68030, 68851)
420 011 CRP Cpu Root Pointer (68030, 68851)
421
422 f function code register (68030, 68851)
423 0 SFC
424 1 DFC
425
426 V VAL register only (68851)
427
428 X BADx, BACx (16 bit)
429 100 BAD Breakpoint Acknowledge Data (68851)
430 101 BAC Breakpoint Acknowledge Control (68851)
431
432 Y PSR (68851) (MMUSR on 68030) (ACUSR on 68ec030)
433 Z PCSR (68851)
434
435 | memory (modes 2-6, 7.*)
436
437 t address test level (68030 only)
438 Stored as 3 bits, range 0-7.
439 Also used for breakpoint instruction now.
440
441 */
442
443 /* Places to put an operand, for non-general operands:
444 Characters used: BbCcDdFfGgHhIijkLlMmNnostWw123456789/
445
446 s source, low bits of first word.
447 d dest, shifted 9 in first word
448 1 second word, shifted 12
449 2 second word, shifted 6
450 3 second word, shifted 0
451 4 third word, shifted 12
452 5 third word, shifted 6
453 6 third word, shifted 0
454 7 second word, shifted 7
455 8 second word, shifted 10
456 9 second word, shifted 5
457 D store in both place 1 and place 3; for divul and divsl.
458 B first word, low byte, for branch displacements
459 W second word (entire), for branch displacements
460 L second and third words (entire), for branch displacements
461 (also overloaded for move16)
462 b second word, low byte
463 w second word (entire) [variable word/long branch offset for dbra]
464 W second word (entire) (must be signed 16 bit value)
465 l second and third word (entire)
466 g variable branch offset for bra and similar instructions.
467 The place to store depends on the magnitude of offset.
468 t store in both place 7 and place 8; for floating point operations
469 c branch offset for cpBcc operations.
470 The place to store is word two if bit six of word one is zero,
471 and words two and three if bit six of word one is one.
472 i Increment by two, to skip over coprocessor extended operands. Only
473 works with the 'I' format.
474 k Dynamic K-factor field. Bits 6-4 of word 2, used as a register number.
475 Also used for dynamic fmovem instruction.
476 C floating point coprocessor constant - 7 bits. Also used for static
477 K-factors...
478 j Movec register #, stored in 12 low bits of second word.
479 m For M[S]ACx; 4 bits split with MSB shifted 6 bits in first word
480 and remaining 3 bits of register shifted 9 bits in first word.
481 Indicate upper/lower in 1 bit shifted 7 bits in second word.
482 Use with `R' or `u' format.
483 n `m' withouth upper/lower indication. (For M[S]ACx; 4 bits split
484 with MSB shifted 6 bits in first word and remaining 3 bits of
485 register shifted 9 bits in first word. No upper/lower
486 indication is done.) Use with `R' or `u' format.
487 o For M[S]ACw; 4 bits shifted 12 in second word (like `1').
488 Indicate upper/lower in 1 bit shifted 7 bits in second word.
489 Use with `R' or `u' format.
490 M For M[S]ACw; 4 bits in low bits of first word. Indicate
491 upper/lower in 1 bit shifted 6 bits in second word. Use with
492 `R' or `u' format.
493 N For M[S]ACw; 4 bits in low bits of second word. Indicate
494 upper/lower in 1 bit shifted 6 bits in second word. Use with
495 `R' or `u' format.
496 h shift indicator (scale factor), 1 bit shifted 10 in second word
497
498 Places to put operand, for general operands:
499 d destination, shifted 6 bits in first word
500 b source, at low bit of first word, and immediate uses one byte
501 w source, at low bit of first word, and immediate uses two bytes
502 l source, at low bit of first word, and immediate uses four bytes
503 s source, at low bit of first word.
504 Used sometimes in contexts where immediate is not allowed anyway.
505 f single precision float, low bit of 1st word, immediate uses 4 bytes
506 F double precision float, low bit of 1st word, immediate uses 8 bytes
507 x extended precision float, low bit of 1st word, immediate uses 12 bytes
508 p packed float, low bit of 1st word, immediate uses 12 bytes
509 G EMAC accumulator, load (bit 4 2nd word, !bit8 first word)
510 H EMAC accumulator, non load (bit 4 2nd word, bit 8 first word)
511 F EMAC ACCx
512 f EMAC ACCy
513 I MAC/EMAC scale factor
514 / Like 's', but set 2nd word, bit 5 if trailing_ampersand set
515 ] first word, bit 10
516 */
517
518 extern const struct m68k_opcode m68k_opcodes[];
519 extern const struct m68k_opcode_alias m68k_opcode_aliases[];
520
521 extern const int m68k_numopcodes, m68k_numaliases;
522
523 /* **** End of m68k-opcode.h */
524 /* **** m68k-dis.c from sourceware.org CVS 2005-08-14. */
525 /* Print Motorola 68k instructions.
526 Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
527 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005
528 Free Software Foundation, Inc.
529
530 This file is free software; you can redistribute it and/or modify
531 it under the terms of the GNU General Public License as published by
532 the Free Software Foundation; either version 2 of the License, or
533 (at your option) any later version.
534
535 This program is distributed in the hope that it will be useful,
536 but WITHOUT ANY WARRANTY; without even the implied warranty of
537 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
538 GNU General Public License for more details.
539
540 You should have received a copy of the GNU General Public License
541 along with this program; if not, see <http://www.gnu.org/licenses/>. */
542
543 /* Local function prototypes. */
544
545 static const char * const fpcr_names[] =
546 {
547 "", "%fpiar", "%fpsr", "%fpiar/%fpsr", "%fpcr",
548 "%fpiar/%fpcr", "%fpsr/%fpcr", "%fpiar/%fpsr/%fpcr"
549 };
550
551 static const char *const reg_names[] =
552 {
553 "%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7",
554 "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%fp", "%sp",
555 "%ps", "%pc"
556 };
557
558 /* Name of register halves for MAC/EMAC.
559 Separate from reg_names since 'spu', 'fpl' look weird. */
560 static const char *const reg_half_names[] =
561 {
562 "%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7",
563 "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%a6", "%a7",
564 "%ps", "%pc"
565 };
566
567 /* Sign-extend an (unsigned char). */
568 #if __STDC__ == 1
569 #define COERCE_SIGNED_CHAR(ch) ((signed char) (ch))
570 #else
571 #define COERCE_SIGNED_CHAR(ch) ((int) (((ch) ^ 0x80) & 0xFF) - 128)
572 #endif
573
574 /* Get a 1 byte signed integer. */
575 #define NEXTBYTE(p) (p += 2, fetch_data(info, p), COERCE_SIGNED_CHAR(p[-1]))
576
577 /* Get a 2 byte signed integer. */
578 #define COERCE16(x) ((int) (((x) ^ 0x8000) - 0x8000))
579 #define NEXTWORD(p) \
580 (p += 2, fetch_data(info, p), \
581 COERCE16 ((p[-2] << 8) + p[-1]))
582
583 /* Get a 4 byte signed integer. */
584 #define COERCE32(x) ((bfd_signed_vma) ((x) ^ 0x80000000) - 0x80000000)
585 #define NEXTLONG(p) \
586 (p += 4, fetch_data(info, p), \
587 (COERCE32 ((((((p[-4] << 8) + p[-3]) << 8) + p[-2]) << 8) + p[-1])))
588
589 /* Get a 4 byte unsigned integer. */
590 #define NEXTULONG(p) \
591 (p += 4, fetch_data(info, p), \
592 (unsigned int) ((((((p[-4] << 8) + p[-3]) << 8) + p[-2]) << 8) + p[-1]))
593
594 /* Get a single precision float. */
595 #define NEXTSINGLE(val, p) \
596 (p += 4, fetch_data(info, p), \
597 floatformat_to_double (&floatformat_ieee_single_big, (char *) p - 4, &val))
598
599 /* Get a double precision float. */
600 #define NEXTDOUBLE(val, p) \
601 (p += 8, fetch_data(info, p), \
602 floatformat_to_double (&floatformat_ieee_double_big, (char *) p - 8, &val))
603
604 /* Get an extended precision float. */
605 #define NEXTEXTEND(val, p) \
606 (p += 12, fetch_data(info, p), \
607 floatformat_to_double (&floatformat_m68881_ext, (char *) p - 12, &val))
608
609 /* Need a function to convert from packed to double
610 precision. Actually, it's easier to print a
611 packed number than a double anyway, so maybe
612 there should be a special case to handle this... */
613 #define NEXTPACKED(p) \
614 (p += 12, fetch_data(info, p), 0.0)
615 \f
616 /* Maximum length of an instruction. */
617 #define MAXLEN 22
618
619 #include <setjmp.h>
620
621 struct private
622 {
623 /* Points to first byte not fetched. */
624 bfd_byte *max_fetched;
625 bfd_byte the_buffer[MAXLEN];
626 bfd_vma insn_start;
627 jmp_buf bailout;
628 };
629
630 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
631 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
632 on error. */
633 static int
634 fetch_data2(struct disassemble_info *info, bfd_byte *addr)
635 {
636 int status;
637 struct private *priv = (struct private *)info->private_data;
638 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
639
640 status = (*info->read_memory_func) (start,
641 priv->max_fetched,
642 addr - priv->max_fetched,
643 info);
644 if (status != 0)
645 {
646 (*info->memory_error_func) (status, start, info);
647 longjmp (priv->bailout, 1);
648 }
649 else
650 priv->max_fetched = addr;
651 return 1;
652 }
653
654 static int
655 fetch_data(struct disassemble_info *info, bfd_byte *addr)
656 {
657 if (addr <= ((struct private *) (info->private_data))->max_fetched) {
658 return 1;
659 } else {
660 return fetch_data2(info, addr);
661 }
662 }
663
664 /* This function is used to print to the bit-bucket. */
665 static int
666 dummy_printer (FILE *file ATTRIBUTE_UNUSED,
667 const char *format ATTRIBUTE_UNUSED,
668 ...)
669 {
670 return 0;
671 }
672
673 static void
674 dummy_print_address (bfd_vma vma ATTRIBUTE_UNUSED,
675 struct disassemble_info *info ATTRIBUTE_UNUSED)
676 {
677 }
678
679 /* Fetch BITS bits from a position in the instruction specified by CODE.
680 CODE is a "place to put an argument", or 'x' for a destination
681 that is a general address (mode and register).
682 BUFFER contains the instruction. */
683
684 static int
685 fetch_arg (unsigned char *buffer,
686 int code,
687 int bits,
688 disassemble_info *info)
689 {
690 int val = 0;
691
692 switch (code)
693 {
694 case '/': /* MAC/EMAC mask bit. */
695 val = buffer[3] >> 5;
696 break;
697
698 case 'G': /* EMAC ACC load. */
699 val = ((buffer[3] >> 3) & 0x2) | ((~buffer[1] >> 7) & 0x1);
700 break;
701
702 case 'H': /* EMAC ACC !load. */
703 val = ((buffer[3] >> 3) & 0x2) | ((buffer[1] >> 7) & 0x1);
704 break;
705
706 case ']': /* EMAC ACCEXT bit. */
707 val = buffer[0] >> 2;
708 break;
709
710 case 'I': /* MAC/EMAC scale factor. */
711 val = buffer[2] >> 1;
712 break;
713
714 case 'F': /* EMAC ACCx. */
715 val = buffer[0] >> 1;
716 break;
717
718 case 'f':
719 val = buffer[1];
720 break;
721
722 case 's':
723 val = buffer[1];
724 break;
725
726 case 'd': /* Destination, for register or quick. */
727 val = (buffer[0] << 8) + buffer[1];
728 val >>= 9;
729 break;
730
731 case 'x': /* Destination, for general arg. */
732 val = (buffer[0] << 8) + buffer[1];
733 val >>= 6;
734 break;
735
736 case 'k':
737 fetch_data(info, buffer + 3);
738 val = (buffer[3] >> 4);
739 break;
740
741 case 'C':
742 fetch_data(info, buffer + 3);
743 val = buffer[3];
744 break;
745
746 case '1':
747 fetch_data(info, buffer + 3);
748 val = (buffer[2] << 8) + buffer[3];
749 val >>= 12;
750 break;
751
752 case '2':
753 fetch_data(info, buffer + 3);
754 val = (buffer[2] << 8) + buffer[3];
755 val >>= 6;
756 break;
757
758 case '3':
759 case 'j':
760 fetch_data(info, buffer + 3);
761 val = (buffer[2] << 8) + buffer[3];
762 break;
763
764 case '4':
765 fetch_data(info, buffer + 5);
766 val = (buffer[4] << 8) + buffer[5];
767 val >>= 12;
768 break;
769
770 case '5':
771 fetch_data(info, buffer + 5);
772 val = (buffer[4] << 8) + buffer[5];
773 val >>= 6;
774 break;
775
776 case '6':
777 fetch_data(info, buffer + 5);
778 val = (buffer[4] << 8) + buffer[5];
779 break;
780
781 case '7':
782 fetch_data(info, buffer + 3);
783 val = (buffer[2] << 8) + buffer[3];
784 val >>= 7;
785 break;
786
787 case '8':
788 fetch_data(info, buffer + 3);
789 val = (buffer[2] << 8) + buffer[3];
790 val >>= 10;
791 break;
792
793 case '9':
794 fetch_data(info, buffer + 3);
795 val = (buffer[2] << 8) + buffer[3];
796 val >>= 5;
797 break;
798
799 case 'e':
800 val = (buffer[1] >> 6);
801 break;
802
803 case 'm':
804 val = (buffer[1] & 0x40 ? 0x8 : 0)
805 | ((buffer[0] >> 1) & 0x7)
806 | (buffer[3] & 0x80 ? 0x10 : 0);
807 break;
808
809 case 'n':
810 val = (buffer[1] & 0x40 ? 0x8 : 0) | ((buffer[0] >> 1) & 0x7);
811 break;
812
813 case 'o':
814 val = (buffer[2] >> 4) | (buffer[3] & 0x80 ? 0x10 : 0);
815 break;
816
817 case 'M':
818 val = (buffer[1] & 0xf) | (buffer[3] & 0x40 ? 0x10 : 0);
819 break;
820
821 case 'N':
822 val = (buffer[3] & 0xf) | (buffer[3] & 0x40 ? 0x10 : 0);
823 break;
824
825 case 'h':
826 val = buffer[2] >> 2;
827 break;
828
829 default:
830 abort ();
831 }
832
833 switch (bits)
834 {
835 case 1:
836 return val & 1;
837 case 2:
838 return val & 3;
839 case 3:
840 return val & 7;
841 case 4:
842 return val & 017;
843 case 5:
844 return val & 037;
845 case 6:
846 return val & 077;
847 case 7:
848 return val & 0177;
849 case 8:
850 return val & 0377;
851 case 12:
852 return val & 07777;
853 default:
854 abort ();
855 }
856 }
857
858 /* Check if an EA is valid for a particular code. This is required
859 for the EMAC instructions since the type of source address determines
860 if it is a EMAC-load instruciton if the EA is mode 2-5, otherwise it
861 is a non-load EMAC instruction and the bits mean register Ry.
862 A similar case exists for the movem instructions where the register
863 mask is interpreted differently for different EAs. */
864
865 static bfd_boolean
866 m68k_valid_ea (char code, int val)
867 {
868 int mode, mask;
869 #define M(n0,n1,n2,n3,n4,n5,n6,n70,n71,n72,n73,n74) \
870 (n0 | n1 << 1 | n2 << 2 | n3 << 3 | n4 << 4 | n5 << 5 | n6 << 6 \
871 | n70 << 7 | n71 << 8 | n72 << 9 | n73 << 10 | n74 << 11)
872
873 switch (code)
874 {
875 case '*':
876 mask = M (1,1,1,1,1,1,1,1,1,1,1,1);
877 break;
878 case '~':
879 mask = M (0,0,1,1,1,1,1,1,1,0,0,0);
880 break;
881 case '%':
882 mask = M (1,1,1,1,1,1,1,1,1,0,0,0);
883 break;
884 case ';':
885 mask = M (1,0,1,1,1,1,1,1,1,1,1,1);
886 break;
887 case '@':
888 mask = M (1,0,1,1,1,1,1,1,1,1,1,0);
889 break;
890 case '!':
891 mask = M (0,0,1,0,0,1,1,1,1,1,1,0);
892 break;
893 case '&':
894 mask = M (0,0,1,0,0,1,1,1,1,0,0,0);
895 break;
896 case '$':
897 mask = M (1,0,1,1,1,1,1,1,1,0,0,0);
898 break;
899 case '?':
900 mask = M (1,0,1,0,0,1,1,1,1,0,0,0);
901 break;
902 case '/':
903 mask = M (1,0,1,0,0,1,1,1,1,1,1,0);
904 break;
905 case '|':
906 mask = M (0,0,1,0,0,1,1,1,1,1,1,0);
907 break;
908 case '>':
909 mask = M (0,0,1,0,1,1,1,1,1,0,0,0);
910 break;
911 case '<':
912 mask = M (0,0,1,1,0,1,1,1,1,1,1,0);
913 break;
914 case 'm':
915 mask = M (1,1,1,1,1,0,0,0,0,0,0,0);
916 break;
917 case 'n':
918 mask = M (0,0,0,0,0,1,0,0,0,1,0,0);
919 break;
920 case 'o':
921 mask = M (0,0,0,0,0,0,1,1,1,0,1,1);
922 break;
923 case 'p':
924 mask = M (1,1,1,1,1,1,0,0,0,0,0,0);
925 break;
926 case 'q':
927 mask = M (1,0,1,1,1,1,0,0,0,0,0,0);
928 break;
929 case 'v':
930 mask = M (1,0,1,1,1,1,0,1,1,0,0,0);
931 break;
932 case 'b':
933 mask = M (1,0,1,1,1,1,0,0,0,1,0,0);
934 break;
935 case 'w':
936 mask = M (0,0,1,1,1,1,0,0,0,1,0,0);
937 break;
938 case 'y':
939 mask = M (0,0,1,0,0,1,0,0,0,0,0,0);
940 break;
941 case 'z':
942 mask = M (0,0,1,0,0,1,0,0,0,1,0,0);
943 break;
944 case '4':
945 mask = M (0,0,1,1,1,1,0,0,0,0,0,0);
946 break;
947 default:
948 abort ();
949 }
950 #undef M
951
952 mode = (val >> 3) & 7;
953 if (mode == 7)
954 mode += val & 7;
955 return (mask & (1 << mode)) != 0;
956 }
957
958 /* Print a base register REGNO and displacement DISP, on INFO->STREAM.
959 REGNO = -1 for pc, -2 for none (suppressed). */
960
961 static void
962 print_base (int regno, bfd_vma disp, disassemble_info *info)
963 {
964 if (regno == -1)
965 {
966 (*info->fprintf_func) (info->stream, "%%pc@(");
967 (*info->print_address_func) (disp, info);
968 }
969 else
970 {
971 char buf[50];
972
973 if (regno == -2)
974 (*info->fprintf_func) (info->stream, "@(");
975 else if (regno == -3)
976 (*info->fprintf_func) (info->stream, "%%zpc@(");
977 else
978 (*info->fprintf_func) (info->stream, "%s@(", reg_names[regno]);
979
980 sprintf_vma (buf, disp);
981 (*info->fprintf_func) (info->stream, "%s", buf);
982 }
983 }
984
985 /* Print an indexed argument. The base register is BASEREG (-1 for pc).
986 P points to extension word, in buffer.
987 ADDR is the nominal core address of that extension word. */
988
989 static unsigned char *
990 print_indexed (int basereg,
991 unsigned char *p,
992 bfd_vma addr,
993 disassemble_info *info)
994 {
995 int word;
996 static const char *const scales[] = { "", ":2", ":4", ":8" };
997 bfd_vma base_disp;
998 bfd_vma outer_disp;
999 char buf[40];
1000 char vmabuf[50];
1001
1002 word = NEXTWORD (p);
1003
1004 /* Generate the text for the index register.
1005 Where this will be output is not yet determined. */
1006 sprintf (buf, "%s:%c%s",
1007 reg_names[(word >> 12) & 0xf],
1008 (word & 0x800) ? 'l' : 'w',
1009 scales[(word >> 9) & 3]);
1010
1011 /* Handle the 68000 style of indexing. */
1012
1013 if ((word & 0x100) == 0)
1014 {
1015 base_disp = word & 0xff;
1016 if ((base_disp & 0x80) != 0)
1017 base_disp -= 0x100;
1018 if (basereg == -1)
1019 base_disp += addr;
1020 print_base (basereg, base_disp, info);
1021 (*info->fprintf_func) (info->stream, ",%s)", buf);
1022 return p;
1023 }
1024
1025 /* Handle the generalized kind. */
1026 /* First, compute the displacement to add to the base register. */
1027 if (word & 0200)
1028 {
1029 if (basereg == -1)
1030 basereg = -3;
1031 else
1032 basereg = -2;
1033 }
1034 if (word & 0100)
1035 buf[0] = '\0';
1036 base_disp = 0;
1037 switch ((word >> 4) & 3)
1038 {
1039 case 2:
1040 base_disp = NEXTWORD (p);
1041 break;
1042 case 3:
1043 base_disp = NEXTLONG (p);
1044 }
1045 if (basereg == -1)
1046 base_disp += addr;
1047
1048 /* Handle single-level case (not indirect). */
1049 if ((word & 7) == 0)
1050 {
1051 print_base (basereg, base_disp, info);
1052 if (buf[0] != '\0')
1053 (*info->fprintf_func) (info->stream, ",%s", buf);
1054 (*info->fprintf_func) (info->stream, ")");
1055 return p;
1056 }
1057
1058 /* Two level. Compute displacement to add after indirection. */
1059 outer_disp = 0;
1060 switch (word & 3)
1061 {
1062 case 2:
1063 outer_disp = NEXTWORD (p);
1064 break;
1065 case 3:
1066 outer_disp = NEXTLONG (p);
1067 }
1068
1069 print_base (basereg, base_disp, info);
1070 if ((word & 4) == 0 && buf[0] != '\0')
1071 {
1072 (*info->fprintf_func) (info->stream, ",%s", buf);
1073 buf[0] = '\0';
1074 }
1075 sprintf_vma (vmabuf, outer_disp);
1076 (*info->fprintf_func) (info->stream, ")@(%s", vmabuf);
1077 if (buf[0] != '\0')
1078 (*info->fprintf_func) (info->stream, ",%s", buf);
1079 (*info->fprintf_func) (info->stream, ")");
1080
1081 return p;
1082 }
1083
1084 /* Returns number of bytes "eaten" by the operand, or
1085 return -1 if an invalid operand was found, or -2 if
1086 an opcode tabe error was found.
1087 ADDR is the pc for this arg to be relative to. */
1088
1089 static int
1090 print_insn_arg (const char *d,
1091 unsigned char *buffer,
1092 unsigned char *p0,
1093 bfd_vma addr,
1094 disassemble_info *info)
1095 {
1096 int val = 0;
1097 int place = d[1];
1098 unsigned char *p = p0;
1099 int regno;
1100 const char *regname;
1101 unsigned char *p1;
1102 double flval;
1103 int flt_p;
1104 bfd_signed_vma disp;
1105 unsigned int uval;
1106
1107 switch (*d)
1108 {
1109 case 'c': /* Cache identifier. */
1110 {
1111 static const char *const cacheFieldName[] = { "nc", "dc", "ic", "bc" };
1112 val = fetch_arg (buffer, place, 2, info);
1113 (*info->fprintf_func) (info->stream, "%s", cacheFieldName[val]);
1114 break;
1115 }
1116
1117 case 'a': /* Address register indirect only. Cf. case '+'. */
1118 {
1119 (*info->fprintf_func)
1120 (info->stream,
1121 "%s@",
1122 reg_names[fetch_arg (buffer, place, 3, info) + 8]);
1123 break;
1124 }
1125
1126 case '_': /* 32-bit absolute address for move16. */
1127 {
1128 uval = NEXTULONG (p);
1129 (*info->print_address_func) (uval, info);
1130 break;
1131 }
1132
1133 case 'C':
1134 (*info->fprintf_func) (info->stream, "%%ccr");
1135 break;
1136
1137 case 'S':
1138 (*info->fprintf_func) (info->stream, "%%sr");
1139 break;
1140
1141 case 'U':
1142 (*info->fprintf_func) (info->stream, "%%usp");
1143 break;
1144
1145 case 'E':
1146 (*info->fprintf_func) (info->stream, "%%acc");
1147 break;
1148
1149 case 'G':
1150 (*info->fprintf_func) (info->stream, "%%macsr");
1151 break;
1152
1153 case 'H':
1154 (*info->fprintf_func) (info->stream, "%%mask");
1155 break;
1156
1157 case 'J':
1158 {
1159 /* FIXME: There's a problem here, different m68k processors call the
1160 same address different names. This table can't get it right
1161 because it doesn't know which processor it's disassembling for. */
1162 static const struct { const char *name; int value; } names[]
1163 = {{"%sfc", 0x000}, {"%dfc", 0x001}, {"%cacr", 0x002},
1164 {"%tc", 0x003}, {"%itt0",0x004}, {"%itt1", 0x005},
1165 {"%dtt0",0x006}, {"%dtt1",0x007}, {"%buscr",0x008},
1166 {"%usp", 0x800}, {"%vbr", 0x801}, {"%caar", 0x802},
1167 {"%msp", 0x803}, {"%isp", 0x804},
1168 {"%flashbar", 0xc04}, {"%rambar", 0xc05}, /* mcf528x added these. */
1169
1170 /* Should we be calling this psr like we do in case 'Y'? */
1171 {"%mmusr",0x805},
1172
1173 {"%urp", 0x806}, {"%srp", 0x807}, {"%pcr", 0x808}};
1174
1175 val = fetch_arg (buffer, place, 12, info);
1176 for (regno = sizeof names / sizeof names[0] - 1; regno >= 0; regno--)
1177 if (names[regno].value == val)
1178 {
1179 (*info->fprintf_func) (info->stream, "%s", names[regno].name);
1180 break;
1181 }
1182 if (regno < 0)
1183 (*info->fprintf_func) (info->stream, "%d", val);
1184 }
1185 break;
1186
1187 case 'Q':
1188 val = fetch_arg (buffer, place, 3, info);
1189 /* 0 means 8, except for the bkpt instruction... */
1190 if (val == 0 && d[1] != 's')
1191 val = 8;
1192 (*info->fprintf_func) (info->stream, "#%d", val);
1193 break;
1194
1195 case 'x':
1196 val = fetch_arg (buffer, place, 3, info);
1197 /* 0 means -1. */
1198 if (val == 0)
1199 val = -1;
1200 (*info->fprintf_func) (info->stream, "#%d", val);
1201 break;
1202
1203 case 'M':
1204 if (place == 'h')
1205 {
1206 static const char *const scalefactor_name[] = { "<<", ">>" };
1207 val = fetch_arg (buffer, place, 1, info);
1208 (*info->fprintf_func) (info->stream, "%s", scalefactor_name[val]);
1209 }
1210 else
1211 {
1212 val = fetch_arg (buffer, place, 8, info);
1213 if (val & 0x80)
1214 val = val - 0x100;
1215 (*info->fprintf_func) (info->stream, "#%d", val);
1216 }
1217 break;
1218
1219 case 'T':
1220 val = fetch_arg (buffer, place, 4, info);
1221 (*info->fprintf_func) (info->stream, "#%d", val);
1222 break;
1223
1224 case 'D':
1225 (*info->fprintf_func) (info->stream, "%s",
1226 reg_names[fetch_arg (buffer, place, 3, info)]);
1227 break;
1228
1229 case 'A':
1230 (*info->fprintf_func)
1231 (info->stream, "%s",
1232 reg_names[fetch_arg (buffer, place, 3, info) + 010]);
1233 break;
1234
1235 case 'R':
1236 (*info->fprintf_func)
1237 (info->stream, "%s",
1238 reg_names[fetch_arg (buffer, place, 4, info)]);
1239 break;
1240
1241 case 'r':
1242 regno = fetch_arg (buffer, place, 4, info);
1243 if (regno > 7)
1244 (*info->fprintf_func) (info->stream, "%s@", reg_names[regno]);
1245 else
1246 (*info->fprintf_func) (info->stream, "@(%s)", reg_names[regno]);
1247 break;
1248
1249 case 'F':
1250 (*info->fprintf_func)
1251 (info->stream, "%%fp%d",
1252 fetch_arg (buffer, place, 3, info));
1253 break;
1254
1255 case 'O':
1256 val = fetch_arg (buffer, place, 6, info);
1257 if (val & 0x20)
1258 (*info->fprintf_func) (info->stream, "%s", reg_names[val & 7]);
1259 else
1260 (*info->fprintf_func) (info->stream, "%d", val);
1261 break;
1262
1263 case '+':
1264 (*info->fprintf_func)
1265 (info->stream, "%s@+",
1266 reg_names[fetch_arg (buffer, place, 3, info) + 8]);
1267 break;
1268
1269 case '-':
1270 (*info->fprintf_func)
1271 (info->stream, "%s@-",
1272 reg_names[fetch_arg (buffer, place, 3, info) + 8]);
1273 break;
1274
1275 case 'k':
1276 if (place == 'k')
1277 (*info->fprintf_func)
1278 (info->stream, "{%s}",
1279 reg_names[fetch_arg (buffer, place, 3, info)]);
1280 else if (place == 'C')
1281 {
1282 val = fetch_arg (buffer, place, 7, info);
1283 if (val > 63) /* This is a signed constant. */
1284 val -= 128;
1285 (*info->fprintf_func) (info->stream, "{#%d}", val);
1286 }
1287 else
1288 return -2;
1289 break;
1290
1291 case '#':
1292 case '^':
1293 p1 = buffer + (*d == '#' ? 2 : 4);
1294 if (place == 's')
1295 val = fetch_arg (buffer, place, 4, info);
1296 else if (place == 'C')
1297 val = fetch_arg (buffer, place, 7, info);
1298 else if (place == '8')
1299 val = fetch_arg (buffer, place, 3, info);
1300 else if (place == '3')
1301 val = fetch_arg (buffer, place, 8, info);
1302 else if (place == 'b')
1303 val = NEXTBYTE (p1);
1304 else if (place == 'w' || place == 'W')
1305 val = NEXTWORD (p1);
1306 else if (place == 'l')
1307 val = NEXTLONG (p1);
1308 else
1309 return -2;
1310 (*info->fprintf_func) (info->stream, "#%d", val);
1311 break;
1312
1313 case 'B':
1314 if (place == 'b')
1315 disp = NEXTBYTE (p);
1316 else if (place == 'B')
1317 disp = COERCE_SIGNED_CHAR (buffer[1]);
1318 else if (place == 'w' || place == 'W')
1319 disp = NEXTWORD (p);
1320 else if (place == 'l' || place == 'L' || place == 'C')
1321 disp = NEXTLONG (p);
1322 else if (place == 'g')
1323 {
1324 disp = NEXTBYTE (buffer);
1325 if (disp == 0)
1326 disp = NEXTWORD (p);
1327 else if (disp == -1)
1328 disp = NEXTLONG (p);
1329 }
1330 else if (place == 'c')
1331 {
1332 if (buffer[1] & 0x40) /* If bit six is one, long offset. */
1333 disp = NEXTLONG (p);
1334 else
1335 disp = NEXTWORD (p);
1336 }
1337 else
1338 return -2;
1339
1340 (*info->print_address_func) (addr + disp, info);
1341 break;
1342
1343 case 'd':
1344 val = NEXTWORD (p);
1345 (*info->fprintf_func)
1346 (info->stream, "%s@(%d)",
1347 reg_names[fetch_arg (buffer, place, 3, info) + 8], val);
1348 break;
1349
1350 case 's':
1351 (*info->fprintf_func) (info->stream, "%s",
1352 fpcr_names[fetch_arg (buffer, place, 3, info)]);
1353 break;
1354
1355 case 'e':
1356 val = fetch_arg(buffer, place, 2, info);
1357 (*info->fprintf_func) (info->stream, "%%acc%d", val);
1358 break;
1359
1360 case 'g':
1361 val = fetch_arg(buffer, place, 1, info);
1362 (*info->fprintf_func) (info->stream, "%%accext%s", val==0 ? "01" : "23");
1363 break;
1364
1365 case 'i':
1366 val = fetch_arg(buffer, place, 2, info);
1367 if (val == 1)
1368 (*info->fprintf_func) (info->stream, "<<");
1369 else if (val == 3)
1370 (*info->fprintf_func) (info->stream, ">>");
1371 else
1372 return -1;
1373 break;
1374
1375 case 'I':
1376 /* Get coprocessor ID... */
1377 val = fetch_arg (buffer, 'd', 3, info);
1378
1379 if (val != 1) /* Unusual coprocessor ID? */
1380 (*info->fprintf_func) (info->stream, "(cpid=%d) ", val);
1381 break;
1382
1383 case '4':
1384 case '*':
1385 case '~':
1386 case '%':
1387 case ';':
1388 case '@':
1389 case '!':
1390 case '$':
1391 case '?':
1392 case '/':
1393 case '&':
1394 case '|':
1395 case '<':
1396 case '>':
1397 case 'm':
1398 case 'n':
1399 case 'o':
1400 case 'p':
1401 case 'q':
1402 case 'v':
1403 case 'b':
1404 case 'w':
1405 case 'y':
1406 case 'z':
1407 if (place == 'd')
1408 {
1409 val = fetch_arg (buffer, 'x', 6, info);
1410 val = ((val & 7) << 3) + ((val >> 3) & 7);
1411 }
1412 else
1413 val = fetch_arg (buffer, 's', 6, info);
1414
1415 /* If the <ea> is invalid for *d, then reject this match. */
1416 if (!m68k_valid_ea (*d, val))
1417 return -1;
1418
1419 /* Get register number assuming address register. */
1420 regno = (val & 7) + 8;
1421 regname = reg_names[regno];
1422 switch (val >> 3)
1423 {
1424 case 0:
1425 (*info->fprintf_func) (info->stream, "%s", reg_names[val]);
1426 break;
1427
1428 case 1:
1429 (*info->fprintf_func) (info->stream, "%s", regname);
1430 break;
1431
1432 case 2:
1433 (*info->fprintf_func) (info->stream, "%s@", regname);
1434 break;
1435
1436 case 3:
1437 (*info->fprintf_func) (info->stream, "%s@+", regname);
1438 break;
1439
1440 case 4:
1441 (*info->fprintf_func) (info->stream, "%s@-", regname);
1442 break;
1443
1444 case 5:
1445 val = NEXTWORD (p);
1446 (*info->fprintf_func) (info->stream, "%s@(%d)", regname, val);
1447 break;
1448
1449 case 6:
1450 p = print_indexed (regno, p, addr, info);
1451 break;
1452
1453 case 7:
1454 switch (val & 7)
1455 {
1456 case 0:
1457 val = NEXTWORD (p);
1458 (*info->print_address_func) (val, info);
1459 break;
1460
1461 case 1:
1462 uval = NEXTULONG (p);
1463 (*info->print_address_func) (uval, info);
1464 break;
1465
1466 case 2:
1467 val = NEXTWORD (p);
1468 (*info->fprintf_func) (info->stream, "%%pc@(");
1469 (*info->print_address_func) (addr + val, info);
1470 (*info->fprintf_func) (info->stream, ")");
1471 break;
1472
1473 case 3:
1474 p = print_indexed (-1, p, addr, info);
1475 break;
1476
1477 case 4:
1478 flt_p = 1; /* Assume it's a float... */
1479 switch (place)
1480 {
1481 case 'b':
1482 val = NEXTBYTE (p);
1483 flt_p = 0;
1484 break;
1485
1486 case 'w':
1487 val = NEXTWORD (p);
1488 flt_p = 0;
1489 break;
1490
1491 case 'l':
1492 val = NEXTLONG (p);
1493 flt_p = 0;
1494 break;
1495
1496 case 'f':
1497 NEXTSINGLE (flval, p);
1498 break;
1499
1500 case 'F':
1501 NEXTDOUBLE (flval, p);
1502 break;
1503
1504 case 'x':
1505 NEXTEXTEND (flval, p);
1506 break;
1507
1508 case 'p':
1509 flval = NEXTPACKED (p);
1510 break;
1511
1512 default:
1513 return -1;
1514 }
1515 if (flt_p) /* Print a float? */
1516 (*info->fprintf_func) (info->stream, "#%g", flval);
1517 else
1518 (*info->fprintf_func) (info->stream, "#%d", val);
1519 break;
1520
1521 default:
1522 return -1;
1523 }
1524 }
1525
1526 /* If place is '/', then this is the case of the mask bit for
1527 mac/emac loads. Now that the arg has been printed, grab the
1528 mask bit and if set, add a '&' to the arg. */
1529 if (place == '/')
1530 {
1531 val = fetch_arg (buffer, place, 1, info);
1532 if (val)
1533 info->fprintf_func (info->stream, "&");
1534 }
1535 break;
1536
1537 case 'L':
1538 case 'l':
1539 if (place == 'w')
1540 {
1541 char doneany;
1542 p1 = buffer + 2;
1543 val = NEXTWORD (p1);
1544 /* Move the pointer ahead if this point is farther ahead
1545 than the last. */
1546 p = p1 > p ? p1 : p;
1547 if (val == 0)
1548 {
1549 (*info->fprintf_func) (info->stream, "#0");
1550 break;
1551 }
1552 if (*d == 'l')
1553 {
1554 int newval = 0;
1555
1556 for (regno = 0; regno < 16; ++regno)
1557 if (val & (0x8000 >> regno))
1558 newval |= 1 << regno;
1559 val = newval;
1560 }
1561 val &= 0xffff;
1562 doneany = 0;
1563 for (regno = 0; regno < 16; ++regno)
1564 if (val & (1 << regno))
1565 {
1566 int first_regno;
1567
1568 if (doneany)
1569 (*info->fprintf_func) (info->stream, "/");
1570 doneany = 1;
1571 (*info->fprintf_func) (info->stream, "%s", reg_names[regno]);
1572 first_regno = regno;
1573 while (val & (1 << (regno + 1)))
1574 ++regno;
1575 if (regno > first_regno)
1576 (*info->fprintf_func) (info->stream, "-%s",
1577 reg_names[regno]);
1578 }
1579 }
1580 else if (place == '3')
1581 {
1582 /* `fmovem' insn. */
1583 char doneany;
1584 val = fetch_arg (buffer, place, 8, info);
1585 if (val == 0)
1586 {
1587 (*info->fprintf_func) (info->stream, "#0");
1588 break;
1589 }
1590 if (*d == 'l')
1591 {
1592 int newval = 0;
1593
1594 for (regno = 0; regno < 8; ++regno)
1595 if (val & (0x80 >> regno))
1596 newval |= 1 << regno;
1597 val = newval;
1598 }
1599 val &= 0xff;
1600 doneany = 0;
1601 for (regno = 0; regno < 8; ++regno)
1602 if (val & (1 << regno))
1603 {
1604 int first_regno;
1605 if (doneany)
1606 (*info->fprintf_func) (info->stream, "/");
1607 doneany = 1;
1608 (*info->fprintf_func) (info->stream, "%%fp%d", regno);
1609 first_regno = regno;
1610 while (val & (1 << (regno + 1)))
1611 ++regno;
1612 if (regno > first_regno)
1613 (*info->fprintf_func) (info->stream, "-%%fp%d", regno);
1614 }
1615 }
1616 else if (place == '8')
1617 {
1618 /* fmoveml for FP status registers. */
1619 (*info->fprintf_func) (info->stream, "%s",
1620 fpcr_names[fetch_arg (buffer, place, 3,
1621 info)]);
1622 }
1623 else
1624 return -2;
1625 break;
1626
1627 case 'X':
1628 place = '8';
1629 case 'Y':
1630 case 'Z':
1631 case 'W':
1632 case '0':
1633 case '1':
1634 case '2':
1635 case '3':
1636 {
1637 int val = fetch_arg (buffer, place, 5, info);
1638 const char *name = 0;
1639
1640 switch (val)
1641 {
1642 case 2: name = "%tt0"; break;
1643 case 3: name = "%tt1"; break;
1644 case 0x10: name = "%tc"; break;
1645 case 0x11: name = "%drp"; break;
1646 case 0x12: name = "%srp"; break;
1647 case 0x13: name = "%crp"; break;
1648 case 0x14: name = "%cal"; break;
1649 case 0x15: name = "%val"; break;
1650 case 0x16: name = "%scc"; break;
1651 case 0x17: name = "%ac"; break;
1652 case 0x18: name = "%psr"; break;
1653 case 0x19: name = "%pcsr"; break;
1654 case 0x1c:
1655 case 0x1d:
1656 {
1657 int break_reg = ((buffer[3] >> 2) & 7);
1658
1659 (*info->fprintf_func)
1660 (info->stream, val == 0x1c ? "%%bad%d" : "%%bac%d",
1661 break_reg);
1662 }
1663 break;
1664 default:
1665 (*info->fprintf_func) (info->stream, "<mmu register %d>", val);
1666 }
1667 if (name)
1668 (*info->fprintf_func) (info->stream, "%s", name);
1669 }
1670 break;
1671
1672 case 'f':
1673 {
1674 int fc = fetch_arg (buffer, place, 5, info);
1675
1676 if (fc == 1)
1677 (*info->fprintf_func) (info->stream, "%%dfc");
1678 else if (fc == 0)
1679 (*info->fprintf_func) (info->stream, "%%sfc");
1680 else
1681 /* xgettext:c-format */
1682 (*info->fprintf_func) (info->stream, _("<function code %d>"), fc);
1683 }
1684 break;
1685
1686 case 'V':
1687 (*info->fprintf_func) (info->stream, "%%val");
1688 break;
1689
1690 case 't':
1691 {
1692 int level = fetch_arg (buffer, place, 3, info);
1693
1694 (*info->fprintf_func) (info->stream, "%d", level);
1695 }
1696 break;
1697
1698 case 'u':
1699 {
1700 short is_upper = 0;
1701 int reg = fetch_arg (buffer, place, 5, info);
1702
1703 if (reg & 0x10)
1704 {
1705 is_upper = 1;
1706 reg &= 0xf;
1707 }
1708 (*info->fprintf_func) (info->stream, "%s%s",
1709 reg_half_names[reg],
1710 is_upper ? "u" : "l");
1711 }
1712 break;
1713
1714 default:
1715 return -2;
1716 }
1717
1718 return p - p0;
1719 }
1720
1721 /* Try to match the current instruction to best and if so, return the
1722 number of bytes consumed from the instruction stream, else zero. */
1723
1724 static int
1725 match_insn_m68k (bfd_vma memaddr,
1726 disassemble_info * info,
1727 const struct m68k_opcode * best,
1728 struct private * priv)
1729 {
1730 unsigned char *save_p;
1731 unsigned char *p;
1732 const char *d;
1733
1734 bfd_byte *buffer = priv->the_buffer;
1735 fprintf_function save_printer = info->fprintf_func;
1736 void (* save_print_address) (bfd_vma, struct disassemble_info *)
1737 = info->print_address_func;
1738
1739 /* Point at first word of argument data,
1740 and at descriptor for first argument. */
1741 p = buffer + 2;
1742
1743 /* Figure out how long the fixed-size portion of the instruction is.
1744 The only place this is stored in the opcode table is
1745 in the arguments--look for arguments which specify fields in the 2nd
1746 or 3rd words of the instruction. */
1747 for (d = best->args; *d; d += 2)
1748 {
1749 /* I don't think it is necessary to be checking d[0] here;
1750 I suspect all this could be moved to the case statement below. */
1751 if (d[0] == '#')
1752 {
1753 if (d[1] == 'l' && p - buffer < 6)
1754 p = buffer + 6;
1755 else if (p - buffer < 4 && d[1] != 'C' && d[1] != '8')
1756 p = buffer + 4;
1757 }
1758
1759 if ((d[0] == 'L' || d[0] == 'l') && d[1] == 'w' && p - buffer < 4)
1760 p = buffer + 4;
1761
1762 switch (d[1])
1763 {
1764 case '1':
1765 case '2':
1766 case '3':
1767 case '7':
1768 case '8':
1769 case '9':
1770 case 'i':
1771 if (p - buffer < 4)
1772 p = buffer + 4;
1773 break;
1774 case '4':
1775 case '5':
1776 case '6':
1777 if (p - buffer < 6)
1778 p = buffer + 6;
1779 break;
1780 default:
1781 break;
1782 }
1783 }
1784
1785 /* pflusha is an exceptions. It takes no arguments but is two words
1786 long. Recognize it by looking at the lower 16 bits of the mask. */
1787 if (p - buffer < 4 && (best->match & 0xFFFF) != 0)
1788 p = buffer + 4;
1789
1790 /* lpstop is another exception. It takes a one word argument but is
1791 three words long. */
1792 if (p - buffer < 6
1793 && (best->match & 0xffff) == 0xffff
1794 && best->args[0] == '#'
1795 && best->args[1] == 'w')
1796 {
1797 /* Copy the one word argument into the usual location for a one
1798 word argument, to simplify printing it. We can get away with
1799 this because we know exactly what the second word is, and we
1800 aren't going to print anything based on it. */
1801 p = buffer + 6;
1802 fetch_data(info, p);
1803 buffer[2] = buffer[4];
1804 buffer[3] = buffer[5];
1805 }
1806
1807 fetch_data(info, p);
1808
1809 d = best->args;
1810
1811 save_p = p;
1812 info->print_address_func = dummy_print_address;
1813 info->fprintf_func = dummy_printer;
1814
1815 /* We scan the operands twice. The first time we don't print anything,
1816 but look for errors. */
1817 for (; *d; d += 2)
1818 {
1819 int eaten = print_insn_arg (d, buffer, p, memaddr + (p - buffer), info);
1820
1821 if (eaten >= 0)
1822 p += eaten;
1823 else if (eaten == -1)
1824 {
1825 info->fprintf_func = save_printer;
1826 info->print_address_func = save_print_address;
1827 return 0;
1828 }
1829 else
1830 {
1831 info->fprintf_func (info->stream,
1832 /* xgettext:c-format */
1833 _("<internal error in opcode table: %s %s>\n"),
1834 best->name, best->args);
1835 info->fprintf_func = save_printer;
1836 info->print_address_func = save_print_address;
1837 return 2;
1838 }
1839 }
1840
1841 p = save_p;
1842 info->fprintf_func = save_printer;
1843 info->print_address_func = save_print_address;
1844
1845 d = best->args;
1846
1847 info->fprintf_func (info->stream, "%s", best->name);
1848
1849 if (*d)
1850 info->fprintf_func (info->stream, " ");
1851
1852 while (*d)
1853 {
1854 p += print_insn_arg (d, buffer, p, memaddr + (p - buffer), info);
1855 d += 2;
1856
1857 if (*d && *(d - 2) != 'I' && *d != 'k')
1858 info->fprintf_func (info->stream, ",");
1859 }
1860
1861 return p - buffer;
1862 }
1863
1864 /* Print the m68k instruction at address MEMADDR in debugged memory,
1865 on INFO->STREAM. Returns length of the instruction, in bytes. */
1866
1867 int
1868 print_insn_m68k (bfd_vma memaddr, disassemble_info *info)
1869 {
1870 int i;
1871 const char *d;
1872 unsigned int arch_mask;
1873 struct private priv;
1874 bfd_byte *buffer = priv.the_buffer;
1875 int major_opcode;
1876 static int numopcodes[16];
1877 static const struct m68k_opcode **opcodes[16];
1878 int val;
1879
1880 if (!opcodes[0])
1881 {
1882 /* Speed up the matching by sorting the opcode
1883 table on the upper four bits of the opcode. */
1884 const struct m68k_opcode **opc_pointer[16];
1885
1886 /* First count how many opcodes are in each of the sixteen buckets. */
1887 for (i = 0; i < m68k_numopcodes; i++)
1888 numopcodes[(m68k_opcodes[i].opcode >> 28) & 15]++;
1889
1890 /* Then create a sorted table of pointers
1891 that point into the unsorted table. */
1892 opc_pointer[0] = malloc (sizeof (struct m68k_opcode *)
1893 * m68k_numopcodes);
1894 opcodes[0] = opc_pointer[0];
1895
1896 for (i = 1; i < 16; i++)
1897 {
1898 opc_pointer[i] = opc_pointer[i - 1] + numopcodes[i - 1];
1899 opcodes[i] = opc_pointer[i];
1900 }
1901
1902 for (i = 0; i < m68k_numopcodes; i++)
1903 *opc_pointer[(m68k_opcodes[i].opcode >> 28) & 15]++ = &m68k_opcodes[i];
1904 }
1905
1906 info->private_data = (PTR) &priv;
1907 /* Tell objdump to use two bytes per chunk
1908 and six bytes per line for displaying raw data. */
1909 info->bytes_per_chunk = 2;
1910 info->bytes_per_line = 6;
1911 info->display_endian = BFD_ENDIAN_BIG;
1912 priv.max_fetched = priv.the_buffer;
1913 priv.insn_start = memaddr;
1914
1915 if (setjmp (priv.bailout) != 0)
1916 /* Error return. */
1917 return -1;
1918
1919 switch (info->mach)
1920 {
1921 default:
1922 case 0:
1923 arch_mask = (unsigned int) -1;
1924 break;
1925 case bfd_mach_m68000:
1926 arch_mask = m68000|m68881|m68851;
1927 break;
1928 case bfd_mach_m68008:
1929 arch_mask = m68008|m68881|m68851;
1930 break;
1931 case bfd_mach_m68010:
1932 arch_mask = m68010|m68881|m68851;
1933 break;
1934 case bfd_mach_m68020:
1935 arch_mask = m68020|m68881|m68851;
1936 break;
1937 case bfd_mach_m68030:
1938 arch_mask = m68030|m68881|m68851;
1939 break;
1940 case bfd_mach_m68040:
1941 arch_mask = m68040|m68881|m68851;
1942 break;
1943 case bfd_mach_m68060:
1944 arch_mask = m68060|m68881|m68851;
1945 break;
1946 case bfd_mach_mcf5200:
1947 arch_mask = mcfisa_a;
1948 break;
1949 case bfd_mach_mcf521x:
1950 case bfd_mach_mcf528x:
1951 arch_mask = mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp|mcfemac;
1952 break;
1953 case bfd_mach_mcf5206e:
1954 arch_mask = mcfisa_a|mcfhwdiv|mcfmac;
1955 break;
1956 case bfd_mach_mcf5249:
1957 arch_mask = mcfisa_a|mcfhwdiv|mcfemac;
1958 break;
1959 case bfd_mach_mcf5307:
1960 arch_mask = mcfisa_a|mcfhwdiv|mcfmac;
1961 break;
1962 case bfd_mach_mcf5407:
1963 arch_mask = mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac;
1964 break;
1965 case bfd_mach_mcf547x:
1966 case bfd_mach_mcf548x:
1967 case bfd_mach_mcfv4e:
1968 arch_mask = mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp|cfloat|mcfemac;
1969 break;
1970 }
1971
1972 fetch_data(info, buffer + 2);
1973 major_opcode = (buffer[0] >> 4) & 15;
1974
1975 for (i = 0; i < numopcodes[major_opcode]; i++)
1976 {
1977 const struct m68k_opcode *opc = opcodes[major_opcode][i];
1978 unsigned long opcode = opc->opcode;
1979 unsigned long match = opc->match;
1980
1981 if (((0xff & buffer[0] & (match >> 24)) == (0xff & (opcode >> 24)))
1982 && ((0xff & buffer[1] & (match >> 16)) == (0xff & (opcode >> 16)))
1983 /* Only fetch the next two bytes if we need to. */
1984 && (((0xffff & match) == 0)
1985 ||
1986 (fetch_data(info, buffer + 4)
1987 && ((0xff & buffer[2] & (match >> 8)) == (0xff & (opcode >> 8)))
1988 && ((0xff & buffer[3] & match) == (0xff & opcode)))
1989 )
1990 && (opc->arch & arch_mask) != 0)
1991 {
1992 /* Don't use for printout the variants of divul and divsl
1993 that have the same register number in two places.
1994 The more general variants will match instead. */
1995 for (d = opc->args; *d; d += 2)
1996 if (d[1] == 'D')
1997 break;
1998
1999 /* Don't use for printout the variants of most floating
2000 point coprocessor instructions which use the same
2001 register number in two places, as above. */
2002 if (*d == '\0')
2003 for (d = opc->args; *d; d += 2)
2004 if (d[1] == 't')
2005 break;
2006
2007 /* Don't match fmovel with more than one register;
2008 wait for fmoveml. */
2009 if (*d == '\0')
2010 {
2011 for (d = opc->args; *d; d += 2)
2012 {
2013 if (d[0] == 's' && d[1] == '8')
2014 {
2015 val = fetch_arg (buffer, d[1], 3, info);
2016 if ((val & (val - 1)) != 0)
2017 break;
2018 }
2019 }
2020 }
2021
2022 if (*d == '\0')
2023 if ((val = match_insn_m68k (memaddr, info, opc, & priv)))
2024 return val;
2025 }
2026 }
2027
2028 /* Handle undefined instructions. */
2029 info->fprintf_func (info->stream, "0%o", (buffer[0] << 8) + buffer[1]);
2030 return 2;
2031 }
2032 /* **** End of m68k-dis.c */
2033 /* **** m68k-opc.h from sourceware.org CVS 2005-08-14. */
2034 /* Opcode table for m680[012346]0/m6888[12]/m68851/mcf5200.
2035 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
2036 2000, 2001, 2003, 2004, 2005
2037 Free Software Foundation, Inc.
2038
2039 This file is part of GDB, GAS, and the GNU binutils.
2040
2041 GDB, GAS, and the GNU binutils are free software; you can redistribute
2042 them and/or modify them under the terms of the GNU General Public
2043 License as published by the Free Software Foundation; either version
2044 1, or (at your option) any later version.
2045
2046 GDB, GAS, and the GNU binutils are distributed in the hope that they
2047 will be useful, but WITHOUT ANY WARRANTY; without even the implied
2048 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
2049 the GNU General Public License for more details.
2050
2051 You should have received a copy of the GNU General Public License
2052 along with this file; see the file COPYING. If not,
2053 see <http://www.gnu.org/licenses/>. */
2054
2055 #define one(x) ((unsigned int) (x) << 16)
2056 #define two(x, y) (((unsigned int) (x) << 16) + (y))
2057
2058 /* The assembler requires that all instances of the same mnemonic must
2059 be consecutive. If they aren't, the assembler will bomb at
2060 runtime. */
2061
2062 const struct m68k_opcode m68k_opcodes[] =
2063 {
2064 {"abcd", 2, one(0140400), one(0170770), "DsDd", m68000up },
2065 {"abcd", 2, one(0140410), one(0170770), "-s-d", m68000up },
2066
2067 {"addaw", 2, one(0150300), one(0170700), "*wAd", m68000up },
2068 {"addal", 2, one(0150700), one(0170700), "*lAd", m68000up | mcfisa_a },
2069
2070 {"addib", 4, one(0003000), one(0177700), "#b$s", m68000up },
2071 {"addiw", 4, one(0003100), one(0177700), "#w$s", m68000up },
2072 {"addil", 6, one(0003200), one(0177700), "#l$s", m68000up },
2073 {"addil", 6, one(0003200), one(0177700), "#lDs", mcfisa_a },
2074
2075 {"addqb", 2, one(0050000), one(0170700), "Qd$b", m68000up },
2076 {"addqw", 2, one(0050100), one(0170700), "Qd%w", m68000up },
2077 {"addql", 2, one(0050200), one(0170700), "Qd%l", m68000up | mcfisa_a },
2078
2079 /* The add opcode can generate the adda, addi, and addq instructions. */
2080 {"addb", 2, one(0050000), one(0170700), "Qd$b", m68000up },
2081 {"addb", 4, one(0003000), one(0177700), "#b$s", m68000up },
2082 {"addb", 2, one(0150000), one(0170700), ";bDd", m68000up },
2083 {"addb", 2, one(0150400), one(0170700), "Dd~b", m68000up },
2084 {"addw", 2, one(0050100), one(0170700), "Qd%w", m68000up },
2085 {"addw", 2, one(0150300), one(0170700), "*wAd", m68000up },
2086 {"addw", 4, one(0003100), one(0177700), "#w$s", m68000up },
2087 {"addw", 2, one(0150100), one(0170700), "*wDd", m68000up },
2088 {"addw", 2, one(0150500), one(0170700), "Dd~w", m68000up },
2089 {"addl", 2, one(0050200), one(0170700), "Qd%l", m68000up | mcfisa_a },
2090 {"addl", 6, one(0003200), one(0177700), "#l$s", m68000up },
2091 {"addl", 6, one(0003200), one(0177700), "#lDs", mcfisa_a },
2092 {"addl", 2, one(0150700), one(0170700), "*lAd", m68000up | mcfisa_a },
2093 {"addl", 2, one(0150200), one(0170700), "*lDd", m68000up | mcfisa_a },
2094 {"addl", 2, one(0150600), one(0170700), "Dd~l", m68000up | mcfisa_a },
2095
2096 {"addxb", 2, one(0150400), one(0170770), "DsDd", m68000up },
2097 {"addxb", 2, one(0150410), one(0170770), "-s-d", m68000up },
2098 {"addxw", 2, one(0150500), one(0170770), "DsDd", m68000up },
2099 {"addxw", 2, one(0150510), one(0170770), "-s-d", m68000up },
2100 {"addxl", 2, one(0150600), one(0170770), "DsDd", m68000up | mcfisa_a },
2101 {"addxl", 2, one(0150610), one(0170770), "-s-d", m68000up },
2102
2103 {"andib", 4, one(0001000), one(0177700), "#b$s", m68000up },
2104 {"andib", 4, one(0001074), one(0177777), "#bCs", m68000up },
2105 {"andiw", 4, one(0001100), one(0177700), "#w$s", m68000up },
2106 {"andiw", 4, one(0001174), one(0177777), "#wSs", m68000up },
2107 {"andil", 6, one(0001200), one(0177700), "#l$s", m68000up },
2108 {"andil", 6, one(0001200), one(0177700), "#lDs", mcfisa_a },
2109 {"andi", 4, one(0001100), one(0177700), "#w$s", m68000up },
2110 {"andi", 4, one(0001074), one(0177777), "#bCs", m68000up },
2111 {"andi", 4, one(0001174), one(0177777), "#wSs", m68000up },
2112
2113 /* The and opcode can generate the andi instruction. */
2114 {"andb", 4, one(0001000), one(0177700), "#b$s", m68000up },
2115 {"andb", 4, one(0001074), one(0177777), "#bCs", m68000up },
2116 {"andb", 2, one(0140000), one(0170700), ";bDd", m68000up },
2117 {"andb", 2, one(0140400), one(0170700), "Dd~b", m68000up },
2118 {"andw", 4, one(0001100), one(0177700), "#w$s", m68000up },
2119 {"andw", 4, one(0001174), one(0177777), "#wSs", m68000up },
2120 {"andw", 2, one(0140100), one(0170700), ";wDd", m68000up },
2121 {"andw", 2, one(0140500), one(0170700), "Dd~w", m68000up },
2122 {"andl", 6, one(0001200), one(0177700), "#l$s", m68000up },
2123 {"andl", 6, one(0001200), one(0177700), "#lDs", mcfisa_a },
2124 {"andl", 2, one(0140200), one(0170700), ";lDd", m68000up | mcfisa_a },
2125 {"andl", 2, one(0140600), one(0170700), "Dd~l", m68000up | mcfisa_a },
2126 {"and", 4, one(0001100), one(0177700), "#w$w", m68000up },
2127 {"and", 4, one(0001074), one(0177777), "#bCs", m68000up },
2128 {"and", 4, one(0001174), one(0177777), "#wSs", m68000up },
2129 {"and", 2, one(0140100), one(0170700), ";wDd", m68000up },
2130 {"and", 2, one(0140500), one(0170700), "Dd~w", m68000up },
2131
2132 {"aslb", 2, one(0160400), one(0170770), "QdDs", m68000up },
2133 {"aslb", 2, one(0160440), one(0170770), "DdDs", m68000up },
2134 {"aslw", 2, one(0160500), one(0170770), "QdDs", m68000up },
2135 {"aslw", 2, one(0160540), one(0170770), "DdDs", m68000up },
2136 {"aslw", 2, one(0160700), one(0177700), "~s", m68000up },
2137 {"asll", 2, one(0160600), one(0170770), "QdDs", m68000up | mcfisa_a },
2138 {"asll", 2, one(0160640), one(0170770), "DdDs", m68000up | mcfisa_a },
2139
2140 {"asrb", 2, one(0160000), one(0170770), "QdDs", m68000up },
2141 {"asrb", 2, one(0160040), one(0170770), "DdDs", m68000up },
2142 {"asrw", 2, one(0160100), one(0170770), "QdDs", m68000up },
2143 {"asrw", 2, one(0160140), one(0170770), "DdDs", m68000up },
2144 {"asrw", 2, one(0160300), one(0177700), "~s", m68000up },
2145 {"asrl", 2, one(0160200), one(0170770), "QdDs", m68000up | mcfisa_a },
2146 {"asrl", 2, one(0160240), one(0170770), "DdDs", m68000up | mcfisa_a },
2147
2148 {"bhiw", 2, one(0061000), one(0177777), "BW", m68000up | mcfisa_a },
2149 {"blsw", 2, one(0061400), one(0177777), "BW", m68000up | mcfisa_a },
2150 {"bccw", 2, one(0062000), one(0177777), "BW", m68000up | mcfisa_a },
2151 {"bcsw", 2, one(0062400), one(0177777), "BW", m68000up | mcfisa_a },
2152 {"bnew", 2, one(0063000), one(0177777), "BW", m68000up | mcfisa_a },
2153 {"beqw", 2, one(0063400), one(0177777), "BW", m68000up | mcfisa_a },
2154 {"bvcw", 2, one(0064000), one(0177777), "BW", m68000up | mcfisa_a },
2155 {"bvsw", 2, one(0064400), one(0177777), "BW", m68000up | mcfisa_a },
2156 {"bplw", 2, one(0065000), one(0177777), "BW", m68000up | mcfisa_a },
2157 {"bmiw", 2, one(0065400), one(0177777), "BW", m68000up | mcfisa_a },
2158 {"bgew", 2, one(0066000), one(0177777), "BW", m68000up | mcfisa_a },
2159 {"bltw", 2, one(0066400), one(0177777), "BW", m68000up | mcfisa_a },
2160 {"bgtw", 2, one(0067000), one(0177777), "BW", m68000up | mcfisa_a },
2161 {"blew", 2, one(0067400), one(0177777), "BW", m68000up | mcfisa_a },
2162
2163 {"bhil", 2, one(0061377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2164 {"blsl", 2, one(0061777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2165 {"bccl", 2, one(0062377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2166 {"bcsl", 2, one(0062777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2167 {"bnel", 2, one(0063377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2168 {"beql", 2, one(0063777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2169 {"bvcl", 2, one(0064377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2170 {"bvsl", 2, one(0064777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2171 {"bpll", 2, one(0065377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2172 {"bmil", 2, one(0065777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2173 {"bgel", 2, one(0066377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2174 {"bltl", 2, one(0066777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2175 {"bgtl", 2, one(0067377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2176 {"blel", 2, one(0067777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2177
2178 {"bhis", 2, one(0061000), one(0177400), "BB", m68000up | mcfisa_a },
2179 {"blss", 2, one(0061400), one(0177400), "BB", m68000up | mcfisa_a },
2180 {"bccs", 2, one(0062000), one(0177400), "BB", m68000up | mcfisa_a },
2181 {"bcss", 2, one(0062400), one(0177400), "BB", m68000up | mcfisa_a },
2182 {"bnes", 2, one(0063000), one(0177400), "BB", m68000up | mcfisa_a },
2183 {"beqs", 2, one(0063400), one(0177400), "BB", m68000up | mcfisa_a },
2184 {"bvcs", 2, one(0064000), one(0177400), "BB", m68000up | mcfisa_a },
2185 {"bvss", 2, one(0064400), one(0177400), "BB", m68000up | mcfisa_a },
2186 {"bpls", 2, one(0065000), one(0177400), "BB", m68000up | mcfisa_a },
2187 {"bmis", 2, one(0065400), one(0177400), "BB", m68000up | mcfisa_a },
2188 {"bges", 2, one(0066000), one(0177400), "BB", m68000up | mcfisa_a },
2189 {"blts", 2, one(0066400), one(0177400), "BB", m68000up | mcfisa_a },
2190 {"bgts", 2, one(0067000), one(0177400), "BB", m68000up | mcfisa_a },
2191 {"bles", 2, one(0067400), one(0177400), "BB", m68000up | mcfisa_a },
2192
2193 {"jhi", 2, one(0061000), one(0177400), "Bg", m68000up | mcfisa_a },
2194 {"jls", 2, one(0061400), one(0177400), "Bg", m68000up | mcfisa_a },
2195 {"jcc", 2, one(0062000), one(0177400), "Bg", m68000up | mcfisa_a },
2196 {"jcs", 2, one(0062400), one(0177400), "Bg", m68000up | mcfisa_a },
2197 {"jne", 2, one(0063000), one(0177400), "Bg", m68000up | mcfisa_a },
2198 {"jeq", 2, one(0063400), one(0177400), "Bg", m68000up | mcfisa_a },
2199 {"jvc", 2, one(0064000), one(0177400), "Bg", m68000up | mcfisa_a },
2200 {"jvs", 2, one(0064400), one(0177400), "Bg", m68000up | mcfisa_a },
2201 {"jpl", 2, one(0065000), one(0177400), "Bg", m68000up | mcfisa_a },
2202 {"jmi", 2, one(0065400), one(0177400), "Bg", m68000up | mcfisa_a },
2203 {"jge", 2, one(0066000), one(0177400), "Bg", m68000up | mcfisa_a },
2204 {"jlt", 2, one(0066400), one(0177400), "Bg", m68000up | mcfisa_a },
2205 {"jgt", 2, one(0067000), one(0177400), "Bg", m68000up | mcfisa_a },
2206 {"jle", 2, one(0067400), one(0177400), "Bg", m68000up | mcfisa_a },
2207
2208 {"bchg", 2, one(0000500), one(0170700), "Dd$s", m68000up | mcfisa_a },
2209 {"bchg", 4, one(0004100), one(0177700), "#b$s", m68000up },
2210 {"bchg", 4, one(0004100), one(0177700), "#bqs", mcfisa_a },
2211
2212 {"bclr", 2, one(0000600), one(0170700), "Dd$s", m68000up | mcfisa_a },
2213 {"bclr", 4, one(0004200), one(0177700), "#b$s", m68000up },
2214 {"bclr", 4, one(0004200), one(0177700), "#bqs", mcfisa_a },
2215
2216 {"bfchg", 4, two(0165300, 0), two(0177700, 0170000), "?sO2O3", m68020up },
2217 {"bfclr", 4, two(0166300, 0), two(0177700, 0170000), "?sO2O3", m68020up },
2218 {"bfexts", 4, two(0165700, 0), two(0177700, 0100000), "/sO2O3D1", m68020up },
2219 {"bfextu", 4, two(0164700, 0), two(0177700, 0100000), "/sO2O3D1", m68020up },
2220 {"bfffo", 4, two(0166700, 0), two(0177700, 0100000), "/sO2O3D1", m68020up },
2221 {"bfins", 4, two(0167700, 0), two(0177700, 0100000), "D1?sO2O3", m68020up },
2222 {"bfset", 4, two(0167300, 0), two(0177700, 0170000), "?sO2O3", m68020up },
2223 {"bftst", 4, two(0164300, 0), two(0177700, 0170000), "/sO2O3", m68020up },
2224
2225 {"bgnd", 2, one(0045372), one(0177777), "", cpu32 },
2226
2227 {"bitrev", 2, one(0000300), one(0177770), "Ds", mcfisa_aa},
2228
2229 {"bkpt", 2, one(0044110), one(0177770), "ts", m68010up },
2230
2231 {"braw", 2, one(0060000), one(0177777), "BW", m68000up | mcfisa_a },
2232 {"bral", 2, one(0060377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2233 {"bras", 2, one(0060000), one(0177400), "BB", m68000up | mcfisa_a },
2234
2235 {"bset", 2, one(0000700), one(0170700), "Dd$s", m68000up | mcfisa_a },
2236 {"bset", 2, one(0000700), one(0170700), "Ddvs", mcfisa_a },
2237 {"bset", 4, one(0004300), one(0177700), "#b$s", m68000up },
2238 {"bset", 4, one(0004300), one(0177700), "#bqs", mcfisa_a },
2239
2240 {"bsrw", 2, one(0060400), one(0177777), "BW", m68000up | mcfisa_a },
2241 {"bsrl", 2, one(0060777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b},
2242 {"bsrs", 2, one(0060400), one(0177400), "BB", m68000up | mcfisa_a },
2243
2244 {"btst", 2, one(0000400), one(0170700), "Dd;b", m68000up | mcfisa_a },
2245 {"btst", 4, one(0004000), one(0177700), "#b@s", m68000up },
2246 {"btst", 4, one(0004000), one(0177700), "#bqs", mcfisa_a },
2247
2248 {"byterev", 2, one(0001300), one(0177770), "Ds", mcfisa_aa},
2249
2250 {"callm", 4, one(0003300), one(0177700), "#b!s", m68020 },
2251
2252 {"cas2w", 6, two(0006374,0), two(0177777,0007070), "D3D6D2D5r1r4", m68020up },
2253 {"cas2w", 6, two(0006374,0), two(0177777,0007070), "D3D6D2D5R1R4", m68020up },
2254 {"cas2l", 6, two(0007374,0), two(0177777,0007070), "D3D6D2D5r1r4", m68020up },
2255 {"cas2l", 6, two(0007374,0), two(0177777,0007070), "D3D6D2D5R1R4", m68020up },
2256
2257 {"casb", 4, two(0005300, 0), two(0177700, 0177070), "D3D2~s", m68020up },
2258 {"casw", 4, two(0006300, 0), two(0177700, 0177070), "D3D2~s", m68020up },
2259 {"casl", 4, two(0007300, 0), two(0177700, 0177070), "D3D2~s", m68020up },
2260
2261 {"chk2b", 4, two(0000300,0004000), two(0177700,07777), "!sR1", m68020up | cpu32 },
2262 {"chk2w", 4, two(0001300,0004000), two(0177700,07777), "!sR1", m68020up | cpu32 },
2263 {"chk2l", 4, two(0002300,0004000), two(0177700,07777), "!sR1", m68020up | cpu32 },
2264
2265 {"chkl", 2, one(0040400), one(0170700), ";lDd", m68000up },
2266 {"chkw", 2, one(0040600), one(0170700), ";wDd", m68000up },
2267
2268 #define SCOPE_LINE (0x1 << 3)
2269 #define SCOPE_PAGE (0x2 << 3)
2270 #define SCOPE_ALL (0x3 << 3)
2271
2272 {"cinva", 2, one(0xf400|SCOPE_ALL), one(0xff38), "ce", m68040up },
2273 {"cinvl", 2, one(0xf400|SCOPE_LINE), one(0xff38), "ceas", m68040up },
2274 {"cinvp", 2, one(0xf400|SCOPE_PAGE), one(0xff38), "ceas", m68040up },
2275
2276 {"cpusha", 2, one(0xf420|SCOPE_ALL), one(0xff38), "ce", m68040up },
2277 {"cpushl", 2, one(0xf420|SCOPE_LINE), one(0xff38), "ceas", m68040up | mcfisa_a },
2278 {"cpushp", 2, one(0xf420|SCOPE_PAGE), one(0xff38), "ceas", m68040up },
2279
2280 #undef SCOPE_LINE
2281 #undef SCOPE_PAGE
2282 #undef SCOPE_ALL
2283
2284 {"clrb", 2, one(0041000), one(0177700), "$s", m68000up | mcfisa_a },
2285 {"clrw", 2, one(0041100), one(0177700), "$s", m68000up | mcfisa_a },
2286 {"clrl", 2, one(0041200), one(0177700), "$s", m68000up | mcfisa_a },
2287
2288 {"cmp2b", 4, two(0000300,0), two(0177700,07777), "!sR1", m68020up | cpu32 },
2289 {"cmp2w", 4, two(0001300,0), two(0177700,07777), "!sR1", m68020up | cpu32 },
2290 {"cmp2l", 4, two(0002300,0), two(0177700,07777), "!sR1", m68020up | cpu32 },
2291
2292 {"cmpaw", 2, one(0130300), one(0170700), "*wAd", m68000up },
2293 {"cmpal", 2, one(0130700), one(0170700), "*lAd", m68000up | mcfisa_a },
2294
2295 {"cmpib", 4, one(0006000), one(0177700), "#b@s", m68000up },
2296 {"cmpib", 4, one(0006000), one(0177700), "#bDs", mcfisa_b },
2297 {"cmpiw", 4, one(0006100), one(0177700), "#w@s", m68000up },
2298 {"cmpiw", 4, one(0006100), one(0177700), "#wDs", mcfisa_b },
2299 {"cmpil", 6, one(0006200), one(0177700), "#l@s", m68000up },
2300 {"cmpil", 6, one(0006200), one(0177700), "#lDs", mcfisa_a },
2301
2302 {"cmpmb", 2, one(0130410), one(0170770), "+s+d", m68000up },
2303 {"cmpmw", 2, one(0130510), one(0170770), "+s+d", m68000up },
2304 {"cmpml", 2, one(0130610), one(0170770), "+s+d", m68000up },
2305
2306 /* The cmp opcode can generate the cmpa, cmpm, and cmpi instructions. */
2307 {"cmpb", 4, one(0006000), one(0177700), "#b@s", m68000up },
2308 {"cmpb", 4, one(0006000), one(0177700), "#bDs", mcfisa_b },
2309 {"cmpb", 2, one(0130410), one(0170770), "+s+d", m68000up },
2310 {"cmpb", 2, one(0130000), one(0170700), ";bDd", m68000up },
2311 {"cmpb", 2, one(0130000), one(0170700), "*bDd", mcfisa_b },
2312 {"cmpw", 2, one(0130300), one(0170700), "*wAd", m68000up },
2313 {"cmpw", 4, one(0006100), one(0177700), "#w@s", m68000up },
2314 {"cmpw", 4, one(0006100), one(0177700), "#wDs", mcfisa_b },
2315 {"cmpw", 2, one(0130510), one(0170770), "+s+d", m68000up },
2316 {"cmpw", 2, one(0130100), one(0170700), "*wDd", m68000up | mcfisa_b },
2317 {"cmpl", 2, one(0130700), one(0170700), "*lAd", m68000up | mcfisa_a },
2318 {"cmpl", 6, one(0006200), one(0177700), "#l@s", m68000up },
2319 {"cmpl", 6, one(0006200), one(0177700), "#lDs", mcfisa_a },
2320 {"cmpl", 2, one(0130610), one(0170770), "+s+d", m68000up },
2321 {"cmpl", 2, one(0130200), one(0170700), "*lDd", m68000up | mcfisa_a },
2322
2323 {"dbcc", 2, one(0052310), one(0177770), "DsBw", m68000up },
2324 {"dbcs", 2, one(0052710), one(0177770), "DsBw", m68000up },
2325 {"dbeq", 2, one(0053710), one(0177770), "DsBw", m68000up },
2326 {"dbf", 2, one(0050710), one(0177770), "DsBw", m68000up },
2327 {"dbge", 2, one(0056310), one(0177770), "DsBw", m68000up },
2328 {"dbgt", 2, one(0057310), one(0177770), "DsBw", m68000up },
2329 {"dbhi", 2, one(0051310), one(0177770), "DsBw", m68000up },
2330 {"dble", 2, one(0057710), one(0177770), "DsBw", m68000up },
2331 {"dbls", 2, one(0051710), one(0177770), "DsBw", m68000up },
2332 {"dblt", 2, one(0056710), one(0177770), "DsBw", m68000up },
2333 {"dbmi", 2, one(0055710), one(0177770), "DsBw", m68000up },
2334 {"dbne", 2, one(0053310), one(0177770), "DsBw", m68000up },
2335 {"dbpl", 2, one(0055310), one(0177770), "DsBw", m68000up },
2336 {"dbt", 2, one(0050310), one(0177770), "DsBw", m68000up },
2337 {"dbvc", 2, one(0054310), one(0177770), "DsBw", m68000up },
2338 {"dbvs", 2, one(0054710), one(0177770), "DsBw", m68000up },
2339
2340 {"divsw", 2, one(0100700), one(0170700), ";wDd", m68000up | mcfhwdiv },
2341
2342 {"divsl", 4, two(0046100,0006000),two(0177700,0107770),";lD3D1", m68020up|cpu32 },
2343 {"divsl", 4, two(0046100,0004000),two(0177700,0107770),";lDD", m68020up|cpu32 },
2344 {"divsl", 4, two(0046100,0004000),two(0177700,0107770),"qsDD", mcfhwdiv },
2345
2346 {"divsll", 4, two(0046100,0004000),two(0177700,0107770),";lD3D1",m68020up|cpu32 },
2347 {"divsll", 4, two(0046100,0004000),two(0177700,0107770),";lDD", m68020up|cpu32 },
2348
2349 {"divuw", 2, one(0100300), one(0170700), ";wDd", m68000up | mcfhwdiv },
2350
2351 {"divul", 4, two(0046100,0002000),two(0177700,0107770),";lD3D1", m68020up|cpu32 },
2352 {"divul", 4, two(0046100,0000000),two(0177700,0107770),";lDD", m68020up|cpu32 },
2353 {"divul", 4, two(0046100,0000000),two(0177700,0107770),"qsDD", mcfhwdiv },
2354
2355 {"divull", 4, two(0046100,0000000),two(0177700,0107770),";lD3D1",m68020up|cpu32 },
2356 {"divull", 4, two(0046100,0000000),two(0177700,0107770),";lDD", m68020up|cpu32 },
2357
2358 {"eorib", 4, one(0005000), one(0177700), "#b$s", m68000up },
2359 {"eorib", 4, one(0005074), one(0177777), "#bCs", m68000up },
2360 {"eoriw", 4, one(0005100), one(0177700), "#w$s", m68000up },
2361 {"eoriw", 4, one(0005174), one(0177777), "#wSs", m68000up },
2362 {"eoril", 6, one(0005200), one(0177700), "#l$s", m68000up },
2363 {"eoril", 6, one(0005200), one(0177700), "#lDs", mcfisa_a },
2364 {"eori", 4, one(0005074), one(0177777), "#bCs", m68000up },
2365 {"eori", 4, one(0005174), one(0177777), "#wSs", m68000up },
2366 {"eori", 4, one(0005100), one(0177700), "#w$s", m68000up },
2367
2368 /* The eor opcode can generate the eori instruction. */
2369 {"eorb", 4, one(0005000), one(0177700), "#b$s", m68000up },
2370 {"eorb", 4, one(0005074), one(0177777), "#bCs", m68000up },
2371 {"eorb", 2, one(0130400), one(0170700), "Dd$s", m68000up },
2372 {"eorw", 4, one(0005100), one(0177700), "#w$s", m68000up },
2373 {"eorw", 4, one(0005174), one(0177777), "#wSs", m68000up },
2374 {"eorw", 2, one(0130500), one(0170700), "Dd$s", m68000up },
2375 {"eorl", 6, one(0005200), one(0177700), "#l$s", m68000up },
2376 {"eorl", 6, one(0005200), one(0177700), "#lDs", mcfisa_a },
2377 {"eorl", 2, one(0130600), one(0170700), "Dd$s", m68000up | mcfisa_a },
2378 {"eor", 4, one(0005074), one(0177777), "#bCs", m68000up },
2379 {"eor", 4, one(0005174), one(0177777), "#wSs", m68000up },
2380 {"eor", 4, one(0005100), one(0177700), "#w$s", m68000up },
2381 {"eor", 2, one(0130500), one(0170700), "Dd$s", m68000up },
2382
2383 {"exg", 2, one(0140500), one(0170770), "DdDs", m68000up },
2384 {"exg", 2, one(0140510), one(0170770), "AdAs", m68000up },
2385 {"exg", 2, one(0140610), one(0170770), "DdAs", m68000up },
2386 {"exg", 2, one(0140610), one(0170770), "AsDd", m68000up },
2387
2388 {"extw", 2, one(0044200), one(0177770), "Ds", m68000up|mcfisa_a },
2389 {"extl", 2, one(0044300), one(0177770), "Ds", m68000up|mcfisa_a },
2390 {"extbl", 2, one(0044700), one(0177770), "Ds", m68020up|cpu32|mcfisa_a },
2391
2392 {"ff1", 2, one(0002300), one(0177770), "Ds", mcfisa_aa},
2393
2394 /* float stuff starts here */
2395
2396 {"fabsb", 4, two(0xF000, 0x5818), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
2397 {"fabsb", 4, two(0xF000, 0x5818), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2398 {"fabsd", 4, two(0xF000, 0x0018), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
2399 {"fabsd", 4, two(0xF000, 0x0018), two(0xF1C0, 0xE07F), "IiFt", cfloat },
2400 {"fabsd", 4, two(0xF000, 0x5418), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
2401 {"fabsd", 4, two(0xF000, 0x5418), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
2402 {"fabsl", 4, two(0xF000, 0x4018), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
2403 {"fabsl", 4, two(0xF000, 0x4018), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2404 {"fabsp", 4, two(0xF000, 0x4C18), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
2405 {"fabss", 4, two(0xF000, 0x4418), two(0xF1C0, 0xFC7F), "Ii;fF7", cfloat },
2406 {"fabss", 4, two(0xF000, 0x4418), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
2407 {"fabsw", 4, two(0xF000, 0x5018), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
2408 {"fabsw", 4, two(0xF000, 0x5018), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2409 {"fabsx", 4, two(0xF000, 0x0018), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
2410 {"fabsx", 4, two(0xF000, 0x4818), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
2411 {"fabsx", 4, two(0xF000, 0x0018), two(0xF1C0, 0xE07F), "IiFt", mfloat },
2412
2413 {"fsabsb", 4, two(0xF000, 0x5858), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up },
2414 {"fsabsb", 4, two(0xF000, 0x5858), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2415 {"fsabsd", 4, two(0xF000, 0x0058), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
2416 {"fsabsd", 4, two(0xF000, 0x0058), two(0xF1C0, 0xE07F), "IiFt", cfloat },
2417 {"fsabsd", 4, two(0xF000, 0x5458), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up },
2418 {"fsabsd", 4, two(0xF000, 0x5458), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
2419 {"fsabsl", 4, two(0xF000, 0x4058), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up },
2420 {"fsabsl", 4, two(0xF000, 0x4058), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2421 {"fsabsp", 4, two(0xF000, 0x4C58), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up },
2422 {"fsabss", 4, two(0xF000, 0x4258), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2423 {"fsabss", 4, two(0xF000, 0x4458), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up },
2424 {"fsabsw", 4, two(0xF000, 0x5058), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up },
2425 {"fsabsw", 4, two(0xF000, 0x5058), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2426 {"fsabsx", 4, two(0xF000, 0x0058), two(0xF1C0, 0xE07F), "IiF8F7", m68040up },
2427 {"fsabsx", 4, two(0xF000, 0x4858), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up },
2428 {"fsabsx", 4, two(0xF000, 0x0058), two(0xF1C0, 0xE07F), "IiFt", m68040up },
2429
2430 {"fdabsb", 4, two(0xF000, 0x585C), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2431 {"fdabsb", 4, two(0xF000, 0x585c), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up},
2432 {"fdabsd", 4, two(0xF000, 0x005C), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
2433 {"fdabsd", 4, two(0xF000, 0x005C), two(0xF1C0, 0xE07F), "IiFt", cfloat },
2434 {"fdabsd", 4, two(0xF000, 0x545C), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
2435 {"fdabsd", 4, two(0xF000, 0x545c), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up},
2436 {"fdabsl", 4, two(0xF000, 0x405C), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2437 {"fdabsl", 4, two(0xF000, 0x405c), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up},
2438 {"fdabsp", 4, two(0xF000, 0x4C5c), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up},
2439 {"fdabss", 4, two(0xF000, 0x425C), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2440 {"fdabss", 4, two(0xF000, 0x445c), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up},
2441 {"fdabsw", 4, two(0xF000, 0x505C), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2442 {"fdabsw", 4, two(0xF000, 0x505c), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up},
2443 {"fdabsx", 4, two(0xF000, 0x005c), two(0xF1C0, 0xE07F), "IiF8F7", m68040up},
2444 {"fdabsx", 4, two(0xF000, 0x485c), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up},
2445 {"fdabsx", 4, two(0xF000, 0x005c), two(0xF1C0, 0xE07F), "IiFt", m68040up},
2446
2447 {"facosb", 4, two(0xF000, 0x581C), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
2448 {"facosd", 4, two(0xF000, 0x541C), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
2449 {"facosl", 4, two(0xF000, 0x401C), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
2450 {"facosp", 4, two(0xF000, 0x4C1C), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
2451 {"facoss", 4, two(0xF000, 0x441C), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
2452 {"facosw", 4, two(0xF000, 0x501C), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
2453 {"facosx", 4, two(0xF000, 0x001C), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
2454 {"facosx", 4, two(0xF000, 0x481C), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
2455 {"facosx", 4, two(0xF000, 0x001C), two(0xF1C0, 0xE07F), "IiFt", mfloat },
2456
2457 {"faddb", 4, two(0xF000, 0x5822), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
2458 {"faddb", 4, two(0xF000, 0x5822), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2459 {"faddd", 4, two(0xF000, 0x0022), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
2460 {"faddd", 4, two(0xF000, 0x5422), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
2461 {"faddd", 4, two(0xF000, 0x5422), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
2462 {"faddd", 4, two(0xF000, 0x5422), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
2463 {"faddl", 4, two(0xF000, 0x4022), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
2464 {"faddl", 4, two(0xF000, 0x4022), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2465 {"faddp", 4, two(0xF000, 0x4C22), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
2466 {"fadds", 4, two(0xF000, 0x4422), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
2467 {"fadds", 4, two(0xF000, 0x4422), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2468 {"faddw", 4, two(0xF000, 0x5022), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
2469 {"faddw", 4, two(0xF000, 0x5022), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2470 {"faddx", 4, two(0xF000, 0x0022), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
2471 {"faddx", 4, two(0xF000, 0x4822), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
2472
2473 {"fsaddb", 4, two(0xF000, 0x5862), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up },
2474 {"fsaddb", 4, two(0xF000, 0x5862), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2475 {"fsaddd", 4, two(0xF000, 0x0066), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
2476 {"fsaddd", 4, two(0xF000, 0x5462), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up },
2477 {"fsaddd", 4, two(0xF000, 0x5462), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
2478 {"fsaddl", 4, two(0xF000, 0x4062), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up },
2479 {"fsaddl", 4, two(0xF000, 0x4062), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2480 {"fsaddp", 4, two(0xF000, 0x4C62), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up },
2481 {"fsadds", 4, two(0xF000, 0x4462), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up },
2482 {"fsadds", 4, two(0xF000, 0x4862), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2483 {"fsaddw", 4, two(0xF000, 0x5062), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up },
2484 {"fsaddw", 4, two(0xF000, 0x5062), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2485 {"fsaddx", 4, two(0xF000, 0x0062), two(0xF1C0, 0xE07F), "IiF8F7", m68040up },
2486 {"fsaddx", 4, two(0xF000, 0x4862), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up },
2487
2488 {"fdaddb", 4, two(0xF000, 0x5826), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2489 {"fdaddb", 4, two(0xF000, 0x5866), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up },
2490 {"fdaddd", 4, two(0xF000, 0x0066), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
2491 {"fdaddd", 4, two(0xF000, 0x5426), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2492 {"fdaddd", 4, two(0xF000, 0x5466), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up },
2493 {"fdaddl", 4, two(0xF000, 0x4026), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
2494 {"fdaddl", 4, two(0xF000, 0x4066), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up },
2495 {"fdaddp", 4, two(0xF000, 0x4C66), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up },
2496 {"fdadds", 4, two(0xF000, 0x4466), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up },
2497 {"fdadds", 4, two(0xF000, 0x4826), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2498 {"fdaddw", 4, two(0xF000, 0x5026), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2499 {"fdaddw", 4, two(0xF000, 0x5066), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up },
2500 {"fdaddx", 4, two(0xF000, 0x0066), two(0xF1C0, 0xE07F), "IiF8F7", m68040up },
2501 {"fdaddx", 4, two(0xF000, 0x4866), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up },
2502
2503 {"fasinb", 4, two(0xF000, 0x580C), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
2504 {"fasind", 4, two(0xF000, 0x540C), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
2505 {"fasinl", 4, two(0xF000, 0x400C), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
2506 {"fasinp", 4, two(0xF000, 0x4C0C), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
2507 {"fasins", 4, two(0xF000, 0x440C), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
2508 {"fasinw", 4, two(0xF000, 0x500C), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
2509 {"fasinx", 4, two(0xF000, 0x000C), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
2510 {"fasinx", 4, two(0xF000, 0x480C), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
2511 {"fasinx", 4, two(0xF000, 0x000C), two(0xF1C0, 0xE07F), "IiFt", mfloat },
2512
2513 {"fatanb", 4, two(0xF000, 0x580A), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
2514 {"fatand", 4, two(0xF000, 0x540A), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
2515 {"fatanl", 4, two(0xF000, 0x400A), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
2516 {"fatanp", 4, two(0xF000, 0x4C0A), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
2517 {"fatans", 4, two(0xF000, 0x440A), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
2518 {"fatanw", 4, two(0xF000, 0x500A), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
2519 {"fatanx", 4, two(0xF000, 0x000A), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
2520 {"fatanx", 4, two(0xF000, 0x480A), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
2521 {"fatanx", 4, two(0xF000, 0x000A), two(0xF1C0, 0xE07F), "IiFt", mfloat },
2522
2523 {"fatanhb", 4, two(0xF000, 0x580D), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
2524 {"fatanhd", 4, two(0xF000, 0x540D), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
2525 {"fatanhl", 4, two(0xF000, 0x400D), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
2526 {"fatanhp", 4, two(0xF000, 0x4C0D), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
2527 {"fatanhs", 4, two(0xF000, 0x440D), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat },
2528 {"fatanhw", 4, two(0xF000, 0x500D), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat },
2529 {"fatanhx", 4, two(0xF000, 0x000D), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
2530 {"fatanhx", 4, two(0xF000, 0x480D), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
2531 {"fatanhx", 4, two(0xF000, 0x000D), two(0xF1C0, 0xE07F), "IiFt", mfloat },
2532
2533 {"fbeq", 2, one(0xF081), one(0xF1FF), "IdBW", mfloat | cfloat },
2534 {"fbf", 2, one(0xF080), one(0xF1FF), "IdBW", mfloat | cfloat },
2535 {"fbge", 2, one(0xF093), one(0xF1FF), "IdBW", mfloat | cfloat },
2536 {"fbgl", 2, one(0xF096), one(0xF1FF), "IdBW", mfloat | cfloat },
2537 {"fbgle", 2, one(0xF097), one(0xF1FF), "IdBW", mfloat | cfloat },
2538 {"fbgt", 2, one(0xF092), one(0xF1FF), "IdBW", mfloat | cfloat },
2539 {"fble", 2, one(0xF095), one(0xF1FF), "IdBW", mfloat | cfloat },
2540 {"fblt", 2, one(0xF094), one(0xF1FF), "IdBW", mfloat | cfloat },
2541 {"fbne", 2, one(0xF08E), one(0xF1FF), "IdBW", mfloat | cfloat },
2542 {"fbnge", 2, one(0xF09C), one(0xF1FF), "IdBW", mfloat | cfloat },
2543 {"fbngl", 2, one(0xF099), one(0xF1FF), "IdBW", mfloat | cfloat },
2544 {"fbngle", 2, one(0xF098), one(0xF1FF), "IdBW", mfloat | cfloat },
2545 {"fbngt", 2, one(0xF09D), one(0xF1FF), "IdBW", mfloat | cfloat },
2546 {"fbnle", 2, one(0xF09A), one(0xF1FF), "IdBW", mfloat | cfloat },
2547 {"fbnlt", 2, one(0xF09B), one(0xF1FF), "IdBW", mfloat | cfloat },
2548 {"fboge", 2, one(0xF083), one(0xF1FF), "IdBW", mfloat | cfloat },
2549 {"fbogl", 2, one(0xF086), one(0xF1FF), "IdBW", mfloat | cfloat },
2550 {"fbogt", 2, one(0xF082), one(0xF1FF), "IdBW", mfloat | cfloat },
2551 {"fbole", 2, one(0xF085), one(0xF1FF), "IdBW", mfloat | cfloat },
2552 {"fbolt", 2, one(0xF084), one(0xF1FF), "IdBW", mfloat | cfloat },
2553 {"fbor", 2, one(0xF087), one(0xF1FF), "IdBW", mfloat | cfloat },
2554 {"fbseq", 2, one(0xF091), one(0xF1FF), "IdBW", mfloat | cfloat },
2555 {"fbsf", 2, one(0xF090), one(0xF1FF), "IdBW", mfloat | cfloat },
2556 {"fbsne", 2, one(0xF09E), one(0xF1FF), "IdBW", mfloat | cfloat },
2557 {"fbst", 2, one(0xF09F), one(0xF1FF), "IdBW", mfloat | cfloat },
2558 {"fbt", 2, one(0xF08F), one(0xF1FF), "IdBW", mfloat | cfloat },
2559 {"fbueq", 2, one(0xF089), one(0xF1FF), "IdBW", mfloat | cfloat },
2560 {"fbuge", 2, one(0xF08B), one(0xF1FF), "IdBW", mfloat | cfloat },
2561 {"fbugt", 2, one(0xF08A), one(0xF1FF), "IdBW", mfloat | cfloat },
2562 {"fbule", 2, one(0xF08D), one(0xF1FF), "IdBW", mfloat | cfloat },
2563 {"fbult", 2, one(0xF08C), one(0xF1FF), "IdBW", mfloat | cfloat },
2564 {"fbun", 2, one(0xF088), one(0xF1FF), "IdBW", mfloat | cfloat },
2565
2566 {"fbeql", 2, one(0xF0C1), one(0xF1FF), "IdBC", mfloat | cfloat },
2567 {"fbfl", 2, one(0xF0C0), one(0xF1FF), "IdBC", mfloat | cfloat },
2568 {"fbgel", 2, one(0xF0D3), one(0xF1FF), "IdBC", mfloat | cfloat },
2569 {"fbgll", 2, one(0xF0D6), one(0xF1FF), "IdBC", mfloat | cfloat },
2570 {"fbglel", 2, one(0xF0D7), one(0xF1FF), "IdBC", mfloat | cfloat },
2571 {"fbgtl", 2, one(0xF0D2), one(0xF1FF), "IdBC", mfloat | cfloat },
2572 {"fblel", 2, one(0xF0D5), one(0xF1FF), "IdBC", mfloat | cfloat },
2573 {"fbltl", 2, one(0xF0D4), one(0xF1FF), "IdBC", mfloat | cfloat },
2574 {"fbnel", 2, one(0xF0CE), one(0xF1FF), "IdBC", mfloat | cfloat },
2575 {"fbngel", 2, one(0xF0DC), one(0xF1FF), "IdBC", mfloat | cfloat },
2576 {"fbngll", 2, one(0xF0D9), one(0xF1FF), "IdBC", mfloat | cfloat },
2577 {"fbnglel", 2, one(0xF0D8), one(0xF1FF), "IdBC", mfloat | cfloat },
2578 {"fbngtl", 2, one(0xF0DD), one(0xF1FF), "IdBC", mfloat | cfloat },
2579 {"fbnlel", 2, one(0xF0DA), one(0xF1FF), "IdBC", mfloat | cfloat },
2580 {"fbnltl", 2, one(0xF0DB), one(0xF1FF), "IdBC", mfloat | cfloat },
2581 {"fbogel", 2, one(0xF0C3), one(0xF1FF), "IdBC", mfloat | cfloat },
2582 {"fbogll", 2, one(0xF0C6), one(0xF1FF), "IdBC", mfloat | cfloat },
2583 {"fbogtl", 2, one(0xF0C2), one(0xF1FF), "IdBC", mfloat | cfloat },
2584 {"fbolel", 2, one(0xF0C5), one(0xF1FF), "IdBC", mfloat | cfloat },
2585 {"fboltl", 2, one(0xF0C4), one(0xF1FF), "IdBC", mfloat | cfloat },
2586 {"fborl", 2, one(0xF0C7), one(0xF1FF), "IdBC", mfloat | cfloat },
2587 {"fbseql", 2, one(0xF0D1), one(0xF1FF), "IdBC", mfloat | cfloat },
2588 {"fbsfl", 2, one(0xF0D0), one(0xF1FF), "IdBC", mfloat | cfloat },
2589 {"fbsnel", 2, one(0xF0DE), one(0xF1FF), "IdBC", mfloat | cfloat },
2590 {"fbstl", 2, one(0xF0DF), one(0xF1FF), "IdBC", mfloat | cfloat },
2591 {"fbtl", 2, one(0xF0CF), one(0xF1FF), "IdBC", mfloat | cfloat },
2592 {"fbueql", 2, one(0xF0C9), one(0xF1FF), "IdBC", mfloat | cfloat },
2593 {"fbugel", 2, one(0xF0CB), one(0xF1FF), "IdBC", mfloat | cfloat },
2594 {"fbugtl", 2, one(0xF0CA), one(0xF1FF), "IdBC", mfloat | cfloat },
2595 {"fbulel", 2, one(0xF0CD), one(0xF1FF), "IdBC", mfloat | cfloat },
2596 {"fbultl", 2, one(0xF0CC), one(0xF1FF), "IdBC", mfloat | cfloat },
2597 {"fbunl", 2, one(0xF0C8), one(0xF1FF), "IdBC", mfloat | cfloat },
2598
2599 {"fjeq", 2, one(0xF081), one(0xF1BF), "IdBc", mfloat | cfloat },
2600 {"fjf", 2, one(0xF080), one(0xF1BF), "IdBc", mfloat | cfloat },
2601 {"fjge", 2, one(0xF093), one(0xF1BF), "IdBc", mfloat | cfloat },
2602 {"fjgl", 2, one(0xF096), one(0xF1BF), "IdBc", mfloat | cfloat },
2603 {"fjgle", 2, one(0xF097), one(0xF1BF), "IdBc", mfloat | cfloat },
2604 {"fjgt", 2, one(0xF092), one(0xF1BF), "IdBc", mfloat | cfloat },
2605 {"fjle", 2, one(0xF095), one(0xF1BF), "IdBc", mfloat | cfloat },
2606 {"fjlt", 2, one(0xF094), one(0xF1BF), "IdBc", mfloat | cfloat },
2607 {"fjne", 2, one(0xF08E), one(0xF1BF), "IdBc", mfloat | cfloat },
2608 {"fjnge", 2, one(0xF09C), one(0xF1BF), "IdBc", mfloat | cfloat },
2609 {"fjngl", 2, one(0xF099), one(0xF1BF), "IdBc", mfloat | cfloat },
2610 {"fjngle", 2, one(0xF098), one(0xF1BF), "IdBc", mfloat | cfloat },
2611 {"fjngt", 2, one(0xF09D), one(0xF1BF), "IdBc", mfloat | cfloat },
2612 {"fjnle", 2, one(0xF09A), one(0xF1BF), "IdBc", mfloat | cfloat },
2613 {"fjnlt", 2, one(0xF09B), one(0xF1BF), "IdBc", mfloat | cfloat },
2614 {"fjoge", 2, one(0xF083), one(0xF1BF), "IdBc", mfloat | cfloat },
2615 {"fjogl", 2, one(0xF086), one(0xF1BF), "IdBc", mfloat | cfloat },
2616 {"fjogt", 2, one(0xF082), one(0xF1BF), "IdBc", mfloat | cfloat },
2617 {"fjole", 2, one(0xF085), one(0xF1BF), "IdBc", mfloat | cfloat },
2618 {"fjolt", 2, one(0xF084), one(0xF1BF), "IdBc", mfloat | cfloat },
2619 {"fjor", 2, one(0xF087), one(0xF1BF), "IdBc", mfloat | cfloat },
2620 {"fjseq", 2, one(0xF091), one(0xF1BF), "IdBc", mfloat | cfloat },
2621 {"fjsf", 2, one(0xF090), one(0xF1BF), "IdBc", mfloat | cfloat },
2622 {"fjsne", 2, one(0xF09E), one(0xF1BF), "IdBc", mfloat | cfloat },
2623 {"fjst", 2, one(0xF09F), one(0xF1BF), "IdBc", mfloat | cfloat },
2624 {"fjt", 2, one(0xF08F), one(0xF1BF), "IdBc", mfloat | cfloat },
2625 {"fjueq", 2, one(0xF089), one(0xF1BF), "IdBc", mfloat | cfloat },
2626 {"fjuge", 2, one(0xF08B), one(0xF1BF), "IdBc", mfloat | cfloat },
2627 {"fjugt", 2, one(0xF08A), one(0xF1BF), "IdBc", mfloat | cfloat },
2628 {"fjule", 2, one(0xF08D), one(0xF1BF), "IdBc", mfloat | cfloat },
2629 {"fjult", 2, one(0xF08C), one(0xF1BF), "IdBc", mfloat | cfloat },
2630 {"fjun", 2, one(0xF088), one(0xF1BF), "IdBc", mfloat | cfloat },
2631
2632 {"fcmpb", 4, two(0xF000, 0x5838), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2633 {"fcmpb", 4, two(0xF000, 0x5838), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
2634 {"fcmpd", 4, two(0xF000, 0x5438), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
2635 {"fcmpd", 4, two(0xF000, 0x5438), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat },
2636 {"fcmpd", 4, two(0xF000, 0x0038), two(0xF1C0, 0xE07F), "IiF8F7", cfloat },
2637 {"fcmpl", 4, two(0xF000, 0x4038), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat },
2638 {"fcmpl", 4, two(0xF000, 0x4038), two(0xF1C0, 0xFC7F), "IibsF7", cfloat },
2639 {"fcmpp", 4, two(0xF000, 0x4C38), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat },
2640 {"fcmps", 4, two(0xF000, 0x4438),