Merge remote-tracking branch 'remotes/stefanha-gitlab/tags/block-pull-request' into...
[qemu.git] / softmmu / memory.c
1 /*
2 * Physical memory management
3 *
4 * Copyright 2011 Red Hat, Inc. and/or its affiliates
5 *
6 * Authors:
7 * Avi Kivity <avi@redhat.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
11 *
12 * Contributions after 2012-01-13 are licensed under the terms of the
13 * GNU GPL, version 2 or (at your option) any later version.
14 */
15
16 #include "qemu/osdep.h"
17 #include "qemu/log.h"
18 #include "qapi/error.h"
19 #include "cpu.h"
20 #include "exec/memory.h"
21 #include "exec/address-spaces.h"
22 #include "qapi/visitor.h"
23 #include "qemu/bitops.h"
24 #include "qemu/error-report.h"
25 #include "qemu/main-loop.h"
26 #include "qemu/qemu-print.h"
27 #include "qom/object.h"
28 #include "trace.h"
29
30 #include "exec/memory-internal.h"
31 #include "exec/ram_addr.h"
32 #include "sysemu/kvm.h"
33 #include "sysemu/runstate.h"
34 #include "sysemu/tcg.h"
35 #include "sysemu/accel.h"
36 #include "hw/boards.h"
37 #include "migration/vmstate.h"
38
39 //#define DEBUG_UNASSIGNED
40
41 static unsigned memory_region_transaction_depth;
42 static bool memory_region_update_pending;
43 static bool ioeventfd_update_pending;
44 bool global_dirty_log;
45
46 static QTAILQ_HEAD(, MemoryListener) memory_listeners
47 = QTAILQ_HEAD_INITIALIZER(memory_listeners);
48
49 static QTAILQ_HEAD(, AddressSpace) address_spaces
50 = QTAILQ_HEAD_INITIALIZER(address_spaces);
51
52 static GHashTable *flat_views;
53
54 typedef struct AddrRange AddrRange;
55
56 /*
57 * Note that signed integers are needed for negative offsetting in aliases
58 * (large MemoryRegion::alias_offset).
59 */
60 struct AddrRange {
61 Int128 start;
62 Int128 size;
63 };
64
65 static AddrRange addrrange_make(Int128 start, Int128 size)
66 {
67 return (AddrRange) { start, size };
68 }
69
70 static bool addrrange_equal(AddrRange r1, AddrRange r2)
71 {
72 return int128_eq(r1.start, r2.start) && int128_eq(r1.size, r2.size);
73 }
74
75 static Int128 addrrange_end(AddrRange r)
76 {
77 return int128_add(r.start, r.size);
78 }
79
80 static AddrRange addrrange_shift(AddrRange range, Int128 delta)
81 {
82 int128_addto(&range.start, delta);
83 return range;
84 }
85
86 static bool addrrange_contains(AddrRange range, Int128 addr)
87 {
88 return int128_ge(addr, range.start)
89 && int128_lt(addr, addrrange_end(range));
90 }
91
92 static bool addrrange_intersects(AddrRange r1, AddrRange r2)
93 {
94 return addrrange_contains(r1, r2.start)
95 || addrrange_contains(r2, r1.start);
96 }
97
98 static AddrRange addrrange_intersection(AddrRange r1, AddrRange r2)
99 {
100 Int128 start = int128_max(r1.start, r2.start);
101 Int128 end = int128_min(addrrange_end(r1), addrrange_end(r2));
102 return addrrange_make(start, int128_sub(end, start));
103 }
104
105 enum ListenerDirection { Forward, Reverse };
106
107 #define MEMORY_LISTENER_CALL_GLOBAL(_callback, _direction, _args...) \
108 do { \
109 MemoryListener *_listener; \
110 \
111 switch (_direction) { \
112 case Forward: \
113 QTAILQ_FOREACH(_listener, &memory_listeners, link) { \
114 if (_listener->_callback) { \
115 _listener->_callback(_listener, ##_args); \
116 } \
117 } \
118 break; \
119 case Reverse: \
120 QTAILQ_FOREACH_REVERSE(_listener, &memory_listeners, link) { \
121 if (_listener->_callback) { \
122 _listener->_callback(_listener, ##_args); \
123 } \
124 } \
125 break; \
126 default: \
127 abort(); \
128 } \
129 } while (0)
130
131 #define MEMORY_LISTENER_CALL(_as, _callback, _direction, _section, _args...) \
132 do { \
133 MemoryListener *_listener; \
134 \
135 switch (_direction) { \
136 case Forward: \
137 QTAILQ_FOREACH(_listener, &(_as)->listeners, link_as) { \
138 if (_listener->_callback) { \
139 _listener->_callback(_listener, _section, ##_args); \
140 } \
141 } \
142 break; \
143 case Reverse: \
144 QTAILQ_FOREACH_REVERSE(_listener, &(_as)->listeners, link_as) { \
145 if (_listener->_callback) { \
146 _listener->_callback(_listener, _section, ##_args); \
147 } \
148 } \
149 break; \
150 default: \
151 abort(); \
152 } \
153 } while (0)
154
155 /* No need to ref/unref .mr, the FlatRange keeps it alive. */
156 #define MEMORY_LISTENER_UPDATE_REGION(fr, as, dir, callback, _args...) \
157 do { \
158 MemoryRegionSection mrs = section_from_flat_range(fr, \
159 address_space_to_flatview(as)); \
160 MEMORY_LISTENER_CALL(as, callback, dir, &mrs, ##_args); \
161 } while(0)
162
163 struct CoalescedMemoryRange {
164 AddrRange addr;
165 QTAILQ_ENTRY(CoalescedMemoryRange) link;
166 };
167
168 struct MemoryRegionIoeventfd {
169 AddrRange addr;
170 bool match_data;
171 uint64_t data;
172 EventNotifier *e;
173 };
174
175 static bool memory_region_ioeventfd_before(MemoryRegionIoeventfd *a,
176 MemoryRegionIoeventfd *b)
177 {
178 if (int128_lt(a->addr.start, b->addr.start)) {
179 return true;
180 } else if (int128_gt(a->addr.start, b->addr.start)) {
181 return false;
182 } else if (int128_lt(a->addr.size, b->addr.size)) {
183 return true;
184 } else if (int128_gt(a->addr.size, b->addr.size)) {
185 return false;
186 } else if (a->match_data < b->match_data) {
187 return true;
188 } else if (a->match_data > b->match_data) {
189 return false;
190 } else if (a->match_data) {
191 if (a->data < b->data) {
192 return true;
193 } else if (a->data > b->data) {
194 return false;
195 }
196 }
197 if (a->e < b->e) {
198 return true;
199 } else if (a->e > b->e) {
200 return false;
201 }
202 return false;
203 }
204
205 static bool memory_region_ioeventfd_equal(MemoryRegionIoeventfd *a,
206 MemoryRegionIoeventfd *b)
207 {
208 if (int128_eq(a->addr.start, b->addr.start) &&
209 (!int128_nz(a->addr.size) || !int128_nz(b->addr.size) ||
210 (int128_eq(a->addr.size, b->addr.size) &&
211 (a->match_data == b->match_data) &&
212 ((a->match_data && (a->data == b->data)) || !a->match_data) &&
213 (a->e == b->e))))
214 return true;
215
216 return false;
217 }
218
219 /* Range of memory in the global map. Addresses are absolute. */
220 struct FlatRange {
221 MemoryRegion *mr;
222 hwaddr offset_in_region;
223 AddrRange addr;
224 uint8_t dirty_log_mask;
225 bool romd_mode;
226 bool readonly;
227 bool nonvolatile;
228 };
229
230 #define FOR_EACH_FLAT_RANGE(var, view) \
231 for (var = (view)->ranges; var < (view)->ranges + (view)->nr; ++var)
232
233 static inline MemoryRegionSection
234 section_from_flat_range(FlatRange *fr, FlatView *fv)
235 {
236 return (MemoryRegionSection) {
237 .mr = fr->mr,
238 .fv = fv,
239 .offset_within_region = fr->offset_in_region,
240 .size = fr->addr.size,
241 .offset_within_address_space = int128_get64(fr->addr.start),
242 .readonly = fr->readonly,
243 .nonvolatile = fr->nonvolatile,
244 };
245 }
246
247 static bool flatrange_equal(FlatRange *a, FlatRange *b)
248 {
249 return a->mr == b->mr
250 && addrrange_equal(a->addr, b->addr)
251 && a->offset_in_region == b->offset_in_region
252 && a->romd_mode == b->romd_mode
253 && a->readonly == b->readonly
254 && a->nonvolatile == b->nonvolatile;
255 }
256
257 static FlatView *flatview_new(MemoryRegion *mr_root)
258 {
259 FlatView *view;
260
261 view = g_new0(FlatView, 1);
262 view->ref = 1;
263 view->root = mr_root;
264 memory_region_ref(mr_root);
265 trace_flatview_new(view, mr_root);
266
267 return view;
268 }
269
270 /* Insert a range into a given position. Caller is responsible for maintaining
271 * sorting order.
272 */
273 static void flatview_insert(FlatView *view, unsigned pos, FlatRange *range)
274 {
275 if (view->nr == view->nr_allocated) {
276 view->nr_allocated = MAX(2 * view->nr, 10);
277 view->ranges = g_realloc(view->ranges,
278 view->nr_allocated * sizeof(*view->ranges));
279 }
280 memmove(view->ranges + pos + 1, view->ranges + pos,
281 (view->nr - pos) * sizeof(FlatRange));
282 view->ranges[pos] = *range;
283 memory_region_ref(range->mr);
284 ++view->nr;
285 }
286
287 static void flatview_destroy(FlatView *view)
288 {
289 int i;
290
291 trace_flatview_destroy(view, view->root);
292 if (view->dispatch) {
293 address_space_dispatch_free(view->dispatch);
294 }
295 for (i = 0; i < view->nr; i++) {
296 memory_region_unref(view->ranges[i].mr);
297 }
298 g_free(view->ranges);
299 memory_region_unref(view->root);
300 g_free(view);
301 }
302
303 static bool flatview_ref(FlatView *view)
304 {
305 return qatomic_fetch_inc_nonzero(&view->ref) > 0;
306 }
307
308 void flatview_unref(FlatView *view)
309 {
310 if (qatomic_fetch_dec(&view->ref) == 1) {
311 trace_flatview_destroy_rcu(view, view->root);
312 assert(view->root);
313 call_rcu(view, flatview_destroy, rcu);
314 }
315 }
316
317 static bool can_merge(FlatRange *r1, FlatRange *r2)
318 {
319 return int128_eq(addrrange_end(r1->addr), r2->addr.start)
320 && r1->mr == r2->mr
321 && int128_eq(int128_add(int128_make64(r1->offset_in_region),
322 r1->addr.size),
323 int128_make64(r2->offset_in_region))
324 && r1->dirty_log_mask == r2->dirty_log_mask
325 && r1->romd_mode == r2->romd_mode
326 && r1->readonly == r2->readonly
327 && r1->nonvolatile == r2->nonvolatile;
328 }
329
330 /* Attempt to simplify a view by merging adjacent ranges */
331 static void flatview_simplify(FlatView *view)
332 {
333 unsigned i, j, k;
334
335 i = 0;
336 while (i < view->nr) {
337 j = i + 1;
338 while (j < view->nr
339 && can_merge(&view->ranges[j-1], &view->ranges[j])) {
340 int128_addto(&view->ranges[i].addr.size, view->ranges[j].addr.size);
341 ++j;
342 }
343 ++i;
344 for (k = i; k < j; k++) {
345 memory_region_unref(view->ranges[k].mr);
346 }
347 memmove(&view->ranges[i], &view->ranges[j],
348 (view->nr - j) * sizeof(view->ranges[j]));
349 view->nr -= j - i;
350 }
351 }
352
353 static bool memory_region_big_endian(MemoryRegion *mr)
354 {
355 #ifdef TARGET_WORDS_BIGENDIAN
356 return mr->ops->endianness != DEVICE_LITTLE_ENDIAN;
357 #else
358 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
359 #endif
360 }
361
362 static void adjust_endianness(MemoryRegion *mr, uint64_t *data, MemOp op)
363 {
364 if ((op & MO_BSWAP) != devend_memop(mr->ops->endianness)) {
365 switch (op & MO_SIZE) {
366 case MO_8:
367 break;
368 case MO_16:
369 *data = bswap16(*data);
370 break;
371 case MO_32:
372 *data = bswap32(*data);
373 break;
374 case MO_64:
375 *data = bswap64(*data);
376 break;
377 default:
378 g_assert_not_reached();
379 }
380 }
381 }
382
383 static inline void memory_region_shift_read_access(uint64_t *value,
384 signed shift,
385 uint64_t mask,
386 uint64_t tmp)
387 {
388 if (shift >= 0) {
389 *value |= (tmp & mask) << shift;
390 } else {
391 *value |= (tmp & mask) >> -shift;
392 }
393 }
394
395 static inline uint64_t memory_region_shift_write_access(uint64_t *value,
396 signed shift,
397 uint64_t mask)
398 {
399 uint64_t tmp;
400
401 if (shift >= 0) {
402 tmp = (*value >> shift) & mask;
403 } else {
404 tmp = (*value << -shift) & mask;
405 }
406
407 return tmp;
408 }
409
410 static hwaddr memory_region_to_absolute_addr(MemoryRegion *mr, hwaddr offset)
411 {
412 MemoryRegion *root;
413 hwaddr abs_addr = offset;
414
415 abs_addr += mr->addr;
416 for (root = mr; root->container; ) {
417 root = root->container;
418 abs_addr += root->addr;
419 }
420
421 return abs_addr;
422 }
423
424 static int get_cpu_index(void)
425 {
426 if (current_cpu) {
427 return current_cpu->cpu_index;
428 }
429 return -1;
430 }
431
432 static MemTxResult memory_region_read_accessor(MemoryRegion *mr,
433 hwaddr addr,
434 uint64_t *value,
435 unsigned size,
436 signed shift,
437 uint64_t mask,
438 MemTxAttrs attrs)
439 {
440 uint64_t tmp;
441
442 tmp = mr->ops->read(mr->opaque, addr, size);
443 if (mr->subpage) {
444 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
445 } else if (trace_event_get_state_backends(TRACE_MEMORY_REGION_OPS_READ)) {
446 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
447 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
448 }
449 memory_region_shift_read_access(value, shift, mask, tmp);
450 return MEMTX_OK;
451 }
452
453 static MemTxResult memory_region_read_with_attrs_accessor(MemoryRegion *mr,
454 hwaddr addr,
455 uint64_t *value,
456 unsigned size,
457 signed shift,
458 uint64_t mask,
459 MemTxAttrs attrs)
460 {
461 uint64_t tmp = 0;
462 MemTxResult r;
463
464 r = mr->ops->read_with_attrs(mr->opaque, addr, &tmp, size, attrs);
465 if (mr->subpage) {
466 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
467 } else if (trace_event_get_state_backends(TRACE_MEMORY_REGION_OPS_READ)) {
468 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
469 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
470 }
471 memory_region_shift_read_access(value, shift, mask, tmp);
472 return r;
473 }
474
475 static MemTxResult memory_region_write_accessor(MemoryRegion *mr,
476 hwaddr addr,
477 uint64_t *value,
478 unsigned size,
479 signed shift,
480 uint64_t mask,
481 MemTxAttrs attrs)
482 {
483 uint64_t tmp = memory_region_shift_write_access(value, shift, mask);
484
485 if (mr->subpage) {
486 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
487 } else if (trace_event_get_state_backends(TRACE_MEMORY_REGION_OPS_WRITE)) {
488 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
489 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
490 }
491 mr->ops->write(mr->opaque, addr, tmp, size);
492 return MEMTX_OK;
493 }
494
495 static MemTxResult memory_region_write_with_attrs_accessor(MemoryRegion *mr,
496 hwaddr addr,
497 uint64_t *value,
498 unsigned size,
499 signed shift,
500 uint64_t mask,
501 MemTxAttrs attrs)
502 {
503 uint64_t tmp = memory_region_shift_write_access(value, shift, mask);
504
505 if (mr->subpage) {
506 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
507 } else if (trace_event_get_state_backends(TRACE_MEMORY_REGION_OPS_WRITE)) {
508 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
509 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
510 }
511 return mr->ops->write_with_attrs(mr->opaque, addr, tmp, size, attrs);
512 }
513
514 static MemTxResult access_with_adjusted_size(hwaddr addr,
515 uint64_t *value,
516 unsigned size,
517 unsigned access_size_min,
518 unsigned access_size_max,
519 MemTxResult (*access_fn)
520 (MemoryRegion *mr,
521 hwaddr addr,
522 uint64_t *value,
523 unsigned size,
524 signed shift,
525 uint64_t mask,
526 MemTxAttrs attrs),
527 MemoryRegion *mr,
528 MemTxAttrs attrs)
529 {
530 uint64_t access_mask;
531 unsigned access_size;
532 unsigned i;
533 MemTxResult r = MEMTX_OK;
534
535 if (!access_size_min) {
536 access_size_min = 1;
537 }
538 if (!access_size_max) {
539 access_size_max = 4;
540 }
541
542 /* FIXME: support unaligned access? */
543 access_size = MAX(MIN(size, access_size_max), access_size_min);
544 access_mask = MAKE_64BIT_MASK(0, access_size * 8);
545 if (memory_region_big_endian(mr)) {
546 for (i = 0; i < size; i += access_size) {
547 r |= access_fn(mr, addr + i, value, access_size,
548 (size - access_size - i) * 8, access_mask, attrs);
549 }
550 } else {
551 for (i = 0; i < size; i += access_size) {
552 r |= access_fn(mr, addr + i, value, access_size, i * 8,
553 access_mask, attrs);
554 }
555 }
556 return r;
557 }
558
559 static AddressSpace *memory_region_to_address_space(MemoryRegion *mr)
560 {
561 AddressSpace *as;
562
563 while (mr->container) {
564 mr = mr->container;
565 }
566 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
567 if (mr == as->root) {
568 return as;
569 }
570 }
571 return NULL;
572 }
573
574 /* Render a memory region into the global view. Ranges in @view obscure
575 * ranges in @mr.
576 */
577 static void render_memory_region(FlatView *view,
578 MemoryRegion *mr,
579 Int128 base,
580 AddrRange clip,
581 bool readonly,
582 bool nonvolatile)
583 {
584 MemoryRegion *subregion;
585 unsigned i;
586 hwaddr offset_in_region;
587 Int128 remain;
588 Int128 now;
589 FlatRange fr;
590 AddrRange tmp;
591
592 if (!mr->enabled) {
593 return;
594 }
595
596 int128_addto(&base, int128_make64(mr->addr));
597 readonly |= mr->readonly;
598 nonvolatile |= mr->nonvolatile;
599
600 tmp = addrrange_make(base, mr->size);
601
602 if (!addrrange_intersects(tmp, clip)) {
603 return;
604 }
605
606 clip = addrrange_intersection(tmp, clip);
607
608 if (mr->alias) {
609 int128_subfrom(&base, int128_make64(mr->alias->addr));
610 int128_subfrom(&base, int128_make64(mr->alias_offset));
611 render_memory_region(view, mr->alias, base, clip,
612 readonly, nonvolatile);
613 return;
614 }
615
616 /* Render subregions in priority order. */
617 QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) {
618 render_memory_region(view, subregion, base, clip,
619 readonly, nonvolatile);
620 }
621
622 if (!mr->terminates) {
623 return;
624 }
625
626 offset_in_region = int128_get64(int128_sub(clip.start, base));
627 base = clip.start;
628 remain = clip.size;
629
630 fr.mr = mr;
631 fr.dirty_log_mask = memory_region_get_dirty_log_mask(mr);
632 fr.romd_mode = mr->romd_mode;
633 fr.readonly = readonly;
634 fr.nonvolatile = nonvolatile;
635
636 /* Render the region itself into any gaps left by the current view. */
637 for (i = 0; i < view->nr && int128_nz(remain); ++i) {
638 if (int128_ge(base, addrrange_end(view->ranges[i].addr))) {
639 continue;
640 }
641 if (int128_lt(base, view->ranges[i].addr.start)) {
642 now = int128_min(remain,
643 int128_sub(view->ranges[i].addr.start, base));
644 fr.offset_in_region = offset_in_region;
645 fr.addr = addrrange_make(base, now);
646 flatview_insert(view, i, &fr);
647 ++i;
648 int128_addto(&base, now);
649 offset_in_region += int128_get64(now);
650 int128_subfrom(&remain, now);
651 }
652 now = int128_sub(int128_min(int128_add(base, remain),
653 addrrange_end(view->ranges[i].addr)),
654 base);
655 int128_addto(&base, now);
656 offset_in_region += int128_get64(now);
657 int128_subfrom(&remain, now);
658 }
659 if (int128_nz(remain)) {
660 fr.offset_in_region = offset_in_region;
661 fr.addr = addrrange_make(base, remain);
662 flatview_insert(view, i, &fr);
663 }
664 }
665
666 void flatview_for_each_range(FlatView *fv, flatview_cb cb , void *opaque)
667 {
668 FlatRange *fr;
669
670 assert(fv);
671 assert(cb);
672
673 FOR_EACH_FLAT_RANGE(fr, fv) {
674 if (cb(fr->addr.start, fr->addr.size, fr->mr, opaque))
675 break;
676 }
677 }
678
679 static MemoryRegion *memory_region_get_flatview_root(MemoryRegion *mr)
680 {
681 while (mr->enabled) {
682 if (mr->alias) {
683 if (!mr->alias_offset && int128_ge(mr->size, mr->alias->size)) {
684 /* The alias is included in its entirety. Use it as
685 * the "real" root, so that we can share more FlatViews.
686 */
687 mr = mr->alias;
688 continue;
689 }
690 } else if (!mr->terminates) {
691 unsigned int found = 0;
692 MemoryRegion *child, *next = NULL;
693 QTAILQ_FOREACH(child, &mr->subregions, subregions_link) {
694 if (child->enabled) {
695 if (++found > 1) {
696 next = NULL;
697 break;
698 }
699 if (!child->addr && int128_ge(mr->size, child->size)) {
700 /* A child is included in its entirety. If it's the only
701 * enabled one, use it in the hope of finding an alias down the
702 * way. This will also let us share FlatViews.
703 */
704 next = child;
705 }
706 }
707 }
708 if (found == 0) {
709 return NULL;
710 }
711 if (next) {
712 mr = next;
713 continue;
714 }
715 }
716
717 return mr;
718 }
719
720 return NULL;
721 }
722
723 /* Render a memory topology into a list of disjoint absolute ranges. */
724 static FlatView *generate_memory_topology(MemoryRegion *mr)
725 {
726 int i;
727 FlatView *view;
728
729 view = flatview_new(mr);
730
731 if (mr) {
732 render_memory_region(view, mr, int128_zero(),
733 addrrange_make(int128_zero(), int128_2_64()),
734 false, false);
735 }
736 flatview_simplify(view);
737
738 view->dispatch = address_space_dispatch_new(view);
739 for (i = 0; i < view->nr; i++) {
740 MemoryRegionSection mrs =
741 section_from_flat_range(&view->ranges[i], view);
742 flatview_add_to_dispatch(view, &mrs);
743 }
744 address_space_dispatch_compact(view->dispatch);
745 g_hash_table_replace(flat_views, mr, view);
746
747 return view;
748 }
749
750 static void address_space_add_del_ioeventfds(AddressSpace *as,
751 MemoryRegionIoeventfd *fds_new,
752 unsigned fds_new_nb,
753 MemoryRegionIoeventfd *fds_old,
754 unsigned fds_old_nb)
755 {
756 unsigned iold, inew;
757 MemoryRegionIoeventfd *fd;
758 MemoryRegionSection section;
759
760 /* Generate a symmetric difference of the old and new fd sets, adding
761 * and deleting as necessary.
762 */
763
764 iold = inew = 0;
765 while (iold < fds_old_nb || inew < fds_new_nb) {
766 if (iold < fds_old_nb
767 && (inew == fds_new_nb
768 || memory_region_ioeventfd_before(&fds_old[iold],
769 &fds_new[inew]))) {
770 fd = &fds_old[iold];
771 section = (MemoryRegionSection) {
772 .fv = address_space_to_flatview(as),
773 .offset_within_address_space = int128_get64(fd->addr.start),
774 .size = fd->addr.size,
775 };
776 MEMORY_LISTENER_CALL(as, eventfd_del, Forward, &section,
777 fd->match_data, fd->data, fd->e);
778 ++iold;
779 } else if (inew < fds_new_nb
780 && (iold == fds_old_nb
781 || memory_region_ioeventfd_before(&fds_new[inew],
782 &fds_old[iold]))) {
783 fd = &fds_new[inew];
784 section = (MemoryRegionSection) {
785 .fv = address_space_to_flatview(as),
786 .offset_within_address_space = int128_get64(fd->addr.start),
787 .size = fd->addr.size,
788 };
789 MEMORY_LISTENER_CALL(as, eventfd_add, Reverse, &section,
790 fd->match_data, fd->data, fd->e);
791 ++inew;
792 } else {
793 ++iold;
794 ++inew;
795 }
796 }
797 }
798
799 FlatView *address_space_get_flatview(AddressSpace *as)
800 {
801 FlatView *view;
802
803 RCU_READ_LOCK_GUARD();
804 do {
805 view = address_space_to_flatview(as);
806 /* If somebody has replaced as->current_map concurrently,
807 * flatview_ref returns false.
808 */
809 } while (!flatview_ref(view));
810 return view;
811 }
812
813 static void address_space_update_ioeventfds(AddressSpace *as)
814 {
815 FlatView *view;
816 FlatRange *fr;
817 unsigned ioeventfd_nb = 0;
818 unsigned ioeventfd_max;
819 MemoryRegionIoeventfd *ioeventfds;
820 AddrRange tmp;
821 unsigned i;
822
823 /*
824 * It is likely that the number of ioeventfds hasn't changed much, so use
825 * the previous size as the starting value, with some headroom to avoid
826 * gratuitous reallocations.
827 */
828 ioeventfd_max = QEMU_ALIGN_UP(as->ioeventfd_nb, 4);
829 ioeventfds = g_new(MemoryRegionIoeventfd, ioeventfd_max);
830
831 view = address_space_get_flatview(as);
832 FOR_EACH_FLAT_RANGE(fr, view) {
833 for (i = 0; i < fr->mr->ioeventfd_nb; ++i) {
834 tmp = addrrange_shift(fr->mr->ioeventfds[i].addr,
835 int128_sub(fr->addr.start,
836 int128_make64(fr->offset_in_region)));
837 if (addrrange_intersects(fr->addr, tmp)) {
838 ++ioeventfd_nb;
839 if (ioeventfd_nb > ioeventfd_max) {
840 ioeventfd_max = MAX(ioeventfd_max * 2, 4);
841 ioeventfds = g_realloc(ioeventfds,
842 ioeventfd_max * sizeof(*ioeventfds));
843 }
844 ioeventfds[ioeventfd_nb-1] = fr->mr->ioeventfds[i];
845 ioeventfds[ioeventfd_nb-1].addr = tmp;
846 }
847 }
848 }
849
850 address_space_add_del_ioeventfds(as, ioeventfds, ioeventfd_nb,
851 as->ioeventfds, as->ioeventfd_nb);
852
853 g_free(as->ioeventfds);
854 as->ioeventfds = ioeventfds;
855 as->ioeventfd_nb = ioeventfd_nb;
856 flatview_unref(view);
857 }
858
859 /*
860 * Notify the memory listeners about the coalesced IO change events of
861 * range `cmr'. Only the part that has intersection of the specified
862 * FlatRange will be sent.
863 */
864 static void flat_range_coalesced_io_notify(FlatRange *fr, AddressSpace *as,
865 CoalescedMemoryRange *cmr, bool add)
866 {
867 AddrRange tmp;
868
869 tmp = addrrange_shift(cmr->addr,
870 int128_sub(fr->addr.start,
871 int128_make64(fr->offset_in_region)));
872 if (!addrrange_intersects(tmp, fr->addr)) {
873 return;
874 }
875 tmp = addrrange_intersection(tmp, fr->addr);
876
877 if (add) {
878 MEMORY_LISTENER_UPDATE_REGION(fr, as, Forward, coalesced_io_add,
879 int128_get64(tmp.start),
880 int128_get64(tmp.size));
881 } else {
882 MEMORY_LISTENER_UPDATE_REGION(fr, as, Reverse, coalesced_io_del,
883 int128_get64(tmp.start),
884 int128_get64(tmp.size));
885 }
886 }
887
888 static void flat_range_coalesced_io_del(FlatRange *fr, AddressSpace *as)
889 {
890 CoalescedMemoryRange *cmr;
891
892 QTAILQ_FOREACH(cmr, &fr->mr->coalesced, link) {
893 flat_range_coalesced_io_notify(fr, as, cmr, false);
894 }
895 }
896
897 static void flat_range_coalesced_io_add(FlatRange *fr, AddressSpace *as)
898 {
899 MemoryRegion *mr = fr->mr;
900 CoalescedMemoryRange *cmr;
901
902 if (QTAILQ_EMPTY(&mr->coalesced)) {
903 return;
904 }
905
906 QTAILQ_FOREACH(cmr, &mr->coalesced, link) {
907 flat_range_coalesced_io_notify(fr, as, cmr, true);
908 }
909 }
910
911 static void address_space_update_topology_pass(AddressSpace *as,
912 const FlatView *old_view,
913 const FlatView *new_view,
914 bool adding)
915 {
916 unsigned iold, inew;
917 FlatRange *frold, *frnew;
918
919 /* Generate a symmetric difference of the old and new memory maps.
920 * Kill ranges in the old map, and instantiate ranges in the new map.
921 */
922 iold = inew = 0;
923 while (iold < old_view->nr || inew < new_view->nr) {
924 if (iold < old_view->nr) {
925 frold = &old_view->ranges[iold];
926 } else {
927 frold = NULL;
928 }
929 if (inew < new_view->nr) {
930 frnew = &new_view->ranges[inew];
931 } else {
932 frnew = NULL;
933 }
934
935 if (frold
936 && (!frnew
937 || int128_lt(frold->addr.start, frnew->addr.start)
938 || (int128_eq(frold->addr.start, frnew->addr.start)
939 && !flatrange_equal(frold, frnew)))) {
940 /* In old but not in new, or in both but attributes changed. */
941
942 if (!adding) {
943 flat_range_coalesced_io_del(frold, as);
944 MEMORY_LISTENER_UPDATE_REGION(frold, as, Reverse, region_del);
945 }
946
947 ++iold;
948 } else if (frold && frnew && flatrange_equal(frold, frnew)) {
949 /* In both and unchanged (except logging may have changed) */
950
951 if (adding) {
952 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_nop);
953 if (frnew->dirty_log_mask & ~frold->dirty_log_mask) {
954 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, log_start,
955 frold->dirty_log_mask,
956 frnew->dirty_log_mask);
957 }
958 if (frold->dirty_log_mask & ~frnew->dirty_log_mask) {
959 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Reverse, log_stop,
960 frold->dirty_log_mask,
961 frnew->dirty_log_mask);
962 }
963 }
964
965 ++iold;
966 ++inew;
967 } else {
968 /* In new */
969
970 if (adding) {
971 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_add);
972 flat_range_coalesced_io_add(frnew, as);
973 }
974
975 ++inew;
976 }
977 }
978 }
979
980 static void flatviews_init(void)
981 {
982 static FlatView *empty_view;
983
984 if (flat_views) {
985 return;
986 }
987
988 flat_views = g_hash_table_new_full(g_direct_hash, g_direct_equal, NULL,
989 (GDestroyNotify) flatview_unref);
990 if (!empty_view) {
991 empty_view = generate_memory_topology(NULL);
992 /* We keep it alive forever in the global variable. */
993 flatview_ref(empty_view);
994 } else {
995 g_hash_table_replace(flat_views, NULL, empty_view);
996 flatview_ref(empty_view);
997 }
998 }
999
1000 static void flatviews_reset(void)
1001 {
1002 AddressSpace *as;
1003
1004 if (flat_views) {
1005 g_hash_table_unref(flat_views);
1006 flat_views = NULL;
1007 }
1008 flatviews_init();
1009
1010 /* Render unique FVs */
1011 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1012 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1013
1014 if (g_hash_table_lookup(flat_views, physmr)) {
1015 continue;
1016 }
1017
1018 generate_memory_topology(physmr);
1019 }
1020 }
1021
1022 static void address_space_set_flatview(AddressSpace *as)
1023 {
1024 FlatView *old_view = address_space_to_flatview(as);
1025 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1026 FlatView *new_view = g_hash_table_lookup(flat_views, physmr);
1027
1028 assert(new_view);
1029
1030 if (old_view == new_view) {
1031 return;
1032 }
1033
1034 if (old_view) {
1035 flatview_ref(old_view);
1036 }
1037
1038 flatview_ref(new_view);
1039
1040 if (!QTAILQ_EMPTY(&as->listeners)) {
1041 FlatView tmpview = { .nr = 0 }, *old_view2 = old_view;
1042
1043 if (!old_view2) {
1044 old_view2 = &tmpview;
1045 }
1046 address_space_update_topology_pass(as, old_view2, new_view, false);
1047 address_space_update_topology_pass(as, old_view2, new_view, true);
1048 }
1049
1050 /* Writes are protected by the BQL. */
1051 qatomic_rcu_set(&as->current_map, new_view);
1052 if (old_view) {
1053 flatview_unref(old_view);
1054 }
1055
1056 /* Note that all the old MemoryRegions are still alive up to this
1057 * point. This relieves most MemoryListeners from the need to
1058 * ref/unref the MemoryRegions they get---unless they use them
1059 * outside the iothread mutex, in which case precise reference
1060 * counting is necessary.
1061 */
1062 if (old_view) {
1063 flatview_unref(old_view);
1064 }
1065 }
1066
1067 static void address_space_update_topology(AddressSpace *as)
1068 {
1069 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1070
1071 flatviews_init();
1072 if (!g_hash_table_lookup(flat_views, physmr)) {
1073 generate_memory_topology(physmr);
1074 }
1075 address_space_set_flatview(as);
1076 }
1077
1078 void memory_region_transaction_begin(void)
1079 {
1080 qemu_flush_coalesced_mmio_buffer();
1081 ++memory_region_transaction_depth;
1082 }
1083
1084 void memory_region_transaction_commit(void)
1085 {
1086 AddressSpace *as;
1087
1088 assert(memory_region_transaction_depth);
1089 assert(qemu_mutex_iothread_locked());
1090
1091 --memory_region_transaction_depth;
1092 if (!memory_region_transaction_depth) {
1093 if (memory_region_update_pending) {
1094 flatviews_reset();
1095
1096 MEMORY_LISTENER_CALL_GLOBAL(begin, Forward);
1097
1098 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1099 address_space_set_flatview(as);
1100 address_space_update_ioeventfds(as);
1101 }
1102 memory_region_update_pending = false;
1103 ioeventfd_update_pending = false;
1104 MEMORY_LISTENER_CALL_GLOBAL(commit, Forward);
1105 } else if (ioeventfd_update_pending) {
1106 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1107 address_space_update_ioeventfds(as);
1108 }
1109 ioeventfd_update_pending = false;
1110 }
1111 }
1112 }
1113
1114 static void memory_region_destructor_none(MemoryRegion *mr)
1115 {
1116 }
1117
1118 static void memory_region_destructor_ram(MemoryRegion *mr)
1119 {
1120 qemu_ram_free(mr->ram_block);
1121 }
1122
1123 static bool memory_region_need_escape(char c)
1124 {
1125 return c == '/' || c == '[' || c == '\\' || c == ']';
1126 }
1127
1128 static char *memory_region_escape_name(const char *name)
1129 {
1130 const char *p;
1131 char *escaped, *q;
1132 uint8_t c;
1133 size_t bytes = 0;
1134
1135 for (p = name; *p; p++) {
1136 bytes += memory_region_need_escape(*p) ? 4 : 1;
1137 }
1138 if (bytes == p - name) {
1139 return g_memdup(name, bytes + 1);
1140 }
1141
1142 escaped = g_malloc(bytes + 1);
1143 for (p = name, q = escaped; *p; p++) {
1144 c = *p;
1145 if (unlikely(memory_region_need_escape(c))) {
1146 *q++ = '\\';
1147 *q++ = 'x';
1148 *q++ = "0123456789abcdef"[c >> 4];
1149 c = "0123456789abcdef"[c & 15];
1150 }
1151 *q++ = c;
1152 }
1153 *q = 0;
1154 return escaped;
1155 }
1156
1157 static void memory_region_do_init(MemoryRegion *mr,
1158 Object *owner,
1159 const char *name,
1160 uint64_t size)
1161 {
1162 mr->size = int128_make64(size);
1163 if (size == UINT64_MAX) {
1164 mr->size = int128_2_64();
1165 }
1166 mr->name = g_strdup(name);
1167 mr->owner = owner;
1168 mr->ram_block = NULL;
1169
1170 if (name) {
1171 char *escaped_name = memory_region_escape_name(name);
1172 char *name_array = g_strdup_printf("%s[*]", escaped_name);
1173
1174 if (!owner) {
1175 owner = container_get(qdev_get_machine(), "/unattached");
1176 }
1177
1178 object_property_add_child(owner, name_array, OBJECT(mr));
1179 object_unref(OBJECT(mr));
1180 g_free(name_array);
1181 g_free(escaped_name);
1182 }
1183 }
1184
1185 void memory_region_init(MemoryRegion *mr,
1186 Object *owner,
1187 const char *name,
1188 uint64_t size)
1189 {
1190 object_initialize(mr, sizeof(*mr), TYPE_MEMORY_REGION);
1191 memory_region_do_init(mr, owner, name, size);
1192 }
1193
1194 static void memory_region_get_container(Object *obj, Visitor *v,
1195 const char *name, void *opaque,
1196 Error **errp)
1197 {
1198 MemoryRegion *mr = MEMORY_REGION(obj);
1199 char *path = (char *)"";
1200
1201 if (mr->container) {
1202 path = object_get_canonical_path(OBJECT(mr->container));
1203 }
1204 visit_type_str(v, name, &path, errp);
1205 if (mr->container) {
1206 g_free(path);
1207 }
1208 }
1209
1210 static Object *memory_region_resolve_container(Object *obj, void *opaque,
1211 const char *part)
1212 {
1213 MemoryRegion *mr = MEMORY_REGION(obj);
1214
1215 return OBJECT(mr->container);
1216 }
1217
1218 static void memory_region_get_priority(Object *obj, Visitor *v,
1219 const char *name, void *opaque,
1220 Error **errp)
1221 {
1222 MemoryRegion *mr = MEMORY_REGION(obj);
1223 int32_t value = mr->priority;
1224
1225 visit_type_int32(v, name, &value, errp);
1226 }
1227
1228 static void memory_region_get_size(Object *obj, Visitor *v, const char *name,
1229 void *opaque, Error **errp)
1230 {
1231 MemoryRegion *mr = MEMORY_REGION(obj);
1232 uint64_t value = memory_region_size(mr);
1233
1234 visit_type_uint64(v, name, &value, errp);
1235 }
1236
1237 static void memory_region_initfn(Object *obj)
1238 {
1239 MemoryRegion *mr = MEMORY_REGION(obj);
1240 ObjectProperty *op;
1241
1242 mr->ops = &unassigned_mem_ops;
1243 mr->enabled = true;
1244 mr->romd_mode = true;
1245 mr->destructor = memory_region_destructor_none;
1246 QTAILQ_INIT(&mr->subregions);
1247 QTAILQ_INIT(&mr->coalesced);
1248
1249 op = object_property_add(OBJECT(mr), "container",
1250 "link<" TYPE_MEMORY_REGION ">",
1251 memory_region_get_container,
1252 NULL, /* memory_region_set_container */
1253 NULL, NULL);
1254 op->resolve = memory_region_resolve_container;
1255
1256 object_property_add_uint64_ptr(OBJECT(mr), "addr",
1257 &mr->addr, OBJ_PROP_FLAG_READ);
1258 object_property_add(OBJECT(mr), "priority", "uint32",
1259 memory_region_get_priority,
1260 NULL, /* memory_region_set_priority */
1261 NULL, NULL);
1262 object_property_add(OBJECT(mr), "size", "uint64",
1263 memory_region_get_size,
1264 NULL, /* memory_region_set_size, */
1265 NULL, NULL);
1266 }
1267
1268 static void iommu_memory_region_initfn(Object *obj)
1269 {
1270 MemoryRegion *mr = MEMORY_REGION(obj);
1271
1272 mr->is_iommu = true;
1273 }
1274
1275 static uint64_t unassigned_mem_read(void *opaque, hwaddr addr,
1276 unsigned size)
1277 {
1278 #ifdef DEBUG_UNASSIGNED
1279 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
1280 #endif
1281 return 0;
1282 }
1283
1284 static void unassigned_mem_write(void *opaque, hwaddr addr,
1285 uint64_t val, unsigned size)
1286 {
1287 #ifdef DEBUG_UNASSIGNED
1288 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%"PRIx64"\n", addr, val);
1289 #endif
1290 }
1291
1292 static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
1293 unsigned size, bool is_write,
1294 MemTxAttrs attrs)
1295 {
1296 return false;
1297 }
1298
1299 const MemoryRegionOps unassigned_mem_ops = {
1300 .valid.accepts = unassigned_mem_accepts,
1301 .endianness = DEVICE_NATIVE_ENDIAN,
1302 };
1303
1304 static uint64_t memory_region_ram_device_read(void *opaque,
1305 hwaddr addr, unsigned size)
1306 {
1307 MemoryRegion *mr = opaque;
1308 uint64_t data = (uint64_t)~0;
1309
1310 switch (size) {
1311 case 1:
1312 data = *(uint8_t *)(mr->ram_block->host + addr);
1313 break;
1314 case 2:
1315 data = *(uint16_t *)(mr->ram_block->host + addr);
1316 break;
1317 case 4:
1318 data = *(uint32_t *)(mr->ram_block->host + addr);
1319 break;
1320 case 8:
1321 data = *(uint64_t *)(mr->ram_block->host + addr);
1322 break;
1323 }
1324
1325 trace_memory_region_ram_device_read(get_cpu_index(), mr, addr, data, size);
1326
1327 return data;
1328 }
1329
1330 static void memory_region_ram_device_write(void *opaque, hwaddr addr,
1331 uint64_t data, unsigned size)
1332 {
1333 MemoryRegion *mr = opaque;
1334
1335 trace_memory_region_ram_device_write(get_cpu_index(), mr, addr, data, size);
1336
1337 switch (size) {
1338 case 1:
1339 *(uint8_t *)(mr->ram_block->host + addr) = (uint8_t)data;
1340 break;
1341 case 2:
1342 *(uint16_t *)(mr->ram_block->host + addr) = (uint16_t)data;
1343 break;
1344 case 4:
1345 *(uint32_t *)(mr->ram_block->host + addr) = (uint32_t)data;
1346 break;
1347 case 8:
1348 *(uint64_t *)(mr->ram_block->host + addr) = data;
1349 break;
1350 }
1351 }
1352
1353 static const MemoryRegionOps ram_device_mem_ops = {
1354 .read = memory_region_ram_device_read,
1355 .write = memory_region_ram_device_write,
1356 .endianness = DEVICE_HOST_ENDIAN,
1357 .valid = {
1358 .min_access_size = 1,
1359 .max_access_size = 8,
1360 .unaligned = true,
1361 },
1362 .impl = {
1363 .min_access_size = 1,
1364 .max_access_size = 8,
1365 .unaligned = true,
1366 },
1367 };
1368
1369 bool memory_region_access_valid(MemoryRegion *mr,
1370 hwaddr addr,
1371 unsigned size,
1372 bool is_write,
1373 MemTxAttrs attrs)
1374 {
1375 if (mr->ops->valid.accepts
1376 && !mr->ops->valid.accepts(mr->opaque, addr, size, is_write, attrs)) {
1377 qemu_log_mask(LOG_GUEST_ERROR, "Invalid access at addr "
1378 "0x%" HWADDR_PRIX ", size %u, "
1379 "region '%s', reason: rejected\n",
1380 addr, size, memory_region_name(mr));
1381 return false;
1382 }
1383
1384 if (!mr->ops->valid.unaligned && (addr & (size - 1))) {
1385 qemu_log_mask(LOG_GUEST_ERROR, "Invalid access at addr "
1386 "0x%" HWADDR_PRIX ", size %u, "
1387 "region '%s', reason: unaligned\n",
1388 addr, size, memory_region_name(mr));
1389 return false;
1390 }
1391
1392 /* Treat zero as compatibility all valid */
1393 if (!mr->ops->valid.max_access_size) {
1394 return true;
1395 }
1396
1397 if (size > mr->ops->valid.max_access_size
1398 || size < mr->ops->valid.min_access_size) {
1399 qemu_log_mask(LOG_GUEST_ERROR, "Invalid access at addr "
1400 "0x%" HWADDR_PRIX ", size %u, "
1401 "region '%s', reason: invalid size "
1402 "(min:%u max:%u)\n",
1403 addr, size, memory_region_name(mr),
1404 mr->ops->valid.min_access_size,
1405 mr->ops->valid.max_access_size);
1406 return false;
1407 }
1408 return true;
1409 }
1410
1411 static MemTxResult memory_region_dispatch_read1(MemoryRegion *mr,
1412 hwaddr addr,
1413 uint64_t *pval,
1414 unsigned size,
1415 MemTxAttrs attrs)
1416 {
1417 *pval = 0;
1418
1419 if (mr->ops->read) {
1420 return access_with_adjusted_size(addr, pval, size,
1421 mr->ops->impl.min_access_size,
1422 mr->ops->impl.max_access_size,
1423 memory_region_read_accessor,
1424 mr, attrs);
1425 } else {
1426 return access_with_adjusted_size(addr, pval, size,
1427 mr->ops->impl.min_access_size,
1428 mr->ops->impl.max_access_size,
1429 memory_region_read_with_attrs_accessor,
1430 mr, attrs);
1431 }
1432 }
1433
1434 MemTxResult memory_region_dispatch_read(MemoryRegion *mr,
1435 hwaddr addr,
1436 uint64_t *pval,
1437 MemOp op,
1438 MemTxAttrs attrs)
1439 {
1440 unsigned size = memop_size(op);
1441 MemTxResult r;
1442
1443 fuzz_dma_read_cb(addr, size, mr, false);
1444 if (!memory_region_access_valid(mr, addr, size, false, attrs)) {
1445 *pval = unassigned_mem_read(mr, addr, size);
1446 return MEMTX_DECODE_ERROR;
1447 }
1448
1449 r = memory_region_dispatch_read1(mr, addr, pval, size, attrs);
1450 adjust_endianness(mr, pval, op);
1451 return r;
1452 }
1453
1454 /* Return true if an eventfd was signalled */
1455 static bool memory_region_dispatch_write_eventfds(MemoryRegion *mr,
1456 hwaddr addr,
1457 uint64_t data,
1458 unsigned size,
1459 MemTxAttrs attrs)
1460 {
1461 MemoryRegionIoeventfd ioeventfd = {
1462 .addr = addrrange_make(int128_make64(addr), int128_make64(size)),
1463 .data = data,
1464 };
1465 unsigned i;
1466
1467 for (i = 0; i < mr->ioeventfd_nb; i++) {
1468 ioeventfd.match_data = mr->ioeventfds[i].match_data;
1469 ioeventfd.e = mr->ioeventfds[i].e;
1470
1471 if (memory_region_ioeventfd_equal(&ioeventfd, &mr->ioeventfds[i])) {
1472 event_notifier_set(ioeventfd.e);
1473 return true;
1474 }
1475 }
1476
1477 return false;
1478 }
1479
1480 MemTxResult memory_region_dispatch_write(MemoryRegion *mr,
1481 hwaddr addr,
1482 uint64_t data,
1483 MemOp op,
1484 MemTxAttrs attrs)
1485 {
1486 unsigned size = memop_size(op);
1487
1488 if (!memory_region_access_valid(mr, addr, size, true, attrs)) {
1489 unassigned_mem_write(mr, addr, data, size);
1490 return MEMTX_DECODE_ERROR;
1491 }
1492
1493 adjust_endianness(mr, &data, op);
1494
1495 if ((!kvm_eventfds_enabled()) &&
1496 memory_region_dispatch_write_eventfds(mr, addr, data, size, attrs)) {
1497 return MEMTX_OK;
1498 }
1499
1500 if (mr->ops->write) {
1501 return access_with_adjusted_size(addr, &data, size,
1502 mr->ops->impl.min_access_size,
1503 mr->ops->impl.max_access_size,
1504 memory_region_write_accessor, mr,
1505 attrs);
1506 } else {
1507 return
1508 access_with_adjusted_size(addr, &data, size,
1509 mr->ops->impl.min_access_size,
1510 mr->ops->impl.max_access_size,
1511 memory_region_write_with_attrs_accessor,
1512 mr, attrs);
1513 }
1514 }
1515
1516 void memory_region_init_io(MemoryRegion *mr,
1517 Object *owner,
1518 const MemoryRegionOps *ops,
1519 void *opaque,
1520 const char *name,
1521 uint64_t size)
1522 {
1523 memory_region_init(mr, owner, name, size);
1524 mr->ops = ops ? ops : &unassigned_mem_ops;
1525 mr->opaque = opaque;
1526 mr->terminates = true;
1527 }
1528
1529 void memory_region_init_ram_nomigrate(MemoryRegion *mr,
1530 Object *owner,
1531 const char *name,
1532 uint64_t size,
1533 Error **errp)
1534 {
1535 memory_region_init_ram_shared_nomigrate(mr, owner, name, size, false, errp);
1536 }
1537
1538 void memory_region_init_ram_shared_nomigrate(MemoryRegion *mr,
1539 Object *owner,
1540 const char *name,
1541 uint64_t size,
1542 bool share,
1543 Error **errp)
1544 {
1545 Error *err = NULL;
1546 memory_region_init(mr, owner, name, size);
1547 mr->ram = true;
1548 mr->terminates = true;
1549 mr->destructor = memory_region_destructor_ram;
1550 mr->ram_block = qemu_ram_alloc(size, share, mr, &err);
1551 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1552 if (err) {
1553 mr->size = int128_zero();
1554 object_unparent(OBJECT(mr));
1555 error_propagate(errp, err);
1556 }
1557 }
1558
1559 void memory_region_init_resizeable_ram(MemoryRegion *mr,
1560 Object *owner,
1561 const char *name,
1562 uint64_t size,
1563 uint64_t max_size,
1564 void (*resized)(const char*,
1565 uint64_t length,
1566 void *host),
1567 Error **errp)
1568 {
1569 Error *err = NULL;
1570 memory_region_init(mr, owner, name, size);
1571 mr->ram = true;
1572 mr->terminates = true;
1573 mr->destructor = memory_region_destructor_ram;
1574 mr->ram_block = qemu_ram_alloc_resizeable(size, max_size, resized,
1575 mr, &err);
1576 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1577 if (err) {
1578 mr->size = int128_zero();
1579 object_unparent(OBJECT(mr));
1580 error_propagate(errp, err);
1581 }
1582 }
1583
1584 #ifdef CONFIG_POSIX
1585 void memory_region_init_ram_from_file(MemoryRegion *mr,
1586 struct Object *owner,
1587 const char *name,
1588 uint64_t size,
1589 uint64_t align,
1590 uint32_t ram_flags,
1591 const char *path,
1592 Error **errp)
1593 {
1594 Error *err = NULL;
1595 memory_region_init(mr, owner, name, size);
1596 mr->ram = true;
1597 mr->terminates = true;
1598 mr->destructor = memory_region_destructor_ram;
1599 mr->align = align;
1600 mr->ram_block = qemu_ram_alloc_from_file(size, mr, ram_flags, path, &err);
1601 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1602 if (err) {
1603 mr->size = int128_zero();
1604 object_unparent(OBJECT(mr));
1605 error_propagate(errp, err);
1606 }
1607 }
1608
1609 void memory_region_init_ram_from_fd(MemoryRegion *mr,
1610 struct Object *owner,
1611 const char *name,
1612 uint64_t size,
1613 bool share,
1614 int fd,
1615 Error **errp)
1616 {
1617 Error *err = NULL;
1618 memory_region_init(mr, owner, name, size);
1619 mr->ram = true;
1620 mr->terminates = true;
1621 mr->destructor = memory_region_destructor_ram;
1622 mr->ram_block = qemu_ram_alloc_from_fd(size, mr,
1623 share ? RAM_SHARED : 0,
1624 fd, &err);
1625 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1626 if (err) {
1627 mr->size = int128_zero();
1628 object_unparent(OBJECT(mr));
1629 error_propagate(errp, err);
1630 }
1631 }
1632 #endif
1633
1634 void memory_region_init_ram_ptr(MemoryRegion *mr,
1635 Object *owner,
1636 const char *name,
1637 uint64_t size,
1638 void *ptr)
1639 {
1640 memory_region_init(mr, owner, name, size);
1641 mr->ram = true;
1642 mr->terminates = true;
1643 mr->destructor = memory_region_destructor_ram;
1644 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1645
1646 /* qemu_ram_alloc_from_ptr cannot fail with ptr != NULL. */
1647 assert(ptr != NULL);
1648 mr->ram_block = qemu_ram_alloc_from_ptr(size, ptr, mr, &error_fatal);
1649 }
1650
1651 void memory_region_init_ram_device_ptr(MemoryRegion *mr,
1652 Object *owner,
1653 const char *name,
1654 uint64_t size,
1655 void *ptr)
1656 {
1657 memory_region_init(mr, owner, name, size);
1658 mr->ram = true;
1659 mr->terminates = true;
1660 mr->ram_device = true;
1661 mr->ops = &ram_device_mem_ops;
1662 mr->opaque = mr;
1663 mr->destructor = memory_region_destructor_ram;
1664 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1665 /* qemu_ram_alloc_from_ptr cannot fail with ptr != NULL. */
1666 assert(ptr != NULL);
1667 mr->ram_block = qemu_ram_alloc_from_ptr(size, ptr, mr, &error_fatal);
1668 }
1669
1670 void memory_region_init_alias(MemoryRegion *mr,
1671 Object *owner,
1672 const char *name,
1673 MemoryRegion *orig,
1674 hwaddr offset,
1675 uint64_t size)
1676 {
1677 memory_region_init(mr, owner, name, size);
1678 mr->alias = orig;
1679 mr->alias_offset = offset;
1680 }
1681
1682 void memory_region_init_rom_nomigrate(MemoryRegion *mr,
1683 struct Object *owner,
1684 const char *name,
1685 uint64_t size,
1686 Error **errp)
1687 {
1688 memory_region_init_ram_shared_nomigrate(mr, owner, name, size, false, errp);
1689 mr->readonly = true;
1690 }
1691
1692 void memory_region_init_rom_device_nomigrate(MemoryRegion *mr,
1693 Object *owner,
1694 const MemoryRegionOps *ops,
1695 void *opaque,
1696 const char *name,
1697 uint64_t size,
1698 Error **errp)
1699 {
1700 Error *err = NULL;
1701 assert(ops);
1702 memory_region_init(mr, owner, name, size);
1703 mr->ops = ops;
1704 mr->opaque = opaque;
1705 mr->terminates = true;
1706 mr->rom_device = true;
1707 mr->destructor = memory_region_destructor_ram;
1708 mr->ram_block = qemu_ram_alloc(size, false, mr, &err);
1709 if (err) {
1710 mr->size = int128_zero();
1711 object_unparent(OBJECT(mr));
1712 error_propagate(errp, err);
1713 }
1714 }
1715
1716 void memory_region_init_iommu(void *_iommu_mr,
1717 size_t instance_size,
1718 const char *mrtypename,
1719 Object *owner,
1720 const char *name,
1721 uint64_t size)
1722 {
1723 struct IOMMUMemoryRegion *iommu_mr;
1724 struct MemoryRegion *mr;
1725
1726 object_initialize(_iommu_mr, instance_size, mrtypename);
1727 mr = MEMORY_REGION(_iommu_mr);
1728 memory_region_do_init(mr, owner, name, size);
1729 iommu_mr = IOMMU_MEMORY_REGION(mr);
1730 mr->terminates = true; /* then re-forwards */
1731 QLIST_INIT(&iommu_mr->iommu_notify);
1732 iommu_mr->iommu_notify_flags = IOMMU_NOTIFIER_NONE;
1733 }
1734
1735 static void memory_region_finalize(Object *obj)
1736 {
1737 MemoryRegion *mr = MEMORY_REGION(obj);
1738
1739 assert(!mr->container);
1740
1741 /* We know the region is not visible in any address space (it
1742 * does not have a container and cannot be a root either because
1743 * it has no references, so we can blindly clear mr->enabled.
1744 * memory_region_set_enabled instead could trigger a transaction
1745 * and cause an infinite loop.
1746 */
1747 mr->enabled = false;
1748 memory_region_transaction_begin();
1749 while (!QTAILQ_EMPTY(&mr->subregions)) {
1750 MemoryRegion *subregion = QTAILQ_FIRST(&mr->subregions);
1751 memory_region_del_subregion(mr, subregion);
1752 }
1753 memory_region_transaction_commit();
1754
1755 mr->destructor(mr);
1756 memory_region_clear_coalescing(mr);
1757 g_free((char *)mr->name);
1758 g_free(mr->ioeventfds);
1759 }
1760
1761 Object *memory_region_owner(MemoryRegion *mr)
1762 {
1763 Object *obj = OBJECT(mr);
1764 return obj->parent;
1765 }
1766
1767 void memory_region_ref(MemoryRegion *mr)
1768 {
1769 /* MMIO callbacks most likely will access data that belongs
1770 * to the owner, hence the need to ref/unref the owner whenever
1771 * the memory region is in use.
1772 *
1773 * The memory region is a child of its owner. As long as the
1774 * owner doesn't call unparent itself on the memory region,
1775 * ref-ing the owner will also keep the memory region alive.
1776 * Memory regions without an owner are supposed to never go away;
1777 * we do not ref/unref them because it slows down DMA sensibly.
1778 */
1779 if (mr && mr->owner) {
1780 object_ref(mr->owner);
1781 }
1782 }
1783
1784 void memory_region_unref(MemoryRegion *mr)
1785 {
1786 if (mr && mr->owner) {
1787 object_unref(mr->owner);
1788 }
1789 }
1790
1791 uint64_t memory_region_size(MemoryRegion *mr)
1792 {
1793 if (int128_eq(mr->size, int128_2_64())) {
1794 return UINT64_MAX;
1795 }
1796 return int128_get64(mr->size);
1797 }
1798
1799 const char *memory_region_name(const MemoryRegion *mr)
1800 {
1801 if (!mr->name) {
1802 ((MemoryRegion *)mr)->name =
1803 g_strdup(object_get_canonical_path_component(OBJECT(mr)));
1804 }
1805 return mr->name;
1806 }
1807
1808 bool memory_region_is_ram_device(MemoryRegion *mr)
1809 {
1810 return mr->ram_device;
1811 }
1812
1813 uint8_t memory_region_get_dirty_log_mask(MemoryRegion *mr)
1814 {
1815 uint8_t mask = mr->dirty_log_mask;
1816 RAMBlock *rb = mr->ram_block;
1817
1818 if (global_dirty_log && ((rb && qemu_ram_is_migratable(rb)) ||
1819 memory_region_is_iommu(mr))) {
1820 mask |= (1 << DIRTY_MEMORY_MIGRATION);
1821 }
1822 return mask;
1823 }
1824
1825 bool memory_region_is_logging(MemoryRegion *mr, uint8_t client)
1826 {
1827 return memory_region_get_dirty_log_mask(mr) & (1 << client);
1828 }
1829
1830 static int memory_region_update_iommu_notify_flags(IOMMUMemoryRegion *iommu_mr,
1831 Error **errp)
1832 {
1833 IOMMUNotifierFlag flags = IOMMU_NOTIFIER_NONE;
1834 IOMMUNotifier *iommu_notifier;
1835 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1836 int ret = 0;
1837
1838 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
1839 flags |= iommu_notifier->notifier_flags;
1840 }
1841
1842 if (flags != iommu_mr->iommu_notify_flags && imrc->notify_flag_changed) {
1843 ret = imrc->notify_flag_changed(iommu_mr,
1844 iommu_mr->iommu_notify_flags,
1845 flags, errp);
1846 }
1847
1848 if (!ret) {
1849 iommu_mr->iommu_notify_flags = flags;
1850 }
1851 return ret;
1852 }
1853
1854 int memory_region_iommu_set_page_size_mask(IOMMUMemoryRegion *iommu_mr,
1855 uint64_t page_size_mask,
1856 Error **errp)
1857 {
1858 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1859 int ret = 0;
1860
1861 if (imrc->iommu_set_page_size_mask) {
1862 ret = imrc->iommu_set_page_size_mask(iommu_mr, page_size_mask, errp);
1863 }
1864 return ret;
1865 }
1866
1867 int memory_region_register_iommu_notifier(MemoryRegion *mr,
1868 IOMMUNotifier *n, Error **errp)
1869 {
1870 IOMMUMemoryRegion *iommu_mr;
1871 int ret;
1872
1873 if (mr->alias) {
1874 return memory_region_register_iommu_notifier(mr->alias, n, errp);
1875 }
1876
1877 /* We need to register for at least one bitfield */
1878 iommu_mr = IOMMU_MEMORY_REGION(mr);
1879 assert(n->notifier_flags != IOMMU_NOTIFIER_NONE);
1880 assert(n->start <= n->end);
1881 assert(n->iommu_idx >= 0 &&
1882 n->iommu_idx < memory_region_iommu_num_indexes(iommu_mr));
1883
1884 QLIST_INSERT_HEAD(&iommu_mr->iommu_notify, n, node);
1885 ret = memory_region_update_iommu_notify_flags(iommu_mr, errp);
1886 if (ret) {
1887 QLIST_REMOVE(n, node);
1888 }
1889 return ret;
1890 }
1891
1892 uint64_t memory_region_iommu_get_min_page_size(IOMMUMemoryRegion *iommu_mr)
1893 {
1894 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1895
1896 if (imrc->get_min_page_size) {
1897 return imrc->get_min_page_size(iommu_mr);
1898 }
1899 return TARGET_PAGE_SIZE;
1900 }
1901
1902 void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n)
1903 {
1904 MemoryRegion *mr = MEMORY_REGION(iommu_mr);
1905 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1906 hwaddr addr, granularity;
1907 IOMMUTLBEntry iotlb;
1908
1909 /* If the IOMMU has its own replay callback, override */
1910 if (imrc->replay) {
1911 imrc->replay(iommu_mr, n);
1912 return;
1913 }
1914
1915 granularity = memory_region_iommu_get_min_page_size(iommu_mr);
1916
1917 for (addr = 0; addr < memory_region_size(mr); addr += granularity) {
1918 iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE, n->iommu_idx);
1919 if (iotlb.perm != IOMMU_NONE) {
1920 n->notify(n, &iotlb);
1921 }
1922
1923 /* if (2^64 - MR size) < granularity, it's possible to get an
1924 * infinite loop here. This should catch such a wraparound */
1925 if ((addr + granularity) < addr) {
1926 break;
1927 }
1928 }
1929 }
1930
1931 void memory_region_unregister_iommu_notifier(MemoryRegion *mr,
1932 IOMMUNotifier *n)
1933 {
1934 IOMMUMemoryRegion *iommu_mr;
1935
1936 if (mr->alias) {
1937 memory_region_unregister_iommu_notifier(mr->alias, n);
1938 return;
1939 }
1940 QLIST_REMOVE(n, node);
1941 iommu_mr = IOMMU_MEMORY_REGION(mr);
1942 memory_region_update_iommu_notify_flags(iommu_mr, NULL);
1943 }
1944
1945 void memory_region_notify_one(IOMMUNotifier *notifier,
1946 IOMMUTLBEntry *entry)
1947 {
1948 IOMMUNotifierFlag request_flags;
1949 hwaddr entry_end = entry->iova + entry->addr_mask;
1950
1951 /*
1952 * Skip the notification if the notification does not overlap
1953 * with registered range.
1954 */
1955 if (notifier->start > entry_end || notifier->end < entry->iova) {
1956 return;
1957 }
1958
1959 assert(entry->iova >= notifier->start && entry_end <= notifier->end);
1960
1961 if (entry->perm & IOMMU_RW) {
1962 request_flags = IOMMU_NOTIFIER_MAP;
1963 } else {
1964 request_flags = IOMMU_NOTIFIER_UNMAP;
1965 }
1966
1967 if (notifier->notifier_flags & request_flags) {
1968 notifier->notify(notifier, entry);
1969 }
1970 }
1971
1972 void memory_region_notify_iommu(IOMMUMemoryRegion *iommu_mr,
1973 int iommu_idx,
1974 IOMMUTLBEntry entry)
1975 {
1976 IOMMUNotifier *iommu_notifier;
1977
1978 assert(memory_region_is_iommu(MEMORY_REGION(iommu_mr)));
1979
1980 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
1981 if (iommu_notifier->iommu_idx == iommu_idx) {
1982 memory_region_notify_one(iommu_notifier, &entry);
1983 }
1984 }
1985 }
1986
1987 int memory_region_iommu_get_attr(IOMMUMemoryRegion *iommu_mr,
1988 enum IOMMUMemoryRegionAttr attr,
1989 void *data)
1990 {
1991 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1992
1993 if (!imrc->get_attr) {
1994 return -EINVAL;
1995 }
1996
1997 return imrc->get_attr(iommu_mr, attr, data);
1998 }
1999
2000 int memory_region_iommu_attrs_to_index(IOMMUMemoryRegion *iommu_mr,
2001 MemTxAttrs attrs)
2002 {
2003 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
2004
2005 if (!imrc->attrs_to_index) {
2006 return 0;
2007 }
2008
2009 return imrc->attrs_to_index(iommu_mr, attrs);
2010 }
2011
2012 int memory_region_iommu_num_indexes(IOMMUMemoryRegion *iommu_mr)
2013 {
2014 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
2015
2016 if (!imrc->num_indexes) {
2017 return 1;
2018 }
2019
2020 return imrc->num_indexes(iommu_mr);
2021 }
2022
2023 void memory_region_set_log(MemoryRegion *mr, bool log, unsigned client)
2024 {
2025 uint8_t mask = 1 << client;
2026 uint8_t old_logging;
2027
2028 assert(client == DIRTY_MEMORY_VGA);
2029 old_logging = mr->vga_logging_count;
2030 mr->vga_logging_count += log ? 1 : -1;
2031 if (!!old_logging == !!mr->vga_logging_count) {
2032 return;
2033 }
2034
2035 memory_region_transaction_begin();
2036 mr->dirty_log_mask = (mr->dirty_log_mask & ~mask) | (log * mask);
2037 memory_region_update_pending |= mr->enabled;
2038 memory_region_transaction_commit();
2039 }
2040
2041 void memory_region_set_dirty(MemoryRegion *mr, hwaddr addr,
2042 hwaddr size)
2043 {
2044 assert(mr->ram_block);
2045 cpu_physical_memory_set_dirty_range(memory_region_get_ram_addr(mr) + addr,
2046 size,
2047 memory_region_get_dirty_log_mask(mr));
2048 }
2049
2050 static void memory_region_sync_dirty_bitmap(MemoryRegion *mr)
2051 {
2052 MemoryListener *listener;
2053 AddressSpace *as;
2054 FlatView *view;
2055 FlatRange *fr;
2056
2057 /* If the same address space has multiple log_sync listeners, we
2058 * visit that address space's FlatView multiple times. But because
2059 * log_sync listeners are rare, it's still cheaper than walking each
2060 * address space once.
2061 */
2062 QTAILQ_FOREACH(listener, &memory_listeners, link) {
2063 if (!listener->log_sync) {
2064 continue;
2065 }
2066 as = listener->address_space;
2067 view = address_space_get_flatview(as);
2068 FOR_EACH_FLAT_RANGE(fr, view) {
2069 if (fr->dirty_log_mask && (!mr || fr->mr == mr)) {
2070 MemoryRegionSection mrs = section_from_flat_range(fr, view);
2071 listener->log_sync(listener, &mrs);
2072 }
2073 }
2074 flatview_unref(view);
2075 }
2076 }
2077
2078 void memory_region_clear_dirty_bitmap(MemoryRegion *mr, hwaddr start,
2079 hwaddr len)
2080 {
2081 MemoryRegionSection mrs;
2082 MemoryListener *listener;
2083 AddressSpace *as;
2084 FlatView *view;
2085 FlatRange *fr;
2086 hwaddr sec_start, sec_end, sec_size;
2087
2088 QTAILQ_FOREACH(listener, &memory_listeners, link) {
2089 if (!listener->log_clear) {
2090 continue;
2091 }
2092 as = listener->address_space;
2093 view = address_space_get_flatview(as);
2094 FOR_EACH_FLAT_RANGE(fr, view) {
2095 if (!fr->dirty_log_mask || fr->mr != mr) {
2096 /*
2097 * Clear dirty bitmap operation only applies to those
2098 * regions whose dirty logging is at least enabled
2099 */
2100 continue;
2101 }
2102
2103 mrs = section_from_flat_range(fr, view);
2104
2105 sec_start = MAX(mrs.offset_within_region, start);
2106 sec_end = mrs.offset_within_region + int128_get64(mrs.size);
2107 sec_end = MIN(sec_end, start + len);
2108
2109 if (sec_start >= sec_end) {
2110 /*
2111 * If this memory region section has no intersection
2112 * with the requested range, skip.
2113 */
2114 continue;
2115 }
2116
2117 /* Valid case; shrink the section if needed */
2118 mrs.offset_within_address_space +=
2119 sec_start - mrs.offset_within_region;
2120 mrs.offset_within_region = sec_start;
2121 sec_size = sec_end - sec_start;
2122 mrs.size = int128_make64(sec_size);
2123 listener->log_clear(listener, &mrs);
2124 }
2125 flatview_unref(view);
2126 }
2127 }
2128
2129 DirtyBitmapSnapshot *memory_region_snapshot_and_clear_dirty(MemoryRegion *mr,
2130 hwaddr addr,
2131 hwaddr size,
2132 unsigned client)
2133 {
2134 DirtyBitmapSnapshot *snapshot;
2135 assert(mr->ram_block);
2136 memory_region_sync_dirty_bitmap(mr);
2137 snapshot = cpu_physical_memory_snapshot_and_clear_dirty(mr, addr, size, client);
2138 memory_global_after_dirty_log_sync();
2139 return snapshot;
2140 }
2141
2142 bool memory_region_snapshot_get_dirty(MemoryRegion *mr, DirtyBitmapSnapshot *snap,
2143 hwaddr addr, hwaddr size)
2144 {
2145 assert(mr->ram_block);
2146 return cpu_physical_memory_snapshot_get_dirty(snap,
2147 memory_region_get_ram_addr(mr) + addr, size);
2148 }
2149
2150 void memory_region_set_readonly(MemoryRegion *mr, bool readonly)
2151 {
2152 if (mr->readonly != readonly) {
2153 memory_region_transaction_begin();
2154 mr->readonly = readonly;
2155 memory_region_update_pending |= mr->enabled;
2156 memory_region_transaction_commit();
2157 }
2158 }
2159
2160 void memory_region_set_nonvolatile(MemoryRegion *mr, bool nonvolatile)
2161 {
2162 if (mr->nonvolatile != nonvolatile) {
2163 memory_region_transaction_begin();
2164 mr->nonvolatile = nonvolatile;
2165 memory_region_update_pending |= mr->enabled;
2166 memory_region_transaction_commit();
2167 }
2168 }
2169
2170 void memory_region_rom_device_set_romd(MemoryRegion *mr, bool romd_mode)
2171 {
2172 if (mr->romd_mode != romd_mode) {
2173 memory_region_transaction_begin();
2174 mr->romd_mode = romd_mode;
2175 memory_region_update_pending |= mr->enabled;
2176 memory_region_transaction_commit();
2177 }
2178 }
2179
2180 void memory_region_reset_dirty(MemoryRegion *mr, hwaddr addr,
2181 hwaddr size, unsigned client)
2182 {
2183 assert(mr->ram_block);
2184 cpu_physical_memory_test_and_clear_dirty(
2185 memory_region_get_ram_addr(mr) + addr, size, client);
2186 }
2187
2188 int memory_region_get_fd(MemoryRegion *mr)
2189 {
2190 int fd;
2191
2192 RCU_READ_LOCK_GUARD();
2193 while (mr->alias) {
2194 mr = mr->alias;
2195 }
2196 fd = mr->ram_block->fd;
2197
2198 return fd;
2199 }
2200
2201 void *memory_region_get_ram_ptr(MemoryRegion *mr)
2202 {
2203 void *ptr;
2204 uint64_t offset = 0;
2205
2206 RCU_READ_LOCK_GUARD();
2207 while (mr->alias) {
2208 offset += mr->alias_offset;
2209 mr = mr->alias;
2210 }
2211 assert(mr->ram_block);
2212 ptr = qemu_map_ram_ptr(mr->ram_block, offset);
2213
2214 return ptr;
2215 }
2216
2217 MemoryRegion *memory_region_from_host(void *ptr, ram_addr_t *offset)
2218 {
2219 RAMBlock *block;
2220
2221 block = qemu_ram_block_from_host(ptr, false, offset);
2222 if (!block) {
2223 return NULL;
2224 }
2225
2226 return block->mr;
2227 }
2228
2229 ram_addr_t memory_region_get_ram_addr(MemoryRegion *mr)
2230 {
2231 return mr->ram_block ? mr->ram_block->offset : RAM_ADDR_INVALID;
2232 }
2233
2234 void memory_region_ram_resize(MemoryRegion *mr, ram_addr_t newsize, Error **errp)
2235 {
2236 assert(mr->ram_block);
2237
2238 qemu_ram_resize(mr->ram_block, newsize, errp);
2239 }
2240
2241 void memory_region_msync(MemoryRegion *mr, hwaddr addr, hwaddr size)
2242 {
2243 if (mr->ram_block) {
2244 qemu_ram_msync(mr->ram_block, addr, size);
2245 }
2246 }
2247
2248 void memory_region_writeback(MemoryRegion *mr, hwaddr addr, hwaddr size)
2249 {
2250 /*
2251 * Might be extended case needed to cover
2252 * different types of memory regions
2253 */
2254 if (mr->dirty_log_mask) {
2255 memory_region_msync(mr, addr, size);
2256 }
2257 }
2258
2259 /*
2260 * Call proper memory listeners about the change on the newly
2261 * added/removed CoalescedMemoryRange.
2262 */
2263 static void memory_region_update_coalesced_range(MemoryRegion *mr,
2264 CoalescedMemoryRange *cmr,
2265 bool add)
2266 {
2267 AddressSpace *as;
2268 FlatView *view;
2269 FlatRange *fr;
2270
2271 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
2272 view = address_space_get_flatview(as);
2273 FOR_EACH_FLAT_RANGE(fr, view) {
2274 if (fr->mr == mr) {
2275 flat_range_coalesced_io_notify(fr, as, cmr, add);
2276 }
2277 }
2278 flatview_unref(view);
2279 }
2280 }
2281
2282 void memory_region_set_coalescing(MemoryRegion *mr)
2283 {
2284 memory_region_clear_coalescing(mr);
2285 memory_region_add_coalescing(mr, 0, int128_get64(mr->size));
2286 }
2287
2288 void memory_region_add_coalescing(MemoryRegion *mr,
2289 hwaddr offset,
2290 uint64_t size)
2291 {
2292 CoalescedMemoryRange *cmr = g_malloc(sizeof(*cmr));
2293
2294 cmr->addr = addrrange_make(int128_make64(offset), int128_make64(size));
2295 QTAILQ_INSERT_TAIL(&mr->coalesced, cmr, link);
2296 memory_region_update_coalesced_range(mr, cmr, true);
2297 memory_region_set_flush_coalesced(mr);
2298 }
2299
2300 void memory_region_clear_coalescing(MemoryRegion *mr)
2301 {
2302 CoalescedMemoryRange *cmr;
2303
2304 if (QTAILQ_EMPTY(&mr->coalesced)) {
2305 return;
2306 }
2307
2308 qemu_flush_coalesced_mmio_buffer();
2309 mr->flush_coalesced_mmio = false;
2310
2311 while (!QTAILQ_EMPTY(&mr->coalesced)) {
2312 cmr = QTAILQ_FIRST(&mr->coalesced);
2313 QTAILQ_REMOVE(&mr->coalesced, cmr, link);
2314 memory_region_update_coalesced_range(mr, cmr, false);
2315 g_free(cmr);
2316 }
2317 }
2318
2319 void memory_region_set_flush_coalesced(MemoryRegion *mr)
2320 {
2321 mr->flush_coalesced_mmio = true;
2322 }
2323
2324 void memory_region_clear_flush_coalesced(MemoryRegion *mr)
2325 {
2326 qemu_flush_coalesced_mmio_buffer();
2327 if (QTAILQ_EMPTY(&mr->coalesced)) {
2328 mr->flush_coalesced_mmio = false;
2329 }
2330 }
2331
2332 static bool userspace_eventfd_warning;
2333
2334 void memory_region_add_eventfd(MemoryRegion *mr,
2335 hwaddr addr,
2336 unsigned size,
2337 bool match_data,
2338 uint64_t data,
2339 EventNotifier *e)
2340 {
2341 MemoryRegionIoeventfd mrfd = {
2342 .addr.start = int128_make64(addr),
2343 .addr.size = int128_make64(size),
2344 .match_data = match_data,
2345 .data = data,
2346 .e = e,
2347 };
2348 unsigned i;
2349
2350 if (kvm_enabled() && (!(kvm_eventfds_enabled() ||
2351 userspace_eventfd_warning))) {
2352 userspace_eventfd_warning = true;
2353 error_report("Using eventfd without MMIO binding in KVM. "
2354 "Suboptimal performance expected");
2355 }
2356
2357 if (size) {
2358 adjust_endianness(mr, &mrfd.data, size_memop(size) | MO_TE);
2359 }
2360 memory_region_transaction_begin();
2361 for (i = 0; i < mr->ioeventfd_nb; ++i) {
2362 if (memory_region_ioeventfd_before(&mrfd, &mr->ioeventfds[i])) {
2363 break;
2364 }
2365 }
2366 ++mr->ioeventfd_nb;
2367 mr->ioeventfds = g_realloc(mr->ioeventfds,
2368 sizeof(*mr->ioeventfds) * mr->ioeventfd_nb);
2369 memmove(&mr->ioeventfds[i+1], &mr->ioeventfds[i],
2370 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb-1 - i));
2371 mr->ioeventfds[i] = mrfd;
2372 ioeventfd_update_pending |= mr->enabled;
2373 memory_region_transaction_commit();
2374 }
2375
2376 void memory_region_del_eventfd(MemoryRegion *mr,
2377 hwaddr addr,
2378 unsigned size,
2379 bool match_data,
2380 uint64_t data,
2381 EventNotifier *e)
2382 {
2383 MemoryRegionIoeventfd mrfd = {
2384 .addr.start = int128_make64(addr),
2385 .addr.size = int128_make64(size),
2386 .match_data = match_data,
2387 .data = data,
2388 .e = e,
2389 };
2390 unsigned i;
2391
2392 if (size) {
2393 adjust_endianness(mr, &mrfd.data, size_memop(size) | MO_TE);
2394 }
2395 memory_region_transaction_begin();
2396 for (i = 0; i < mr->ioeventfd_nb; ++i) {
2397 if (memory_region_ioeventfd_equal(&mrfd, &mr->ioeventfds[i])) {
2398 break;
2399 }
2400 }
2401 assert(i != mr->ioeventfd_nb);
2402 memmove(&mr->ioeventfds[i], &mr->ioeventfds[i+1],
2403 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb - (i+1)));
2404 --mr->ioeventfd_nb;
2405 mr->ioeventfds = g_realloc(mr->ioeventfds,
2406 sizeof(*mr->ioeventfds)*mr->ioeventfd_nb + 1);
2407 ioeventfd_update_pending |= mr->enabled;
2408 memory_region_transaction_commit();
2409 }
2410
2411 static void memory_region_update_container_subregions(MemoryRegion *subregion)
2412 {
2413 MemoryRegion *mr = subregion->container;
2414 MemoryRegion *other;
2415
2416 memory_region_transaction_begin();
2417
2418 memory_region_ref(subregion);
2419 QTAILQ_FOREACH(other, &mr->subregions, subregions_link) {
2420 if (subregion->priority >= other->priority) {
2421 QTAILQ_INSERT_BEFORE(other, subregion, subregions_link);
2422 goto done;
2423 }
2424 }
2425 QTAILQ_INSERT_TAIL(&mr->subregions, subregion, subregions_link);
2426 done:
2427 memory_region_update_pending |= mr->enabled && subregion->enabled;
2428 memory_region_transaction_commit();
2429 }
2430
2431 static void memory_region_add_subregion_common(MemoryRegion *mr,
2432 hwaddr offset,
2433 MemoryRegion *subregion)
2434 {
2435 assert(!subregion->container);
2436 subregion->container = mr;
2437 subregion->addr = offset;
2438 memory_region_update_container_subregions(subregion);
2439 }
2440
2441 void memory_region_add_subregion(MemoryRegion *mr,
2442 hwaddr offset,
2443 MemoryRegion *subregion)
2444 {
2445 subregion->priority = 0;
2446 memory_region_add_subregion_common(mr, offset, subregion);
2447 }
2448
2449 void memory_region_add_subregion_overlap(MemoryRegion *mr,
2450 hwaddr offset,
2451 MemoryRegion *subregion,
2452 int priority)
2453 {
2454 subregion->priority = priority;
2455 memory_region_add_subregion_common(mr, offset, subregion);
2456 }
2457
2458 void memory_region_del_subregion(MemoryRegion *mr,
2459 MemoryRegion *subregion)
2460 {
2461 memory_region_transaction_begin();
2462 assert(subregion->container == mr);
2463 subregion->container = NULL;
2464 QTAILQ_REMOVE(&mr->subregions, subregion, subregions_link);
2465 memory_region_unref(subregion);
2466 memory_region_update_pending |= mr->enabled && subregion->enabled;
2467 memory_region_transaction_commit();
2468 }
2469
2470 void memory_region_set_enabled(MemoryRegion *mr, bool enabled)
2471 {
2472 if (enabled == mr->enabled) {
2473 return;
2474 }
2475 memory_region_transaction_begin();
2476 mr->enabled = enabled;
2477 memory_region_update_pending = true;
2478 memory_region_transaction_commit();
2479 }
2480
2481 void memory_region_set_size(MemoryRegion *mr, uint64_t size)
2482 {
2483 Int128 s = int128_make64(size);
2484
2485 if (size == UINT64_MAX) {
2486 s = int128_2_64();
2487 }
2488 if (int128_eq(s, mr->size)) {
2489 return;
2490 }
2491 memory_region_transaction_begin();
2492 mr->size = s;
2493 memory_region_update_pending = true;
2494 memory_region_transaction_commit();
2495 }
2496
2497 static void memory_region_readd_subregion(MemoryRegion *mr)
2498 {
2499 MemoryRegion *container = mr->container;
2500
2501 if (container) {
2502 memory_region_transaction_begin();
2503 memory_region_ref(mr);
2504 memory_region_del_subregion(container, mr);
2505 mr->container = container;
2506 memory_region_update_container_subregions(mr);
2507 memory_region_unref(mr);
2508 memory_region_transaction_commit();
2509 }
2510 }
2511
2512 void memory_region_set_address(MemoryRegion *mr, hwaddr addr)
2513 {
2514 if (addr != mr->addr) {
2515 mr->addr = addr;
2516 memory_region_readd_subregion(mr);
2517 }
2518 }
2519
2520 void memory_region_set_alias_offset(MemoryRegion *mr, hwaddr offset)
2521 {
2522 assert(mr->alias);
2523
2524 if (offset == mr->alias_offset) {
2525 return;
2526 }
2527
2528 memory_region_transaction_begin();
2529 mr->alias_offset = offset;
2530 memory_region_update_pending |= mr->enabled;
2531 memory_region_transaction_commit();
2532 }
2533
2534 uint64_t memory_region_get_alignment(const MemoryRegion *mr)
2535 {
2536 return mr->align;
2537 }
2538
2539 static int cmp_flatrange_addr(const void *addr_, const void *fr_)
2540 {
2541 const AddrRange *addr = addr_;
2542 const FlatRange *fr = fr_;
2543
2544 if (int128_le(addrrange_end(*addr), fr->addr.start)) {
2545 return -1;
2546 } else if (int128_ge(addr->start, addrrange_end(fr->addr))) {
2547 return 1;
2548 }
2549 return 0;
2550 }
2551
2552 static FlatRange *flatview_lookup(FlatView *view, AddrRange addr)
2553 {
2554 return bsearch(&addr, view->ranges, view->nr,
2555 sizeof(FlatRange), cmp_flatrange_addr);
2556 }
2557
2558 bool memory_region_is_mapped(MemoryRegion *mr)
2559 {
2560 return mr->container ? true : false;
2561 }
2562
2563 /* Same as memory_region_find, but it does not add a reference to the
2564 * returned region. It must be called from an RCU critical section.
2565 */
2566 static MemoryRegionSection memory_region_find_rcu(MemoryRegion *mr,
2567 hwaddr addr, uint64_t size)
2568 {
2569 MemoryRegionSection ret = { .mr = NULL };
2570 MemoryRegion *root;
2571 AddressSpace *as;
2572 AddrRange range;
2573 FlatView *view;
2574 FlatRange *fr;
2575
2576 addr += mr->addr;
2577 for (root = mr; root->container; ) {
2578 root = root->container;
2579 addr += root->addr;
2580 }
2581
2582 as = memory_region_to_address_space(root);
2583 if (!as) {
2584 return ret;
2585 }
2586 range = addrrange_make(int128_make64(addr), int128_make64(size));
2587
2588 view = address_space_to_flatview(as);
2589 fr = flatview_lookup(view, range);
2590 if (!fr) {
2591 return ret;
2592 }
2593
2594 while (fr > view->ranges && addrrange_intersects(fr[-1].addr, range)) {
2595 --fr;
2596 }
2597
2598 ret.mr = fr->mr;
2599 ret.fv = view;
2600 range = addrrange_intersection(range, fr->addr);
2601 ret.offset_within_region = fr->offset_in_region;
2602 ret.offset_within_region += int128_get64(int128_sub(range.start,
2603 fr->addr.start));
2604 ret.size = range.size;
2605 ret.offset_within_address_space = int128_get64(range.start);
2606 ret.readonly = fr->readonly;
2607 ret.nonvolatile = fr->nonvolatile;
2608 return ret;
2609 }
2610
2611 MemoryRegionSection memory_region_find(MemoryRegion *mr,
2612 hwaddr addr, uint64_t size)
2613 {
2614 MemoryRegionSection ret;
2615 RCU_READ_LOCK_GUARD();
2616 ret = memory_region_find_rcu(mr, addr, size);
2617 if (ret.mr) {
2618 memory_region_ref(ret.mr);
2619 }
2620 return ret;
2621 }
2622
2623 bool memory_region_present(MemoryRegion *container, hwaddr addr)
2624 {
2625 MemoryRegion *mr;
2626
2627 RCU_READ_LOCK_GUARD();
2628 mr = memory_region_find_rcu(container, addr, 1).mr;
2629 return mr && mr != container;
2630 }
2631
2632 void memory_global_dirty_log_sync(void)
2633 {
2634 memory_region_sync_dirty_bitmap(NULL);
2635 }
2636
2637 void memory_global_after_dirty_log_sync(void)
2638 {
2639 MEMORY_LISTENER_CALL_GLOBAL(log_global_after_sync, Forward);
2640 }
2641
2642 static VMChangeStateEntry *vmstate_change;
2643
2644 void memory_global_dirty_log_start(void)
2645 {
2646 if (vmstate_change) {
2647 qemu_del_vm_change_state_handler(vmstate_change);
2648 vmstate_change = NULL;
2649 }
2650
2651 global_dirty_log = true;
2652
2653 MEMORY_LISTENER_CALL_GLOBAL(log_global_start, Forward);
2654
2655 /* Refresh DIRTY_MEMORY_MIGRATION bit. */
2656 memory_region_transaction_begin();
2657 memory_region_update_pending = true;
2658 memory_region_transaction_commit();
2659 }
2660
2661 static void memory_global_dirty_log_do_stop(void)
2662 {
2663 global_dirty_log = false;
2664
2665 /* Refresh DIRTY_MEMORY_MIGRATION bit. */
2666 memory_region_transaction_begin();
2667 memory_region_update_pending = true;
2668 memory_region_transaction_commit();
2669
2670 MEMORY_LISTENER_CALL_GLOBAL(log_global_stop, Reverse);
2671 }
2672
2673 static void memory_vm_change_state_handler(void *opaque, int running,
2674 RunState state)
2675 {
2676 if (running) {
2677 memory_global_dirty_log_do_stop();
2678
2679 if (vmstate_change) {
2680 qemu_del_vm_change_state_handler(vmstate_change);
2681 vmstate_change = NULL;
2682 }
2683 }
2684 }
2685
2686 void memory_global_dirty_log_stop(void)
2687 {
2688 if (!runstate_is_running()) {
2689 if (vmstate_change) {
2690 return;
2691 }
2692 vmstate_change = qemu_add_vm_change_state_handler(
2693 memory_vm_change_state_handler, NULL);
2694 return;
2695 }
2696
2697 memory_global_dirty_log_do_stop();
2698 }
2699
2700 static void listener_add_address_space(MemoryListener *listener,
2701 AddressSpace *as)
2702 {
2703 FlatView *view;
2704 FlatRange *fr;
2705
2706 if (listener->begin) {
2707 listener->begin(listener);
2708 }
2709 if (global_dirty_log) {
2710 if (listener->log_global_start) {
2711 listener->log_global_start(listener);
2712 }
2713 }
2714
2715 view = address_space_get_flatview(as);
2716 FOR_EACH_FLAT_RANGE(fr, view) {
2717 MemoryRegionSection section = section_from_flat_range(fr, view);
2718
2719 if (listener->region_add) {
2720 listener->region_add(listener, &section);
2721 }
2722 if (fr->dirty_log_mask && listener->log_start) {
2723 listener->log_start(listener, &section, 0, fr->dirty_log_mask);
2724 }
2725 }
2726 if (listener->commit) {
2727 listener->commit(listener);
2728 }
2729 flatview_unref(view);
2730 }
2731
2732 static void listener_del_address_space(MemoryListener *listener,
2733 AddressSpace *as)
2734 {
2735 FlatView *view;
2736 FlatRange *fr;
2737
2738 if (listener->begin) {
2739 listener->begin(listener);
2740 }
2741 view = address_space_get_flatview(as);
2742 FOR_EACH_FLAT_RANGE(fr, view) {
2743 MemoryRegionSection section = section_from_flat_range(fr, view);
2744
2745 if (fr->dirty_log_mask && listener->log_stop) {
2746 listener->log_stop(listener, &section, fr->dirty_log_mask, 0);
2747 }
2748 if (listener->region_del) {
2749 listener->region_del(listener, &section);
2750 }
2751 }
2752 if (listener->commit) {
2753 listener->commit(listener);
2754 }
2755 flatview_unref(view);
2756 }
2757
2758 void memory_listener_register(MemoryListener *listener, AddressSpace *as)
2759 {
2760 MemoryListener *other = NULL;
2761
2762 listener->address_space = as;
2763 if (QTAILQ_EMPTY(&memory_listeners)
2764 || listener->priority >= QTAILQ_LAST(&memory_listeners)->priority) {
2765 QTAILQ_INSERT_TAIL(&memory_listeners, listener, link);
2766 } else {
2767 QTAILQ_FOREACH(other, &memory_listeners, link) {
2768 if (listener->priority < other->priority) {
2769 break;
2770 }
2771 }
2772 QTAILQ_INSERT_BEFORE(other, listener, link);
2773 }
2774
2775 if (QTAILQ_EMPTY(&as->listeners)
2776 || listener->priority >= QTAILQ_LAST(&as->listeners)->priority) {
2777 QTAILQ_INSERT_TAIL(&as->listeners, listener, link_as);
2778 } else {
2779 QTAILQ_FOREACH(other, &as->listeners, link_as) {
2780 if (listener->priority < other->priority) {
2781 break;
2782 }
2783 }
2784 QTAILQ_INSERT_BEFORE(other, listener, link_as);
2785 }
2786
2787 listener_add_address_space(listener, as);
2788 }
2789
2790 void memory_listener_unregister(MemoryListener *listener)
2791 {
2792 if (!listener->address_space) {
2793 return;
2794 }
2795
2796 listener_del_address_space(listener, listener->address_space);
2797 QTAILQ_REMOVE(&memory_listeners, listener, link);
2798 QTAILQ_REMOVE(&listener->address_space->listeners, listener, link_as);
2799 listener->address_space = NULL;
2800 }
2801
2802 void address_space_remove_listeners(AddressSpace *as)
2803 {
2804 while (!QTAILQ_EMPTY(&as->listeners)) {
2805 memory_listener_unregister(QTAILQ_FIRST(&as->listeners));
2806 }
2807 }
2808
2809 void address_space_init(AddressSpace *as, MemoryRegion *root, const char *name)
2810 {
2811 memory_region_ref(root);
2812 as->root = root;
2813 as->current_map = NULL;
2814 as->ioeventfd_nb = 0;
2815 as->ioeventfds = NULL;
2816 QTAILQ_INIT(&as->listeners);
2817 QTAILQ_INSERT_TAIL(&address_spaces, as, address_spaces_link);
2818 as->name = g_strdup(name ? name : "anonymous");
2819 address_space_update_topology(as);
2820 address_space_update_ioeventfds(as);
2821 }
2822
2823 static void do_address_space_destroy(AddressSpace *as)
2824 {
2825 assert(QTAILQ_EMPTY(&as->listeners));
2826
2827 flatview_unref(as->current_map);
2828 g_free(as->name);
2829 g_free(as->ioeventfds);
2830 memory_region_unref(as->root);
2831 }
2832
2833 void address_space_destroy(AddressSpace *as)
2834 {
2835 MemoryRegion *root = as->root;
2836
2837 /* Flush out anything from MemoryListeners listening in on this */
2838 memory_region_transaction_begin();
2839 as->root = NULL;
2840 memory_region_transaction_commit();
2841 QTAILQ_REMOVE(&address_spaces, as, address_spaces_link);
2842
2843 /* At this point, as->dispatch and as->current_map are dummy
2844 * entries that the guest should never use. Wait for the old
2845 * values to expire before freeing the data.
2846 */
2847 as->root = root;
2848 call_rcu(as, do_address_space_destroy, rcu);
2849 }
2850
2851 static const char *memory_region_type(MemoryRegion *mr)
2852 {
2853 if (mr->alias) {
2854 return memory_region_type(mr->alias);
2855 }
2856 if (memory_region_is_ram_device(mr)) {
2857 return "ramd";
2858 } else if (memory_region_is_romd(mr)) {
2859 return "romd";
2860 } else if (memory_region_is_rom(mr)) {
2861 return "rom";
2862 } else if (memory_region_is_ram(mr)) {
2863 return "ram";
2864 } else {
2865 return "i/o";
2866 }
2867 }
2868
2869 typedef struct MemoryRegionList MemoryRegionList;
2870
2871 struct MemoryRegionList {
2872 const MemoryRegion *mr;
2873 QTAILQ_ENTRY(MemoryRegionList) mrqueue;
2874 };
2875
2876 typedef QTAILQ_HEAD(, MemoryRegionList) MemoryRegionListHead;
2877
2878 #define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \
2879 int128_sub((size), int128_one())) : 0)
2880 #define MTREE_INDENT " "
2881
2882 static void mtree_expand_owner(const char *label, Object *obj)
2883 {
2884 DeviceState *dev = (DeviceState *) object_dynamic_cast(obj, TYPE_DEVICE);
2885
2886 qemu_printf(" %s:{%s", label, dev ? "dev" : "obj");
2887 if (dev && dev->id) {
2888 qemu_printf(" id=%s", dev->id);
2889 } else {
2890 char *canonical_path = object_get_canonical_path(obj);
2891 if (canonical_path) {
2892 qemu_printf(" path=%s", canonical_path);
2893 g_free(canonical_path);
2894 } else {
2895 qemu_printf(" type=%s", object_get_typename(obj));
2896 }
2897 }
2898 qemu_printf("}");
2899 }
2900
2901 static void mtree_print_mr_owner(const MemoryRegion *mr)
2902 {
2903 Object *owner = mr->owner;
2904 Object *parent = memory_region_owner((MemoryRegion *)mr);
2905
2906 if (!owner && !parent) {
2907 qemu_printf(" orphan");
2908 return;
2909 }
2910 if (owner) {
2911 mtree_expand_owner("owner", owner);
2912 }
2913 if (parent && parent != owner) {
2914 mtree_expand_owner("parent", parent);
2915 }
2916 }
2917
2918 static void mtree_print_mr(const MemoryRegion *mr, unsigned int level,
2919 hwaddr base,
2920 MemoryRegionListHead *alias_print_queue,
2921 bool owner, bool display_disabled)
2922 {
2923 MemoryRegionList *new_ml, *ml, *next_ml;
2924 MemoryRegionListHead submr_print_queue;
2925 const MemoryRegion *submr;
2926 unsigned int i;
2927 hwaddr cur_start, cur_end;
2928
2929 if (!mr) {
2930 return;
2931 }
2932
2933 cur_start = base + mr->addr;
2934 cur_end = cur_start + MR_SIZE(mr->size);
2935
2936 /*
2937 * Try to detect overflow of memory region. This should never
2938 * happen normally. When it happens, we dump something to warn the
2939 * user who is observing this.
2940 */
2941 if (cur_start < base || cur_end < cur_start) {
2942 qemu_printf("[DETECTED OVERFLOW!] ");
2943 }
2944
2945 if (mr->alias) {
2946 MemoryRegionList *ml;
2947 bool found = false;
2948
2949 /* check if the alias is already in the queue */
2950 QTAILQ_FOREACH(ml, alias_print_queue, mrqueue) {
2951 if (ml->mr == mr->alias) {
2952 found = true;
2953 }
2954 }
2955
2956 if (!found) {
2957 ml = g_new(MemoryRegionList, 1);
2958 ml->mr = mr->alias;
2959 QTAILQ_INSERT_TAIL(alias_print_queue, ml, mrqueue);
2960 }
2961 if (mr->enabled || display_disabled) {
2962 for (i = 0; i < level; i++) {
2963 qemu_printf(MTREE_INDENT);
2964 }
2965 qemu_printf(TARGET_FMT_plx "-" TARGET_FMT_plx
2966 " (prio %d, %s%s): alias %s @%s " TARGET_FMT_plx
2967 "-" TARGET_FMT_plx "%s",
2968 cur_start, cur_end,
2969 mr->priority,
2970 mr->nonvolatile ? "nv-" : "",
2971 memory_region_type((MemoryRegion *)mr),
2972 memory_region_name(mr),
2973 memory_region_name(mr->alias),
2974 mr->alias_offset,
2975 mr->alias_offset + MR_SIZE(mr->size),
2976 mr->enabled ? "" : " [disabled]");
2977 if (owner) {
2978 mtree_print_mr_owner(mr);
2979 }
2980 qemu_printf("\n");
2981 }
2982 } else {
2983 if (mr->enabled || display_disabled) {
2984 for (i = 0; i < level; i++) {
2985 qemu_printf(MTREE_INDENT);
2986 }
2987 qemu_printf(TARGET_FMT_plx "-" TARGET_FMT_plx
2988 " (prio %d, %s%s): %s%s",
2989 cur_start, cur_end,
2990 mr->priority,
2991 mr->nonvolatile ? "nv-" : "",
2992 memory_region_type((MemoryRegion *)mr),
2993 memory_region_name(mr),
2994 mr->enabled ? "" : " [disabled]");
2995 if (owner) {
2996 mtree_print_mr_owner(mr);
2997 }
2998 qemu_printf("\n");
2999 }
3000 }
3001
3002 QTAILQ_INIT(&submr_print_queue);
3003
3004 QTAILQ_FOREACH(submr, &mr->subregions, subregions_link) {
3005 new_ml = g_new(MemoryRegionList, 1);
3006 new_ml->mr = submr;
3007 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
3008 if (new_ml->mr->addr < ml->mr->addr ||
3009 (new_ml->mr->addr == ml->mr->addr &&
3010 new_ml->mr->priority > ml->mr->priority)) {
3011 QTAILQ_INSERT_BEFORE(ml, new_ml, mrqueue);
3012 new_ml = NULL;
3013 break;
3014 }
3015 }
3016 if (new_ml) {
3017 QTAILQ_INSERT_TAIL(&submr_print_queue, new_ml, mrqueue);
3018 }
3019 }
3020
3021 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
3022 mtree_print_mr(ml->mr, level + 1, cur_start,
3023 alias_print_queue, owner, display_disabled);
3024 }
3025
3026 QTAILQ_FOREACH_SAFE(ml, &submr_print_queue, mrqueue, next_ml) {
3027 g_free(ml);
3028 }
3029 }
3030
3031 struct FlatViewInfo {
3032 int counter;
3033 bool dispatch_tree;
3034 bool owner;
3035 AccelClass *ac;
3036 };
3037
3038 static void mtree_print_flatview(gpointer key, gpointer value,
3039 gpointer user_data)
3040 {
3041 FlatView *view = key;
3042 GArray *fv_address_spaces = value;
3043 struct FlatViewInfo *fvi = user_data;
3044 FlatRange *range = &view->ranges[0];
3045 MemoryRegion *mr;
3046 int n = view->nr;
3047 int i;
3048 AddressSpace *as;
3049
3050 qemu_printf("FlatView #%d\n", fvi->counter);
3051 ++fvi->counter;
3052
3053 for (i = 0; i < fv_address_spaces->len; ++i) {
3054 as = g_array_index(fv_address_spaces, AddressSpace*, i);
3055 qemu_printf(" AS \"%s\", root: %s",
3056 as->name, memory_region_name(as->root));
3057 if (as->root->alias) {
3058 qemu_printf(", alias %s", memory_region_name(as->root->alias));
3059 }
3060 qemu_printf("\n");
3061 }
3062
3063 qemu_printf(" Root memory region: %s\n",
3064 view->root ? memory_region_name(view->root) : "(none)");
3065
3066 if (n <= 0) {
3067 qemu_printf(MTREE_INDENT "No rendered FlatView\n\n");
3068 return;
3069 }
3070
3071 while (n--) {
3072 mr = range->mr;
3073 if (range->offset_in_region) {
3074 qemu_printf(MTREE_INDENT TARGET_FMT_plx "-" TARGET_FMT_plx
3075 " (prio %d, %s%s): %s @" TARGET_FMT_plx,
3076 int128_get64(range->addr.start),
3077 int128_get64(range->addr.start)
3078 + MR_SIZE(range->addr.size),
3079 mr->priority,
3080 range->nonvolatile ? "nv-" : "",
3081 range->readonly ? "rom" : memory_region_type(mr),
3082 memory_region_name(mr),
3083 range->offset_in_region);
3084 } else {
3085 qemu_printf(MTREE_INDENT TARGET_FMT_plx "-" TARGET_FMT_plx
3086 " (prio %d, %s%s): %s",
3087 int128_get64(range->addr.start),
3088 int128_get64(range->addr.start)
3089 + MR_SIZE(range->addr.size),
3090 mr->priority,
3091 range->nonvolatile ? "nv-" : "",
3092 range->readonly ? "rom" : memory_region_type(mr),
3093 memory_region_name(mr));
3094 }
3095 if (fvi->owner) {
3096 mtree_print_mr_owner(mr);
3097 }
3098
3099 if (fvi->ac) {
3100 for (i = 0; i < fv_address_spaces->len; ++i) {
3101 as = g_array_index(fv_address_spaces, AddressSpace*, i);
3102 if (fvi->ac->has_memory(current_machine, as,
3103 int128_get64(range->addr.start),
3104 MR_SIZE(range->addr.size) + 1)) {
3105 qemu_printf(" %s", fvi->ac->name);
3106 }
3107 }
3108 }
3109 qemu_printf("\n");
3110 range++;
3111 }
3112
3113 #if !defined(CONFIG_USER_ONLY)
3114 if (fvi->dispatch_tree && view->root) {
3115 mtree_print_dispatch(view->dispatch, view->root);
3116 }
3117 #endif
3118
3119 qemu_printf("\n");
3120 }
3121
3122 static gboolean mtree_info_flatview_free(gpointer key, gpointer value,
3123 gpointer user_data)
3124 {
3125 FlatView *view = key;
3126 GArray *fv_address_spaces = value;
3127
3128 g_array_unref(fv_address_spaces);
3129 flatview_unref(view);
3130
3131 return true;
3132 }
3133
3134 void mtree_info(bool flatview, bool dispatch_tree, bool owner, bool disabled)
3135 {
3136 MemoryRegionListHead ml_head;
3137 MemoryRegionList *ml, *ml2;
3138 AddressSpace *as;
3139
3140 if (flatview) {
3141 FlatView *view;
3142 struct FlatViewInfo fvi = {
3143 .counter = 0,
3144 .dispatch_tree = dispatch_tree,
3145 .owner = owner,
3146 };
3147 GArray *fv_address_spaces;
3148 GHashTable *views = g_hash_table_new(g_direct_hash, g_direct_equal);
3149 AccelClass *ac = ACCEL_GET_CLASS(current_accel());
3150
3151 if (ac->has_memory) {
3152 fvi.ac = ac;
3153 }
3154
3155 /* Gather all FVs in one table */
3156 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
3157 view = address_space_get_flatview(as);
3158
3159 fv_address_spaces = g_hash_table_lookup(views, view);
3160 if (!fv_address_spaces) {
3161 fv_address_spaces = g_array_new(false, false, sizeof(as));
3162 g_hash_table_insert(views, view, fv_address_spaces);
3163 }
3164
3165 g_array_append_val(fv_address_spaces, as);
3166 }
3167
3168 /* Print */
3169 g_hash_table_foreach(views, mtree_print_flatview, &fvi);
3170
3171 /* Free */
3172 g_hash_table_foreach_remove(views, mtree_info_flatview_free, 0);
3173 g_hash_table_unref(views);
3174
3175 return;
3176 }
3177
3178 QTAILQ_INIT(&ml_head);
3179
3180 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
3181 qemu_printf("address-space: %s\n", as->name);
3182 mtree_print_mr(as->root, 1, 0, &ml_head, owner, disabled);
3183 qemu_printf("\n");
3184 }
3185
3186 /* print aliased regions */
3187 QTAILQ_FOREACH(ml, &ml_head, mrqueue) {
3188 qemu_printf("memory-region: %s\n", memory_region_name(ml->mr));
3189 mtree_print_mr(ml->mr, 1, 0, &ml_head, owner, disabled);
3190 qemu_printf("\n");
3191 }
3192
3193 QTAILQ_FOREACH_SAFE(ml, &ml_head, mrqueue, ml2) {
3194 g_free(ml);
3195 }
3196 }
3197
3198 void memory_region_init_ram(MemoryRegion *mr,
3199 struct Object *owner,
3200 const char *name,
3201 uint64_t size,
3202 Error **errp)
3203 {
3204 DeviceState *owner_dev;
3205 Error *err = NULL;
3206
3207 memory_region_init_ram_nomigrate(mr, owner, name, size, &err);
3208 if (err) {
3209 error_propagate(errp, err);
3210 return;
3211 }
3212 /* This will assert if owner is neither NULL nor a DeviceState.
3213 * We only want the owner here for the purposes of defining a
3214 * unique name for migration. TODO: Ideally we should implement
3215 * a naming scheme for Objects which are not DeviceStates, in
3216 * which case we can relax this restriction.
3217 */
3218 owner_dev = DEVICE(owner);
3219 vmstate_register_ram(mr, owner_dev);
3220 }
3221
3222 void memory_region_init_rom(MemoryRegion *mr,
3223 struct Object *owner,
3224 const char *name,
3225 uint64_t size,
3226 Error **errp)
3227 {
3228 DeviceState *owner_dev;
3229 Error *err = NULL;
3230
3231 memory_region_init_rom_nomigrate(mr, owner, name, size, &err);
3232 if (err) {
3233 error_propagate(errp, err);
3234 return;
3235 }
3236 /* This will assert if owner is neither NULL nor a DeviceState.
3237 * We only want the owner here for the purposes of defining a
3238 * unique name for migration. TODO: Ideally we should implement
3239 * a naming scheme for Objects which are not DeviceStates, in
3240 * which case we can relax this restriction.
3241 */
3242 owner_dev = DEVICE(owner);
3243 vmstate_register_ram(mr, owner_dev);
3244 }
3245
3246 void memory_region_init_rom_device(MemoryRegion *mr,
3247 struct Object *owner,
3248 const MemoryRegionOps *ops,
3249 void *opaque,
3250 const char *name,
3251 uint64_t size,
3252 Error **errp)
3253 {
3254 DeviceState *owner_dev;
3255 Error *err = NULL;
3256
3257 memory_region_init_rom_device_nomigrate(mr, owner, ops, opaque,
3258 name, size, &err);
3259 if (err) {
3260 error_propagate(errp, err);
3261 return;
3262 }
3263 /* This will assert if owner is neither NULL nor a DeviceState.
3264 * We only want the owner here for the purposes of defining a
3265 * unique name for migration. TODO: Ideally we should implement
3266 * a naming scheme for Objects which are not DeviceStates, in
3267 * which case we can relax this restriction.
3268 */
3269 owner_dev = DEVICE(owner);
3270 vmstate_register_ram(mr, owner_dev);
3271 }
3272
3273 /*
3274 * Support softmmu builds with CONFIG_FUZZ using a weak symbol and a stub for
3275 * the fuzz_dma_read_cb callback
3276 */
3277 #ifdef CONFIG_FUZZ
3278 void __attribute__((weak)) fuzz_dma_read_cb(size_t addr,
3279 size_t len,
3280 MemoryRegion *mr,
3281 bool is_write)
3282 {
3283 }
3284 #endif
3285
3286 static const TypeInfo memory_region_info = {
3287 .parent = TYPE_OBJECT,
3288 .name = TYPE_MEMORY_REGION,
3289 .class_size = sizeof(MemoryRegionClass),
3290 .instance_size = sizeof(MemoryRegion),
3291 .instance_init = memory_region_initfn,
3292 .instance_finalize = memory_region_finalize,
3293 };
3294
3295 static const TypeInfo iommu_memory_region_info = {
3296 .parent = TYPE_MEMORY_REGION,
3297 .name = TYPE_IOMMU_MEMORY_REGION,
3298 .class_size = sizeof(IOMMUMemoryRegionClass),
3299 .instance_size = sizeof(IOMMUMemoryRegion),
3300 .instance_init = iommu_memory_region_initfn,
3301 .abstract = true,
3302 };
3303
3304 static void memory_register_types(void)
3305 {
3306 type_register_static(&memory_region_info);
3307 type_register_static(&iommu_memory_region_info);
3308 }
3309
3310 type_init(memory_register_types)