Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20210921' into staging
[qemu.git] / softmmu / physmem.c
1 /*
2 * RAM allocation and memory access
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu-common.h"
22 #include "qapi/error.h"
23
24 #include "qemu/cutils.h"
25 #include "qemu/cacheflush.h"
26
27 #ifdef CONFIG_TCG
28 #include "hw/core/tcg-cpu-ops.h"
29 #endif /* CONFIG_TCG */
30
31 #include "exec/exec-all.h"
32 #include "exec/target_page.h"
33 #include "hw/qdev-core.h"
34 #include "hw/qdev-properties.h"
35 #include "hw/boards.h"
36 #include "hw/xen/xen.h"
37 #include "sysemu/kvm.h"
38 #include "sysemu/tcg.h"
39 #include "sysemu/qtest.h"
40 #include "qemu/timer.h"
41 #include "qemu/config-file.h"
42 #include "qemu/error-report.h"
43 #include "qemu/qemu-print.h"
44 #include "exec/memory.h"
45 #include "exec/ioport.h"
46 #include "sysemu/dma.h"
47 #include "sysemu/hostmem.h"
48 #include "sysemu/hw_accel.h"
49 #include "sysemu/xen-mapcache.h"
50 #include "trace/trace-root.h"
51
52 #ifdef CONFIG_FALLOCATE_PUNCH_HOLE
53 #include <linux/falloc.h>
54 #endif
55
56 #include "qemu/rcu_queue.h"
57 #include "qemu/main-loop.h"
58 #include "exec/translate-all.h"
59 #include "sysemu/replay.h"
60
61 #include "exec/memory-internal.h"
62 #include "exec/ram_addr.h"
63 #include "exec/log.h"
64
65 #include "qemu/pmem.h"
66
67 #include "migration/vmstate.h"
68
69 #include "qemu/range.h"
70 #ifndef _WIN32
71 #include "qemu/mmap-alloc.h"
72 #endif
73
74 #include "monitor/monitor.h"
75
76 #ifdef CONFIG_LIBDAXCTL
77 #include <daxctl/libdaxctl.h>
78 #endif
79
80 //#define DEBUG_SUBPAGE
81
82 /* ram_list is read under rcu_read_lock()/rcu_read_unlock(). Writes
83 * are protected by the ramlist lock.
84 */
85 RAMList ram_list = { .blocks = QLIST_HEAD_INITIALIZER(ram_list.blocks) };
86
87 static MemoryRegion *system_memory;
88 static MemoryRegion *system_io;
89
90 AddressSpace address_space_io;
91 AddressSpace address_space_memory;
92
93 static MemoryRegion io_mem_unassigned;
94
95 typedef struct PhysPageEntry PhysPageEntry;
96
97 struct PhysPageEntry {
98 /* How many bits skip to next level (in units of L2_SIZE). 0 for a leaf. */
99 uint32_t skip : 6;
100 /* index into phys_sections (!skip) or phys_map_nodes (skip) */
101 uint32_t ptr : 26;
102 };
103
104 #define PHYS_MAP_NODE_NIL (((uint32_t)~0) >> 6)
105
106 /* Size of the L2 (and L3, etc) page tables. */
107 #define ADDR_SPACE_BITS 64
108
109 #define P_L2_BITS 9
110 #define P_L2_SIZE (1 << P_L2_BITS)
111
112 #define P_L2_LEVELS (((ADDR_SPACE_BITS - TARGET_PAGE_BITS - 1) / P_L2_BITS) + 1)
113
114 typedef PhysPageEntry Node[P_L2_SIZE];
115
116 typedef struct PhysPageMap {
117 struct rcu_head rcu;
118
119 unsigned sections_nb;
120 unsigned sections_nb_alloc;
121 unsigned nodes_nb;
122 unsigned nodes_nb_alloc;
123 Node *nodes;
124 MemoryRegionSection *sections;
125 } PhysPageMap;
126
127 struct AddressSpaceDispatch {
128 MemoryRegionSection *mru_section;
129 /* This is a multi-level map on the physical address space.
130 * The bottom level has pointers to MemoryRegionSections.
131 */
132 PhysPageEntry phys_map;
133 PhysPageMap map;
134 };
135
136 #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
137 typedef struct subpage_t {
138 MemoryRegion iomem;
139 FlatView *fv;
140 hwaddr base;
141 uint16_t sub_section[];
142 } subpage_t;
143
144 #define PHYS_SECTION_UNASSIGNED 0
145
146 static void io_mem_init(void);
147 static void memory_map_init(void);
148 static void tcg_log_global_after_sync(MemoryListener *listener);
149 static void tcg_commit(MemoryListener *listener);
150
151 /**
152 * CPUAddressSpace: all the information a CPU needs about an AddressSpace
153 * @cpu: the CPU whose AddressSpace this is
154 * @as: the AddressSpace itself
155 * @memory_dispatch: its dispatch pointer (cached, RCU protected)
156 * @tcg_as_listener: listener for tracking changes to the AddressSpace
157 */
158 struct CPUAddressSpace {
159 CPUState *cpu;
160 AddressSpace *as;
161 struct AddressSpaceDispatch *memory_dispatch;
162 MemoryListener tcg_as_listener;
163 };
164
165 struct DirtyBitmapSnapshot {
166 ram_addr_t start;
167 ram_addr_t end;
168 unsigned long dirty[];
169 };
170
171 static void phys_map_node_reserve(PhysPageMap *map, unsigned nodes)
172 {
173 static unsigned alloc_hint = 16;
174 if (map->nodes_nb + nodes > map->nodes_nb_alloc) {
175 map->nodes_nb_alloc = MAX(alloc_hint, map->nodes_nb + nodes);
176 map->nodes = g_renew(Node, map->nodes, map->nodes_nb_alloc);
177 alloc_hint = map->nodes_nb_alloc;
178 }
179 }
180
181 static uint32_t phys_map_node_alloc(PhysPageMap *map, bool leaf)
182 {
183 unsigned i;
184 uint32_t ret;
185 PhysPageEntry e;
186 PhysPageEntry *p;
187
188 ret = map->nodes_nb++;
189 p = map->nodes[ret];
190 assert(ret != PHYS_MAP_NODE_NIL);
191 assert(ret != map->nodes_nb_alloc);
192
193 e.skip = leaf ? 0 : 1;
194 e.ptr = leaf ? PHYS_SECTION_UNASSIGNED : PHYS_MAP_NODE_NIL;
195 for (i = 0; i < P_L2_SIZE; ++i) {
196 memcpy(&p[i], &e, sizeof(e));
197 }
198 return ret;
199 }
200
201 static void phys_page_set_level(PhysPageMap *map, PhysPageEntry *lp,
202 hwaddr *index, uint64_t *nb, uint16_t leaf,
203 int level)
204 {
205 PhysPageEntry *p;
206 hwaddr step = (hwaddr)1 << (level * P_L2_BITS);
207
208 if (lp->skip && lp->ptr == PHYS_MAP_NODE_NIL) {
209 lp->ptr = phys_map_node_alloc(map, level == 0);
210 }
211 p = map->nodes[lp->ptr];
212 lp = &p[(*index >> (level * P_L2_BITS)) & (P_L2_SIZE - 1)];
213
214 while (*nb && lp < &p[P_L2_SIZE]) {
215 if ((*index & (step - 1)) == 0 && *nb >= step) {
216 lp->skip = 0;
217 lp->ptr = leaf;
218 *index += step;
219 *nb -= step;
220 } else {
221 phys_page_set_level(map, lp, index, nb, leaf, level - 1);
222 }
223 ++lp;
224 }
225 }
226
227 static void phys_page_set(AddressSpaceDispatch *d,
228 hwaddr index, uint64_t nb,
229 uint16_t leaf)
230 {
231 /* Wildly overreserve - it doesn't matter much. */
232 phys_map_node_reserve(&d->map, 3 * P_L2_LEVELS);
233
234 phys_page_set_level(&d->map, &d->phys_map, &index, &nb, leaf, P_L2_LEVELS - 1);
235 }
236
237 /* Compact a non leaf page entry. Simply detect that the entry has a single child,
238 * and update our entry so we can skip it and go directly to the destination.
239 */
240 static void phys_page_compact(PhysPageEntry *lp, Node *nodes)
241 {
242 unsigned valid_ptr = P_L2_SIZE;
243 int valid = 0;
244 PhysPageEntry *p;
245 int i;
246
247 if (lp->ptr == PHYS_MAP_NODE_NIL) {
248 return;
249 }
250
251 p = nodes[lp->ptr];
252 for (i = 0; i < P_L2_SIZE; i++) {
253 if (p[i].ptr == PHYS_MAP_NODE_NIL) {
254 continue;
255 }
256
257 valid_ptr = i;
258 valid++;
259 if (p[i].skip) {
260 phys_page_compact(&p[i], nodes);
261 }
262 }
263
264 /* We can only compress if there's only one child. */
265 if (valid != 1) {
266 return;
267 }
268
269 assert(valid_ptr < P_L2_SIZE);
270
271 /* Don't compress if it won't fit in the # of bits we have. */
272 if (P_L2_LEVELS >= (1 << 6) &&
273 lp->skip + p[valid_ptr].skip >= (1 << 6)) {
274 return;
275 }
276
277 lp->ptr = p[valid_ptr].ptr;
278 if (!p[valid_ptr].skip) {
279 /* If our only child is a leaf, make this a leaf. */
280 /* By design, we should have made this node a leaf to begin with so we
281 * should never reach here.
282 * But since it's so simple to handle this, let's do it just in case we
283 * change this rule.
284 */
285 lp->skip = 0;
286 } else {
287 lp->skip += p[valid_ptr].skip;
288 }
289 }
290
291 void address_space_dispatch_compact(AddressSpaceDispatch *d)
292 {
293 if (d->phys_map.skip) {
294 phys_page_compact(&d->phys_map, d->map.nodes);
295 }
296 }
297
298 static inline bool section_covers_addr(const MemoryRegionSection *section,
299 hwaddr addr)
300 {
301 /* Memory topology clips a memory region to [0, 2^64); size.hi > 0 means
302 * the section must cover the entire address space.
303 */
304 return int128_gethi(section->size) ||
305 range_covers_byte(section->offset_within_address_space,
306 int128_getlo(section->size), addr);
307 }
308
309 static MemoryRegionSection *phys_page_find(AddressSpaceDispatch *d, hwaddr addr)
310 {
311 PhysPageEntry lp = d->phys_map, *p;
312 Node *nodes = d->map.nodes;
313 MemoryRegionSection *sections = d->map.sections;
314 hwaddr index = addr >> TARGET_PAGE_BITS;
315 int i;
316
317 for (i = P_L2_LEVELS; lp.skip && (i -= lp.skip) >= 0;) {
318 if (lp.ptr == PHYS_MAP_NODE_NIL) {
319 return &sections[PHYS_SECTION_UNASSIGNED];
320 }
321 p = nodes[lp.ptr];
322 lp = p[(index >> (i * P_L2_BITS)) & (P_L2_SIZE - 1)];
323 }
324
325 if (section_covers_addr(&sections[lp.ptr], addr)) {
326 return &sections[lp.ptr];
327 } else {
328 return &sections[PHYS_SECTION_UNASSIGNED];
329 }
330 }
331
332 /* Called from RCU critical section */
333 static MemoryRegionSection *address_space_lookup_region(AddressSpaceDispatch *d,
334 hwaddr addr,
335 bool resolve_subpage)
336 {
337 MemoryRegionSection *section = qatomic_read(&d->mru_section);
338 subpage_t *subpage;
339
340 if (!section || section == &d->map.sections[PHYS_SECTION_UNASSIGNED] ||
341 !section_covers_addr(section, addr)) {
342 section = phys_page_find(d, addr);
343 qatomic_set(&d->mru_section, section);
344 }
345 if (resolve_subpage && section->mr->subpage) {
346 subpage = container_of(section->mr, subpage_t, iomem);
347 section = &d->map.sections[subpage->sub_section[SUBPAGE_IDX(addr)]];
348 }
349 return section;
350 }
351
352 /* Called from RCU critical section */
353 static MemoryRegionSection *
354 address_space_translate_internal(AddressSpaceDispatch *d, hwaddr addr, hwaddr *xlat,
355 hwaddr *plen, bool resolve_subpage)
356 {
357 MemoryRegionSection *section;
358 MemoryRegion *mr;
359 Int128 diff;
360
361 section = address_space_lookup_region(d, addr, resolve_subpage);
362 /* Compute offset within MemoryRegionSection */
363 addr -= section->offset_within_address_space;
364
365 /* Compute offset within MemoryRegion */
366 *xlat = addr + section->offset_within_region;
367
368 mr = section->mr;
369
370 /* MMIO registers can be expected to perform full-width accesses based only
371 * on their address, without considering adjacent registers that could
372 * decode to completely different MemoryRegions. When such registers
373 * exist (e.g. I/O ports 0xcf8 and 0xcf9 on most PC chipsets), MMIO
374 * regions overlap wildly. For this reason we cannot clamp the accesses
375 * here.
376 *
377 * If the length is small (as is the case for address_space_ldl/stl),
378 * everything works fine. If the incoming length is large, however,
379 * the caller really has to do the clamping through memory_access_size.
380 */
381 if (memory_region_is_ram(mr)) {
382 diff = int128_sub(section->size, int128_make64(addr));
383 *plen = int128_get64(int128_min(diff, int128_make64(*plen)));
384 }
385 return section;
386 }
387
388 /**
389 * address_space_translate_iommu - translate an address through an IOMMU
390 * memory region and then through the target address space.
391 *
392 * @iommu_mr: the IOMMU memory region that we start the translation from
393 * @addr: the address to be translated through the MMU
394 * @xlat: the translated address offset within the destination memory region.
395 * It cannot be %NULL.
396 * @plen_out: valid read/write length of the translated address. It
397 * cannot be %NULL.
398 * @page_mask_out: page mask for the translated address. This
399 * should only be meaningful for IOMMU translated
400 * addresses, since there may be huge pages that this bit
401 * would tell. It can be %NULL if we don't care about it.
402 * @is_write: whether the translation operation is for write
403 * @is_mmio: whether this can be MMIO, set true if it can
404 * @target_as: the address space targeted by the IOMMU
405 * @attrs: transaction attributes
406 *
407 * This function is called from RCU critical section. It is the common
408 * part of flatview_do_translate and address_space_translate_cached.
409 */
410 static MemoryRegionSection address_space_translate_iommu(IOMMUMemoryRegion *iommu_mr,
411 hwaddr *xlat,
412 hwaddr *plen_out,
413 hwaddr *page_mask_out,
414 bool is_write,
415 bool is_mmio,
416 AddressSpace **target_as,
417 MemTxAttrs attrs)
418 {
419 MemoryRegionSection *section;
420 hwaddr page_mask = (hwaddr)-1;
421
422 do {
423 hwaddr addr = *xlat;
424 IOMMUMemoryRegionClass *imrc = memory_region_get_iommu_class_nocheck(iommu_mr);
425 int iommu_idx = 0;
426 IOMMUTLBEntry iotlb;
427
428 if (imrc->attrs_to_index) {
429 iommu_idx = imrc->attrs_to_index(iommu_mr, attrs);
430 }
431
432 iotlb = imrc->translate(iommu_mr, addr, is_write ?
433 IOMMU_WO : IOMMU_RO, iommu_idx);
434
435 if (!(iotlb.perm & (1 << is_write))) {
436 goto unassigned;
437 }
438
439 addr = ((iotlb.translated_addr & ~iotlb.addr_mask)
440 | (addr & iotlb.addr_mask));
441 page_mask &= iotlb.addr_mask;
442 *plen_out = MIN(*plen_out, (addr | iotlb.addr_mask) - addr + 1);
443 *target_as = iotlb.target_as;
444
445 section = address_space_translate_internal(
446 address_space_to_dispatch(iotlb.target_as), addr, xlat,
447 plen_out, is_mmio);
448
449 iommu_mr = memory_region_get_iommu(section->mr);
450 } while (unlikely(iommu_mr));
451
452 if (page_mask_out) {
453 *page_mask_out = page_mask;
454 }
455 return *section;
456
457 unassigned:
458 return (MemoryRegionSection) { .mr = &io_mem_unassigned };
459 }
460
461 /**
462 * flatview_do_translate - translate an address in FlatView
463 *
464 * @fv: the flat view that we want to translate on
465 * @addr: the address to be translated in above address space
466 * @xlat: the translated address offset within memory region. It
467 * cannot be @NULL.
468 * @plen_out: valid read/write length of the translated address. It
469 * can be @NULL when we don't care about it.
470 * @page_mask_out: page mask for the translated address. This
471 * should only be meaningful for IOMMU translated
472 * addresses, since there may be huge pages that this bit
473 * would tell. It can be @NULL if we don't care about it.
474 * @is_write: whether the translation operation is for write
475 * @is_mmio: whether this can be MMIO, set true if it can
476 * @target_as: the address space targeted by the IOMMU
477 * @attrs: memory transaction attributes
478 *
479 * This function is called from RCU critical section
480 */
481 static MemoryRegionSection flatview_do_translate(FlatView *fv,
482 hwaddr addr,
483 hwaddr *xlat,
484 hwaddr *plen_out,
485 hwaddr *page_mask_out,
486 bool is_write,
487 bool is_mmio,
488 AddressSpace **target_as,
489 MemTxAttrs attrs)
490 {
491 MemoryRegionSection *section;
492 IOMMUMemoryRegion *iommu_mr;
493 hwaddr plen = (hwaddr)(-1);
494
495 if (!plen_out) {
496 plen_out = &plen;
497 }
498
499 section = address_space_translate_internal(
500 flatview_to_dispatch(fv), addr, xlat,
501 plen_out, is_mmio);
502
503 iommu_mr = memory_region_get_iommu(section->mr);
504 if (unlikely(iommu_mr)) {
505 return address_space_translate_iommu(iommu_mr, xlat,
506 plen_out, page_mask_out,
507 is_write, is_mmio,
508 target_as, attrs);
509 }
510 if (page_mask_out) {
511 /* Not behind an IOMMU, use default page size. */
512 *page_mask_out = ~TARGET_PAGE_MASK;
513 }
514
515 return *section;
516 }
517
518 /* Called from RCU critical section */
519 IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
520 bool is_write, MemTxAttrs attrs)
521 {
522 MemoryRegionSection section;
523 hwaddr xlat, page_mask;
524
525 /*
526 * This can never be MMIO, and we don't really care about plen,
527 * but page mask.
528 */
529 section = flatview_do_translate(address_space_to_flatview(as), addr, &xlat,
530 NULL, &page_mask, is_write, false, &as,
531 attrs);
532
533 /* Illegal translation */
534 if (section.mr == &io_mem_unassigned) {
535 goto iotlb_fail;
536 }
537
538 /* Convert memory region offset into address space offset */
539 xlat += section.offset_within_address_space -
540 section.offset_within_region;
541
542 return (IOMMUTLBEntry) {
543 .target_as = as,
544 .iova = addr & ~page_mask,
545 .translated_addr = xlat & ~page_mask,
546 .addr_mask = page_mask,
547 /* IOTLBs are for DMAs, and DMA only allows on RAMs. */
548 .perm = IOMMU_RW,
549 };
550
551 iotlb_fail:
552 return (IOMMUTLBEntry) {0};
553 }
554
555 /* Called from RCU critical section */
556 MemoryRegion *flatview_translate(FlatView *fv, hwaddr addr, hwaddr *xlat,
557 hwaddr *plen, bool is_write,
558 MemTxAttrs attrs)
559 {
560 MemoryRegion *mr;
561 MemoryRegionSection section;
562 AddressSpace *as = NULL;
563
564 /* This can be MMIO, so setup MMIO bit. */
565 section = flatview_do_translate(fv, addr, xlat, plen, NULL,
566 is_write, true, &as, attrs);
567 mr = section.mr;
568
569 if (xen_enabled() && memory_access_is_direct(mr, is_write)) {
570 hwaddr page = ((addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE) - addr;
571 *plen = MIN(page, *plen);
572 }
573
574 return mr;
575 }
576
577 typedef struct TCGIOMMUNotifier {
578 IOMMUNotifier n;
579 MemoryRegion *mr;
580 CPUState *cpu;
581 int iommu_idx;
582 bool active;
583 } TCGIOMMUNotifier;
584
585 static void tcg_iommu_unmap_notify(IOMMUNotifier *n, IOMMUTLBEntry *iotlb)
586 {
587 TCGIOMMUNotifier *notifier = container_of(n, TCGIOMMUNotifier, n);
588
589 if (!notifier->active) {
590 return;
591 }
592 tlb_flush(notifier->cpu);
593 notifier->active = false;
594 /* We leave the notifier struct on the list to avoid reallocating it later.
595 * Generally the number of IOMMUs a CPU deals with will be small.
596 * In any case we can't unregister the iommu notifier from a notify
597 * callback.
598 */
599 }
600
601 static void tcg_register_iommu_notifier(CPUState *cpu,
602 IOMMUMemoryRegion *iommu_mr,
603 int iommu_idx)
604 {
605 /* Make sure this CPU has an IOMMU notifier registered for this
606 * IOMMU/IOMMU index combination, so that we can flush its TLB
607 * when the IOMMU tells us the mappings we've cached have changed.
608 */
609 MemoryRegion *mr = MEMORY_REGION(iommu_mr);
610 TCGIOMMUNotifier *notifier = NULL;
611 int i;
612
613 for (i = 0; i < cpu->iommu_notifiers->len; i++) {
614 notifier = g_array_index(cpu->iommu_notifiers, TCGIOMMUNotifier *, i);
615 if (notifier->mr == mr && notifier->iommu_idx == iommu_idx) {
616 break;
617 }
618 }
619 if (i == cpu->iommu_notifiers->len) {
620 /* Not found, add a new entry at the end of the array */
621 cpu->iommu_notifiers = g_array_set_size(cpu->iommu_notifiers, i + 1);
622 notifier = g_new0(TCGIOMMUNotifier, 1);
623 g_array_index(cpu->iommu_notifiers, TCGIOMMUNotifier *, i) = notifier;
624
625 notifier->mr = mr;
626 notifier->iommu_idx = iommu_idx;
627 notifier->cpu = cpu;
628 /* Rather than trying to register interest in the specific part
629 * of the iommu's address space that we've accessed and then
630 * expand it later as subsequent accesses touch more of it, we
631 * just register interest in the whole thing, on the assumption
632 * that iommu reconfiguration will be rare.
633 */
634 iommu_notifier_init(&notifier->n,
635 tcg_iommu_unmap_notify,
636 IOMMU_NOTIFIER_UNMAP,
637 0,
638 HWADDR_MAX,
639 iommu_idx);
640 memory_region_register_iommu_notifier(notifier->mr, &notifier->n,
641 &error_fatal);
642 }
643
644 if (!notifier->active) {
645 notifier->active = true;
646 }
647 }
648
649 void tcg_iommu_free_notifier_list(CPUState *cpu)
650 {
651 /* Destroy the CPU's notifier list */
652 int i;
653 TCGIOMMUNotifier *notifier;
654
655 for (i = 0; i < cpu->iommu_notifiers->len; i++) {
656 notifier = g_array_index(cpu->iommu_notifiers, TCGIOMMUNotifier *, i);
657 memory_region_unregister_iommu_notifier(notifier->mr, &notifier->n);
658 g_free(notifier);
659 }
660 g_array_free(cpu->iommu_notifiers, true);
661 }
662
663 void tcg_iommu_init_notifier_list(CPUState *cpu)
664 {
665 cpu->iommu_notifiers = g_array_new(false, true, sizeof(TCGIOMMUNotifier *));
666 }
667
668 /* Called from RCU critical section */
669 MemoryRegionSection *
670 address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr,
671 hwaddr *xlat, hwaddr *plen,
672 MemTxAttrs attrs, int *prot)
673 {
674 MemoryRegionSection *section;
675 IOMMUMemoryRegion *iommu_mr;
676 IOMMUMemoryRegionClass *imrc;
677 IOMMUTLBEntry iotlb;
678 int iommu_idx;
679 AddressSpaceDispatch *d =
680 qatomic_rcu_read(&cpu->cpu_ases[asidx].memory_dispatch);
681
682 for (;;) {
683 section = address_space_translate_internal(d, addr, &addr, plen, false);
684
685 iommu_mr = memory_region_get_iommu(section->mr);
686 if (!iommu_mr) {
687 break;
688 }
689
690 imrc = memory_region_get_iommu_class_nocheck(iommu_mr);
691
692 iommu_idx = imrc->attrs_to_index(iommu_mr, attrs);
693 tcg_register_iommu_notifier(cpu, iommu_mr, iommu_idx);
694 /* We need all the permissions, so pass IOMMU_NONE so the IOMMU
695 * doesn't short-cut its translation table walk.
696 */
697 iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE, iommu_idx);
698 addr = ((iotlb.translated_addr & ~iotlb.addr_mask)
699 | (addr & iotlb.addr_mask));
700 /* Update the caller's prot bits to remove permissions the IOMMU
701 * is giving us a failure response for. If we get down to no
702 * permissions left at all we can give up now.
703 */
704 if (!(iotlb.perm & IOMMU_RO)) {
705 *prot &= ~(PAGE_READ | PAGE_EXEC);
706 }
707 if (!(iotlb.perm & IOMMU_WO)) {
708 *prot &= ~PAGE_WRITE;
709 }
710
711 if (!*prot) {
712 goto translate_fail;
713 }
714
715 d = flatview_to_dispatch(address_space_to_flatview(iotlb.target_as));
716 }
717
718 assert(!memory_region_is_iommu(section->mr));
719 *xlat = addr;
720 return section;
721
722 translate_fail:
723 return &d->map.sections[PHYS_SECTION_UNASSIGNED];
724 }
725
726 void cpu_address_space_init(CPUState *cpu, int asidx,
727 const char *prefix, MemoryRegion *mr)
728 {
729 CPUAddressSpace *newas;
730 AddressSpace *as = g_new0(AddressSpace, 1);
731 char *as_name;
732
733 assert(mr);
734 as_name = g_strdup_printf("%s-%d", prefix, cpu->cpu_index);
735 address_space_init(as, mr, as_name);
736 g_free(as_name);
737
738 /* Target code should have set num_ases before calling us */
739 assert(asidx < cpu->num_ases);
740
741 if (asidx == 0) {
742 /* address space 0 gets the convenience alias */
743 cpu->as = as;
744 }
745
746 /* KVM cannot currently support multiple address spaces. */
747 assert(asidx == 0 || !kvm_enabled());
748
749 if (!cpu->cpu_ases) {
750 cpu->cpu_ases = g_new0(CPUAddressSpace, cpu->num_ases);
751 }
752
753 newas = &cpu->cpu_ases[asidx];
754 newas->cpu = cpu;
755 newas->as = as;
756 if (tcg_enabled()) {
757 newas->tcg_as_listener.log_global_after_sync = tcg_log_global_after_sync;
758 newas->tcg_as_listener.commit = tcg_commit;
759 memory_listener_register(&newas->tcg_as_listener, as);
760 }
761 }
762
763 AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx)
764 {
765 /* Return the AddressSpace corresponding to the specified index */
766 return cpu->cpu_ases[asidx].as;
767 }
768
769 /* Add a watchpoint. */
770 int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
771 int flags, CPUWatchpoint **watchpoint)
772 {
773 CPUWatchpoint *wp;
774 vaddr in_page;
775
776 /* forbid ranges which are empty or run off the end of the address space */
777 if (len == 0 || (addr + len - 1) < addr) {
778 error_report("tried to set invalid watchpoint at %"
779 VADDR_PRIx ", len=%" VADDR_PRIu, addr, len);
780 return -EINVAL;
781 }
782 wp = g_malloc(sizeof(*wp));
783
784 wp->vaddr = addr;
785 wp->len = len;
786 wp->flags = flags;
787
788 /* keep all GDB-injected watchpoints in front */
789 if (flags & BP_GDB) {
790 QTAILQ_INSERT_HEAD(&cpu->watchpoints, wp, entry);
791 } else {
792 QTAILQ_INSERT_TAIL(&cpu->watchpoints, wp, entry);
793 }
794
795 in_page = -(addr | TARGET_PAGE_MASK);
796 if (len <= in_page) {
797 tlb_flush_page(cpu, addr);
798 } else {
799 tlb_flush(cpu);
800 }
801
802 if (watchpoint)
803 *watchpoint = wp;
804 return 0;
805 }
806
807 /* Remove a specific watchpoint. */
808 int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len,
809 int flags)
810 {
811 CPUWatchpoint *wp;
812
813 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
814 if (addr == wp->vaddr && len == wp->len
815 && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) {
816 cpu_watchpoint_remove_by_ref(cpu, wp);
817 return 0;
818 }
819 }
820 return -ENOENT;
821 }
822
823 /* Remove a specific watchpoint by reference. */
824 void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint)
825 {
826 QTAILQ_REMOVE(&cpu->watchpoints, watchpoint, entry);
827
828 tlb_flush_page(cpu, watchpoint->vaddr);
829
830 g_free(watchpoint);
831 }
832
833 /* Remove all matching watchpoints. */
834 void cpu_watchpoint_remove_all(CPUState *cpu, int mask)
835 {
836 CPUWatchpoint *wp, *next;
837
838 QTAILQ_FOREACH_SAFE(wp, &cpu->watchpoints, entry, next) {
839 if (wp->flags & mask) {
840 cpu_watchpoint_remove_by_ref(cpu, wp);
841 }
842 }
843 }
844
845 #ifdef CONFIG_TCG
846 /* Return true if this watchpoint address matches the specified
847 * access (ie the address range covered by the watchpoint overlaps
848 * partially or completely with the address range covered by the
849 * access).
850 */
851 static inline bool watchpoint_address_matches(CPUWatchpoint *wp,
852 vaddr addr, vaddr len)
853 {
854 /* We know the lengths are non-zero, but a little caution is
855 * required to avoid errors in the case where the range ends
856 * exactly at the top of the address space and so addr + len
857 * wraps round to zero.
858 */
859 vaddr wpend = wp->vaddr + wp->len - 1;
860 vaddr addrend = addr + len - 1;
861
862 return !(addr > wpend || wp->vaddr > addrend);
863 }
864
865 /* Return flags for watchpoints that match addr + prot. */
866 int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len)
867 {
868 CPUWatchpoint *wp;
869 int ret = 0;
870
871 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
872 if (watchpoint_address_matches(wp, addr, len)) {
873 ret |= wp->flags;
874 }
875 }
876 return ret;
877 }
878
879 /* Generate a debug exception if a watchpoint has been hit. */
880 void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
881 MemTxAttrs attrs, int flags, uintptr_t ra)
882 {
883 CPUClass *cc = CPU_GET_CLASS(cpu);
884 CPUWatchpoint *wp;
885
886 assert(tcg_enabled());
887 if (cpu->watchpoint_hit) {
888 /*
889 * We re-entered the check after replacing the TB.
890 * Now raise the debug interrupt so that it will
891 * trigger after the current instruction.
892 */
893 qemu_mutex_lock_iothread();
894 cpu_interrupt(cpu, CPU_INTERRUPT_DEBUG);
895 qemu_mutex_unlock_iothread();
896 return;
897 }
898
899 if (cc->tcg_ops->adjust_watchpoint_address) {
900 /* this is currently used only by ARM BE32 */
901 addr = cc->tcg_ops->adjust_watchpoint_address(cpu, addr, len);
902 }
903 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
904 if (watchpoint_address_matches(wp, addr, len)
905 && (wp->flags & flags)) {
906 if (replay_running_debug()) {
907 /*
908 * replay_breakpoint reads icount.
909 * Force recompile to succeed, because icount may
910 * be read only at the end of the block.
911 */
912 if (!cpu->can_do_io) {
913 /* Force execution of one insn next time. */
914 cpu->cflags_next_tb = 1 | CF_LAST_IO | curr_cflags(cpu);
915 cpu_loop_exit_restore(cpu, ra);
916 }
917 /*
918 * Don't process the watchpoints when we are
919 * in a reverse debugging operation.
920 */
921 replay_breakpoint();
922 return;
923 }
924 if (flags == BP_MEM_READ) {
925 wp->flags |= BP_WATCHPOINT_HIT_READ;
926 } else {
927 wp->flags |= BP_WATCHPOINT_HIT_WRITE;
928 }
929 wp->hitaddr = MAX(addr, wp->vaddr);
930 wp->hitattrs = attrs;
931 if (!cpu->watchpoint_hit) {
932 if (wp->flags & BP_CPU && cc->tcg_ops->debug_check_watchpoint &&
933 !cc->tcg_ops->debug_check_watchpoint(cpu, wp)) {
934 wp->flags &= ~BP_WATCHPOINT_HIT;
935 continue;
936 }
937 cpu->watchpoint_hit = wp;
938
939 mmap_lock();
940 tb_check_watchpoint(cpu, ra);
941 if (wp->flags & BP_STOP_BEFORE_ACCESS) {
942 cpu->exception_index = EXCP_DEBUG;
943 mmap_unlock();
944 cpu_loop_exit_restore(cpu, ra);
945 } else {
946 /* Force execution of one insn next time. */
947 cpu->cflags_next_tb = 1 | curr_cflags(cpu);
948 mmap_unlock();
949 if (ra) {
950 cpu_restore_state(cpu, ra, true);
951 }
952 cpu_loop_exit_noexc(cpu);
953 }
954 }
955 } else {
956 wp->flags &= ~BP_WATCHPOINT_HIT;
957 }
958 }
959 }
960
961 #endif /* CONFIG_TCG */
962
963 /* Called from RCU critical section */
964 static RAMBlock *qemu_get_ram_block(ram_addr_t addr)
965 {
966 RAMBlock *block;
967
968 block = qatomic_rcu_read(&ram_list.mru_block);
969 if (block && addr - block->offset < block->max_length) {
970 return block;
971 }
972 RAMBLOCK_FOREACH(block) {
973 if (addr - block->offset < block->max_length) {
974 goto found;
975 }
976 }
977
978 fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr);
979 abort();
980
981 found:
982 /* It is safe to write mru_block outside the iothread lock. This
983 * is what happens:
984 *
985 * mru_block = xxx
986 * rcu_read_unlock()
987 * xxx removed from list
988 * rcu_read_lock()
989 * read mru_block
990 * mru_block = NULL;
991 * call_rcu(reclaim_ramblock, xxx);
992 * rcu_read_unlock()
993 *
994 * qatomic_rcu_set is not needed here. The block was already published
995 * when it was placed into the list. Here we're just making an extra
996 * copy of the pointer.
997 */
998 ram_list.mru_block = block;
999 return block;
1000 }
1001
1002 static void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length)
1003 {
1004 CPUState *cpu;
1005 ram_addr_t start1;
1006 RAMBlock *block;
1007 ram_addr_t end;
1008
1009 assert(tcg_enabled());
1010 end = TARGET_PAGE_ALIGN(start + length);
1011 start &= TARGET_PAGE_MASK;
1012
1013 RCU_READ_LOCK_GUARD();
1014 block = qemu_get_ram_block(start);
1015 assert(block == qemu_get_ram_block(end - 1));
1016 start1 = (uintptr_t)ramblock_ptr(block, start - block->offset);
1017 CPU_FOREACH(cpu) {
1018 tlb_reset_dirty(cpu, start1, length);
1019 }
1020 }
1021
1022 /* Note: start and end must be within the same ram block. */
1023 bool cpu_physical_memory_test_and_clear_dirty(ram_addr_t start,
1024 ram_addr_t length,
1025 unsigned client)
1026 {
1027 DirtyMemoryBlocks *blocks;
1028 unsigned long end, page, start_page;
1029 bool dirty = false;
1030 RAMBlock *ramblock;
1031 uint64_t mr_offset, mr_size;
1032
1033 if (length == 0) {
1034 return false;
1035 }
1036
1037 end = TARGET_PAGE_ALIGN(start + length) >> TARGET_PAGE_BITS;
1038 start_page = start >> TARGET_PAGE_BITS;
1039 page = start_page;
1040
1041 WITH_RCU_READ_LOCK_GUARD() {
1042 blocks = qatomic_rcu_read(&ram_list.dirty_memory[client]);
1043 ramblock = qemu_get_ram_block(start);
1044 /* Range sanity check on the ramblock */
1045 assert(start >= ramblock->offset &&
1046 start + length <= ramblock->offset + ramblock->used_length);
1047
1048 while (page < end) {
1049 unsigned long idx = page / DIRTY_MEMORY_BLOCK_SIZE;
1050 unsigned long offset = page % DIRTY_MEMORY_BLOCK_SIZE;
1051 unsigned long num = MIN(end - page,
1052 DIRTY_MEMORY_BLOCK_SIZE - offset);
1053
1054 dirty |= bitmap_test_and_clear_atomic(blocks->blocks[idx],
1055 offset, num);
1056 page += num;
1057 }
1058
1059 mr_offset = (ram_addr_t)(start_page << TARGET_PAGE_BITS) - ramblock->offset;
1060 mr_size = (end - start_page) << TARGET_PAGE_BITS;
1061 memory_region_clear_dirty_bitmap(ramblock->mr, mr_offset, mr_size);
1062 }
1063
1064 if (dirty && tcg_enabled()) {
1065 tlb_reset_dirty_range_all(start, length);
1066 }
1067
1068 return dirty;
1069 }
1070
1071 DirtyBitmapSnapshot *cpu_physical_memory_snapshot_and_clear_dirty
1072 (MemoryRegion *mr, hwaddr offset, hwaddr length, unsigned client)
1073 {
1074 DirtyMemoryBlocks *blocks;
1075 ram_addr_t start = memory_region_get_ram_addr(mr) + offset;
1076 unsigned long align = 1UL << (TARGET_PAGE_BITS + BITS_PER_LEVEL);
1077 ram_addr_t first = QEMU_ALIGN_DOWN(start, align);
1078 ram_addr_t last = QEMU_ALIGN_UP(start + length, align);
1079 DirtyBitmapSnapshot *snap;
1080 unsigned long page, end, dest;
1081
1082 snap = g_malloc0(sizeof(*snap) +
1083 ((last - first) >> (TARGET_PAGE_BITS + 3)));
1084 snap->start = first;
1085 snap->end = last;
1086
1087 page = first >> TARGET_PAGE_BITS;
1088 end = last >> TARGET_PAGE_BITS;
1089 dest = 0;
1090
1091 WITH_RCU_READ_LOCK_GUARD() {
1092 blocks = qatomic_rcu_read(&ram_list.dirty_memory[client]);
1093
1094 while (page < end) {
1095 unsigned long idx = page / DIRTY_MEMORY_BLOCK_SIZE;
1096 unsigned long offset = page % DIRTY_MEMORY_BLOCK_SIZE;
1097 unsigned long num = MIN(end - page,
1098 DIRTY_MEMORY_BLOCK_SIZE - offset);
1099
1100 assert(QEMU_IS_ALIGNED(offset, (1 << BITS_PER_LEVEL)));
1101 assert(QEMU_IS_ALIGNED(num, (1 << BITS_PER_LEVEL)));
1102 offset >>= BITS_PER_LEVEL;
1103
1104 bitmap_copy_and_clear_atomic(snap->dirty + dest,
1105 blocks->blocks[idx] + offset,
1106 num);
1107 page += num;
1108 dest += num >> BITS_PER_LEVEL;
1109 }
1110 }
1111
1112 if (tcg_enabled()) {
1113 tlb_reset_dirty_range_all(start, length);
1114 }
1115
1116 memory_region_clear_dirty_bitmap(mr, offset, length);
1117
1118 return snap;
1119 }
1120
1121 bool cpu_physical_memory_snapshot_get_dirty(DirtyBitmapSnapshot *snap,
1122 ram_addr_t start,
1123 ram_addr_t length)
1124 {
1125 unsigned long page, end;
1126
1127 assert(start >= snap->start);
1128 assert(start + length <= snap->end);
1129
1130 end = TARGET_PAGE_ALIGN(start + length - snap->start) >> TARGET_PAGE_BITS;
1131 page = (start - snap->start) >> TARGET_PAGE_BITS;
1132
1133 while (page < end) {
1134 if (test_bit(page, snap->dirty)) {
1135 return true;
1136 }
1137 page++;
1138 }
1139 return false;
1140 }
1141
1142 /* Called from RCU critical section */
1143 hwaddr memory_region_section_get_iotlb(CPUState *cpu,
1144 MemoryRegionSection *section)
1145 {
1146 AddressSpaceDispatch *d = flatview_to_dispatch(section->fv);
1147 return section - d->map.sections;
1148 }
1149
1150 static int subpage_register(subpage_t *mmio, uint32_t start, uint32_t end,
1151 uint16_t section);
1152 static subpage_t *subpage_init(FlatView *fv, hwaddr base);
1153
1154 static uint16_t phys_section_add(PhysPageMap *map,
1155 MemoryRegionSection *section)
1156 {
1157 /* The physical section number is ORed with a page-aligned
1158 * pointer to produce the iotlb entries. Thus it should
1159 * never overflow into the page-aligned value.
1160 */
1161 assert(map->sections_nb < TARGET_PAGE_SIZE);
1162
1163 if (map->sections_nb == map->sections_nb_alloc) {
1164 map->sections_nb_alloc = MAX(map->sections_nb_alloc * 2, 16);
1165 map->sections = g_renew(MemoryRegionSection, map->sections,
1166 map->sections_nb_alloc);
1167 }
1168 map->sections[map->sections_nb] = *section;
1169 memory_region_ref(section->mr);
1170 return map->sections_nb++;
1171 }
1172
1173 static void phys_section_destroy(MemoryRegion *mr)
1174 {
1175 bool have_sub_page = mr->subpage;
1176
1177 memory_region_unref(mr);
1178
1179 if (have_sub_page) {
1180 subpage_t *subpage = container_of(mr, subpage_t, iomem);
1181 object_unref(OBJECT(&subpage->iomem));
1182 g_free(subpage);
1183 }
1184 }
1185
1186 static void phys_sections_free(PhysPageMap *map)
1187 {
1188 while (map->sections_nb > 0) {
1189 MemoryRegionSection *section = &map->sections[--map->sections_nb];
1190 phys_section_destroy(section->mr);
1191 }
1192 g_free(map->sections);
1193 g_free(map->nodes);
1194 }
1195
1196 static void register_subpage(FlatView *fv, MemoryRegionSection *section)
1197 {
1198 AddressSpaceDispatch *d = flatview_to_dispatch(fv);
1199 subpage_t *subpage;
1200 hwaddr base = section->offset_within_address_space
1201 & TARGET_PAGE_MASK;
1202 MemoryRegionSection *existing = phys_page_find(d, base);
1203 MemoryRegionSection subsection = {
1204 .offset_within_address_space = base,
1205 .size = int128_make64(TARGET_PAGE_SIZE),
1206 };
1207 hwaddr start, end;
1208
1209 assert(existing->mr->subpage || existing->mr == &io_mem_unassigned);
1210
1211 if (!(existing->mr->subpage)) {
1212 subpage = subpage_init(fv, base);
1213 subsection.fv = fv;
1214 subsection.mr = &subpage->iomem;
1215 phys_page_set(d, base >> TARGET_PAGE_BITS, 1,
1216 phys_section_add(&d->map, &subsection));
1217 } else {
1218 subpage = container_of(existing->mr, subpage_t, iomem);
1219 }
1220 start = section->offset_within_address_space & ~TARGET_PAGE_MASK;
1221 end = start + int128_get64(section->size) - 1;
1222 subpage_register(subpage, start, end,
1223 phys_section_add(&d->map, section));
1224 }
1225
1226
1227 static void register_multipage(FlatView *fv,
1228 MemoryRegionSection *section)
1229 {
1230 AddressSpaceDispatch *d = flatview_to_dispatch(fv);
1231 hwaddr start_addr = section->offset_within_address_space;
1232 uint16_t section_index = phys_section_add(&d->map, section);
1233 uint64_t num_pages = int128_get64(int128_rshift(section->size,
1234 TARGET_PAGE_BITS));
1235
1236 assert(num_pages);
1237 phys_page_set(d, start_addr >> TARGET_PAGE_BITS, num_pages, section_index);
1238 }
1239
1240 /*
1241 * The range in *section* may look like this:
1242 *
1243 * |s|PPPPPPP|s|
1244 *
1245 * where s stands for subpage and P for page.
1246 */
1247 void flatview_add_to_dispatch(FlatView *fv, MemoryRegionSection *section)
1248 {
1249 MemoryRegionSection remain = *section;
1250 Int128 page_size = int128_make64(TARGET_PAGE_SIZE);
1251
1252 /* register first subpage */
1253 if (remain.offset_within_address_space & ~TARGET_PAGE_MASK) {
1254 uint64_t left = TARGET_PAGE_ALIGN(remain.offset_within_address_space)
1255 - remain.offset_within_address_space;
1256
1257 MemoryRegionSection now = remain;
1258 now.size = int128_min(int128_make64(left), now.size);
1259 register_subpage(fv, &now);
1260 if (int128_eq(remain.size, now.size)) {
1261 return;
1262 }
1263 remain.size = int128_sub(remain.size, now.size);
1264 remain.offset_within_address_space += int128_get64(now.size);
1265 remain.offset_within_region += int128_get64(now.size);
1266 }
1267
1268 /* register whole pages */
1269 if (int128_ge(remain.size, page_size)) {
1270 MemoryRegionSection now = remain;
1271 now.size = int128_and(now.size, int128_neg(page_size));
1272 register_multipage(fv, &now);
1273 if (int128_eq(remain.size, now.size)) {
1274 return;
1275 }
1276 remain.size = int128_sub(remain.size, now.size);
1277 remain.offset_within_address_space += int128_get64(now.size);
1278 remain.offset_within_region += int128_get64(now.size);
1279 }
1280
1281 /* register last subpage */
1282 register_subpage(fv, &remain);
1283 }
1284
1285 void qemu_flush_coalesced_mmio_buffer(void)
1286 {
1287 if (kvm_enabled())
1288 kvm_flush_coalesced_mmio_buffer();
1289 }
1290
1291 void qemu_mutex_lock_ramlist(void)
1292 {
1293 qemu_mutex_lock(&ram_list.mutex);
1294 }
1295
1296 void qemu_mutex_unlock_ramlist(void)
1297 {
1298 qemu_mutex_unlock(&ram_list.mutex);
1299 }
1300
1301 void ram_block_dump(Monitor *mon)
1302 {
1303 RAMBlock *block;
1304 char *psize;
1305
1306 RCU_READ_LOCK_GUARD();
1307 monitor_printf(mon, "%24s %8s %18s %18s %18s\n",
1308 "Block Name", "PSize", "Offset", "Used", "Total");
1309 RAMBLOCK_FOREACH(block) {
1310 psize = size_to_str(block->page_size);
1311 monitor_printf(mon, "%24s %8s 0x%016" PRIx64 " 0x%016" PRIx64
1312 " 0x%016" PRIx64 "\n", block->idstr, psize,
1313 (uint64_t)block->offset,
1314 (uint64_t)block->used_length,
1315 (uint64_t)block->max_length);
1316 g_free(psize);
1317 }
1318 }
1319
1320 #ifdef __linux__
1321 /*
1322 * FIXME TOCTTOU: this iterates over memory backends' mem-path, which
1323 * may or may not name the same files / on the same filesystem now as
1324 * when we actually open and map them. Iterate over the file
1325 * descriptors instead, and use qemu_fd_getpagesize().
1326 */
1327 static int find_min_backend_pagesize(Object *obj, void *opaque)
1328 {
1329 long *hpsize_min = opaque;
1330
1331 if (object_dynamic_cast(obj, TYPE_MEMORY_BACKEND)) {
1332 HostMemoryBackend *backend = MEMORY_BACKEND(obj);
1333 long hpsize = host_memory_backend_pagesize(backend);
1334
1335 if (host_memory_backend_is_mapped(backend) && (hpsize < *hpsize_min)) {
1336 *hpsize_min = hpsize;
1337 }
1338 }
1339
1340 return 0;
1341 }
1342
1343 static int find_max_backend_pagesize(Object *obj, void *opaque)
1344 {
1345 long *hpsize_max = opaque;
1346
1347 if (object_dynamic_cast(obj, TYPE_MEMORY_BACKEND)) {
1348 HostMemoryBackend *backend = MEMORY_BACKEND(obj);
1349 long hpsize = host_memory_backend_pagesize(backend);
1350
1351 if (host_memory_backend_is_mapped(backend) && (hpsize > *hpsize_max)) {
1352 *hpsize_max = hpsize;
1353 }
1354 }
1355
1356 return 0;
1357 }
1358
1359 /*
1360 * TODO: We assume right now that all mapped host memory backends are
1361 * used as RAM, however some might be used for different purposes.
1362 */
1363 long qemu_minrampagesize(void)
1364 {
1365 long hpsize = LONG_MAX;
1366 Object *memdev_root = object_resolve_path("/objects", NULL);
1367
1368 object_child_foreach(memdev_root, find_min_backend_pagesize, &hpsize);
1369 return hpsize;
1370 }
1371
1372 long qemu_maxrampagesize(void)
1373 {
1374 long pagesize = 0;
1375 Object *memdev_root = object_resolve_path("/objects", NULL);
1376
1377 object_child_foreach(memdev_root, find_max_backend_pagesize, &pagesize);
1378 return pagesize;
1379 }
1380 #else
1381 long qemu_minrampagesize(void)
1382 {
1383 return qemu_real_host_page_size;
1384 }
1385 long qemu_maxrampagesize(void)
1386 {
1387 return qemu_real_host_page_size;
1388 }
1389 #endif
1390
1391 #ifdef CONFIG_POSIX
1392 static int64_t get_file_size(int fd)
1393 {
1394 int64_t size;
1395 #if defined(__linux__)
1396 struct stat st;
1397
1398 if (fstat(fd, &st) < 0) {
1399 return -errno;
1400 }
1401
1402 /* Special handling for devdax character devices */
1403 if (S_ISCHR(st.st_mode)) {
1404 g_autofree char *subsystem_path = NULL;
1405 g_autofree char *subsystem = NULL;
1406
1407 subsystem_path = g_strdup_printf("/sys/dev/char/%d:%d/subsystem",
1408 major(st.st_rdev), minor(st.st_rdev));
1409 subsystem = g_file_read_link(subsystem_path, NULL);
1410
1411 if (subsystem && g_str_has_suffix(subsystem, "/dax")) {
1412 g_autofree char *size_path = NULL;
1413 g_autofree char *size_str = NULL;
1414
1415 size_path = g_strdup_printf("/sys/dev/char/%d:%d/size",
1416 major(st.st_rdev), minor(st.st_rdev));
1417
1418 if (g_file_get_contents(size_path, &size_str, NULL, NULL)) {
1419 return g_ascii_strtoll(size_str, NULL, 0);
1420 }
1421 }
1422 }
1423 #endif /* defined(__linux__) */
1424
1425 /* st.st_size may be zero for special files yet lseek(2) works */
1426 size = lseek(fd, 0, SEEK_END);
1427 if (size < 0) {
1428 return -errno;
1429 }
1430 return size;
1431 }
1432
1433 static int64_t get_file_align(int fd)
1434 {
1435 int64_t align = -1;
1436 #if defined(__linux__) && defined(CONFIG_LIBDAXCTL)
1437 struct stat st;
1438
1439 if (fstat(fd, &st) < 0) {
1440 return -errno;
1441 }
1442
1443 /* Special handling for devdax character devices */
1444 if (S_ISCHR(st.st_mode)) {
1445 g_autofree char *path = NULL;
1446 g_autofree char *rpath = NULL;
1447 struct daxctl_ctx *ctx;
1448 struct daxctl_region *region;
1449 int rc = 0;
1450
1451 path = g_strdup_printf("/sys/dev/char/%d:%d",
1452 major(st.st_rdev), minor(st.st_rdev));
1453 rpath = realpath(path, NULL);
1454
1455 rc = daxctl_new(&ctx);
1456 if (rc) {
1457 return -1;
1458 }
1459
1460 daxctl_region_foreach(ctx, region) {
1461 if (strstr(rpath, daxctl_region_get_path(region))) {
1462 align = daxctl_region_get_align(region);
1463 break;
1464 }
1465 }
1466 daxctl_unref(ctx);
1467 }
1468 #endif /* defined(__linux__) && defined(CONFIG_LIBDAXCTL) */
1469
1470 return align;
1471 }
1472
1473 static int file_ram_open(const char *path,
1474 const char *region_name,
1475 bool readonly,
1476 bool *created,
1477 Error **errp)
1478 {
1479 char *filename;
1480 char *sanitized_name;
1481 char *c;
1482 int fd = -1;
1483
1484 *created = false;
1485 for (;;) {
1486 fd = open(path, readonly ? O_RDONLY : O_RDWR);
1487 if (fd >= 0) {
1488 /* @path names an existing file, use it */
1489 break;
1490 }
1491 if (errno == ENOENT) {
1492 /* @path names a file that doesn't exist, create it */
1493 fd = open(path, O_RDWR | O_CREAT | O_EXCL, 0644);
1494 if (fd >= 0) {
1495 *created = true;
1496 break;
1497 }
1498 } else if (errno == EISDIR) {
1499 /* @path names a directory, create a file there */
1500 /* Make name safe to use with mkstemp by replacing '/' with '_'. */
1501 sanitized_name = g_strdup(region_name);
1502 for (c = sanitized_name; *c != '\0'; c++) {
1503 if (*c == '/') {
1504 *c = '_';
1505 }
1506 }
1507
1508 filename = g_strdup_printf("%s/qemu_back_mem.%s.XXXXXX", path,
1509 sanitized_name);
1510 g_free(sanitized_name);
1511
1512 fd = mkstemp(filename);
1513 if (fd >= 0) {
1514 unlink(filename);
1515 g_free(filename);
1516 break;
1517 }
1518 g_free(filename);
1519 }
1520 if (errno != EEXIST && errno != EINTR) {
1521 error_setg_errno(errp, errno,
1522 "can't open backing store %s for guest RAM",
1523 path);
1524 return -1;
1525 }
1526 /*
1527 * Try again on EINTR and EEXIST. The latter happens when
1528 * something else creates the file between our two open().
1529 */
1530 }
1531
1532 return fd;
1533 }
1534
1535 static void *file_ram_alloc(RAMBlock *block,
1536 ram_addr_t memory,
1537 int fd,
1538 bool readonly,
1539 bool truncate,
1540 off_t offset,
1541 Error **errp)
1542 {
1543 uint32_t qemu_map_flags;
1544 void *area;
1545
1546 block->page_size = qemu_fd_getpagesize(fd);
1547 if (block->mr->align % block->page_size) {
1548 error_setg(errp, "alignment 0x%" PRIx64
1549 " must be multiples of page size 0x%zx",
1550 block->mr->align, block->page_size);
1551 return NULL;
1552 } else if (block->mr->align && !is_power_of_2(block->mr->align)) {
1553 error_setg(errp, "alignment 0x%" PRIx64
1554 " must be a power of two", block->mr->align);
1555 return NULL;
1556 }
1557 block->mr->align = MAX(block->page_size, block->mr->align);
1558 #if defined(__s390x__)
1559 if (kvm_enabled()) {
1560 block->mr->align = MAX(block->mr->align, QEMU_VMALLOC_ALIGN);
1561 }
1562 #endif
1563
1564 if (memory < block->page_size) {
1565 error_setg(errp, "memory size 0x" RAM_ADDR_FMT " must be equal to "
1566 "or larger than page size 0x%zx",
1567 memory, block->page_size);
1568 return NULL;
1569 }
1570
1571 memory = ROUND_UP(memory, block->page_size);
1572
1573 /*
1574 * ftruncate is not supported by hugetlbfs in older
1575 * hosts, so don't bother bailing out on errors.
1576 * If anything goes wrong with it under other filesystems,
1577 * mmap will fail.
1578 *
1579 * Do not truncate the non-empty backend file to avoid corrupting
1580 * the existing data in the file. Disabling shrinking is not
1581 * enough. For example, the current vNVDIMM implementation stores
1582 * the guest NVDIMM labels at the end of the backend file. If the
1583 * backend file is later extended, QEMU will not be able to find
1584 * those labels. Therefore, extending the non-empty backend file
1585 * is disabled as well.
1586 */
1587 if (truncate && ftruncate(fd, memory)) {
1588 perror("ftruncate");
1589 }
1590
1591 qemu_map_flags = readonly ? QEMU_MAP_READONLY : 0;
1592 qemu_map_flags |= (block->flags & RAM_SHARED) ? QEMU_MAP_SHARED : 0;
1593 qemu_map_flags |= (block->flags & RAM_PMEM) ? QEMU_MAP_SYNC : 0;
1594 qemu_map_flags |= (block->flags & RAM_NORESERVE) ? QEMU_MAP_NORESERVE : 0;
1595 area = qemu_ram_mmap(fd, memory, block->mr->align, qemu_map_flags, offset);
1596 if (area == MAP_FAILED) {
1597 error_setg_errno(errp, errno,
1598 "unable to map backing store for guest RAM");
1599 return NULL;
1600 }
1601
1602 block->fd = fd;
1603 return area;
1604 }
1605 #endif
1606
1607 /* Allocate space within the ram_addr_t space that governs the
1608 * dirty bitmaps.
1609 * Called with the ramlist lock held.
1610 */
1611 static ram_addr_t find_ram_offset(ram_addr_t size)
1612 {
1613 RAMBlock *block, *next_block;
1614 ram_addr_t offset = RAM_ADDR_MAX, mingap = RAM_ADDR_MAX;
1615
1616 assert(size != 0); /* it would hand out same offset multiple times */
1617
1618 if (QLIST_EMPTY_RCU(&ram_list.blocks)) {
1619 return 0;
1620 }
1621
1622 RAMBLOCK_FOREACH(block) {
1623 ram_addr_t candidate, next = RAM_ADDR_MAX;
1624
1625 /* Align blocks to start on a 'long' in the bitmap
1626 * which makes the bitmap sync'ing take the fast path.
1627 */
1628 candidate = block->offset + block->max_length;
1629 candidate = ROUND_UP(candidate, BITS_PER_LONG << TARGET_PAGE_BITS);
1630
1631 /* Search for the closest following block
1632 * and find the gap.
1633 */
1634 RAMBLOCK_FOREACH(next_block) {
1635 if (next_block->offset >= candidate) {
1636 next = MIN(next, next_block->offset);
1637 }
1638 }
1639
1640 /* If it fits remember our place and remember the size
1641 * of gap, but keep going so that we might find a smaller
1642 * gap to fill so avoiding fragmentation.
1643 */
1644 if (next - candidate >= size && next - candidate < mingap) {
1645 offset = candidate;
1646 mingap = next - candidate;
1647 }
1648
1649 trace_find_ram_offset_loop(size, candidate, offset, next, mingap);
1650 }
1651
1652 if (offset == RAM_ADDR_MAX) {
1653 fprintf(stderr, "Failed to find gap of requested size: %" PRIu64 "\n",
1654 (uint64_t)size);
1655 abort();
1656 }
1657
1658 trace_find_ram_offset(size, offset);
1659
1660 return offset;
1661 }
1662
1663 static unsigned long last_ram_page(void)
1664 {
1665 RAMBlock *block;
1666 ram_addr_t last = 0;
1667
1668 RCU_READ_LOCK_GUARD();
1669 RAMBLOCK_FOREACH(block) {
1670 last = MAX(last, block->offset + block->max_length);
1671 }
1672 return last >> TARGET_PAGE_BITS;
1673 }
1674
1675 static void qemu_ram_setup_dump(void *addr, ram_addr_t size)
1676 {
1677 int ret;
1678
1679 /* Use MADV_DONTDUMP, if user doesn't want the guest memory in the core */
1680 if (!machine_dump_guest_core(current_machine)) {
1681 ret = qemu_madvise(addr, size, QEMU_MADV_DONTDUMP);
1682 if (ret) {
1683 perror("qemu_madvise");
1684 fprintf(stderr, "madvise doesn't support MADV_DONTDUMP, "
1685 "but dump_guest_core=off specified\n");
1686 }
1687 }
1688 }
1689
1690 const char *qemu_ram_get_idstr(RAMBlock *rb)
1691 {
1692 return rb->idstr;
1693 }
1694
1695 void *qemu_ram_get_host_addr(RAMBlock *rb)
1696 {
1697 return rb->host;
1698 }
1699
1700 ram_addr_t qemu_ram_get_offset(RAMBlock *rb)
1701 {
1702 return rb->offset;
1703 }
1704
1705 ram_addr_t qemu_ram_get_used_length(RAMBlock *rb)
1706 {
1707 return rb->used_length;
1708 }
1709
1710 ram_addr_t qemu_ram_get_max_length(RAMBlock *rb)
1711 {
1712 return rb->max_length;
1713 }
1714
1715 bool qemu_ram_is_shared(RAMBlock *rb)
1716 {
1717 return rb->flags & RAM_SHARED;
1718 }
1719
1720 bool qemu_ram_is_noreserve(RAMBlock *rb)
1721 {
1722 return rb->flags & RAM_NORESERVE;
1723 }
1724
1725 /* Note: Only set at the start of postcopy */
1726 bool qemu_ram_is_uf_zeroable(RAMBlock *rb)
1727 {
1728 return rb->flags & RAM_UF_ZEROPAGE;
1729 }
1730
1731 void qemu_ram_set_uf_zeroable(RAMBlock *rb)
1732 {
1733 rb->flags |= RAM_UF_ZEROPAGE;
1734 }
1735
1736 bool qemu_ram_is_migratable(RAMBlock *rb)
1737 {
1738 return rb->flags & RAM_MIGRATABLE;
1739 }
1740
1741 void qemu_ram_set_migratable(RAMBlock *rb)
1742 {
1743 rb->flags |= RAM_MIGRATABLE;
1744 }
1745
1746 void qemu_ram_unset_migratable(RAMBlock *rb)
1747 {
1748 rb->flags &= ~RAM_MIGRATABLE;
1749 }
1750
1751 /* Called with iothread lock held. */
1752 void qemu_ram_set_idstr(RAMBlock *new_block, const char *name, DeviceState *dev)
1753 {
1754 RAMBlock *block;
1755
1756 assert(new_block);
1757 assert(!new_block->idstr[0]);
1758
1759 if (dev) {
1760 char *id = qdev_get_dev_path(dev);
1761 if (id) {
1762 snprintf(new_block->idstr, sizeof(new_block->idstr), "%s/", id);
1763 g_free(id);
1764 }
1765 }
1766 pstrcat(new_block->idstr, sizeof(new_block->idstr), name);
1767
1768 RCU_READ_LOCK_GUARD();
1769 RAMBLOCK_FOREACH(block) {
1770 if (block != new_block &&
1771 !strcmp(block->idstr, new_block->idstr)) {
1772 fprintf(stderr, "RAMBlock \"%s\" already registered, abort!\n",
1773 new_block->idstr);
1774 abort();
1775 }
1776 }
1777 }
1778
1779 /* Called with iothread lock held. */
1780 void qemu_ram_unset_idstr(RAMBlock *block)
1781 {
1782 /* FIXME: arch_init.c assumes that this is not called throughout
1783 * migration. Ignore the problem since hot-unplug during migration
1784 * does not work anyway.
1785 */
1786 if (block) {
1787 memset(block->idstr, 0, sizeof(block->idstr));
1788 }
1789 }
1790
1791 size_t qemu_ram_pagesize(RAMBlock *rb)
1792 {
1793 return rb->page_size;
1794 }
1795
1796 /* Returns the largest size of page in use */
1797 size_t qemu_ram_pagesize_largest(void)
1798 {
1799 RAMBlock *block;
1800 size_t largest = 0;
1801
1802 RAMBLOCK_FOREACH(block) {
1803 largest = MAX(largest, qemu_ram_pagesize(block));
1804 }
1805
1806 return largest;
1807 }
1808
1809 static int memory_try_enable_merging(void *addr, size_t len)
1810 {
1811 if (!machine_mem_merge(current_machine)) {
1812 /* disabled by the user */
1813 return 0;
1814 }
1815
1816 return qemu_madvise(addr, len, QEMU_MADV_MERGEABLE);
1817 }
1818
1819 /*
1820 * Resizing RAM while migrating can result in the migration being canceled.
1821 * Care has to be taken if the guest might have already detected the memory.
1822 *
1823 * As memory core doesn't know how is memory accessed, it is up to
1824 * resize callback to update device state and/or add assertions to detect
1825 * misuse, if necessary.
1826 */
1827 int qemu_ram_resize(RAMBlock *block, ram_addr_t newsize, Error **errp)
1828 {
1829 const ram_addr_t oldsize = block->used_length;
1830 const ram_addr_t unaligned_size = newsize;
1831
1832 assert(block);
1833
1834 newsize = HOST_PAGE_ALIGN(newsize);
1835
1836 if (block->used_length == newsize) {
1837 /*
1838 * We don't have to resize the ram block (which only knows aligned
1839 * sizes), however, we have to notify if the unaligned size changed.
1840 */
1841 if (unaligned_size != memory_region_size(block->mr)) {
1842 memory_region_set_size(block->mr, unaligned_size);
1843 if (block->resized) {
1844 block->resized(block->idstr, unaligned_size, block->host);
1845 }
1846 }
1847 return 0;
1848 }
1849
1850 if (!(block->flags & RAM_RESIZEABLE)) {
1851 error_setg_errno(errp, EINVAL,
1852 "Size mismatch: %s: 0x" RAM_ADDR_FMT
1853 " != 0x" RAM_ADDR_FMT, block->idstr,
1854 newsize, block->used_length);
1855 return -EINVAL;
1856 }
1857
1858 if (block->max_length < newsize) {
1859 error_setg_errno(errp, EINVAL,
1860 "Size too large: %s: 0x" RAM_ADDR_FMT
1861 " > 0x" RAM_ADDR_FMT, block->idstr,
1862 newsize, block->max_length);
1863 return -EINVAL;
1864 }
1865
1866 /* Notify before modifying the ram block and touching the bitmaps. */
1867 if (block->host) {
1868 ram_block_notify_resize(block->host, oldsize, newsize);
1869 }
1870
1871 cpu_physical_memory_clear_dirty_range(block->offset, block->used_length);
1872 block->used_length = newsize;
1873 cpu_physical_memory_set_dirty_range(block->offset, block->used_length,
1874 DIRTY_CLIENTS_ALL);
1875 memory_region_set_size(block->mr, unaligned_size);
1876 if (block->resized) {
1877 block->resized(block->idstr, unaligned_size, block->host);
1878 }
1879 return 0;
1880 }
1881
1882 /*
1883 * Trigger sync on the given ram block for range [start, start + length]
1884 * with the backing store if one is available.
1885 * Otherwise no-op.
1886 * @Note: this is supposed to be a synchronous op.
1887 */
1888 void qemu_ram_msync(RAMBlock *block, ram_addr_t start, ram_addr_t length)
1889 {
1890 /* The requested range should fit in within the block range */
1891 g_assert((start + length) <= block->used_length);
1892
1893 #ifdef CONFIG_LIBPMEM
1894 /* The lack of support for pmem should not block the sync */
1895 if (ramblock_is_pmem(block)) {
1896 void *addr = ramblock_ptr(block, start);
1897 pmem_persist(addr, length);
1898 return;
1899 }
1900 #endif
1901 if (block->fd >= 0) {
1902 /**
1903 * Case there is no support for PMEM or the memory has not been
1904 * specified as persistent (or is not one) - use the msync.
1905 * Less optimal but still achieves the same goal
1906 */
1907 void *addr = ramblock_ptr(block, start);
1908 if (qemu_msync(addr, length, block->fd)) {
1909 warn_report("%s: failed to sync memory range: start: "
1910 RAM_ADDR_FMT " length: " RAM_ADDR_FMT,
1911 __func__, start, length);
1912 }
1913 }
1914 }
1915
1916 /* Called with ram_list.mutex held */
1917 static void dirty_memory_extend(ram_addr_t old_ram_size,
1918 ram_addr_t new_ram_size)
1919 {
1920 ram_addr_t old_num_blocks = DIV_ROUND_UP(old_ram_size,
1921 DIRTY_MEMORY_BLOCK_SIZE);
1922 ram_addr_t new_num_blocks = DIV_ROUND_UP(new_ram_size,
1923 DIRTY_MEMORY_BLOCK_SIZE);
1924 int i;
1925
1926 /* Only need to extend if block count increased */
1927 if (new_num_blocks <= old_num_blocks) {
1928 return;
1929 }
1930
1931 for (i = 0; i < DIRTY_MEMORY_NUM; i++) {
1932 DirtyMemoryBlocks *old_blocks;
1933 DirtyMemoryBlocks *new_blocks;
1934 int j;
1935
1936 old_blocks = qatomic_rcu_read(&ram_list.dirty_memory[i]);
1937 new_blocks = g_malloc(sizeof(*new_blocks) +
1938 sizeof(new_blocks->blocks[0]) * new_num_blocks);
1939
1940 if (old_num_blocks) {
1941 memcpy(new_blocks->blocks, old_blocks->blocks,
1942 old_num_blocks * sizeof(old_blocks->blocks[0]));
1943 }
1944
1945 for (j = old_num_blocks; j < new_num_blocks; j++) {
1946 new_blocks->blocks[j] = bitmap_new(DIRTY_MEMORY_BLOCK_SIZE);
1947 }
1948
1949 qatomic_rcu_set(&ram_list.dirty_memory[i], new_blocks);
1950
1951 if (old_blocks) {
1952 g_free_rcu(old_blocks, rcu);
1953 }
1954 }
1955 }
1956
1957 static void ram_block_add(RAMBlock *new_block, Error **errp)
1958 {
1959 const bool noreserve = qemu_ram_is_noreserve(new_block);
1960 const bool shared = qemu_ram_is_shared(new_block);
1961 RAMBlock *block;
1962 RAMBlock *last_block = NULL;
1963 ram_addr_t old_ram_size, new_ram_size;
1964 Error *err = NULL;
1965
1966 old_ram_size = last_ram_page();
1967
1968 qemu_mutex_lock_ramlist();
1969 new_block->offset = find_ram_offset(new_block->max_length);
1970
1971 if (!new_block->host) {
1972 if (xen_enabled()) {
1973 xen_ram_alloc(new_block->offset, new_block->max_length,
1974 new_block->mr, &err);
1975 if (err) {
1976 error_propagate(errp, err);
1977 qemu_mutex_unlock_ramlist();
1978 return;
1979 }
1980 } else {
1981 new_block->host = qemu_anon_ram_alloc(new_block->max_length,
1982 &new_block->mr->align,
1983 shared, noreserve);
1984 if (!new_block->host) {
1985 error_setg_errno(errp, errno,
1986 "cannot set up guest memory '%s'",
1987 memory_region_name(new_block->mr));
1988 qemu_mutex_unlock_ramlist();
1989 return;
1990 }
1991 memory_try_enable_merging(new_block->host, new_block->max_length);
1992 }
1993 }
1994
1995 new_ram_size = MAX(old_ram_size,
1996 (new_block->offset + new_block->max_length) >> TARGET_PAGE_BITS);
1997 if (new_ram_size > old_ram_size) {
1998 dirty_memory_extend(old_ram_size, new_ram_size);
1999 }
2000 /* Keep the list sorted from biggest to smallest block. Unlike QTAILQ,
2001 * QLIST (which has an RCU-friendly variant) does not have insertion at
2002 * tail, so save the last element in last_block.
2003 */
2004 RAMBLOCK_FOREACH(block) {
2005 last_block = block;
2006 if (block->max_length < new_block->max_length) {
2007 break;
2008 }
2009 }
2010 if (block) {
2011 QLIST_INSERT_BEFORE_RCU(block, new_block, next);
2012 } else if (last_block) {
2013 QLIST_INSERT_AFTER_RCU(last_block, new_block, next);
2014 } else { /* list is empty */
2015 QLIST_INSERT_HEAD_RCU(&ram_list.blocks, new_block, next);
2016 }
2017 ram_list.mru_block = NULL;
2018
2019 /* Write list before version */
2020 smp_wmb();
2021 ram_list.version++;
2022 qemu_mutex_unlock_ramlist();
2023
2024 cpu_physical_memory_set_dirty_range(new_block->offset,
2025 new_block->used_length,
2026 DIRTY_CLIENTS_ALL);
2027
2028 if (new_block->host) {
2029 qemu_ram_setup_dump(new_block->host, new_block->max_length);
2030 qemu_madvise(new_block->host, new_block->max_length, QEMU_MADV_HUGEPAGE);
2031 /*
2032 * MADV_DONTFORK is also needed by KVM in absence of synchronous MMU
2033 * Configure it unless the machine is a qtest server, in which case
2034 * KVM is not used and it may be forked (eg for fuzzing purposes).
2035 */
2036 if (!qtest_enabled()) {
2037 qemu_madvise(new_block->host, new_block->max_length,
2038 QEMU_MADV_DONTFORK);
2039 }
2040 ram_block_notify_add(new_block->host, new_block->used_length,
2041 new_block->max_length);
2042 }
2043 }
2044
2045 #ifdef CONFIG_POSIX
2046 RAMBlock *qemu_ram_alloc_from_fd(ram_addr_t size, MemoryRegion *mr,
2047 uint32_t ram_flags, int fd, off_t offset,
2048 bool readonly, Error **errp)
2049 {
2050 RAMBlock *new_block;
2051 Error *local_err = NULL;
2052 int64_t file_size, file_align;
2053
2054 /* Just support these ram flags by now. */
2055 assert((ram_flags & ~(RAM_SHARED | RAM_PMEM | RAM_NORESERVE)) == 0);
2056
2057 if (xen_enabled()) {
2058 error_setg(errp, "-mem-path not supported with Xen");
2059 return NULL;
2060 }
2061
2062 if (kvm_enabled() && !kvm_has_sync_mmu()) {
2063 error_setg(errp,
2064 "host lacks kvm mmu notifiers, -mem-path unsupported");
2065 return NULL;
2066 }
2067
2068 size = HOST_PAGE_ALIGN(size);
2069 file_size = get_file_size(fd);
2070 if (file_size > 0 && file_size < size) {
2071 error_setg(errp, "backing store size 0x%" PRIx64
2072 " does not match 'size' option 0x" RAM_ADDR_FMT,
2073 file_size, size);
2074 return NULL;
2075 }
2076
2077 file_align = get_file_align(fd);
2078 if (file_align > 0 && mr && file_align > mr->align) {
2079 error_setg(errp, "backing store align 0x%" PRIx64
2080 " is larger than 'align' option 0x%" PRIx64,
2081 file_align, mr->align);
2082 return NULL;
2083 }
2084
2085 new_block = g_malloc0(sizeof(*new_block));
2086 new_block->mr = mr;
2087 new_block->used_length = size;
2088 new_block->max_length = size;
2089 new_block->flags = ram_flags;
2090 new_block->host = file_ram_alloc(new_block, size, fd, readonly,
2091 !file_size, offset, errp);
2092 if (!new_block->host) {
2093 g_free(new_block);
2094 return NULL;
2095 }
2096
2097 ram_block_add(new_block, &local_err);
2098 if (local_err) {
2099 g_free(new_block);
2100 error_propagate(errp, local_err);
2101 return NULL;
2102 }
2103 return new_block;
2104
2105 }
2106
2107
2108 RAMBlock *qemu_ram_alloc_from_file(ram_addr_t size, MemoryRegion *mr,
2109 uint32_t ram_flags, const char *mem_path,
2110 bool readonly, Error **errp)
2111 {
2112 int fd;
2113 bool created;
2114 RAMBlock *block;
2115
2116 fd = file_ram_open(mem_path, memory_region_name(mr), readonly, &created,
2117 errp);
2118 if (fd < 0) {
2119 return NULL;
2120 }
2121
2122 block = qemu_ram_alloc_from_fd(size, mr, ram_flags, fd, 0, readonly, errp);
2123 if (!block) {
2124 if (created) {
2125 unlink(mem_path);
2126 }
2127 close(fd);
2128 return NULL;
2129 }
2130
2131 return block;
2132 }
2133 #endif
2134
2135 static
2136 RAMBlock *qemu_ram_alloc_internal(ram_addr_t size, ram_addr_t max_size,
2137 void (*resized)(const char*,
2138 uint64_t length,
2139 void *host),
2140 void *host, uint32_t ram_flags,
2141 MemoryRegion *mr, Error **errp)
2142 {
2143 RAMBlock *new_block;
2144 Error *local_err = NULL;
2145
2146 assert((ram_flags & ~(RAM_SHARED | RAM_RESIZEABLE | RAM_PREALLOC)) == 0);
2147 assert((ram_flags & ~(RAM_SHARED | RAM_RESIZEABLE | RAM_PREALLOC |
2148 RAM_NORESERVE)) == 0);
2149 assert(!host ^ (ram_flags & RAM_PREALLOC));
2150
2151 size = HOST_PAGE_ALIGN(size);
2152 max_size = HOST_PAGE_ALIGN(max_size);
2153 new_block = g_malloc0(sizeof(*new_block));
2154 new_block->mr = mr;
2155 new_block->resized = resized;
2156 new_block->used_length = size;
2157 new_block->max_length = max_size;
2158 assert(max_size >= size);
2159 new_block->fd = -1;
2160 new_block->page_size = qemu_real_host_page_size;
2161 new_block->host = host;
2162 new_block->flags = ram_flags;
2163 ram_block_add(new_block, &local_err);
2164 if (local_err) {
2165 g_free(new_block);
2166 error_propagate(errp, local_err);
2167 return NULL;
2168 }
2169 return new_block;
2170 }
2171
2172 RAMBlock *qemu_ram_alloc_from_ptr(ram_addr_t size, void *host,
2173 MemoryRegion *mr, Error **errp)
2174 {
2175 return qemu_ram_alloc_internal(size, size, NULL, host, RAM_PREALLOC, mr,
2176 errp);
2177 }
2178
2179 RAMBlock *qemu_ram_alloc(ram_addr_t size, uint32_t ram_flags,
2180 MemoryRegion *mr, Error **errp)
2181 {
2182 assert((ram_flags & ~(RAM_SHARED | RAM_NORESERVE)) == 0);
2183 return qemu_ram_alloc_internal(size, size, NULL, NULL, ram_flags, mr, errp);
2184 }
2185
2186 RAMBlock *qemu_ram_alloc_resizeable(ram_addr_t size, ram_addr_t maxsz,
2187 void (*resized)(const char*,
2188 uint64_t length,
2189 void *host),
2190 MemoryRegion *mr, Error **errp)
2191 {
2192 return qemu_ram_alloc_internal(size, maxsz, resized, NULL,
2193 RAM_RESIZEABLE, mr, errp);
2194 }
2195
2196 static void reclaim_ramblock(RAMBlock *block)
2197 {
2198 if (block->flags & RAM_PREALLOC) {
2199 ;
2200 } else if (xen_enabled()) {
2201 xen_invalidate_map_cache_entry(block->host);
2202 #ifndef _WIN32
2203 } else if (block->fd >= 0) {
2204 qemu_ram_munmap(block->fd, block->host, block->max_length);
2205 close(block->fd);
2206 #endif
2207 } else {
2208 qemu_anon_ram_free(block->host, block->max_length);
2209 }
2210 g_free(block);
2211 }
2212
2213 void qemu_ram_free(RAMBlock *block)
2214 {
2215 if (!block) {
2216 return;
2217 }
2218
2219 if (block->host) {
2220 ram_block_notify_remove(block->host, block->used_length,
2221 block->max_length);
2222 }
2223
2224 qemu_mutex_lock_ramlist();
2225 QLIST_REMOVE_RCU(block, next);
2226 ram_list.mru_block = NULL;
2227 /* Write list before version */
2228 smp_wmb();
2229 ram_list.version++;
2230 call_rcu(block, reclaim_ramblock, rcu);
2231 qemu_mutex_unlock_ramlist();
2232 }
2233
2234 #ifndef _WIN32
2235 void qemu_ram_remap(ram_addr_t addr, ram_addr_t length)
2236 {
2237 RAMBlock *block;
2238 ram_addr_t offset;
2239 int flags;
2240 void *area, *vaddr;
2241
2242 RAMBLOCK_FOREACH(block) {
2243 offset = addr - block->offset;
2244 if (offset < block->max_length) {
2245 vaddr = ramblock_ptr(block, offset);
2246 if (block->flags & RAM_PREALLOC) {
2247 ;
2248 } else if (xen_enabled()) {
2249 abort();
2250 } else {
2251 flags = MAP_FIXED;
2252 flags |= block->flags & RAM_SHARED ?
2253 MAP_SHARED : MAP_PRIVATE;
2254 flags |= block->flags & RAM_NORESERVE ? MAP_NORESERVE : 0;
2255 if (block->fd >= 0) {
2256 area = mmap(vaddr, length, PROT_READ | PROT_WRITE,
2257 flags, block->fd, offset);
2258 } else {
2259 flags |= MAP_ANONYMOUS;
2260 area = mmap(vaddr, length, PROT_READ | PROT_WRITE,
2261 flags, -1, 0);
2262 }
2263 if (area != vaddr) {
2264 error_report("Could not remap addr: "
2265 RAM_ADDR_FMT "@" RAM_ADDR_FMT "",
2266 length, addr);
2267 exit(1);
2268 }
2269 memory_try_enable_merging(vaddr, length);
2270 qemu_ram_setup_dump(vaddr, length);
2271 }
2272 }
2273 }
2274 }
2275 #endif /* !_WIN32 */
2276
2277 /* Return a host pointer to ram allocated with qemu_ram_alloc.
2278 * This should not be used for general purpose DMA. Use address_space_map
2279 * or address_space_rw instead. For local memory (e.g. video ram) that the
2280 * device owns, use memory_region_get_ram_ptr.
2281 *
2282 * Called within RCU critical section.
2283 */
2284 void *qemu_map_ram_ptr(RAMBlock *ram_block, ram_addr_t addr)
2285 {
2286 RAMBlock *block = ram_block;
2287
2288 if (block == NULL) {
2289 block = qemu_get_ram_block(addr);
2290 addr -= block->offset;
2291 }
2292
2293 if (xen_enabled() && block->host == NULL) {
2294 /* We need to check if the requested address is in the RAM
2295 * because we don't want to map the entire memory in QEMU.
2296 * In that case just map until the end of the page.
2297 */
2298 if (block->offset == 0) {
2299 return xen_map_cache(addr, 0, 0, false);
2300 }
2301
2302 block->host = xen_map_cache(block->offset, block->max_length, 1, false);
2303 }
2304 return ramblock_ptr(block, addr);
2305 }
2306
2307 /* Return a host pointer to guest's ram. Similar to qemu_map_ram_ptr
2308 * but takes a size argument.
2309 *
2310 * Called within RCU critical section.
2311 */
2312 static void *qemu_ram_ptr_length(RAMBlock *ram_block, ram_addr_t addr,
2313 hwaddr *size, bool lock)
2314 {
2315 RAMBlock *block = ram_block;
2316 if (*size == 0) {
2317 return NULL;
2318 }
2319
2320 if (block == NULL) {
2321 block = qemu_get_ram_block(addr);
2322 addr -= block->offset;
2323 }
2324 *size = MIN(*size, block->max_length - addr);
2325
2326 if (xen_enabled() && block->host == NULL) {
2327 /* We need to check if the requested address is in the RAM
2328 * because we don't want to map the entire memory in QEMU.
2329 * In that case just map the requested area.
2330 */
2331 if (block->offset == 0) {
2332 return xen_map_cache(addr, *size, lock, lock);
2333 }
2334
2335 block->host = xen_map_cache(block->offset, block->max_length, 1, lock);
2336 }
2337
2338 return ramblock_ptr(block, addr);
2339 }
2340
2341 /* Return the offset of a hostpointer within a ramblock */
2342 ram_addr_t qemu_ram_block_host_offset(RAMBlock *rb, void *host)
2343 {
2344 ram_addr_t res = (uint8_t *)host - (uint8_t *)rb->host;
2345 assert((uintptr_t)host >= (uintptr_t)rb->host);
2346 assert(res < rb->max_length);
2347
2348 return res;
2349 }
2350
2351 /*
2352 * Translates a host ptr back to a RAMBlock, a ram_addr and an offset
2353 * in that RAMBlock.
2354 *
2355 * ptr: Host pointer to look up
2356 * round_offset: If true round the result offset down to a page boundary
2357 * *ram_addr: set to result ram_addr
2358 * *offset: set to result offset within the RAMBlock
2359 *
2360 * Returns: RAMBlock (or NULL if not found)
2361 *
2362 * By the time this function returns, the returned pointer is not protected
2363 * by RCU anymore. If the caller is not within an RCU critical section and
2364 * does not hold the iothread lock, it must have other means of protecting the
2365 * pointer, such as a reference to the region that includes the incoming
2366 * ram_addr_t.
2367 */
2368 RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset,
2369 ram_addr_t *offset)
2370 {
2371 RAMBlock *block;
2372 uint8_t *host = ptr;
2373
2374 if (xen_enabled()) {
2375 ram_addr_t ram_addr;
2376 RCU_READ_LOCK_GUARD();
2377 ram_addr = xen_ram_addr_from_mapcache(ptr);
2378 block = qemu_get_ram_block(ram_addr);
2379 if (block) {
2380 *offset = ram_addr - block->offset;
2381 }
2382 return block;
2383 }
2384
2385 RCU_READ_LOCK_GUARD();
2386 block = qatomic_rcu_read(&ram_list.mru_block);
2387 if (block && block->host && host - block->host < block->max_length) {
2388 goto found;
2389 }
2390
2391 RAMBLOCK_FOREACH(block) {
2392 /* This case append when the block is not mapped. */
2393 if (block->host == NULL) {
2394 continue;
2395 }
2396 if (host - block->host < block->max_length) {
2397 goto found;
2398 }
2399 }
2400
2401 return NULL;
2402
2403 found:
2404 *offset = (host - block->host);
2405 if (round_offset) {
2406 *offset &= TARGET_PAGE_MASK;
2407 }
2408 return block;
2409 }
2410
2411 /*
2412 * Finds the named RAMBlock
2413 *
2414 * name: The name of RAMBlock to find
2415 *
2416 * Returns: RAMBlock (or NULL if not found)
2417 */
2418 RAMBlock *qemu_ram_block_by_name(const char *name)
2419 {
2420 RAMBlock *block;
2421
2422 RAMBLOCK_FOREACH(block) {
2423 if (!strcmp(name, block->idstr)) {
2424 return block;
2425 }
2426 }
2427
2428 return NULL;
2429 }
2430
2431 /* Some of the softmmu routines need to translate from a host pointer
2432 (typically a TLB entry) back to a ram offset. */
2433 ram_addr_t qemu_ram_addr_from_host(void *ptr)
2434 {
2435 RAMBlock *block;
2436 ram_addr_t offset;
2437
2438 block = qemu_ram_block_from_host(ptr, false, &offset);
2439 if (!block) {
2440 return RAM_ADDR_INVALID;
2441 }
2442
2443 return block->offset + offset;
2444 }
2445
2446 static MemTxResult flatview_read(FlatView *fv, hwaddr addr,
2447 MemTxAttrs attrs, void *buf, hwaddr len);
2448 static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs,
2449 const void *buf, hwaddr len);
2450 static bool flatview_access_valid(FlatView *fv, hwaddr addr, hwaddr len,
2451 bool is_write, MemTxAttrs attrs);
2452
2453 static MemTxResult subpage_read(void *opaque, hwaddr addr, uint64_t *data,
2454 unsigned len, MemTxAttrs attrs)
2455 {
2456 subpage_t *subpage = opaque;
2457 uint8_t buf[8];
2458 MemTxResult res;
2459
2460 #if defined(DEBUG_SUBPAGE)
2461 printf("%s: subpage %p len %u addr " TARGET_FMT_plx "\n", __func__,
2462 subpage, len, addr);
2463 #endif
2464 res = flatview_read(subpage->fv, addr + subpage->base, attrs, buf, len);
2465 if (res) {
2466 return res;
2467 }
2468 *data = ldn_p(buf, len);
2469 return MEMTX_OK;
2470 }
2471
2472 static MemTxResult subpage_write(void *opaque, hwaddr addr,
2473 uint64_t value, unsigned len, MemTxAttrs attrs)
2474 {
2475 subpage_t *subpage = opaque;
2476 uint8_t buf[8];
2477
2478 #if defined(DEBUG_SUBPAGE)
2479 printf("%s: subpage %p len %u addr " TARGET_FMT_plx
2480 " value %"PRIx64"\n",
2481 __func__, subpage, len, addr, value);
2482 #endif
2483 stn_p(buf, len, value);
2484 return flatview_write(subpage->fv, addr + subpage->base, attrs, buf, len);
2485 }
2486
2487 static bool subpage_accepts(void *opaque, hwaddr addr,
2488 unsigned len, bool is_write,
2489 MemTxAttrs attrs)
2490 {
2491 subpage_t *subpage = opaque;
2492 #if defined(DEBUG_SUBPAGE)
2493 printf("%s: subpage %p %c len %u addr " TARGET_FMT_plx "\n",
2494 __func__, subpage, is_write ? 'w' : 'r', len, addr);
2495 #endif
2496
2497 return flatview_access_valid(subpage->fv, addr + subpage->base,
2498 len, is_write, attrs);
2499 }
2500
2501 static const MemoryRegionOps subpage_ops = {
2502 .read_with_attrs = subpage_read,
2503 .write_with_attrs = subpage_write,
2504 .impl.min_access_size = 1,
2505 .impl.max_access_size = 8,
2506 .valid.min_access_size = 1,
2507 .valid.max_access_size = 8,
2508 .valid.accepts = subpage_accepts,
2509 .endianness = DEVICE_NATIVE_ENDIAN,
2510 };
2511
2512 static int subpage_register(subpage_t *mmio, uint32_t start, uint32_t end,
2513 uint16_t section)
2514 {
2515 int idx, eidx;
2516
2517 if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE)
2518 return -1;
2519 idx = SUBPAGE_IDX(start);
2520 eidx = SUBPAGE_IDX(end);
2521 #if defined(DEBUG_SUBPAGE)
2522 printf("%s: %p start %08x end %08x idx %08x eidx %08x section %d\n",
2523 __func__, mmio, start, end, idx, eidx, section);
2524 #endif
2525 for (; idx <= eidx; idx++) {
2526 mmio->sub_section[idx] = section;
2527 }
2528
2529 return 0;
2530 }
2531
2532 static subpage_t *subpage_init(FlatView *fv, hwaddr base)
2533 {
2534 subpage_t *mmio;
2535
2536 /* mmio->sub_section is set to PHYS_SECTION_UNASSIGNED with g_malloc0 */
2537 mmio = g_malloc0(sizeof(subpage_t) + TARGET_PAGE_SIZE * sizeof(uint16_t));
2538 mmio->fv = fv;
2539 mmio->base = base;
2540 memory_region_init_io(&mmio->iomem, NULL, &subpage_ops, mmio,
2541 NULL, TARGET_PAGE_SIZE);
2542 mmio->iomem.subpage = true;
2543 #if defined(DEBUG_SUBPAGE)
2544 printf("%s: %p base " TARGET_FMT_plx " len %08x\n", __func__,
2545 mmio, base, TARGET_PAGE_SIZE);
2546 #endif
2547
2548 return mmio;
2549 }
2550
2551 static uint16_t dummy_section(PhysPageMap *map, FlatView *fv, MemoryRegion *mr)
2552 {
2553 assert(fv);
2554 MemoryRegionSection section = {
2555 .fv = fv,
2556 .mr = mr,
2557 .offset_within_address_space = 0,
2558 .offset_within_region = 0,
2559 .size = int128_2_64(),
2560 };
2561
2562 return phys_section_add(map, &section);
2563 }
2564
2565 MemoryRegionSection *iotlb_to_section(CPUState *cpu,
2566 hwaddr index, MemTxAttrs attrs)
2567 {
2568 int asidx = cpu_asidx_from_attrs(cpu, attrs);
2569 CPUAddressSpace *cpuas = &cpu->cpu_ases[asidx];
2570 AddressSpaceDispatch *d = qatomic_rcu_read(&cpuas->memory_dispatch);
2571 MemoryRegionSection *sections = d->map.sections;
2572
2573 return &sections[index & ~TARGET_PAGE_MASK];
2574 }
2575
2576 static void io_mem_init(void)
2577 {
2578 memory_region_init_io(&io_mem_unassigned, NULL, &unassigned_mem_ops, NULL,
2579 NULL, UINT64_MAX);
2580 }
2581
2582 AddressSpaceDispatch *address_space_dispatch_new(FlatView *fv)
2583 {
2584 AddressSpaceDispatch *d = g_new0(AddressSpaceDispatch, 1);
2585 uint16_t n;
2586
2587 n = dummy_section(&d->map, fv, &io_mem_unassigned);
2588 assert(n == PHYS_SECTION_UNASSIGNED);
2589
2590 d->phys_map = (PhysPageEntry) { .ptr = PHYS_MAP_NODE_NIL, .skip = 1 };
2591
2592 return d;
2593 }
2594
2595 void address_space_dispatch_free(AddressSpaceDispatch *d)
2596 {
2597 phys_sections_free(&d->map);
2598 g_free(d);
2599 }
2600
2601 static void do_nothing(CPUState *cpu, run_on_cpu_data d)
2602 {
2603 }
2604
2605 static void tcg_log_global_after_sync(MemoryListener *listener)
2606 {
2607 CPUAddressSpace *cpuas;
2608
2609 /* Wait for the CPU to end the current TB. This avoids the following
2610 * incorrect race:
2611 *
2612 * vCPU migration
2613 * ---------------------- -------------------------
2614 * TLB check -> slow path
2615 * notdirty_mem_write
2616 * write to RAM
2617 * mark dirty
2618 * clear dirty flag
2619 * TLB check -> fast path
2620 * read memory
2621 * write to RAM
2622 *
2623 * by pushing the migration thread's memory read after the vCPU thread has
2624 * written the memory.
2625 */
2626 if (replay_mode == REPLAY_MODE_NONE) {
2627 /*
2628 * VGA can make calls to this function while updating the screen.
2629 * In record/replay mode this causes a deadlock, because
2630 * run_on_cpu waits for rr mutex. Therefore no races are possible
2631 * in this case and no need for making run_on_cpu when
2632 * record/replay is not enabled.
2633 */
2634 cpuas = container_of(listener, CPUAddressSpace, tcg_as_listener);
2635 run_on_cpu(cpuas->cpu, do_nothing, RUN_ON_CPU_NULL);
2636 }
2637 }
2638
2639 static void tcg_commit(MemoryListener *listener)
2640 {
2641 CPUAddressSpace *cpuas;
2642 AddressSpaceDispatch *d;
2643
2644 assert(tcg_enabled());
2645 /* since each CPU stores ram addresses in its TLB cache, we must
2646 reset the modified entries */
2647 cpuas = container_of(listener, CPUAddressSpace, tcg_as_listener);
2648 cpu_reloading_memory_map();
2649 /* The CPU and TLB are protected by the iothread lock.
2650 * We reload the dispatch pointer now because cpu_reloading_memory_map()
2651 * may have split the RCU critical section.
2652 */
2653 d = address_space_to_dispatch(cpuas->as);
2654 qatomic_rcu_set(&cpuas->memory_dispatch, d);
2655 tlb_flush(cpuas->cpu);
2656 }
2657
2658 static void memory_map_init(void)
2659 {
2660 system_memory = g_malloc(sizeof(*system_memory));
2661
2662 memory_region_init(system_memory, NULL, "system", UINT64_MAX);
2663 address_space_init(&address_space_memory, system_memory, "memory");
2664
2665 system_io = g_malloc(sizeof(*system_io));
2666 memory_region_init_io(system_io, NULL, &unassigned_io_ops, NULL, "io",
2667 65536);
2668 address_space_init(&address_space_io, system_io, "I/O");
2669 }
2670
2671 MemoryRegion *get_system_memory(void)
2672 {
2673 return system_memory;
2674 }
2675
2676 MemoryRegion *get_system_io(void)
2677 {
2678 return system_io;
2679 }
2680
2681 static void invalidate_and_set_dirty(MemoryRegion *mr, hwaddr addr,
2682 hwaddr length)
2683 {
2684 uint8_t dirty_log_mask = memory_region_get_dirty_log_mask(mr);
2685 addr += memory_region_get_ram_addr(mr);
2686
2687 /* No early return if dirty_log_mask is or becomes 0, because
2688 * cpu_physical_memory_set_dirty_range will still call
2689 * xen_modified_memory.
2690 */
2691 if (dirty_log_mask) {
2692 dirty_log_mask =
2693 cpu_physical_memory_range_includes_clean(addr, length, dirty_log_mask);
2694 }
2695 if (dirty_log_mask & (1 << DIRTY_MEMORY_CODE)) {
2696 assert(tcg_enabled());
2697 tb_invalidate_phys_range(addr, addr + length);
2698 dirty_log_mask &= ~(1 << DIRTY_MEMORY_CODE);
2699 }
2700 cpu_physical_memory_set_dirty_range(addr, length, dirty_log_mask);
2701 }
2702
2703 void memory_region_flush_rom_device(MemoryRegion *mr, hwaddr addr, hwaddr size)
2704 {
2705 /*
2706 * In principle this function would work on other memory region types too,
2707 * but the ROM device use case is the only one where this operation is
2708 * necessary. Other memory regions should use the
2709 * address_space_read/write() APIs.
2710 */
2711 assert(memory_region_is_romd(mr));
2712
2713 invalidate_and_set_dirty(mr, addr, size);
2714 }
2715
2716 static int memory_access_size(MemoryRegion *mr, unsigned l, hwaddr addr)
2717 {
2718 unsigned access_size_max = mr->ops->valid.max_access_size;
2719
2720 /* Regions are assumed to support 1-4 byte accesses unless
2721 otherwise specified. */
2722 if (access_size_max == 0) {
2723 access_size_max = 4;
2724 }
2725
2726 /* Bound the maximum access by the alignment of the address. */
2727 if (!mr->ops->impl.unaligned) {
2728 unsigned align_size_max = addr & -addr;
2729 if (align_size_max != 0 && align_size_max < access_size_max) {
2730 access_size_max = align_size_max;
2731 }
2732 }
2733
2734 /* Don't attempt accesses larger than the maximum. */
2735 if (l > access_size_max) {
2736 l = access_size_max;
2737 }
2738 l = pow2floor(l);
2739
2740 return l;
2741 }
2742
2743 static bool prepare_mmio_access(MemoryRegion *mr)
2744 {
2745 bool release_lock = false;
2746
2747 if (!qemu_mutex_iothread_locked()) {
2748 qemu_mutex_lock_iothread();
2749 release_lock = true;
2750 }
2751 if (mr->flush_coalesced_mmio) {
2752 qemu_flush_coalesced_mmio_buffer();
2753 }
2754
2755 return release_lock;
2756 }
2757
2758 /* Called within RCU critical section. */
2759 static MemTxResult flatview_write_continue(FlatView *fv, hwaddr addr,
2760 MemTxAttrs attrs,
2761 const void *ptr,
2762 hwaddr len, hwaddr addr1,
2763 hwaddr l, MemoryRegion *mr)
2764 {
2765 uint8_t *ram_ptr;
2766 uint64_t val;
2767 MemTxResult result = MEMTX_OK;
2768 bool release_lock = false;
2769 const uint8_t *buf = ptr;
2770
2771 for (;;) {
2772 if (!memory_access_is_direct(mr, true)) {
2773 release_lock |= prepare_mmio_access(mr);
2774 l = memory_access_size(mr, l, addr1);
2775 /* XXX: could force current_cpu to NULL to avoid
2776 potential bugs */
2777 val = ldn_he_p(buf, l);
2778 result |= memory_region_dispatch_write(mr, addr1, val,
2779 size_memop(l), attrs);
2780 } else {
2781 /* RAM case */
2782 ram_ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false);
2783 memcpy(ram_ptr, buf, l);
2784 invalidate_and_set_dirty(mr, addr1, l);
2785 }
2786
2787 if (release_lock) {
2788 qemu_mutex_unlock_iothread();
2789 release_lock = false;
2790 }
2791
2792 len -= l;
2793 buf += l;
2794 addr += l;
2795
2796 if (!len) {
2797 break;
2798 }
2799
2800 l = len;
2801 mr = flatview_translate(fv, addr, &addr1, &l, true, attrs);
2802 }
2803
2804 return result;
2805 }
2806
2807 /* Called from RCU critical section. */
2808 static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs,
2809 const void *buf, hwaddr len)
2810 {
2811 hwaddr l;
2812 hwaddr addr1;
2813 MemoryRegion *mr;
2814 MemTxResult result = MEMTX_OK;
2815
2816 l = len;
2817 mr = flatview_translate(fv, addr, &addr1, &l, true, attrs);
2818 result = flatview_write_continue(fv, addr, attrs, buf, len,
2819 addr1, l, mr);
2820
2821 return result;
2822 }
2823
2824 /* Called within RCU critical section. */
2825 MemTxResult flatview_read_continue(FlatView *fv, hwaddr addr,
2826 MemTxAttrs attrs, void *ptr,
2827 hwaddr len, hwaddr addr1, hwaddr l,
2828 MemoryRegion *mr)
2829 {
2830 uint8_t *ram_ptr;
2831 uint64_t val;
2832 MemTxResult result = MEMTX_OK;
2833 bool release_lock = false;
2834 uint8_t *buf = ptr;
2835
2836 fuzz_dma_read_cb(addr, len, mr);
2837 for (;;) {
2838 if (!memory_access_is_direct(mr, false)) {
2839 /* I/O case */
2840 release_lock |= prepare_mmio_access(mr);
2841 l = memory_access_size(mr, l, addr1);
2842 result |= memory_region_dispatch_read(mr, addr1, &val,
2843 size_memop(l), attrs);
2844 stn_he_p(buf, l, val);
2845 } else {
2846 /* RAM case */
2847 ram_ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false);
2848 memcpy(buf, ram_ptr, l);
2849 }
2850
2851 if (release_lock) {
2852 qemu_mutex_unlock_iothread();
2853 release_lock = false;
2854 }
2855
2856 len -= l;
2857 buf += l;
2858 addr += l;
2859
2860 if (!len) {
2861 break;
2862 }
2863
2864 l = len;
2865 mr = flatview_translate(fv, addr, &addr1, &l, false, attrs);
2866 }
2867
2868 return result;
2869 }
2870
2871 /* Called from RCU critical section. */
2872 static MemTxResult flatview_read(FlatView *fv, hwaddr addr,
2873 MemTxAttrs attrs, void *buf, hwaddr len)
2874 {
2875 hwaddr l;
2876 hwaddr addr1;
2877 MemoryRegion *mr;
2878
2879 l = len;
2880 mr = flatview_translate(fv, addr, &addr1, &l, false, attrs);
2881 return flatview_read_continue(fv, addr, attrs, buf, len,
2882 addr1, l, mr);
2883 }
2884
2885 MemTxResult address_space_read_full(AddressSpace *as, hwaddr addr,
2886 MemTxAttrs attrs, void *buf, hwaddr len)
2887 {
2888 MemTxResult result = MEMTX_OK;
2889 FlatView *fv;
2890
2891 if (len > 0) {
2892 RCU_READ_LOCK_GUARD();
2893 fv = address_space_to_flatview(as);
2894 result = flatview_read(fv, addr, attrs, buf, len);
2895 }
2896
2897 return result;
2898 }
2899
2900 MemTxResult address_space_write(AddressSpace *as, hwaddr addr,
2901 MemTxAttrs attrs,
2902 const void *buf, hwaddr len)
2903 {
2904 MemTxResult result = MEMTX_OK;
2905 FlatView *fv;
2906
2907 if (len > 0) {
2908 RCU_READ_LOCK_GUARD();
2909 fv = address_space_to_flatview(as);
2910 result = flatview_write(fv, addr, attrs, buf, len);
2911 }
2912
2913 return result;
2914 }
2915
2916 MemTxResult address_space_rw(AddressSpace *as, hwaddr addr, MemTxAttrs attrs,
2917 void *buf, hwaddr len, bool is_write)
2918 {
2919 if (is_write) {
2920 return address_space_write(as, addr, attrs, buf, len);
2921 } else {
2922 return address_space_read_full(as, addr, attrs, buf, len);
2923 }
2924 }
2925
2926 void cpu_physical_memory_rw(hwaddr addr, void *buf,
2927 hwaddr len, bool is_write)
2928 {
2929 address_space_rw(&address_space_memory, addr, MEMTXATTRS_UNSPECIFIED,
2930 buf, len, is_write);
2931 }
2932
2933 enum write_rom_type {
2934 WRITE_DATA,
2935 FLUSH_CACHE,
2936 };
2937
2938 static inline MemTxResult address_space_write_rom_internal(AddressSpace *as,
2939 hwaddr addr,
2940 MemTxAttrs attrs,
2941 const void *ptr,
2942 hwaddr len,
2943 enum write_rom_type type)
2944 {
2945 hwaddr l;
2946 uint8_t *ram_ptr;
2947 hwaddr addr1;
2948 MemoryRegion *mr;
2949 const uint8_t *buf = ptr;
2950
2951 RCU_READ_LOCK_GUARD();
2952 while (len > 0) {
2953 l = len;
2954 mr = address_space_translate(as, addr, &addr1, &l, true, attrs);
2955
2956 if (!(memory_region_is_ram(mr) ||
2957 memory_region_is_romd(mr))) {
2958 l = memory_access_size(mr, l, addr1);
2959 } else {
2960 /* ROM/RAM case */
2961 ram_ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
2962 switch (type) {
2963 case WRITE_DATA:
2964 memcpy(ram_ptr, buf, l);
2965 invalidate_and_set_dirty(mr, addr1, l);
2966 break;
2967 case FLUSH_CACHE:
2968 flush_idcache_range((uintptr_t)ram_ptr, (uintptr_t)ram_ptr, l);
2969 break;
2970 }
2971 }
2972 len -= l;
2973 buf += l;
2974 addr += l;
2975 }
2976 return MEMTX_OK;
2977 }
2978
2979 /* used for ROM loading : can write in RAM and ROM */
2980 MemTxResult address_space_write_rom(AddressSpace *as, hwaddr addr,
2981 MemTxAttrs attrs,
2982 const void *buf, hwaddr len)
2983 {
2984 return address_space_write_rom_internal(as, addr, attrs,
2985 buf, len, WRITE_DATA);
2986 }
2987
2988 void cpu_flush_icache_range(hwaddr start, hwaddr len)
2989 {
2990 /*
2991 * This function should do the same thing as an icache flush that was
2992 * triggered from within the guest. For TCG we are always cache coherent,
2993 * so there is no need to flush anything. For KVM / Xen we need to flush
2994 * the host's instruction cache at least.
2995 */
2996 if (tcg_enabled()) {
2997 return;
2998 }
2999
3000 address_space_write_rom_internal(&address_space_memory,
3001 start, MEMTXATTRS_UNSPECIFIED,
3002 NULL, len, FLUSH_CACHE);
3003 }
3004
3005 typedef struct {
3006 MemoryRegion *mr;
3007 void *buffer;
3008 hwaddr addr;
3009 hwaddr len;
3010 bool in_use;
3011 } BounceBuffer;
3012
3013 static BounceBuffer bounce;
3014
3015 typedef struct MapClient {
3016 QEMUBH *bh;
3017 QLIST_ENTRY(MapClient) link;
3018 } MapClient;
3019
3020 QemuMutex map_client_list_lock;
3021 static QLIST_HEAD(, MapClient) map_client_list
3022 = QLIST_HEAD_INITIALIZER(map_client_list);
3023
3024 static void cpu_unregister_map_client_do(MapClient *client)
3025 {
3026 QLIST_REMOVE(client, link);
3027 g_free(client);
3028 }
3029
3030 static void cpu_notify_map_clients_locked(void)
3031 {
3032 MapClient *client;
3033
3034 while (!QLIST_EMPTY(&map_client_list)) {
3035 client = QLIST_FIRST(&map_client_list);
3036 qemu_bh_schedule(client->bh);
3037 cpu_unregister_map_client_do(client);
3038 }
3039 }
3040
3041 void cpu_register_map_client(QEMUBH *bh)
3042 {
3043 MapClient *client = g_malloc(sizeof(*client));
3044
3045 qemu_mutex_lock(&map_client_list_lock);
3046 client->bh = bh;
3047 QLIST_INSERT_HEAD(&map_client_list, client, link);
3048 if (!qatomic_read(&bounce.in_use)) {
3049 cpu_notify_map_clients_locked();
3050 }
3051 qemu_mutex_unlock(&map_client_list_lock);
3052 }
3053
3054 void cpu_exec_init_all(void)
3055 {
3056 qemu_mutex_init(&ram_list.mutex);
3057 /* The data structures we set up here depend on knowing the page size,
3058 * so no more changes can be made after this point.
3059 * In an ideal world, nothing we did before we had finished the
3060 * machine setup would care about the target page size, and we could
3061 * do this much later, rather than requiring board models to state
3062 * up front what their requirements are.
3063 */
3064 finalize_target_page_bits();
3065 io_mem_init();
3066 memory_map_init();
3067 qemu_mutex_init(&map_client_list_lock);
3068 }
3069
3070 void cpu_unregister_map_client(QEMUBH *bh)
3071 {
3072 MapClient *client;
3073
3074 qemu_mutex_lock(&map_client_list_lock);
3075 QLIST_FOREACH(client, &map_client_list, link) {
3076 if (client->bh == bh) {
3077 cpu_unregister_map_client_do(client);
3078 break;
3079 }
3080 }
3081 qemu_mutex_unlock(&map_client_list_lock);
3082 }
3083
3084 static void cpu_notify_map_clients(void)
3085 {
3086 qemu_mutex_lock(&map_client_list_lock);
3087 cpu_notify_map_clients_locked();
3088 qemu_mutex_unlock(&map_client_list_lock);
3089 }
3090
3091 static bool flatview_access_valid(FlatView *fv, hwaddr addr, hwaddr len,
3092 bool is_write, MemTxAttrs attrs)
3093 {
3094 MemoryRegion *mr;
3095 hwaddr l, xlat;
3096
3097 while (len > 0) {
3098 l = len;
3099 mr = flatview_translate(fv, addr, &xlat, &l, is_write, attrs);
3100 if (!memory_access_is_direct(mr, is_write)) {
3101 l = memory_access_size(mr, l, addr);
3102 if (!memory_region_access_valid(mr, xlat, l, is_write, attrs)) {
3103 return false;
3104 }
3105 }
3106
3107 len -= l;
3108 addr += l;
3109 }
3110 return true;
3111 }
3112
3113 bool address_space_access_valid(AddressSpace *as, hwaddr addr,
3114 hwaddr len, bool is_write,
3115 MemTxAttrs attrs)
3116 {
3117 FlatView *fv;
3118 bool result;
3119
3120 RCU_READ_LOCK_GUARD();
3121 fv = address_space_to_flatview(as);
3122 result = flatview_access_valid(fv, addr, len, is_write, attrs);
3123 return result;
3124 }
3125
3126 static hwaddr
3127 flatview_extend_translation(FlatView *fv, hwaddr addr,
3128 hwaddr target_len,
3129 MemoryRegion *mr, hwaddr base, hwaddr len,
3130 bool is_write, MemTxAttrs attrs)
3131 {
3132 hwaddr done = 0;
3133 hwaddr xlat;
3134 MemoryRegion *this_mr;
3135
3136 for (;;) {
3137 target_len -= len;
3138 addr += len;
3139 done += len;
3140 if (target_len == 0) {
3141 return done;
3142 }
3143
3144 len = target_len;
3145 this_mr = flatview_translate(fv, addr, &xlat,
3146 &len, is_write, attrs);
3147 if (this_mr != mr || xlat != base + done) {
3148 return done;
3149 }
3150 }
3151 }
3152
3153 /* Map a physical memory region into a host virtual address.
3154 * May map a subset of the requested range, given by and returned in *plen.
3155 * May return NULL if resources needed to perform the mapping are exhausted.
3156 * Use only for reads OR writes - not for read-modify-write operations.
3157 * Use cpu_register_map_client() to know when retrying the map operation is
3158 * likely to succeed.
3159 */
3160 void *address_space_map(AddressSpace *as,
3161 hwaddr addr,
3162 hwaddr *plen,
3163 bool is_write,
3164 MemTxAttrs attrs)
3165 {
3166 hwaddr len = *plen;
3167 hwaddr l, xlat;
3168 MemoryRegion *mr;
3169 void *ptr;
3170 FlatView *fv;
3171
3172 if (len == 0) {
3173 return NULL;
3174 }
3175
3176 l = len;
3177 RCU_READ_LOCK_GUARD();
3178 fv = address_space_to_flatview(as);
3179 mr = flatview_translate(fv, addr, &xlat, &l, is_write, attrs);
3180
3181 if (!memory_access_is_direct(mr, is_write)) {
3182 if (qatomic_xchg(&bounce.in_use, true)) {
3183 *plen = 0;
3184 return NULL;
3185 }
3186 /* Avoid unbounded allocations */
3187 l = MIN(l, TARGET_PAGE_SIZE);
3188 bounce.buffer = qemu_memalign(TARGET_PAGE_SIZE, l);
3189 bounce.addr = addr;
3190 bounce.len = l;
3191
3192 memory_region_ref(mr);
3193 bounce.mr = mr;
3194 if (!is_write) {
3195 flatview_read(fv, addr, MEMTXATTRS_UNSPECIFIED,
3196 bounce.buffer, l);
3197 }
3198
3199 *plen = l;
3200 return bounce.buffer;
3201 }
3202
3203
3204 memory_region_ref(mr);
3205 *plen = flatview_extend_translation(fv, addr, len, mr, xlat,
3206 l, is_write, attrs);
3207 fuzz_dma_read_cb(addr, *plen, mr);
3208 ptr = qemu_ram_ptr_length(mr->ram_block, xlat, plen, true);
3209
3210 return ptr;
3211 }
3212
3213 /* Unmaps a memory region previously mapped by address_space_map().
3214 * Will also mark the memory as dirty if is_write is true. access_len gives
3215 * the amount of memory that was actually read or written by the caller.
3216 */
3217 void address_space_unmap(AddressSpace *as, void *buffer, hwaddr len,
3218 bool is_write, hwaddr access_len)
3219 {
3220 if (buffer != bounce.buffer) {
3221 MemoryRegion *mr;
3222 ram_addr_t addr1;
3223
3224 mr = memory_region_from_host(buffer, &addr1);
3225 assert(mr != NULL);
3226 if (is_write) {
3227 invalidate_and_set_dirty(mr, addr1, access_len);
3228 }
3229 if (xen_enabled()) {
3230 xen_invalidate_map_cache_entry(buffer);
3231 }
3232 memory_region_unref(mr);
3233 return;
3234 }
3235 if (is_write) {
3236 address_space_write(as, bounce.addr, MEMTXATTRS_UNSPECIFIED,
3237 bounce.buffer, access_len);
3238 }
3239 qemu_vfree(bounce.buffer);
3240 bounce.buffer = NULL;
3241 memory_region_unref(bounce.mr);
3242 qatomic_mb_set(&bounce.in_use, false);
3243 cpu_notify_map_clients();
3244 }
3245
3246 void *cpu_physical_memory_map(hwaddr addr,
3247 hwaddr *plen,
3248 bool is_write)
3249 {
3250 return address_space_map(&address_space_memory, addr, plen, is_write,
3251 MEMTXATTRS_UNSPECIFIED);
3252 }
3253
3254 void cpu_physical_memory_unmap(void *buffer, hwaddr len,
3255 bool is_write, hwaddr access_len)
3256 {
3257 return address_space_unmap(&address_space_memory, buffer, len, is_write, access_len);
3258 }
3259
3260 #define ARG1_DECL AddressSpace *as
3261 #define ARG1 as
3262 #define SUFFIX
3263 #define TRANSLATE(...) address_space_translate(as, __VA_ARGS__)
3264 #define RCU_READ_LOCK(...) rcu_read_lock()
3265 #define RCU_READ_UNLOCK(...) rcu_read_unlock()
3266 #include "memory_ldst.c.inc"
3267
3268 int64_t address_space_cache_init(MemoryRegionCache *cache,
3269 AddressSpace *as,
3270 hwaddr addr,
3271 hwaddr len,
3272 bool is_write)
3273 {
3274 AddressSpaceDispatch *d;
3275 hwaddr l;
3276 MemoryRegion *mr;
3277 Int128 diff;
3278
3279 assert(len > 0);
3280
3281 l = len;
3282 cache->fv = address_space_get_flatview(as);
3283 d = flatview_to_dispatch(cache->fv);
3284 cache->mrs = *address_space_translate_internal(d, addr, &cache->xlat, &l, true);
3285
3286 /*
3287 * cache->xlat is now relative to cache->mrs.mr, not to the section itself.
3288 * Take that into account to compute how many bytes are there between
3289 * cache->xlat and the end of the section.
3290 */
3291 diff = int128_sub(cache->mrs.size,
3292 int128_make64(cache->xlat - cache->mrs.offset_within_region));
3293 l = int128_get64(int128_min(diff, int128_make64(l)));
3294
3295 mr = cache->mrs.mr;
3296 memory_region_ref(mr);
3297 if (memory_access_is_direct(mr, is_write)) {
3298 /* We don't care about the memory attributes here as we're only
3299 * doing this if we found actual RAM, which behaves the same
3300 * regardless of attributes; so UNSPECIFIED is fine.
3301 */
3302 l = flatview_extend_translation(cache->fv, addr, len, mr,
3303 cache->xlat, l, is_write,
3304 MEMTXATTRS_UNSPECIFIED);
3305 cache->ptr = qemu_ram_ptr_length(mr->ram_block, cache->xlat, &l, true);
3306 } else {
3307 cache->ptr = NULL;
3308 }
3309
3310 cache->len = l;
3311 cache->is_write = is_write;
3312 return l;
3313 }
3314
3315 void address_space_cache_invalidate(MemoryRegionCache *cache,
3316 hwaddr addr,
3317 hwaddr access_len)
3318 {
3319 assert(cache->is_write);
3320 if (likely(cache->ptr)) {
3321 invalidate_and_set_dirty(cache->mrs.mr, addr + cache->xlat, access_len);
3322 }
3323 }
3324
3325 void address_space_cache_destroy(MemoryRegionCache *cache)
3326 {
3327 if (!cache->mrs.mr) {
3328 return;
3329 }
3330
3331 if (xen_enabled()) {
3332 xen_invalidate_map_cache_entry(cache->ptr);
3333 }
3334 memory_region_unref(cache->mrs.mr);
3335 flatview_unref(cache->fv);
3336 cache->mrs.mr = NULL;
3337 cache->fv = NULL;
3338 }
3339
3340 /* Called from RCU critical section. This function has the same
3341 * semantics as address_space_translate, but it only works on a
3342 * predefined range of a MemoryRegion that was mapped with
3343 * address_space_cache_init.
3344 */
3345 static inline MemoryRegion *address_space_translate_cached(
3346 MemoryRegionCache *cache, hwaddr addr, hwaddr *xlat,
3347 hwaddr *plen, bool is_write, MemTxAttrs attrs)
3348 {
3349 MemoryRegionSection section;
3350 MemoryRegion *mr;
3351 IOMMUMemoryRegion *iommu_mr;
3352 AddressSpace *target_as;
3353
3354 assert(!cache->ptr);
3355 *xlat = addr + cache->xlat;
3356
3357 mr = cache->mrs.mr;
3358 iommu_mr = memory_region_get_iommu(mr);
3359 if (!iommu_mr) {
3360 /* MMIO region. */
3361 return mr;
3362 }
3363
3364 section = address_space_translate_iommu(iommu_mr, xlat, plen,
3365 NULL, is_write, true,
3366 &target_as, attrs);
3367 return section.mr;
3368 }
3369
3370 /* Called from RCU critical section. address_space_read_cached uses this
3371 * out of line function when the target is an MMIO or IOMMU region.
3372 */
3373 MemTxResult
3374 address_space_read_cached_slow(MemoryRegionCache *cache, hwaddr addr,
3375 void *buf, hwaddr len)
3376 {
3377 hwaddr addr1, l;
3378 MemoryRegion *mr;
3379
3380 l = len;
3381 mr = address_space_translate_cached(cache, addr, &addr1, &l, false,
3382 MEMTXATTRS_UNSPECIFIED);
3383 return flatview_read_continue(cache->fv,
3384 addr, MEMTXATTRS_UNSPECIFIED, buf, len,
3385 addr1, l, mr);
3386 }
3387
3388 /* Called from RCU critical section. address_space_write_cached uses this
3389 * out of line function when the target is an MMIO or IOMMU region.
3390 */
3391 MemTxResult
3392 address_space_write_cached_slow(MemoryRegionCache *cache, hwaddr addr,
3393 const void *buf, hwaddr len)
3394 {
3395 hwaddr addr1, l;
3396 MemoryRegion *mr;
3397
3398 l = len;
3399 mr = address_space_translate_cached(cache, addr, &addr1, &l, true,
3400 MEMTXATTRS_UNSPECIFIED);
3401 return flatview_write_continue(cache->fv,
3402 addr, MEMTXATTRS_UNSPECIFIED, buf, len,
3403 addr1, l, mr);
3404 }
3405
3406 #define ARG1_DECL MemoryRegionCache *cache
3407 #define ARG1 cache
3408 #define SUFFIX _cached_slow
3409 #define TRANSLATE(...) address_space_translate_cached(cache, __VA_ARGS__)
3410 #define RCU_READ_LOCK() ((void)0)
3411 #define RCU_READ_UNLOCK() ((void)0)
3412 #include "memory_ldst.c.inc"
3413
3414 /* virtual memory access for debug (includes writing to ROM) */
3415 int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
3416 void *ptr, target_ulong len, bool is_write)
3417 {
3418 hwaddr phys_addr;
3419 target_ulong l, page;
3420 uint8_t *buf = ptr;
3421
3422 cpu_synchronize_state(cpu);
3423 while (len > 0) {
3424 int asidx;
3425 MemTxAttrs attrs;
3426 MemTxResult res;
3427
3428 page = addr & TARGET_PAGE_MASK;
3429 phys_addr = cpu_get_phys_page_attrs_debug(cpu, page, &attrs);
3430 asidx = cpu_asidx_from_attrs(cpu, attrs);
3431 /* if no physical page mapped, return an error */
3432 if (phys_addr == -1)
3433 return -1;
3434 l = (page + TARGET_PAGE_SIZE) - addr;
3435 if (l > len)
3436 l = len;
3437 phys_addr += (addr & ~TARGET_PAGE_MASK);
3438 if (is_write) {
3439 res = address_space_write_rom(cpu->cpu_ases[asidx].as, phys_addr,
3440 attrs, buf, l);
3441 } else {
3442 res = address_space_read(cpu->cpu_ases[asidx].as, phys_addr,
3443 attrs, buf, l);
3444 }
3445 if (res != MEMTX_OK) {
3446 return -1;
3447 }
3448 len -= l;
3449 buf += l;
3450 addr += l;
3451 }
3452 return 0;
3453 }
3454
3455 /*
3456 * Allows code that needs to deal with migration bitmaps etc to still be built
3457 * target independent.
3458 */
3459 size_t qemu_target_page_size(void)
3460 {
3461 return TARGET_PAGE_SIZE;
3462 }
3463
3464 int qemu_target_page_bits(void)
3465 {
3466 return TARGET_PAGE_BITS;
3467 }
3468
3469 int qemu_target_page_bits_min(void)
3470 {
3471 return TARGET_PAGE_BITS_MIN;
3472 }
3473
3474 bool cpu_physical_memory_is_io(hwaddr phys_addr)
3475 {
3476 MemoryRegion*mr;
3477 hwaddr l = 1;
3478 bool res;
3479
3480 RCU_READ_LOCK_GUARD();
3481 mr = address_space_translate(&address_space_memory,
3482 phys_addr, &phys_addr, &l, false,
3483 MEMTXATTRS_UNSPECIFIED);
3484
3485 res = !(memory_region_is_ram(mr) || memory_region_is_romd(mr));
3486 return res;
3487 }
3488
3489 int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque)
3490 {
3491 RAMBlock *block;
3492 int ret = 0;
3493
3494 RCU_READ_LOCK_GUARD();
3495 RAMBLOCK_FOREACH(block) {
3496 ret = func(block, opaque);
3497 if (ret) {
3498 break;
3499 }
3500 }
3501 return ret;
3502 }
3503
3504 /*
3505 * Unmap pages of memory from start to start+length such that
3506 * they a) read as 0, b) Trigger whatever fault mechanism
3507 * the OS provides for postcopy.
3508 * The pages must be unmapped by the end of the function.
3509 * Returns: 0 on success, none-0 on failure
3510 *
3511 */
3512 int ram_block_discard_range(RAMBlock *rb, uint64_t start, size_t length)
3513 {
3514 int ret = -1;
3515
3516 uint8_t *host_startaddr = rb->host + start;
3517
3518 if (!QEMU_PTR_IS_ALIGNED(host_startaddr, rb->page_size)) {
3519 error_report("ram_block_discard_range: Unaligned start address: %p",
3520 host_startaddr);
3521 goto err;
3522 }
3523
3524 if ((start + length) <= rb->max_length) {
3525 bool need_madvise, need_fallocate;
3526 if (!QEMU_IS_ALIGNED(length, rb->page_size)) {
3527 error_report("ram_block_discard_range: Unaligned length: %zx",
3528 length);
3529 goto err;
3530 }
3531
3532 errno = ENOTSUP; /* If we are missing MADVISE etc */
3533
3534 /* The logic here is messy;
3535 * madvise DONTNEED fails for hugepages
3536 * fallocate works on hugepages and shmem
3537 * shared anonymous memory requires madvise REMOVE
3538 */
3539 need_madvise = (rb->page_size == qemu_host_page_size);
3540 need_fallocate = rb->fd != -1;
3541 if (need_fallocate) {
3542 /* For a file, this causes the area of the file to be zero'd
3543 * if read, and for hugetlbfs also causes it to be unmapped
3544 * so a userfault will trigger.
3545 */
3546 #ifdef CONFIG_FALLOCATE_PUNCH_HOLE
3547 ret = fallocate(rb->fd, FALLOC_FL_PUNCH_HOLE | FALLOC_FL_KEEP_SIZE,
3548 start, length);
3549 if (ret) {
3550 ret = -errno;
3551 error_report("ram_block_discard_range: Failed to fallocate "
3552 "%s:%" PRIx64 " +%zx (%d)",
3553 rb->idstr, start, length, ret);
3554 goto err;
3555 }
3556 #else
3557 ret = -ENOSYS;
3558 error_report("ram_block_discard_range: fallocate not available/file"
3559 "%s:%" PRIx64 " +%zx (%d)",
3560 rb->idstr, start, length, ret);
3561 goto err;
3562 #endif
3563 }
3564 if (need_madvise) {
3565 /* For normal RAM this causes it to be unmapped,
3566 * for shared memory it causes the local mapping to disappear
3567 * and to fall back on the file contents (which we just
3568 * fallocate'd away).
3569 */
3570 #if defined(CONFIG_MADVISE)
3571 if (qemu_ram_is_shared(rb) && rb->fd < 0) {
3572 ret = madvise(host_startaddr, length, QEMU_MADV_REMOVE);
3573 } else {
3574 ret = madvise(host_startaddr, length, QEMU_MADV_DONTNEED);
3575 }
3576 if (ret) {
3577 ret = -errno;
3578 error_report("ram_block_discard_range: Failed to discard range "
3579 "%s:%" PRIx64 " +%zx (%d)",
3580 rb->idstr, start, length, ret);
3581 goto err;
3582 }
3583 #else
3584 ret = -ENOSYS;
3585 error_report("ram_block_discard_range: MADVISE not available"
3586 "%s:%" PRIx64 " +%zx (%d)",
3587 rb->idstr, start, length, ret);
3588 goto err;
3589 #endif
3590 }
3591 trace_ram_block_discard_range(rb->idstr, host_startaddr, length,
3592 need_madvise, need_fallocate, ret);
3593 } else {
3594 error_report("ram_block_discard_range: Overrun block '%s' (%" PRIu64
3595 "/%zx/" RAM_ADDR_FMT")",
3596 rb->idstr, start, length, rb->max_length);
3597 }
3598
3599 err:
3600 return ret;
3601 }
3602
3603 bool ramblock_is_pmem(RAMBlock *rb)
3604 {
3605 return rb->flags & RAM_PMEM;
3606 }
3607
3608 static void mtree_print_phys_entries(int start, int end, int skip, int ptr)
3609 {
3610 if (start == end - 1) {
3611 qemu_printf("\t%3d ", start);
3612 } else {
3613 qemu_printf("\t%3d..%-3d ", start, end - 1);
3614 }
3615 qemu_printf(" skip=%d ", skip);
3616 if (ptr == PHYS_MAP_NODE_NIL) {
3617 qemu_printf(" ptr=NIL");
3618 } else if (!skip) {
3619 qemu_printf(" ptr=#%d", ptr);
3620 } else {
3621 qemu_printf(" ptr=[%d]", ptr);
3622 }
3623 qemu_printf("\n");
3624 }
3625
3626 #define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \
3627 int128_sub((size), int128_one())) : 0)
3628
3629 void mtree_print_dispatch(AddressSpaceDispatch *d, MemoryRegion *root)
3630 {
3631 int i;
3632
3633 qemu_printf(" Dispatch\n");
3634 qemu_printf(" Physical sections\n");
3635
3636 for (i = 0; i < d->map.sections_nb; ++i) {
3637 MemoryRegionSection *s = d->map.sections + i;
3638 const char *names[] = { " [unassigned]", " [not dirty]",
3639 " [ROM]", " [watch]" };
3640
3641 qemu_printf(" #%d @" TARGET_FMT_plx ".." TARGET_FMT_plx
3642 " %s%s%s%s%s",
3643 i,
3644 s->offset_within_address_space,
3645 s->offset_within_address_space + MR_SIZE(s->mr->size),
3646 s->mr->name ? s->mr->name : "(noname)",
3647 i < ARRAY_SIZE(names) ? names[i] : "",
3648 s->mr == root ? " [ROOT]" : "",
3649 s == d->mru_section ? " [MRU]" : "",
3650 s->mr->is_iommu ? " [iommu]" : "");
3651
3652 if (s->mr->alias) {
3653 qemu_printf(" alias=%s", s->mr->alias->name ?
3654 s->mr->alias->name : "noname");
3655 }
3656 qemu_printf("\n");
3657 }
3658
3659 qemu_printf(" Nodes (%d bits per level, %d levels) ptr=[%d] skip=%d\n",
3660 P_L2_BITS, P_L2_LEVELS, d->phys_map.ptr, d->phys_map.skip);
3661 for (i = 0; i < d->map.nodes_nb; ++i) {
3662 int j, jprev;
3663 PhysPageEntry prev;
3664 Node *n = d->map.nodes + i;
3665
3666 qemu_printf(" [%d]\n", i);
3667
3668 for (j = 0, jprev = 0, prev = *n[0]; j < ARRAY_SIZE(*n); ++j) {
3669 PhysPageEntry *pe = *n + j;
3670
3671 if (pe->ptr == prev.ptr && pe->skip == prev.skip) {
3672 continue;
3673 }
3674
3675 mtree_print_phys_entries(jprev, j, prev.skip, prev.ptr);
3676
3677 jprev = j;
3678 prev = *pe;
3679 }
3680
3681 if (jprev != ARRAY_SIZE(*n)) {
3682 mtree_print_phys_entries(jprev, j, prev.skip, prev.ptr);
3683 }
3684 }
3685 }
3686
3687 /* Require any discards to work. */
3688 static unsigned int ram_block_discard_required_cnt;
3689 /* Require only coordinated discards to work. */
3690 static unsigned int ram_block_coordinated_discard_required_cnt;
3691 /* Disable any discards. */
3692 static unsigned int ram_block_discard_disabled_cnt;
3693 /* Disable only uncoordinated discards. */
3694 static unsigned int ram_block_uncoordinated_discard_disabled_cnt;
3695 static QemuMutex ram_block_discard_disable_mutex;
3696
3697 static void ram_block_discard_disable_mutex_lock(void)
3698 {
3699 static gsize initialized;
3700
3701 if (g_once_init_enter(&initialized)) {
3702 qemu_mutex_init(&ram_block_discard_disable_mutex);
3703 g_once_init_leave(&initialized, 1);
3704 }
3705 qemu_mutex_lock(&ram_block_discard_disable_mutex);
3706 }
3707
3708 static void ram_block_discard_disable_mutex_unlock(void)
3709 {
3710 qemu_mutex_unlock(&ram_block_discard_disable_mutex);
3711 }
3712
3713 int ram_block_discard_disable(bool state)
3714 {
3715 int ret = 0;
3716
3717 ram_block_discard_disable_mutex_lock();
3718 if (!state) {
3719 ram_block_discard_disabled_cnt--;
3720 } else if (ram_block_discard_required_cnt ||
3721 ram_block_coordinated_discard_required_cnt) {
3722 ret = -EBUSY;
3723 } else {
3724 ram_block_discard_disabled_cnt++;
3725 }
3726 ram_block_discard_disable_mutex_unlock();
3727 return ret;
3728 }
3729
3730 int ram_block_uncoordinated_discard_disable(bool state)
3731 {
3732 int ret = 0;
3733
3734 ram_block_discard_disable_mutex_lock();
3735 if (!state) {
3736 ram_block_uncoordinated_discard_disabled_cnt--;
3737 } else if (ram_block_discard_required_cnt) {
3738 ret = -EBUSY;
3739 } else {
3740 ram_block_uncoordinated_discard_disabled_cnt++;
3741 }
3742 ram_block_discard_disable_mutex_unlock();
3743 return ret;
3744 }
3745
3746 int ram_block_discard_require(bool state)
3747 {
3748 int ret = 0;
3749
3750 ram_block_discard_disable_mutex_lock();
3751 if (!state) {
3752 ram_block_discard_required_cnt--;
3753 } else if (ram_block_discard_disabled_cnt ||
3754 ram_block_uncoordinated_discard_disabled_cnt) {
3755 ret = -EBUSY;
3756 } else {
3757 ram_block_discard_required_cnt++;
3758 }
3759 ram_block_discard_disable_mutex_unlock();
3760 return ret;
3761 }
3762
3763 int ram_block_coordinated_discard_require(bool state)
3764 {
3765 int ret = 0;
3766
3767 ram_block_discard_disable_mutex_lock();
3768 if (!state) {
3769 ram_block_coordinated_discard_required_cnt--;
3770 } else if (ram_block_discard_disabled_cnt) {
3771 ret = -EBUSY;
3772 } else {
3773 ram_block_coordinated_discard_required_cnt++;
3774 }
3775 ram_block_discard_disable_mutex_unlock();
3776 return ret;
3777 }
3778
3779 bool ram_block_discard_is_disabled(void)
3780 {
3781 return qatomic_read(&ram_block_discard_disabled_cnt) ||
3782 qatomic_read(&ram_block_uncoordinated_discard_disabled_cnt);
3783 }
3784
3785 bool ram_block_discard_is_required(void)
3786 {
3787 return qatomic_read(&ram_block_discard_required_cnt) ||
3788 qatomic_read(&ram_block_coordinated_discard_required_cnt);
3789 }