kvmclock: Add comment explaining why we need cpu_clean_all_dirty()
[qemu.git] / softmmu_template.h
1 /*
2 * Software MMU support
3 *
4 * Generate helpers used by TCG for qemu_ld/st ops and code load
5 * functions.
6 *
7 * Included from target op helpers and exec.c.
8 *
9 * Copyright (c) 2003 Fabrice Bellard
10 *
11 * This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU Lesser General Public
13 * License as published by the Free Software Foundation; either
14 * version 2 of the License, or (at your option) any later version.
15 *
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * Lesser General Public License for more details.
20 *
21 * You should have received a copy of the GNU Lesser General Public
22 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
23 */
24 #include "qemu/timer.h"
25 #include "exec/address-spaces.h"
26 #include "exec/memory.h"
27
28 #define DATA_SIZE (1 << SHIFT)
29
30 #if DATA_SIZE == 8
31 #define SUFFIX q
32 #define LSUFFIX q
33 #define SDATA_TYPE int64_t
34 #define DATA_TYPE uint64_t
35 #elif DATA_SIZE == 4
36 #define SUFFIX l
37 #define LSUFFIX l
38 #define SDATA_TYPE int32_t
39 #define DATA_TYPE uint32_t
40 #elif DATA_SIZE == 2
41 #define SUFFIX w
42 #define LSUFFIX uw
43 #define SDATA_TYPE int16_t
44 #define DATA_TYPE uint16_t
45 #elif DATA_SIZE == 1
46 #define SUFFIX b
47 #define LSUFFIX ub
48 #define SDATA_TYPE int8_t
49 #define DATA_TYPE uint8_t
50 #else
51 #error unsupported data size
52 #endif
53
54
55 /* For the benefit of TCG generated code, we want to avoid the complication
56 of ABI-specific return type promotion and always return a value extended
57 to the register size of the host. This is tcg_target_long, except in the
58 case of a 32-bit host and 64-bit data, and for that we always have
59 uint64_t. Don't bother with this widened value for SOFTMMU_CODE_ACCESS. */
60 #if defined(SOFTMMU_CODE_ACCESS) || DATA_SIZE == 8
61 # define WORD_TYPE DATA_TYPE
62 # define USUFFIX SUFFIX
63 #else
64 # define WORD_TYPE tcg_target_ulong
65 # define USUFFIX glue(u, SUFFIX)
66 # define SSUFFIX glue(s, SUFFIX)
67 #endif
68
69 #ifdef SOFTMMU_CODE_ACCESS
70 #define READ_ACCESS_TYPE MMU_INST_FETCH
71 #define ADDR_READ addr_code
72 #else
73 #define READ_ACCESS_TYPE MMU_DATA_LOAD
74 #define ADDR_READ addr_read
75 #endif
76
77 #if DATA_SIZE == 8
78 # define BSWAP(X) bswap64(X)
79 #elif DATA_SIZE == 4
80 # define BSWAP(X) bswap32(X)
81 #elif DATA_SIZE == 2
82 # define BSWAP(X) bswap16(X)
83 #else
84 # define BSWAP(X) (X)
85 #endif
86
87 #ifdef TARGET_WORDS_BIGENDIAN
88 # define TGT_BE(X) (X)
89 # define TGT_LE(X) BSWAP(X)
90 #else
91 # define TGT_BE(X) BSWAP(X)
92 # define TGT_LE(X) (X)
93 #endif
94
95 #if DATA_SIZE == 1
96 # define helper_le_ld_name glue(glue(helper_ret_ld, USUFFIX), MMUSUFFIX)
97 # define helper_be_ld_name helper_le_ld_name
98 # define helper_le_lds_name glue(glue(helper_ret_ld, SSUFFIX), MMUSUFFIX)
99 # define helper_be_lds_name helper_le_lds_name
100 # define helper_le_st_name glue(glue(helper_ret_st, SUFFIX), MMUSUFFIX)
101 # define helper_be_st_name helper_le_st_name
102 #else
103 # define helper_le_ld_name glue(glue(helper_le_ld, USUFFIX), MMUSUFFIX)
104 # define helper_be_ld_name glue(glue(helper_be_ld, USUFFIX), MMUSUFFIX)
105 # define helper_le_lds_name glue(glue(helper_le_ld, SSUFFIX), MMUSUFFIX)
106 # define helper_be_lds_name glue(glue(helper_be_ld, SSUFFIX), MMUSUFFIX)
107 # define helper_le_st_name glue(glue(helper_le_st, SUFFIX), MMUSUFFIX)
108 # define helper_be_st_name glue(glue(helper_be_st, SUFFIX), MMUSUFFIX)
109 #endif
110
111 #ifdef TARGET_WORDS_BIGENDIAN
112 # define helper_te_ld_name helper_be_ld_name
113 # define helper_te_st_name helper_be_st_name
114 #else
115 # define helper_te_ld_name helper_le_ld_name
116 # define helper_te_st_name helper_le_st_name
117 #endif
118
119 /* macro to check the victim tlb */
120 #define VICTIM_TLB_HIT(ty) \
121 ({ \
122 /* we are about to do a page table walk. our last hope is the \
123 * victim tlb. try to refill from the victim tlb before walking the \
124 * page table. */ \
125 int vidx; \
126 hwaddr tmpiotlb; \
127 CPUTLBEntry tmptlb; \
128 for (vidx = CPU_VTLB_SIZE-1; vidx >= 0; --vidx) { \
129 if (env->tlb_v_table[mmu_idx][vidx].ty == (addr & TARGET_PAGE_MASK)) {\
130 /* found entry in victim tlb, swap tlb and iotlb */ \
131 tmptlb = env->tlb_table[mmu_idx][index]; \
132 env->tlb_table[mmu_idx][index] = env->tlb_v_table[mmu_idx][vidx]; \
133 env->tlb_v_table[mmu_idx][vidx] = tmptlb; \
134 tmpiotlb = env->iotlb[mmu_idx][index]; \
135 env->iotlb[mmu_idx][index] = env->iotlb_v[mmu_idx][vidx]; \
136 env->iotlb_v[mmu_idx][vidx] = tmpiotlb; \
137 break; \
138 } \
139 } \
140 /* return true when there is a vtlb hit, i.e. vidx >=0 */ \
141 vidx >= 0; \
142 })
143
144 #ifndef SOFTMMU_CODE_ACCESS
145 static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env,
146 hwaddr physaddr,
147 target_ulong addr,
148 uintptr_t retaddr)
149 {
150 uint64_t val;
151 CPUState *cpu = ENV_GET_CPU(env);
152 MemoryRegion *mr = iotlb_to_region(cpu->as, physaddr);
153
154 physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
155 cpu->mem_io_pc = retaddr;
156 if (mr != &io_mem_rom && mr != &io_mem_notdirty && !cpu_can_do_io(cpu)) {
157 cpu_io_recompile(cpu, retaddr);
158 }
159
160 cpu->mem_io_vaddr = addr;
161 io_mem_read(mr, physaddr, &val, 1 << SHIFT);
162 return val;
163 }
164 #endif
165
166 #ifdef SOFTMMU_CODE_ACCESS
167 static __attribute__((unused))
168 #endif
169 WORD_TYPE helper_le_ld_name(CPUArchState *env, target_ulong addr, int mmu_idx,
170 uintptr_t retaddr)
171 {
172 int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
173 target_ulong tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
174 uintptr_t haddr;
175 DATA_TYPE res;
176
177 /* Adjust the given return address. */
178 retaddr -= GETPC_ADJ;
179
180 /* If the TLB entry is for a different page, reload and try again. */
181 if ((addr & TARGET_PAGE_MASK)
182 != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
183 #ifdef ALIGNED_ONLY
184 if ((addr & (DATA_SIZE - 1)) != 0) {
185 cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
186 mmu_idx, retaddr);
187 }
188 #endif
189 if (!VICTIM_TLB_HIT(ADDR_READ)) {
190 tlb_fill(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
191 mmu_idx, retaddr);
192 }
193 tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
194 }
195
196 /* Handle an IO access. */
197 if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
198 hwaddr ioaddr;
199 if ((addr & (DATA_SIZE - 1)) != 0) {
200 goto do_unaligned_access;
201 }
202 ioaddr = env->iotlb[mmu_idx][index];
203
204 /* ??? Note that the io helpers always read data in the target
205 byte ordering. We should push the LE/BE request down into io. */
206 res = glue(io_read, SUFFIX)(env, ioaddr, addr, retaddr);
207 res = TGT_LE(res);
208 return res;
209 }
210
211 /* Handle slow unaligned access (it spans two pages or IO). */
212 if (DATA_SIZE > 1
213 && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
214 >= TARGET_PAGE_SIZE)) {
215 target_ulong addr1, addr2;
216 DATA_TYPE res1, res2;
217 unsigned shift;
218 do_unaligned_access:
219 #ifdef ALIGNED_ONLY
220 cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
221 mmu_idx, retaddr);
222 #endif
223 addr1 = addr & ~(DATA_SIZE - 1);
224 addr2 = addr1 + DATA_SIZE;
225 /* Note the adjustment at the beginning of the function.
226 Undo that for the recursion. */
227 res1 = helper_le_ld_name(env, addr1, mmu_idx, retaddr + GETPC_ADJ);
228 res2 = helper_le_ld_name(env, addr2, mmu_idx, retaddr + GETPC_ADJ);
229 shift = (addr & (DATA_SIZE - 1)) * 8;
230
231 /* Little-endian combine. */
232 res = (res1 >> shift) | (res2 << ((DATA_SIZE * 8) - shift));
233 return res;
234 }
235
236 /* Handle aligned access or unaligned access in the same page. */
237 #ifdef ALIGNED_ONLY
238 if ((addr & (DATA_SIZE - 1)) != 0) {
239 cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
240 mmu_idx, retaddr);
241 }
242 #endif
243
244 haddr = addr + env->tlb_table[mmu_idx][index].addend;
245 #if DATA_SIZE == 1
246 res = glue(glue(ld, LSUFFIX), _p)((uint8_t *)haddr);
247 #else
248 res = glue(glue(ld, LSUFFIX), _le_p)((uint8_t *)haddr);
249 #endif
250 return res;
251 }
252
253 #if DATA_SIZE > 1
254 #ifdef SOFTMMU_CODE_ACCESS
255 static __attribute__((unused))
256 #endif
257 WORD_TYPE helper_be_ld_name(CPUArchState *env, target_ulong addr, int mmu_idx,
258 uintptr_t retaddr)
259 {
260 int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
261 target_ulong tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
262 uintptr_t haddr;
263 DATA_TYPE res;
264
265 /* Adjust the given return address. */
266 retaddr -= GETPC_ADJ;
267
268 /* If the TLB entry is for a different page, reload and try again. */
269 if ((addr & TARGET_PAGE_MASK)
270 != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
271 #ifdef ALIGNED_ONLY
272 if ((addr & (DATA_SIZE - 1)) != 0) {
273 cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
274 mmu_idx, retaddr);
275 }
276 #endif
277 if (!VICTIM_TLB_HIT(ADDR_READ)) {
278 tlb_fill(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
279 mmu_idx, retaddr);
280 }
281 tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
282 }
283
284 /* Handle an IO access. */
285 if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
286 hwaddr ioaddr;
287 if ((addr & (DATA_SIZE - 1)) != 0) {
288 goto do_unaligned_access;
289 }
290 ioaddr = env->iotlb[mmu_idx][index];
291
292 /* ??? Note that the io helpers always read data in the target
293 byte ordering. We should push the LE/BE request down into io. */
294 res = glue(io_read, SUFFIX)(env, ioaddr, addr, retaddr);
295 res = TGT_BE(res);
296 return res;
297 }
298
299 /* Handle slow unaligned access (it spans two pages or IO). */
300 if (DATA_SIZE > 1
301 && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
302 >= TARGET_PAGE_SIZE)) {
303 target_ulong addr1, addr2;
304 DATA_TYPE res1, res2;
305 unsigned shift;
306 do_unaligned_access:
307 #ifdef ALIGNED_ONLY
308 cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
309 mmu_idx, retaddr);
310 #endif
311 addr1 = addr & ~(DATA_SIZE - 1);
312 addr2 = addr1 + DATA_SIZE;
313 /* Note the adjustment at the beginning of the function.
314 Undo that for the recursion. */
315 res1 = helper_be_ld_name(env, addr1, mmu_idx, retaddr + GETPC_ADJ);
316 res2 = helper_be_ld_name(env, addr2, mmu_idx, retaddr + GETPC_ADJ);
317 shift = (addr & (DATA_SIZE - 1)) * 8;
318
319 /* Big-endian combine. */
320 res = (res1 << shift) | (res2 >> ((DATA_SIZE * 8) - shift));
321 return res;
322 }
323
324 /* Handle aligned access or unaligned access in the same page. */
325 #ifdef ALIGNED_ONLY
326 if ((addr & (DATA_SIZE - 1)) != 0) {
327 cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
328 mmu_idx, retaddr);
329 }
330 #endif
331
332 haddr = addr + env->tlb_table[mmu_idx][index].addend;
333 res = glue(glue(ld, LSUFFIX), _be_p)((uint8_t *)haddr);
334 return res;
335 }
336 #endif /* DATA_SIZE > 1 */
337
338 DATA_TYPE
339 glue(glue(helper_ld, SUFFIX), MMUSUFFIX)(CPUArchState *env, target_ulong addr,
340 int mmu_idx)
341 {
342 return helper_te_ld_name (env, addr, mmu_idx, GETRA());
343 }
344
345 #ifndef SOFTMMU_CODE_ACCESS
346
347 /* Provide signed versions of the load routines as well. We can of course
348 avoid this for 64-bit data, or for 32-bit data on 32-bit host. */
349 #if DATA_SIZE * 8 < TCG_TARGET_REG_BITS
350 WORD_TYPE helper_le_lds_name(CPUArchState *env, target_ulong addr,
351 int mmu_idx, uintptr_t retaddr)
352 {
353 return (SDATA_TYPE)helper_le_ld_name(env, addr, mmu_idx, retaddr);
354 }
355
356 # if DATA_SIZE > 1
357 WORD_TYPE helper_be_lds_name(CPUArchState *env, target_ulong addr,
358 int mmu_idx, uintptr_t retaddr)
359 {
360 return (SDATA_TYPE)helper_be_ld_name(env, addr, mmu_idx, retaddr);
361 }
362 # endif
363 #endif
364
365 static inline void glue(io_write, SUFFIX)(CPUArchState *env,
366 hwaddr physaddr,
367 DATA_TYPE val,
368 target_ulong addr,
369 uintptr_t retaddr)
370 {
371 CPUState *cpu = ENV_GET_CPU(env);
372 MemoryRegion *mr = iotlb_to_region(cpu->as, physaddr);
373
374 physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
375 if (mr != &io_mem_rom && mr != &io_mem_notdirty && !cpu_can_do_io(cpu)) {
376 cpu_io_recompile(cpu, retaddr);
377 }
378
379 cpu->mem_io_vaddr = addr;
380 cpu->mem_io_pc = retaddr;
381 io_mem_write(mr, physaddr, val, 1 << SHIFT);
382 }
383
384 void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
385 int mmu_idx, uintptr_t retaddr)
386 {
387 int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
388 target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
389 uintptr_t haddr;
390
391 /* Adjust the given return address. */
392 retaddr -= GETPC_ADJ;
393
394 /* If the TLB entry is for a different page, reload and try again. */
395 if ((addr & TARGET_PAGE_MASK)
396 != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
397 #ifdef ALIGNED_ONLY
398 if ((addr & (DATA_SIZE - 1)) != 0) {
399 cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
400 mmu_idx, retaddr);
401 }
402 #endif
403 if (!VICTIM_TLB_HIT(addr_write)) {
404 tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr);
405 }
406 tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
407 }
408
409 /* Handle an IO access. */
410 if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
411 hwaddr ioaddr;
412 if ((addr & (DATA_SIZE - 1)) != 0) {
413 goto do_unaligned_access;
414 }
415 ioaddr = env->iotlb[mmu_idx][index];
416
417 /* ??? Note that the io helpers always read data in the target
418 byte ordering. We should push the LE/BE request down into io. */
419 val = TGT_LE(val);
420 glue(io_write, SUFFIX)(env, ioaddr, val, addr, retaddr);
421 return;
422 }
423
424 /* Handle slow unaligned access (it spans two pages or IO). */
425 if (DATA_SIZE > 1
426 && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
427 >= TARGET_PAGE_SIZE)) {
428 int i;
429 do_unaligned_access:
430 #ifdef ALIGNED_ONLY
431 cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
432 mmu_idx, retaddr);
433 #endif
434 /* XXX: not efficient, but simple */
435 /* Note: relies on the fact that tlb_fill() does not remove the
436 * previous page from the TLB cache. */
437 for (i = DATA_SIZE - 1; i >= 0; i--) {
438 /* Little-endian extract. */
439 uint8_t val8 = val >> (i * 8);
440 /* Note the adjustment at the beginning of the function.
441 Undo that for the recursion. */
442 glue(helper_ret_stb, MMUSUFFIX)(env, addr + i, val8,
443 mmu_idx, retaddr + GETPC_ADJ);
444 }
445 return;
446 }
447
448 /* Handle aligned access or unaligned access in the same page. */
449 #ifdef ALIGNED_ONLY
450 if ((addr & (DATA_SIZE - 1)) != 0) {
451 cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
452 mmu_idx, retaddr);
453 }
454 #endif
455
456 haddr = addr + env->tlb_table[mmu_idx][index].addend;
457 #if DATA_SIZE == 1
458 glue(glue(st, SUFFIX), _p)((uint8_t *)haddr, val);
459 #else
460 glue(glue(st, SUFFIX), _le_p)((uint8_t *)haddr, val);
461 #endif
462 }
463
464 #if DATA_SIZE > 1
465 void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
466 int mmu_idx, uintptr_t retaddr)
467 {
468 int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
469 target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
470 uintptr_t haddr;
471
472 /* Adjust the given return address. */
473 retaddr -= GETPC_ADJ;
474
475 /* If the TLB entry is for a different page, reload and try again. */
476 if ((addr & TARGET_PAGE_MASK)
477 != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
478 #ifdef ALIGNED_ONLY
479 if ((addr & (DATA_SIZE - 1)) != 0) {
480 cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
481 mmu_idx, retaddr);
482 }
483 #endif
484 if (!VICTIM_TLB_HIT(addr_write)) {
485 tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr);
486 }
487 tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
488 }
489
490 /* Handle an IO access. */
491 if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
492 hwaddr ioaddr;
493 if ((addr & (DATA_SIZE - 1)) != 0) {
494 goto do_unaligned_access;
495 }
496 ioaddr = env->iotlb[mmu_idx][index];
497
498 /* ??? Note that the io helpers always read data in the target
499 byte ordering. We should push the LE/BE request down into io. */
500 val = TGT_BE(val);
501 glue(io_write, SUFFIX)(env, ioaddr, val, addr, retaddr);
502 return;
503 }
504
505 /* Handle slow unaligned access (it spans two pages or IO). */
506 if (DATA_SIZE > 1
507 && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
508 >= TARGET_PAGE_SIZE)) {
509 int i;
510 do_unaligned_access:
511 #ifdef ALIGNED_ONLY
512 cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
513 mmu_idx, retaddr);
514 #endif
515 /* XXX: not efficient, but simple */
516 /* Note: relies on the fact that tlb_fill() does not remove the
517 * previous page from the TLB cache. */
518 for (i = DATA_SIZE - 1; i >= 0; i--) {
519 /* Big-endian extract. */
520 uint8_t val8 = val >> (((DATA_SIZE - 1) * 8) - (i * 8));
521 /* Note the adjustment at the beginning of the function.
522 Undo that for the recursion. */
523 glue(helper_ret_stb, MMUSUFFIX)(env, addr + i, val8,
524 mmu_idx, retaddr + GETPC_ADJ);
525 }
526 return;
527 }
528
529 /* Handle aligned access or unaligned access in the same page. */
530 #ifdef ALIGNED_ONLY
531 if ((addr & (DATA_SIZE - 1)) != 0) {
532 cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
533 mmu_idx, retaddr);
534 }
535 #endif
536
537 haddr = addr + env->tlb_table[mmu_idx][index].addend;
538 glue(glue(st, SUFFIX), _be_p)((uint8_t *)haddr, val);
539 }
540 #endif /* DATA_SIZE > 1 */
541
542 void
543 glue(glue(helper_st, SUFFIX), MMUSUFFIX)(CPUArchState *env, target_ulong addr,
544 DATA_TYPE val, int mmu_idx)
545 {
546 helper_te_st_name(env, addr, val, mmu_idx, GETRA());
547 }
548
549 #endif /* !defined(SOFTMMU_CODE_ACCESS) */
550
551 #undef READ_ACCESS_TYPE
552 #undef SHIFT
553 #undef DATA_TYPE
554 #undef SUFFIX
555 #undef LSUFFIX
556 #undef DATA_SIZE
557 #undef ADDR_READ
558 #undef WORD_TYPE
559 #undef SDATA_TYPE
560 #undef USUFFIX
561 #undef SSUFFIX
562 #undef BSWAP
563 #undef TGT_BE
564 #undef TGT_LE
565 #undef CPU_BE
566 #undef CPU_LE
567 #undef helper_le_ld_name
568 #undef helper_be_ld_name
569 #undef helper_le_lds_name
570 #undef helper_be_lds_name
571 #undef helper_le_st_name
572 #undef helper_be_st_name
573 #undef helper_te_ld_name
574 #undef helper_te_st_name