2 * i386 CPUID helper functions
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
20 #include "qemu/cutils.h"
23 #include "exec/exec-all.h"
24 #include "sysemu/kvm.h"
25 #include "sysemu/cpus.h"
28 #include "qemu/error-report.h"
29 #include "qemu/option.h"
30 #include "qemu/config-file.h"
31 #include "qapi/qmp/qerror.h"
32 #include "qapi/qmp/types.h"
34 #include "qapi-types.h"
35 #include "qapi-visit.h"
36 #include "qapi/visitor.h"
37 #include "qom/qom-qobject.h"
38 #include "sysemu/arch_init.h"
40 #if defined(CONFIG_KVM)
41 #include <linux/kvm_para.h>
44 #include "sysemu/sysemu.h"
45 #include "hw/qdev-properties.h"
46 #include "hw/i386/topology.h"
47 #ifndef CONFIG_USER_ONLY
48 #include "exec/address-spaces.h"
50 #include "hw/xen/xen.h"
51 #include "hw/i386/apic_internal.h"
54 #include "disas/capstone.h"
57 /* Cache topology CPUID constants: */
59 /* CPUID Leaf 2 Descriptors */
61 #define CPUID_2_L1D_32KB_8WAY_64B 0x2c
62 #define CPUID_2_L1I_32KB_8WAY_64B 0x30
63 #define CPUID_2_L2_2MB_8WAY_64B 0x7d
64 #define CPUID_2_L3_16MB_16WAY_64B 0x4d
67 /* CPUID Leaf 4 constants: */
70 #define CPUID_4_TYPE_DCACHE 1
71 #define CPUID_4_TYPE_ICACHE 2
72 #define CPUID_4_TYPE_UNIFIED 3
74 #define CPUID_4_LEVEL(l) ((l) << 5)
76 #define CPUID_4_SELF_INIT_LEVEL (1 << 8)
77 #define CPUID_4_FULLY_ASSOC (1 << 9)
80 #define CPUID_4_NO_INVD_SHARING (1 << 0)
81 #define CPUID_4_INCLUSIVE (1 << 1)
82 #define CPUID_4_COMPLEX_IDX (1 << 2)
84 #define ASSOC_FULL 0xFF
86 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */
87 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
97 a == ASSOC_FULL ? 0xF : \
98 0 /* invalid value */)
101 /* Definitions of the hardcoded cache entries we expose: */
104 #define L1D_LINE_SIZE 64
105 #define L1D_ASSOCIATIVITY 8
107 #define L1D_PARTITIONS 1
108 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
109 #define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
110 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
111 #define L1D_LINES_PER_TAG 1
112 #define L1D_SIZE_KB_AMD 64
113 #define L1D_ASSOCIATIVITY_AMD 2
115 /* L1 instruction cache: */
116 #define L1I_LINE_SIZE 64
117 #define L1I_ASSOCIATIVITY 8
119 #define L1I_PARTITIONS 1
120 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
121 #define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
122 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
123 #define L1I_LINES_PER_TAG 1
124 #define L1I_SIZE_KB_AMD 64
125 #define L1I_ASSOCIATIVITY_AMD 2
127 /* Level 2 unified cache: */
128 #define L2_LINE_SIZE 64
129 #define L2_ASSOCIATIVITY 16
131 #define L2_PARTITIONS 1
132 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
133 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
134 #define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
135 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
136 #define L2_LINES_PER_TAG 1
137 #define L2_SIZE_KB_AMD 512
139 /* Level 3 unified cache: */
140 #define L3_SIZE_KB 0 /* disabled */
141 #define L3_ASSOCIATIVITY 0 /* disabled */
142 #define L3_LINES_PER_TAG 0 /* disabled */
143 #define L3_LINE_SIZE 0 /* disabled */
144 #define L3_N_LINE_SIZE 64
145 #define L3_N_ASSOCIATIVITY 16
146 #define L3_N_SETS 16384
147 #define L3_N_PARTITIONS 1
148 #define L3_N_DESCRIPTOR CPUID_2_L3_16MB_16WAY_64B
149 #define L3_N_LINES_PER_TAG 1
150 #define L3_N_SIZE_KB_AMD 16384
152 /* TLB definitions: */
154 #define L1_DTLB_2M_ASSOC 1
155 #define L1_DTLB_2M_ENTRIES 255
156 #define L1_DTLB_4K_ASSOC 1
157 #define L1_DTLB_4K_ENTRIES 255
159 #define L1_ITLB_2M_ASSOC 1
160 #define L1_ITLB_2M_ENTRIES 255
161 #define L1_ITLB_4K_ASSOC 1
162 #define L1_ITLB_4K_ENTRIES 255
164 #define L2_DTLB_2M_ASSOC 0 /* disabled */
165 #define L2_DTLB_2M_ENTRIES 0 /* disabled */
166 #define L2_DTLB_4K_ASSOC 4
167 #define L2_DTLB_4K_ENTRIES 512
169 #define L2_ITLB_2M_ASSOC 0 /* disabled */
170 #define L2_ITLB_2M_ENTRIES 0 /* disabled */
171 #define L2_ITLB_4K_ASSOC 4
172 #define L2_ITLB_4K_ENTRIES 512
176 static void x86_cpu_vendor_words2str(char *dst
, uint32_t vendor1
,
177 uint32_t vendor2
, uint32_t vendor3
)
180 for (i
= 0; i
< 4; i
++) {
181 dst
[i
] = vendor1
>> (8 * i
);
182 dst
[i
+ 4] = vendor2
>> (8 * i
);
183 dst
[i
+ 8] = vendor3
>> (8 * i
);
185 dst
[CPUID_VENDOR_SZ
] = '\0';
188 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
189 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
190 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
191 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
192 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
193 CPUID_PSE36 | CPUID_FXSR)
194 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
195 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
196 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
197 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
198 CPUID_PAE | CPUID_SEP | CPUID_APIC)
200 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
201 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
202 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
203 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
204 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
205 /* partly implemented:
206 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
208 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
209 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
210 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
211 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
212 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
213 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
215 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
216 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
217 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
218 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
219 CPUID_EXT_F16C, CPUID_EXT_RDRAND */
222 #define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
224 #define TCG_EXT2_X86_64_FEATURES 0
227 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
228 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
229 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
230 TCG_EXT2_X86_64_FEATURES)
231 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
232 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
233 #define TCG_EXT4_FEATURES 0
234 #define TCG_SVM_FEATURES 0
235 #define TCG_KVM_FEATURES 0
236 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
237 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
238 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
239 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
242 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
243 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
244 CPUID_7_0_EBX_RDSEED */
245 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_OSPKE | \
247 #define TCG_7_0_EDX_FEATURES 0
248 #define TCG_APM_FEATURES 0
249 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
250 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
252 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
254 typedef struct FeatureWordInfo
{
255 /* feature flags names are taken from "Intel Processor Identification and
256 * the CPUID Instruction" and AMD's "CPUID Specification".
257 * In cases of disagreement between feature naming conventions,
258 * aliases may be added.
260 const char *feat_names
[32];
261 uint32_t cpuid_eax
; /* Input EAX for CPUID */
262 bool cpuid_needs_ecx
; /* CPUID instruction uses ECX as input */
263 uint32_t cpuid_ecx
; /* Input ECX value for CPUID */
264 int cpuid_reg
; /* output register (R_* constant) */
265 uint32_t tcg_features
; /* Feature flags supported by TCG */
266 uint32_t unmigratable_flags
; /* Feature flags known to be unmigratable */
267 uint32_t migratable_flags
; /* Feature flags known to be migratable */
270 static FeatureWordInfo feature_word_info
[FEATURE_WORDS
] = {
273 "fpu", "vme", "de", "pse",
274 "tsc", "msr", "pae", "mce",
275 "cx8", "apic", NULL
, "sep",
276 "mtrr", "pge", "mca", "cmov",
277 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
278 NULL
, "ds" /* Intel dts */, "acpi", "mmx",
279 "fxsr", "sse", "sse2", "ss",
280 "ht" /* Intel htt */, "tm", "ia64", "pbe",
282 .cpuid_eax
= 1, .cpuid_reg
= R_EDX
,
283 .tcg_features
= TCG_FEATURES
,
287 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
288 "ds-cpl", "vmx", "smx", "est",
289 "tm2", "ssse3", "cid", NULL
,
290 "fma", "cx16", "xtpr", "pdcm",
291 NULL
, "pcid", "dca", "sse4.1",
292 "sse4.2", "x2apic", "movbe", "popcnt",
293 "tsc-deadline", "aes", "xsave", "osxsave",
294 "avx", "f16c", "rdrand", "hypervisor",
296 .cpuid_eax
= 1, .cpuid_reg
= R_ECX
,
297 .tcg_features
= TCG_EXT_FEATURES
,
299 /* Feature names that are already defined on feature_name[] but
300 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
301 * names on feat_names below. They are copied automatically
302 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
304 [FEAT_8000_0001_EDX
] = {
306 NULL
/* fpu */, NULL
/* vme */, NULL
/* de */, NULL
/* pse */,
307 NULL
/* tsc */, NULL
/* msr */, NULL
/* pae */, NULL
/* mce */,
308 NULL
/* cx8 */, NULL
/* apic */, NULL
, "syscall",
309 NULL
/* mtrr */, NULL
/* pge */, NULL
/* mca */, NULL
/* cmov */,
310 NULL
/* pat */, NULL
/* pse36 */, NULL
, NULL
/* Linux mp */,
311 "nx", NULL
, "mmxext", NULL
/* mmx */,
312 NULL
/* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
313 NULL
, "lm", "3dnowext", "3dnow",
315 .cpuid_eax
= 0x80000001, .cpuid_reg
= R_EDX
,
316 .tcg_features
= TCG_EXT2_FEATURES
,
318 [FEAT_8000_0001_ECX
] = {
320 "lahf-lm", "cmp-legacy", "svm", "extapic",
321 "cr8legacy", "abm", "sse4a", "misalignsse",
322 "3dnowprefetch", "osvw", "ibs", "xop",
323 "skinit", "wdt", NULL
, "lwp",
324 "fma4", "tce", NULL
, "nodeid-msr",
325 NULL
, "tbm", "topoext", "perfctr-core",
326 "perfctr-nb", NULL
, NULL
, NULL
,
327 NULL
, NULL
, NULL
, NULL
,
329 .cpuid_eax
= 0x80000001, .cpuid_reg
= R_ECX
,
330 .tcg_features
= TCG_EXT3_FEATURES
,
332 [FEAT_C000_0001_EDX
] = {
334 NULL
, NULL
, "xstore", "xstore-en",
335 NULL
, NULL
, "xcrypt", "xcrypt-en",
336 "ace2", "ace2-en", "phe", "phe-en",
337 "pmm", "pmm-en", NULL
, NULL
,
338 NULL
, NULL
, NULL
, NULL
,
339 NULL
, NULL
, NULL
, NULL
,
340 NULL
, NULL
, NULL
, NULL
,
341 NULL
, NULL
, NULL
, NULL
,
343 .cpuid_eax
= 0xC0000001, .cpuid_reg
= R_EDX
,
344 .tcg_features
= TCG_EXT4_FEATURES
,
348 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
349 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
350 NULL
, "kvm-pv-tlb-flush", NULL
, NULL
,
351 NULL
, NULL
, NULL
, NULL
,
352 NULL
, NULL
, NULL
, NULL
,
353 NULL
, NULL
, NULL
, NULL
,
354 "kvmclock-stable-bit", NULL
, NULL
, NULL
,
355 NULL
, NULL
, NULL
, NULL
,
357 .cpuid_eax
= KVM_CPUID_FEATURES
, .cpuid_reg
= R_EAX
,
358 .tcg_features
= TCG_KVM_FEATURES
,
360 [FEAT_HYPERV_EAX
] = {
362 NULL
/* hv_msr_vp_runtime_access */, NULL
/* hv_msr_time_refcount_access */,
363 NULL
/* hv_msr_synic_access */, NULL
/* hv_msr_stimer_access */,
364 NULL
/* hv_msr_apic_access */, NULL
/* hv_msr_hypercall_access */,
365 NULL
/* hv_vpindex_access */, NULL
/* hv_msr_reset_access */,
366 NULL
/* hv_msr_stats_access */, NULL
/* hv_reftsc_access */,
367 NULL
/* hv_msr_idle_access */, NULL
/* hv_msr_frequency_access */,
368 NULL
, NULL
, NULL
, NULL
,
369 NULL
, NULL
, NULL
, NULL
,
370 NULL
, NULL
, NULL
, NULL
,
371 NULL
, NULL
, NULL
, NULL
,
372 NULL
, NULL
, NULL
, NULL
,
374 .cpuid_eax
= 0x40000003, .cpuid_reg
= R_EAX
,
376 [FEAT_HYPERV_EBX
] = {
378 NULL
/* hv_create_partitions */, NULL
/* hv_access_partition_id */,
379 NULL
/* hv_access_memory_pool */, NULL
/* hv_adjust_message_buffers */,
380 NULL
/* hv_post_messages */, NULL
/* hv_signal_events */,
381 NULL
/* hv_create_port */, NULL
/* hv_connect_port */,
382 NULL
/* hv_access_stats */, NULL
, NULL
, NULL
/* hv_debugging */,
383 NULL
/* hv_cpu_power_management */, NULL
/* hv_configure_profiler */,
385 NULL
, NULL
, NULL
, NULL
,
386 NULL
, NULL
, NULL
, NULL
,
387 NULL
, NULL
, NULL
, NULL
,
388 NULL
, NULL
, NULL
, NULL
,
390 .cpuid_eax
= 0x40000003, .cpuid_reg
= R_EBX
,
392 [FEAT_HYPERV_EDX
] = {
394 NULL
/* hv_mwait */, NULL
/* hv_guest_debugging */,
395 NULL
/* hv_perf_monitor */, NULL
/* hv_cpu_dynamic_part */,
396 NULL
/* hv_hypercall_params_xmm */, NULL
/* hv_guest_idle_state */,
398 NULL
, NULL
, NULL
/* hv_guest_crash_msr */, NULL
,
399 NULL
, NULL
, NULL
, NULL
,
400 NULL
, NULL
, NULL
, NULL
,
401 NULL
, NULL
, NULL
, NULL
,
402 NULL
, NULL
, NULL
, NULL
,
403 NULL
, NULL
, NULL
, NULL
,
405 .cpuid_eax
= 0x40000003, .cpuid_reg
= R_EDX
,
409 "npt", "lbrv", "svm-lock", "nrip-save",
410 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
411 NULL
, NULL
, "pause-filter", NULL
,
412 "pfthreshold", NULL
, NULL
, NULL
,
413 NULL
, NULL
, NULL
, NULL
,
414 NULL
, NULL
, NULL
, NULL
,
415 NULL
, NULL
, NULL
, NULL
,
416 NULL
, NULL
, NULL
, NULL
,
418 .cpuid_eax
= 0x8000000A, .cpuid_reg
= R_EDX
,
419 .tcg_features
= TCG_SVM_FEATURES
,
423 "fsgsbase", "tsc-adjust", NULL
, "bmi1",
424 "hle", "avx2", NULL
, "smep",
425 "bmi2", "erms", "invpcid", "rtm",
426 NULL
, NULL
, "mpx", NULL
,
427 "avx512f", "avx512dq", "rdseed", "adx",
428 "smap", "avx512ifma", "pcommit", "clflushopt",
429 "clwb", NULL
, "avx512pf", "avx512er",
430 "avx512cd", "sha-ni", "avx512bw", "avx512vl",
433 .cpuid_needs_ecx
= true, .cpuid_ecx
= 0,
435 .tcg_features
= TCG_7_0_EBX_FEATURES
,
439 NULL
, "avx512vbmi", "umip", "pku",
440 "ospke", NULL
, NULL
, NULL
,
441 NULL
, NULL
, NULL
, NULL
,
442 NULL
, NULL
, "avx512-vpopcntdq", NULL
,
443 "la57", NULL
, NULL
, NULL
,
444 NULL
, NULL
, "rdpid", NULL
,
445 NULL
, NULL
, NULL
, NULL
,
446 NULL
, NULL
, NULL
, NULL
,
449 .cpuid_needs_ecx
= true, .cpuid_ecx
= 0,
451 .tcg_features
= TCG_7_0_ECX_FEATURES
,
455 NULL
, NULL
, "avx512-4vnniw", "avx512-4fmaps",
456 NULL
, NULL
, NULL
, NULL
,
457 NULL
, NULL
, NULL
, NULL
,
458 NULL
, NULL
, NULL
, NULL
,
459 NULL
, NULL
, NULL
, NULL
,
460 NULL
, NULL
, NULL
, NULL
,
461 NULL
, NULL
, "spec-ctrl", NULL
,
462 NULL
, NULL
, NULL
, "ssbd",
465 .cpuid_needs_ecx
= true, .cpuid_ecx
= 0,
467 .tcg_features
= TCG_7_0_EDX_FEATURES
,
469 [FEAT_8000_0007_EDX
] = {
471 NULL
, NULL
, NULL
, NULL
,
472 NULL
, NULL
, NULL
, NULL
,
473 "invtsc", NULL
, NULL
, NULL
,
474 NULL
, NULL
, NULL
, NULL
,
475 NULL
, NULL
, NULL
, NULL
,
476 NULL
, NULL
, NULL
, NULL
,
477 NULL
, NULL
, NULL
, NULL
,
478 NULL
, NULL
, NULL
, NULL
,
480 .cpuid_eax
= 0x80000007,
482 .tcg_features
= TCG_APM_FEATURES
,
483 .unmigratable_flags
= CPUID_APM_INVTSC
,
485 [FEAT_8000_0008_EBX
] = {
487 NULL
, NULL
, NULL
, NULL
,
488 NULL
, NULL
, NULL
, NULL
,
489 NULL
, NULL
, NULL
, NULL
,
490 "ibpb", NULL
, NULL
, NULL
,
491 NULL
, NULL
, NULL
, NULL
,
492 NULL
, NULL
, NULL
, NULL
,
493 NULL
, "virt-ssbd", NULL
, NULL
,
494 NULL
, NULL
, NULL
, NULL
,
496 .cpuid_eax
= 0x80000008,
499 .unmigratable_flags
= 0,
503 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
504 NULL
, NULL
, NULL
, NULL
,
505 NULL
, NULL
, NULL
, NULL
,
506 NULL
, NULL
, NULL
, NULL
,
507 NULL
, NULL
, NULL
, NULL
,
508 NULL
, NULL
, NULL
, NULL
,
509 NULL
, NULL
, NULL
, NULL
,
510 NULL
, NULL
, NULL
, NULL
,
513 .cpuid_needs_ecx
= true, .cpuid_ecx
= 1,
515 .tcg_features
= TCG_XSAVE_FEATURES
,
519 NULL
, NULL
, "arat", NULL
,
520 NULL
, NULL
, NULL
, NULL
,
521 NULL
, NULL
, NULL
, NULL
,
522 NULL
, NULL
, NULL
, NULL
,
523 NULL
, NULL
, NULL
, NULL
,
524 NULL
, NULL
, NULL
, NULL
,
525 NULL
, NULL
, NULL
, NULL
,
526 NULL
, NULL
, NULL
, NULL
,
528 .cpuid_eax
= 6, .cpuid_reg
= R_EAX
,
529 .tcg_features
= TCG_6_EAX_FEATURES
,
531 [FEAT_XSAVE_COMP_LO
] = {
533 .cpuid_needs_ecx
= true, .cpuid_ecx
= 0,
536 .migratable_flags
= XSTATE_FP_MASK
| XSTATE_SSE_MASK
|
537 XSTATE_YMM_MASK
| XSTATE_BNDREGS_MASK
| XSTATE_BNDCSR_MASK
|
538 XSTATE_OPMASK_MASK
| XSTATE_ZMM_Hi256_MASK
| XSTATE_Hi16_ZMM_MASK
|
541 [FEAT_XSAVE_COMP_HI
] = {
543 .cpuid_needs_ecx
= true, .cpuid_ecx
= 0,
549 typedef struct X86RegisterInfo32
{
550 /* Name of register */
552 /* QAPI enum value register */
553 X86CPURegister32 qapi_enum
;
556 #define REGISTER(reg) \
557 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
558 static const X86RegisterInfo32 x86_reg_info_32
[CPU_NB_REGS32
] = {
570 typedef struct ExtSaveArea
{
571 uint32_t feature
, bits
;
572 uint32_t offset
, size
;
575 static const ExtSaveArea x86_ext_save_areas
[] = {
577 /* x87 FP state component is always enabled if XSAVE is supported */
578 .feature
= FEAT_1_ECX
, .bits
= CPUID_EXT_XSAVE
,
579 /* x87 state is in the legacy region of the XSAVE area */
581 .size
= sizeof(X86LegacyXSaveArea
) + sizeof(X86XSaveHeader
),
584 /* SSE state component is always enabled if XSAVE is supported */
585 .feature
= FEAT_1_ECX
, .bits
= CPUID_EXT_XSAVE
,
586 /* SSE state is in the legacy region of the XSAVE area */
588 .size
= sizeof(X86LegacyXSaveArea
) + sizeof(X86XSaveHeader
),
591 { .feature
= FEAT_1_ECX
, .bits
= CPUID_EXT_AVX
,
592 .offset
= offsetof(X86XSaveArea
, avx_state
),
593 .size
= sizeof(XSaveAVX
) },
594 [XSTATE_BNDREGS_BIT
] =
595 { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_MPX
,
596 .offset
= offsetof(X86XSaveArea
, bndreg_state
),
597 .size
= sizeof(XSaveBNDREG
) },
598 [XSTATE_BNDCSR_BIT
] =
599 { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_MPX
,
600 .offset
= offsetof(X86XSaveArea
, bndcsr_state
),
601 .size
= sizeof(XSaveBNDCSR
) },
602 [XSTATE_OPMASK_BIT
] =
603 { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_AVX512F
,
604 .offset
= offsetof(X86XSaveArea
, opmask_state
),
605 .size
= sizeof(XSaveOpmask
) },
606 [XSTATE_ZMM_Hi256_BIT
] =
607 { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_AVX512F
,
608 .offset
= offsetof(X86XSaveArea
, zmm_hi256_state
),
609 .size
= sizeof(XSaveZMM_Hi256
) },
610 [XSTATE_Hi16_ZMM_BIT
] =
611 { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_AVX512F
,
612 .offset
= offsetof(X86XSaveArea
, hi16_zmm_state
),
613 .size
= sizeof(XSaveHi16_ZMM
) },
615 { .feature
= FEAT_7_0_ECX
, .bits
= CPUID_7_0_ECX_PKU
,
616 .offset
= offsetof(X86XSaveArea
, pkru_state
),
617 .size
= sizeof(XSavePKRU
) },
620 static uint32_t xsave_area_size(uint64_t mask
)
625 for (i
= 0; i
< ARRAY_SIZE(x86_ext_save_areas
); i
++) {
626 const ExtSaveArea
*esa
= &x86_ext_save_areas
[i
];
627 if ((mask
>> i
) & 1) {
628 ret
= MAX(ret
, esa
->offset
+ esa
->size
);
634 static inline uint64_t x86_cpu_xsave_components(X86CPU
*cpu
)
636 return ((uint64_t)cpu
->env
.features
[FEAT_XSAVE_COMP_HI
]) << 32 |
637 cpu
->env
.features
[FEAT_XSAVE_COMP_LO
];
640 const char *get_register_name_32(unsigned int reg
)
642 if (reg
>= CPU_NB_REGS32
) {
645 return x86_reg_info_32
[reg
].name
;
649 * Returns the set of feature flags that are supported and migratable by
650 * QEMU, for a given FeatureWord.
652 static uint32_t x86_cpu_get_migratable_flags(FeatureWord w
)
654 FeatureWordInfo
*wi
= &feature_word_info
[w
];
658 for (i
= 0; i
< 32; i
++) {
659 uint32_t f
= 1U << i
;
661 /* If the feature name is known, it is implicitly considered migratable,
662 * unless it is explicitly set in unmigratable_flags */
663 if ((wi
->migratable_flags
& f
) ||
664 (wi
->feat_names
[i
] && !(wi
->unmigratable_flags
& f
))) {
671 void host_cpuid(uint32_t function
, uint32_t count
,
672 uint32_t *eax
, uint32_t *ebx
, uint32_t *ecx
, uint32_t *edx
)
678 : "=a"(vec
[0]), "=b"(vec
[1]),
679 "=c"(vec
[2]), "=d"(vec
[3])
680 : "0"(function
), "c"(count
) : "cc");
681 #elif defined(__i386__)
682 asm volatile("pusha \n\t"
684 "mov %%eax, 0(%2) \n\t"
685 "mov %%ebx, 4(%2) \n\t"
686 "mov %%ecx, 8(%2) \n\t"
687 "mov %%edx, 12(%2) \n\t"
689 : : "a"(function
), "c"(count
), "S"(vec
)
705 void host_vendor_fms(char *vendor
, int *family
, int *model
, int *stepping
)
707 uint32_t eax
, ebx
, ecx
, edx
;
709 host_cpuid(0x0, 0, &eax
, &ebx
, &ecx
, &edx
);
710 x86_cpu_vendor_words2str(vendor
, ebx
, edx
, ecx
);
712 host_cpuid(0x1, 0, &eax
, &ebx
, &ecx
, &edx
);
714 *family
= ((eax
>> 8) & 0x0F) + ((eax
>> 20) & 0xFF);
717 *model
= ((eax
>> 4) & 0x0F) | ((eax
& 0xF0000) >> 12);
720 *stepping
= eax
& 0x0F;
724 /* CPU class name definitions: */
726 /* Return type name for a given CPU model name
727 * Caller is responsible for freeing the returned string.
729 static char *x86_cpu_type_name(const char *model_name
)
731 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name
);
734 static ObjectClass
*x86_cpu_class_by_name(const char *cpu_model
)
739 if (cpu_model
== NULL
) {
743 typename
= x86_cpu_type_name(cpu_model
);
744 oc
= object_class_by_name(typename
);
749 static char *x86_cpu_class_get_model_name(X86CPUClass
*cc
)
751 const char *class_name
= object_class_get_name(OBJECT_CLASS(cc
));
752 assert(g_str_has_suffix(class_name
, X86_CPU_TYPE_SUFFIX
));
753 return g_strndup(class_name
,
754 strlen(class_name
) - strlen(X86_CPU_TYPE_SUFFIX
));
757 struct X86CPUDefinition
{
761 /* vendor is zero-terminated, 12 character ASCII string */
762 char vendor
[CPUID_VENDOR_SZ
+ 1];
766 FeatureWordArray features
;
767 const char *model_id
;
770 static X86CPUDefinition builtin_x86_defs
[] = {
774 .vendor
= CPUID_VENDOR_AMD
,
778 .features
[FEAT_1_EDX
] =
780 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
782 .features
[FEAT_1_ECX
] =
783 CPUID_EXT_SSE3
| CPUID_EXT_CX16
,
784 .features
[FEAT_8000_0001_EDX
] =
785 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
786 .features
[FEAT_8000_0001_ECX
] =
787 CPUID_EXT3_LAHF_LM
| CPUID_EXT3_SVM
,
788 .xlevel
= 0x8000000A,
789 .model_id
= "QEMU Virtual CPU version " QEMU_HW_VERSION
,
794 .vendor
= CPUID_VENDOR_AMD
,
798 /* Missing: CPUID_HT */
799 .features
[FEAT_1_EDX
] =
801 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
802 CPUID_PSE36
| CPUID_VME
,
803 .features
[FEAT_1_ECX
] =
804 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_CX16
|
806 .features
[FEAT_8000_0001_EDX
] =
807 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
|
808 CPUID_EXT2_3DNOW
| CPUID_EXT2_3DNOWEXT
| CPUID_EXT2_MMXEXT
|
809 CPUID_EXT2_FFXSR
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_RDTSCP
,
810 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
812 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
813 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
814 .features
[FEAT_8000_0001_ECX
] =
815 CPUID_EXT3_LAHF_LM
| CPUID_EXT3_SVM
|
816 CPUID_EXT3_ABM
| CPUID_EXT3_SSE4A
,
817 /* Missing: CPUID_SVM_LBRV */
818 .features
[FEAT_SVM
] =
820 .xlevel
= 0x8000001A,
821 .model_id
= "AMD Phenom(tm) 9550 Quad-Core Processor"
826 .vendor
= CPUID_VENDOR_INTEL
,
830 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
831 .features
[FEAT_1_EDX
] =
833 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
834 CPUID_PSE36
| CPUID_VME
| CPUID_ACPI
| CPUID_SS
,
835 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
836 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
837 .features
[FEAT_1_ECX
] =
838 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_SSSE3
|
840 .features
[FEAT_8000_0001_EDX
] =
841 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
842 .features
[FEAT_8000_0001_ECX
] =
844 .xlevel
= 0x80000008,
845 .model_id
= "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
850 .vendor
= CPUID_VENDOR_INTEL
,
854 /* Missing: CPUID_HT */
855 .features
[FEAT_1_EDX
] =
856 PPRO_FEATURES
| CPUID_VME
|
857 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
859 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
860 .features
[FEAT_1_ECX
] =
861 CPUID_EXT_SSE3
| CPUID_EXT_CX16
,
862 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
863 .features
[FEAT_8000_0001_EDX
] =
864 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
865 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
866 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
867 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
868 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
869 .features
[FEAT_8000_0001_ECX
] =
871 .xlevel
= 0x80000008,
872 .model_id
= "Common KVM processor"
877 .vendor
= CPUID_VENDOR_INTEL
,
881 .features
[FEAT_1_EDX
] =
883 .features
[FEAT_1_ECX
] =
885 .xlevel
= 0x80000004,
886 .model_id
= "QEMU Virtual CPU version " QEMU_HW_VERSION
,
891 .vendor
= CPUID_VENDOR_INTEL
,
895 .features
[FEAT_1_EDX
] =
896 PPRO_FEATURES
| CPUID_VME
|
897 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_PSE36
,
898 .features
[FEAT_1_ECX
] =
900 .features
[FEAT_8000_0001_ECX
] =
902 .xlevel
= 0x80000008,
903 .model_id
= "Common 32-bit KVM processor"
908 .vendor
= CPUID_VENDOR_INTEL
,
912 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
913 .features
[FEAT_1_EDX
] =
914 PPRO_FEATURES
| CPUID_VME
|
915 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_ACPI
|
917 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
918 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
919 .features
[FEAT_1_ECX
] =
920 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
,
921 .features
[FEAT_8000_0001_EDX
] =
923 .xlevel
= 0x80000008,
924 .model_id
= "Genuine Intel(R) CPU T2600 @ 2.16GHz",
929 .vendor
= CPUID_VENDOR_INTEL
,
933 .features
[FEAT_1_EDX
] =
941 .vendor
= CPUID_VENDOR_INTEL
,
945 .features
[FEAT_1_EDX
] =
953 .vendor
= CPUID_VENDOR_INTEL
,
957 .features
[FEAT_1_EDX
] =
965 .vendor
= CPUID_VENDOR_INTEL
,
969 .features
[FEAT_1_EDX
] =
977 .vendor
= CPUID_VENDOR_AMD
,
981 .features
[FEAT_1_EDX
] =
982 PPRO_FEATURES
| CPUID_PSE36
| CPUID_VME
| CPUID_MTRR
|
984 .features
[FEAT_8000_0001_EDX
] =
985 CPUID_EXT2_MMXEXT
| CPUID_EXT2_3DNOW
| CPUID_EXT2_3DNOWEXT
,
986 .xlevel
= 0x80000008,
987 .model_id
= "QEMU Virtual CPU version " QEMU_HW_VERSION
,
992 .vendor
= CPUID_VENDOR_INTEL
,
996 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
997 .features
[FEAT_1_EDX
] =
999 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_VME
|
1000 CPUID_ACPI
| CPUID_SS
,
1001 /* Some CPUs got no CPUID_SEP */
1002 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
1004 .features
[FEAT_1_ECX
] =
1005 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_SSSE3
|
1007 .features
[FEAT_8000_0001_EDX
] =
1009 .features
[FEAT_8000_0001_ECX
] =
1011 .xlevel
= 0x80000008,
1012 .model_id
= "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
1017 .vendor
= CPUID_VENDOR_INTEL
,
1021 .features
[FEAT_1_EDX
] =
1022 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1023 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1024 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1025 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1026 CPUID_DE
| CPUID_FP87
,
1027 .features
[FEAT_1_ECX
] =
1028 CPUID_EXT_SSSE3
| CPUID_EXT_SSE3
,
1029 .features
[FEAT_8000_0001_EDX
] =
1030 CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
1031 .features
[FEAT_8000_0001_ECX
] =
1033 .xlevel
= 0x80000008,
1034 .model_id
= "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
1039 .vendor
= CPUID_VENDOR_INTEL
,
1043 .features
[FEAT_1_EDX
] =
1044 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1045 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1046 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1047 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1048 CPUID_DE
| CPUID_FP87
,
1049 .features
[FEAT_1_ECX
] =
1050 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1052 .features
[FEAT_8000_0001_EDX
] =
1053 CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
1054 .features
[FEAT_8000_0001_ECX
] =
1056 .xlevel
= 0x80000008,
1057 .model_id
= "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
1062 .vendor
= CPUID_VENDOR_INTEL
,
1066 .features
[FEAT_1_EDX
] =
1067 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1068 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1069 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1070 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1071 CPUID_DE
| CPUID_FP87
,
1072 .features
[FEAT_1_ECX
] =
1073 CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
1074 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_SSE3
,
1075 .features
[FEAT_8000_0001_EDX
] =
1076 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
1077 .features
[FEAT_8000_0001_ECX
] =
1079 .xlevel
= 0x80000008,
1080 .model_id
= "Intel Core i7 9xx (Nehalem Class Core i7)",
1083 .name
= "Nehalem-IBRS",
1085 .vendor
= CPUID_VENDOR_INTEL
,
1089 .features
[FEAT_1_EDX
] =
1090 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1091 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1092 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1093 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1094 CPUID_DE
| CPUID_FP87
,
1095 .features
[FEAT_1_ECX
] =
1096 CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
1097 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_SSE3
,
1098 .features
[FEAT_7_0_EDX
] =
1099 CPUID_7_0_EDX_SPEC_CTRL
,
1100 .features
[FEAT_8000_0001_EDX
] =
1101 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
1102 .features
[FEAT_8000_0001_ECX
] =
1104 .xlevel
= 0x80000008,
1105 .model_id
= "Intel Core i7 9xx (Nehalem Core i7, IBRS update)",
1110 .vendor
= CPUID_VENDOR_INTEL
,
1114 .features
[FEAT_1_EDX
] =
1115 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1116 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1117 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1118 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1119 CPUID_DE
| CPUID_FP87
,
1120 .features
[FEAT_1_ECX
] =
1121 CPUID_EXT_AES
| CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
|
1122 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1123 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
,
1124 .features
[FEAT_8000_0001_EDX
] =
1125 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
1126 .features
[FEAT_8000_0001_ECX
] =
1128 .features
[FEAT_6_EAX
] =
1130 .xlevel
= 0x80000008,
1131 .model_id
= "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
1134 .name
= "Westmere-IBRS",
1136 .vendor
= CPUID_VENDOR_INTEL
,
1140 .features
[FEAT_1_EDX
] =
1141 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1142 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1143 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1144 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1145 CPUID_DE
| CPUID_FP87
,
1146 .features
[FEAT_1_ECX
] =
1147 CPUID_EXT_AES
| CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
|
1148 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1149 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
,
1150 .features
[FEAT_8000_0001_EDX
] =
1151 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
1152 .features
[FEAT_8000_0001_ECX
] =
1154 .features
[FEAT_7_0_EDX
] =
1155 CPUID_7_0_EDX_SPEC_CTRL
,
1156 .features
[FEAT_6_EAX
] =
1158 .xlevel
= 0x80000008,
1159 .model_id
= "Westmere E56xx/L56xx/X56xx (IBRS update)",
1162 .name
= "SandyBridge",
1164 .vendor
= CPUID_VENDOR_INTEL
,
1168 .features
[FEAT_1_EDX
] =
1169 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1170 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1171 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1172 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1173 CPUID_DE
| CPUID_FP87
,
1174 .features
[FEAT_1_ECX
] =
1175 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1176 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_POPCNT
|
1177 CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
1178 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
|
1180 .features
[FEAT_8000_0001_EDX
] =
1181 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1183 .features
[FEAT_8000_0001_ECX
] =
1185 .features
[FEAT_XSAVE
] =
1186 CPUID_XSAVE_XSAVEOPT
,
1187 .features
[FEAT_6_EAX
] =
1189 .xlevel
= 0x80000008,
1190 .model_id
= "Intel Xeon E312xx (Sandy Bridge)",
1193 .name
= "SandyBridge-IBRS",
1195 .vendor
= CPUID_VENDOR_INTEL
,
1199 .features
[FEAT_1_EDX
] =
1200 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1201 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1202 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1203 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1204 CPUID_DE
| CPUID_FP87
,
1205 .features
[FEAT_1_ECX
] =
1206 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1207 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_POPCNT
|
1208 CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
1209 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
|
1211 .features
[FEAT_8000_0001_EDX
] =
1212 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1214 .features
[FEAT_8000_0001_ECX
] =
1216 .features
[FEAT_7_0_EDX
] =
1217 CPUID_7_0_EDX_SPEC_CTRL
,
1218 .features
[FEAT_XSAVE
] =
1219 CPUID_XSAVE_XSAVEOPT
,
1220 .features
[FEAT_6_EAX
] =
1222 .xlevel
= 0x80000008,
1223 .model_id
= "Intel Xeon E312xx (Sandy Bridge, IBRS update)",
1226 .name
= "IvyBridge",
1228 .vendor
= CPUID_VENDOR_INTEL
,
1232 .features
[FEAT_1_EDX
] =
1233 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1234 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1235 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1236 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1237 CPUID_DE
| CPUID_FP87
,
1238 .features
[FEAT_1_ECX
] =
1239 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1240 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_POPCNT
|
1241 CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
1242 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
|
1243 CPUID_EXT_SSE3
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
1244 .features
[FEAT_7_0_EBX
] =
1245 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_SMEP
|
1247 .features
[FEAT_8000_0001_EDX
] =
1248 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1250 .features
[FEAT_8000_0001_ECX
] =
1252 .features
[FEAT_XSAVE
] =
1253 CPUID_XSAVE_XSAVEOPT
,
1254 .features
[FEAT_6_EAX
] =
1256 .xlevel
= 0x80000008,
1257 .model_id
= "Intel Xeon E3-12xx v2 (Ivy Bridge)",
1260 .name
= "IvyBridge-IBRS",
1262 .vendor
= CPUID_VENDOR_INTEL
,
1266 .features
[FEAT_1_EDX
] =
1267 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1268 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1269 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1270 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1271 CPUID_DE
| CPUID_FP87
,
1272 .features
[FEAT_1_ECX
] =
1273 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1274 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_POPCNT
|
1275 CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
1276 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
|
1277 CPUID_EXT_SSE3
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
1278 .features
[FEAT_7_0_EBX
] =
1279 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_SMEP
|
1281 .features
[FEAT_8000_0001_EDX
] =
1282 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1284 .features
[FEAT_8000_0001_ECX
] =
1286 .features
[FEAT_7_0_EDX
] =
1287 CPUID_7_0_EDX_SPEC_CTRL
,
1288 .features
[FEAT_XSAVE
] =
1289 CPUID_XSAVE_XSAVEOPT
,
1290 .features
[FEAT_6_EAX
] =
1292 .xlevel
= 0x80000008,
1293 .model_id
= "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)",
1296 .name
= "Haswell-noTSX",
1298 .vendor
= CPUID_VENDOR_INTEL
,
1302 .features
[FEAT_1_EDX
] =
1303 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1304 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1305 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1306 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1307 CPUID_DE
| CPUID_FP87
,
1308 .features
[FEAT_1_ECX
] =
1309 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1310 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
1311 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1312 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
1313 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
1314 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
1315 .features
[FEAT_8000_0001_EDX
] =
1316 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1318 .features
[FEAT_8000_0001_ECX
] =
1319 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
,
1320 .features
[FEAT_7_0_EBX
] =
1321 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
1322 CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
1323 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
,
1324 .features
[FEAT_XSAVE
] =
1325 CPUID_XSAVE_XSAVEOPT
,
1326 .features
[FEAT_6_EAX
] =
1328 .xlevel
= 0x80000008,
1329 .model_id
= "Intel Core Processor (Haswell, no TSX)",
1332 .name
= "Haswell-noTSX-IBRS",
1334 .vendor
= CPUID_VENDOR_INTEL
,
1338 .features
[FEAT_1_EDX
] =
1339 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1340 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1341 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1342 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1343 CPUID_DE
| CPUID_FP87
,
1344 .features
[FEAT_1_ECX
] =
1345 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1346 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
1347 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1348 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
1349 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
1350 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
1351 .features
[FEAT_8000_0001_EDX
] =
1352 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1354 .features
[FEAT_8000_0001_ECX
] =
1355 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
,
1356 .features
[FEAT_7_0_EDX
] =
1357 CPUID_7_0_EDX_SPEC_CTRL
,
1358 .features
[FEAT_7_0_EBX
] =
1359 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
1360 CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
1361 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
,
1362 .features
[FEAT_XSAVE
] =
1363 CPUID_XSAVE_XSAVEOPT
,
1364 .features
[FEAT_6_EAX
] =
1366 .xlevel
= 0x80000008,
1367 .model_id
= "Intel Core Processor (Haswell, no TSX, IBRS)",
1372 .vendor
= CPUID_VENDOR_INTEL
,
1376 .features
[FEAT_1_EDX
] =
1377 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1378 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1379 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1380 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1381 CPUID_DE
| CPUID_FP87
,
1382 .features
[FEAT_1_ECX
] =
1383 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1384 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
1385 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1386 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
1387 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
1388 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
1389 .features
[FEAT_8000_0001_EDX
] =
1390 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1392 .features
[FEAT_8000_0001_ECX
] =
1393 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
,
1394 .features
[FEAT_7_0_EBX
] =
1395 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
1396 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
1397 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
1399 .features
[FEAT_XSAVE
] =
1400 CPUID_XSAVE_XSAVEOPT
,
1401 .features
[FEAT_6_EAX
] =
1403 .xlevel
= 0x80000008,
1404 .model_id
= "Intel Core Processor (Haswell)",
1407 .name
= "Haswell-IBRS",
1409 .vendor
= CPUID_VENDOR_INTEL
,
1413 .features
[FEAT_1_EDX
] =
1414 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1415 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1416 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1417 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1418 CPUID_DE
| CPUID_FP87
,
1419 .features
[FEAT_1_ECX
] =
1420 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1421 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
1422 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1423 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
1424 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
1425 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
1426 .features
[FEAT_8000_0001_EDX
] =
1427 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1429 .features
[FEAT_8000_0001_ECX
] =
1430 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
,
1431 .features
[FEAT_7_0_EDX
] =
1432 CPUID_7_0_EDX_SPEC_CTRL
,
1433 .features
[FEAT_7_0_EBX
] =
1434 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
1435 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
1436 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
1438 .features
[FEAT_XSAVE
] =
1439 CPUID_XSAVE_XSAVEOPT
,
1440 .features
[FEAT_6_EAX
] =
1442 .xlevel
= 0x80000008,
1443 .model_id
= "Intel Core Processor (Haswell, IBRS)",
1446 .name
= "Broadwell-noTSX",
1448 .vendor
= CPUID_VENDOR_INTEL
,
1452 .features
[FEAT_1_EDX
] =
1453 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1454 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1455 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1456 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1457 CPUID_DE
| CPUID_FP87
,
1458 .features
[FEAT_1_ECX
] =
1459 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1460 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
1461 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1462 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
1463 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
1464 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
1465 .features
[FEAT_8000_0001_EDX
] =
1466 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1468 .features
[FEAT_8000_0001_ECX
] =
1469 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
1470 .features
[FEAT_7_0_EBX
] =
1471 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
1472 CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
1473 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
1474 CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
1476 .features
[FEAT_XSAVE
] =
1477 CPUID_XSAVE_XSAVEOPT
,
1478 .features
[FEAT_6_EAX
] =
1480 .xlevel
= 0x80000008,
1481 .model_id
= "Intel Core Processor (Broadwell, no TSX)",
1484 .name
= "Broadwell-noTSX-IBRS",
1486 .vendor
= CPUID_VENDOR_INTEL
,
1490 .features
[FEAT_1_EDX
] =
1491 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1492 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1493 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1494 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1495 CPUID_DE
| CPUID_FP87
,
1496 .features
[FEAT_1_ECX
] =
1497 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1498 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
1499 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1500 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
1501 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
1502 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
1503 .features
[FEAT_8000_0001_EDX
] =
1504 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1506 .features
[FEAT_8000_0001_ECX
] =
1507 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
1508 .features
[FEAT_7_0_EDX
] =
1509 CPUID_7_0_EDX_SPEC_CTRL
,
1510 .features
[FEAT_7_0_EBX
] =
1511 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
1512 CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
1513 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
1514 CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
1516 .features
[FEAT_XSAVE
] =
1517 CPUID_XSAVE_XSAVEOPT
,
1518 .features
[FEAT_6_EAX
] =
1520 .xlevel
= 0x80000008,
1521 .model_id
= "Intel Core Processor (Broadwell, no TSX, IBRS)",
1524 .name
= "Broadwell",
1526 .vendor
= CPUID_VENDOR_INTEL
,
1530 .features
[FEAT_1_EDX
] =
1531 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1532 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1533 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1534 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1535 CPUID_DE
| CPUID_FP87
,
1536 .features
[FEAT_1_ECX
] =
1537 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1538 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
1539 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1540 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
1541 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
1542 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
1543 .features
[FEAT_8000_0001_EDX
] =
1544 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1546 .features
[FEAT_8000_0001_ECX
] =
1547 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
1548 .features
[FEAT_7_0_EBX
] =
1549 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
1550 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
1551 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
1552 CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
1554 .features
[FEAT_XSAVE
] =
1555 CPUID_XSAVE_XSAVEOPT
,
1556 .features
[FEAT_6_EAX
] =
1558 .xlevel
= 0x80000008,
1559 .model_id
= "Intel Core Processor (Broadwell)",
1562 .name
= "Broadwell-IBRS",
1564 .vendor
= CPUID_VENDOR_INTEL
,
1568 .features
[FEAT_1_EDX
] =
1569 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1570 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1571 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1572 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1573 CPUID_DE
| CPUID_FP87
,
1574 .features
[FEAT_1_ECX
] =
1575 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1576 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
1577 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1578 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
1579 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
1580 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
1581 .features
[FEAT_8000_0001_EDX
] =
1582 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1584 .features
[FEAT_8000_0001_ECX
] =
1585 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
1586 .features
[FEAT_7_0_EDX
] =
1587 CPUID_7_0_EDX_SPEC_CTRL
,
1588 .features
[FEAT_7_0_EBX
] =
1589 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
1590 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
1591 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
1592 CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
1594 .features
[FEAT_XSAVE
] =
1595 CPUID_XSAVE_XSAVEOPT
,
1596 .features
[FEAT_6_EAX
] =
1598 .xlevel
= 0x80000008,
1599 .model_id
= "Intel Core Processor (Broadwell, IBRS)",
1602 .name
= "Skylake-Client",
1604 .vendor
= CPUID_VENDOR_INTEL
,
1608 .features
[FEAT_1_EDX
] =
1609 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1610 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1611 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1612 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1613 CPUID_DE
| CPUID_FP87
,
1614 .features
[FEAT_1_ECX
] =
1615 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1616 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
1617 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1618 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
1619 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
1620 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
1621 .features
[FEAT_8000_0001_EDX
] =
1622 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1624 .features
[FEAT_8000_0001_ECX
] =
1625 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
1626 .features
[FEAT_7_0_EBX
] =
1627 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
1628 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
1629 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
1630 CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
1631 CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_MPX
,
1632 /* Missing: XSAVES (not supported by some Linux versions,
1633 * including v4.1 to v4.12).
1634 * KVM doesn't yet expose any XSAVES state save component,
1635 * and the only one defined in Skylake (processor tracing)
1636 * probably will block migration anyway.
1638 .features
[FEAT_XSAVE
] =
1639 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
1640 CPUID_XSAVE_XGETBV1
,
1641 .features
[FEAT_6_EAX
] =
1643 .xlevel
= 0x80000008,
1644 .model_id
= "Intel Core Processor (Skylake)",
1647 .name
= "Skylake-Client-IBRS",
1649 .vendor
= CPUID_VENDOR_INTEL
,
1653 .features
[FEAT_1_EDX
] =
1654 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1655 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1656 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1657 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1658 CPUID_DE
| CPUID_FP87
,
1659 .features
[FEAT_1_ECX
] =
1660 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1661 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
1662 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1663 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
1664 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
1665 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
1666 .features
[FEAT_8000_0001_EDX
] =
1667 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1669 .features
[FEAT_8000_0001_ECX
] =
1670 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
1671 .features
[FEAT_7_0_EDX
] =
1672 CPUID_7_0_EDX_SPEC_CTRL
,
1673 .features
[FEAT_7_0_EBX
] =
1674 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
1675 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
1676 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
1677 CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
1678 CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_MPX
,
1679 /* Missing: XSAVES (not supported by some Linux versions,
1680 * including v4.1 to v4.12).
1681 * KVM doesn't yet expose any XSAVES state save component,
1682 * and the only one defined in Skylake (processor tracing)
1683 * probably will block migration anyway.
1685 .features
[FEAT_XSAVE
] =
1686 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
1687 CPUID_XSAVE_XGETBV1
,
1688 .features
[FEAT_6_EAX
] =
1690 .xlevel
= 0x80000008,
1691 .model_id
= "Intel Core Processor (Skylake, IBRS)",
1694 .name
= "Skylake-Server",
1696 .vendor
= CPUID_VENDOR_INTEL
,
1700 .features
[FEAT_1_EDX
] =
1701 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1702 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1703 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1704 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1705 CPUID_DE
| CPUID_FP87
,
1706 .features
[FEAT_1_ECX
] =
1707 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1708 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
1709 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1710 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
1711 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
1712 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
1713 .features
[FEAT_8000_0001_EDX
] =
1714 CPUID_EXT2_LM
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_RDTSCP
|
1715 CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
1716 .features
[FEAT_8000_0001_ECX
] =
1717 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
1718 .features
[FEAT_7_0_EBX
] =
1719 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
1720 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
1721 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
1722 CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
1723 CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_MPX
| CPUID_7_0_EBX_CLWB
|
1724 CPUID_7_0_EBX_AVX512F
| CPUID_7_0_EBX_AVX512DQ
|
1725 CPUID_7_0_EBX_AVX512BW
| CPUID_7_0_EBX_AVX512CD
|
1726 CPUID_7_0_EBX_AVX512VL
,
1727 /* Missing: XSAVES (not supported by some Linux versions,
1728 * including v4.1 to v4.12).
1729 * KVM doesn't yet expose any XSAVES state save component,
1730 * and the only one defined in Skylake (processor tracing)
1731 * probably will block migration anyway.
1733 .features
[FEAT_XSAVE
] =
1734 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
1735 CPUID_XSAVE_XGETBV1
,
1736 .features
[FEAT_6_EAX
] =
1738 .xlevel
= 0x80000008,
1739 .model_id
= "Intel Xeon Processor (Skylake)",
1742 .name
= "Skylake-Server-IBRS",
1744 .vendor
= CPUID_VENDOR_INTEL
,
1748 .features
[FEAT_1_EDX
] =
1749 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1750 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1751 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1752 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1753 CPUID_DE
| CPUID_FP87
,
1754 .features
[FEAT_1_ECX
] =
1755 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1756 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
1757 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1758 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
1759 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
1760 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
1761 .features
[FEAT_8000_0001_EDX
] =
1762 CPUID_EXT2_LM
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_RDTSCP
|
1763 CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
1764 .features
[FEAT_8000_0001_ECX
] =
1765 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
1766 .features
[FEAT_7_0_EDX
] =
1767 CPUID_7_0_EDX_SPEC_CTRL
,
1768 .features
[FEAT_7_0_EBX
] =
1769 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
1770 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
1771 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
1772 CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
1773 CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_MPX
| CPUID_7_0_EBX_CLWB
|
1774 CPUID_7_0_EBX_AVX512F
| CPUID_7_0_EBX_AVX512DQ
|
1775 CPUID_7_0_EBX_AVX512BW
| CPUID_7_0_EBX_AVX512CD
|
1776 CPUID_7_0_EBX_AVX512VL
,
1777 /* Missing: XSAVES (not supported by some Linux versions,
1778 * including v4.1 to v4.12).
1779 * KVM doesn't yet expose any XSAVES state save component,
1780 * and the only one defined in Skylake (processor tracing)
1781 * probably will block migration anyway.
1783 .features
[FEAT_XSAVE
] =
1784 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
1785 CPUID_XSAVE_XGETBV1
,
1786 .features
[FEAT_6_EAX
] =
1788 .xlevel
= 0x80000008,
1789 .model_id
= "Intel Xeon Processor (Skylake, IBRS)",
1792 .name
= "Opteron_G1",
1794 .vendor
= CPUID_VENDOR_AMD
,
1798 .features
[FEAT_1_EDX
] =
1799 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1800 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1801 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1802 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1803 CPUID_DE
| CPUID_FP87
,
1804 .features
[FEAT_1_ECX
] =
1806 .features
[FEAT_8000_0001_EDX
] =
1807 CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
1808 .xlevel
= 0x80000008,
1809 .model_id
= "AMD Opteron 240 (Gen 1 Class Opteron)",
1812 .name
= "Opteron_G2",
1814 .vendor
= CPUID_VENDOR_AMD
,
1818 .features
[FEAT_1_EDX
] =
1819 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1820 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1821 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1822 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1823 CPUID_DE
| CPUID_FP87
,
1824 .features
[FEAT_1_ECX
] =
1825 CPUID_EXT_CX16
| CPUID_EXT_SSE3
,
1826 /* Missing: CPUID_EXT2_RDTSCP */
1827 .features
[FEAT_8000_0001_EDX
] =
1828 CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
1829 .features
[FEAT_8000_0001_ECX
] =
1830 CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
,
1831 .xlevel
= 0x80000008,
1832 .model_id
= "AMD Opteron 22xx (Gen 2 Class Opteron)",
1835 .name
= "Opteron_G3",
1837 .vendor
= CPUID_VENDOR_AMD
,
1841 .features
[FEAT_1_EDX
] =
1842 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1843 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1844 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1845 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1846 CPUID_DE
| CPUID_FP87
,
1847 .features
[FEAT_1_ECX
] =
1848 CPUID_EXT_POPCNT
| CPUID_EXT_CX16
| CPUID_EXT_MONITOR
|
1850 /* Missing: CPUID_EXT2_RDTSCP */
1851 .features
[FEAT_8000_0001_EDX
] =
1852 CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
1853 .features
[FEAT_8000_0001_ECX
] =
1854 CPUID_EXT3_MISALIGNSSE
| CPUID_EXT3_SSE4A
|
1855 CPUID_EXT3_ABM
| CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
,
1856 .xlevel
= 0x80000008,
1857 .model_id
= "AMD Opteron 23xx (Gen 3 Class Opteron)",
1860 .name
= "Opteron_G4",
1862 .vendor
= CPUID_VENDOR_AMD
,
1866 .features
[FEAT_1_EDX
] =
1867 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1868 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1869 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1870 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1871 CPUID_DE
| CPUID_FP87
,
1872 .features
[FEAT_1_ECX
] =
1873 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1874 CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
1875 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
|
1877 /* Missing: CPUID_EXT2_RDTSCP */
1878 .features
[FEAT_8000_0001_EDX
] =
1879 CPUID_EXT2_LM
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_NX
|
1881 .features
[FEAT_8000_0001_ECX
] =
1882 CPUID_EXT3_FMA4
| CPUID_EXT3_XOP
|
1883 CPUID_EXT3_3DNOWPREFETCH
| CPUID_EXT3_MISALIGNSSE
|
1884 CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
| CPUID_EXT3_SVM
|
1887 .xlevel
= 0x8000001A,
1888 .model_id
= "AMD Opteron 62xx class CPU",
1891 .name
= "Opteron_G5",
1893 .vendor
= CPUID_VENDOR_AMD
,
1897 .features
[FEAT_1_EDX
] =
1898 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1899 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1900 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1901 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1902 CPUID_DE
| CPUID_FP87
,
1903 .features
[FEAT_1_ECX
] =
1904 CPUID_EXT_F16C
| CPUID_EXT_AVX
| CPUID_EXT_XSAVE
|
1905 CPUID_EXT_AES
| CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
|
1906 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_FMA
|
1907 CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
,
1908 /* Missing: CPUID_EXT2_RDTSCP */
1909 .features
[FEAT_8000_0001_EDX
] =
1910 CPUID_EXT2_LM
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_NX
|
1912 .features
[FEAT_8000_0001_ECX
] =
1913 CPUID_EXT3_TBM
| CPUID_EXT3_FMA4
| CPUID_EXT3_XOP
|
1914 CPUID_EXT3_3DNOWPREFETCH
| CPUID_EXT3_MISALIGNSSE
|
1915 CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
| CPUID_EXT3_SVM
|
1918 .xlevel
= 0x8000001A,
1919 .model_id
= "AMD Opteron 63xx class CPU",
1924 .vendor
= CPUID_VENDOR_AMD
,
1928 .features
[FEAT_1_EDX
] =
1929 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
| CPUID_CLFLUSH
|
1930 CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
| CPUID_PGE
|
1931 CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
| CPUID_MCE
|
1932 CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
| CPUID_DE
|
1933 CPUID_VME
| CPUID_FP87
,
1934 .features
[FEAT_1_ECX
] =
1935 CPUID_EXT_RDRAND
| CPUID_EXT_F16C
| CPUID_EXT_AVX
|
1936 CPUID_EXT_XSAVE
| CPUID_EXT_AES
| CPUID_EXT_POPCNT
|
1937 CPUID_EXT_MOVBE
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
1938 CPUID_EXT_CX16
| CPUID_EXT_FMA
| CPUID_EXT_SSSE3
|
1939 CPUID_EXT_MONITOR
| CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
,
1940 .features
[FEAT_8000_0001_EDX
] =
1941 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_PDPE1GB
|
1942 CPUID_EXT2_FFXSR
| CPUID_EXT2_MMXEXT
| CPUID_EXT2_NX
|
1944 .features
[FEAT_8000_0001_ECX
] =
1945 CPUID_EXT3_OSVW
| CPUID_EXT3_3DNOWPREFETCH
|
1946 CPUID_EXT3_MISALIGNSSE
| CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
|
1947 CPUID_EXT3_CR8LEG
| CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
,
1948 .features
[FEAT_7_0_EBX
] =
1949 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
| CPUID_7_0_EBX_AVX2
|
1950 CPUID_7_0_EBX_SMEP
| CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_RDSEED
|
1951 CPUID_7_0_EBX_ADX
| CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_CLFLUSHOPT
|
1952 CPUID_7_0_EBX_SHA_NI
,
1953 /* Missing: XSAVES (not supported by some Linux versions,
1954 * including v4.1 to v4.12).
1955 * KVM doesn't yet expose any XSAVES state save component.
1957 .features
[FEAT_XSAVE
] =
1958 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
1959 CPUID_XSAVE_XGETBV1
,
1960 .features
[FEAT_6_EAX
] =
1962 .xlevel
= 0x8000000A,
1963 .model_id
= "AMD EPYC Processor",
1966 .name
= "EPYC-IBPB",
1968 .vendor
= CPUID_VENDOR_AMD
,
1972 .features
[FEAT_1_EDX
] =
1973 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
| CPUID_CLFLUSH
|
1974 CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
| CPUID_PGE
|
1975 CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
| CPUID_MCE
|
1976 CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
| CPUID_DE
|
1977 CPUID_VME
| CPUID_FP87
,
1978 .features
[FEAT_1_ECX
] =
1979 CPUID_EXT_RDRAND
| CPUID_EXT_F16C
| CPUID_EXT_AVX
|
1980 CPUID_EXT_XSAVE
| CPUID_EXT_AES
| CPUID_EXT_POPCNT
|
1981 CPUID_EXT_MOVBE
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
1982 CPUID_EXT_CX16
| CPUID_EXT_FMA
| CPUID_EXT_SSSE3
|
1983 CPUID_EXT_MONITOR
| CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
,
1984 .features
[FEAT_8000_0001_EDX
] =
1985 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_PDPE1GB
|
1986 CPUID_EXT2_FFXSR
| CPUID_EXT2_MMXEXT
| CPUID_EXT2_NX
|
1988 .features
[FEAT_8000_0001_ECX
] =
1989 CPUID_EXT3_OSVW
| CPUID_EXT3_3DNOWPREFETCH
|
1990 CPUID_EXT3_MISALIGNSSE
| CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
|
1991 CPUID_EXT3_CR8LEG
| CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
,
1992 .features
[FEAT_8000_0008_EBX
] =
1993 CPUID_8000_0008_EBX_IBPB
,
1994 .features
[FEAT_7_0_EBX
] =
1995 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
| CPUID_7_0_EBX_AVX2
|
1996 CPUID_7_0_EBX_SMEP
| CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_RDSEED
|
1997 CPUID_7_0_EBX_ADX
| CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_CLFLUSHOPT
|
1998 CPUID_7_0_EBX_SHA_NI
,
1999 /* Missing: XSAVES (not supported by some Linux versions,
2000 * including v4.1 to v4.12).
2001 * KVM doesn't yet expose any XSAVES state save component.
2003 .features
[FEAT_XSAVE
] =
2004 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
2005 CPUID_XSAVE_XGETBV1
,
2006 .features
[FEAT_6_EAX
] =
2008 .xlevel
= 0x8000000A,
2009 .model_id
= "AMD EPYC Processor (with IBPB)",
2013 typedef struct PropValue
{
2014 const char *prop
, *value
;
2017 /* KVM-specific features that are automatically added/removed
2018 * from all CPU models when KVM is enabled.
2020 static PropValue kvm_default_props
[] = {
2021 { "kvmclock", "on" },
2022 { "kvm-nopiodelay", "on" },
2023 { "kvm-asyncpf", "on" },
2024 { "kvm-steal-time", "on" },
2025 { "kvm-pv-eoi", "on" },
2026 { "kvmclock-stable-bit", "on" },
2029 { "monitor", "off" },
2034 /* TCG-specific defaults that override all CPU models when using TCG
2036 static PropValue tcg_default_props
[] = {
2042 void x86_cpu_change_kvm_default(const char *prop
, const char *value
)
2045 for (pv
= kvm_default_props
; pv
->prop
; pv
++) {
2046 if (!strcmp(pv
->prop
, prop
)) {
2052 /* It is valid to call this function only for properties that
2053 * are already present in the kvm_default_props table.
2058 static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w
,
2059 bool migratable_only
);
2061 static bool lmce_supported(void)
2063 uint64_t mce_cap
= 0;
2066 if (kvm_ioctl(kvm_state
, KVM_X86_GET_MCE_CAP_SUPPORTED
, &mce_cap
) < 0) {
2071 return !!(mce_cap
& MCG_LMCE_P
);
2074 #define CPUID_MODEL_ID_SZ 48
2077 * cpu_x86_fill_model_id:
2078 * Get CPUID model ID string from host CPU.
2080 * @str should have at least CPUID_MODEL_ID_SZ bytes
2082 * The function does NOT add a null terminator to the string
2085 static int cpu_x86_fill_model_id(char *str
)
2087 uint32_t eax
= 0, ebx
= 0, ecx
= 0, edx
= 0;
2090 for (i
= 0; i
< 3; i
++) {
2091 host_cpuid(0x80000002 + i
, 0, &eax
, &ebx
, &ecx
, &edx
);
2092 memcpy(str
+ i
* 16 + 0, &eax
, 4);
2093 memcpy(str
+ i
* 16 + 4, &ebx
, 4);
2094 memcpy(str
+ i
* 16 + 8, &ecx
, 4);
2095 memcpy(str
+ i
* 16 + 12, &edx
, 4);
2100 static Property max_x86_cpu_properties
[] = {
2101 DEFINE_PROP_BOOL("migratable", X86CPU
, migratable
, true),
2102 DEFINE_PROP_BOOL("host-cache-info", X86CPU
, cache_info_passthrough
, false),
2103 DEFINE_PROP_END_OF_LIST()
2106 static void max_x86_cpu_class_init(ObjectClass
*oc
, void *data
)
2108 DeviceClass
*dc
= DEVICE_CLASS(oc
);
2109 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
2113 xcc
->model_description
=
2114 "Enables all features supported by the accelerator in the current host";
2116 dc
->props
= max_x86_cpu_properties
;
2119 static void x86_cpu_load_def(X86CPU
*cpu
, X86CPUDefinition
*def
, Error
**errp
);
2121 static void max_x86_cpu_initfn(Object
*obj
)
2123 X86CPU
*cpu
= X86_CPU(obj
);
2124 CPUX86State
*env
= &cpu
->env
;
2125 KVMState
*s
= kvm_state
;
2127 /* We can't fill the features array here because we don't know yet if
2128 * "migratable" is true or false.
2130 cpu
->max_features
= true;
2132 if (kvm_enabled()) {
2133 char vendor
[CPUID_VENDOR_SZ
+ 1] = { 0 };
2134 char model_id
[CPUID_MODEL_ID_SZ
+ 1] = { 0 };
2135 int family
, model
, stepping
;
2137 host_vendor_fms(vendor
, &family
, &model
, &stepping
);
2139 cpu_x86_fill_model_id(model_id
);
2141 object_property_set_str(OBJECT(cpu
), vendor
, "vendor", &error_abort
);
2142 object_property_set_int(OBJECT(cpu
), family
, "family", &error_abort
);
2143 object_property_set_int(OBJECT(cpu
), model
, "model", &error_abort
);
2144 object_property_set_int(OBJECT(cpu
), stepping
, "stepping",
2146 object_property_set_str(OBJECT(cpu
), model_id
, "model-id",
2149 env
->cpuid_min_level
=
2150 kvm_arch_get_supported_cpuid(s
, 0x0, 0, R_EAX
);
2151 env
->cpuid_min_xlevel
=
2152 kvm_arch_get_supported_cpuid(s
, 0x80000000, 0, R_EAX
);
2153 env
->cpuid_min_xlevel2
=
2154 kvm_arch_get_supported_cpuid(s
, 0xC0000000, 0, R_EAX
);
2156 if (lmce_supported()) {
2157 object_property_set_bool(OBJECT(cpu
), true, "lmce", &error_abort
);
2160 object_property_set_str(OBJECT(cpu
), CPUID_VENDOR_AMD
,
2161 "vendor", &error_abort
);
2162 object_property_set_int(OBJECT(cpu
), 6, "family", &error_abort
);
2163 object_property_set_int(OBJECT(cpu
), 6, "model", &error_abort
);
2164 object_property_set_int(OBJECT(cpu
), 3, "stepping", &error_abort
);
2165 object_property_set_str(OBJECT(cpu
),
2166 "QEMU TCG CPU version " QEMU_HW_VERSION
,
2167 "model-id", &error_abort
);
2170 object_property_set_bool(OBJECT(cpu
), true, "pmu", &error_abort
);
2173 static const TypeInfo max_x86_cpu_type_info
= {
2174 .name
= X86_CPU_TYPE_NAME("max"),
2175 .parent
= TYPE_X86_CPU
,
2176 .instance_init
= max_x86_cpu_initfn
,
2177 .class_init
= max_x86_cpu_class_init
,
2182 static void host_x86_cpu_class_init(ObjectClass
*oc
, void *data
)
2184 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
2186 xcc
->kvm_required
= true;
2189 xcc
->model_description
=
2190 "KVM processor with all supported host features "
2191 "(only available in KVM mode)";
2194 static const TypeInfo host_x86_cpu_type_info
= {
2195 .name
= X86_CPU_TYPE_NAME("host"),
2196 .parent
= X86_CPU_TYPE_NAME("max"),
2197 .class_init
= host_x86_cpu_class_init
,
2202 static void report_unavailable_features(FeatureWord w
, uint32_t mask
)
2204 FeatureWordInfo
*f
= &feature_word_info
[w
];
2207 for (i
= 0; i
< 32; ++i
) {
2208 if ((1UL << i
) & mask
) {
2209 const char *reg
= get_register_name_32(f
->cpuid_reg
);
2211 warn_report("%s doesn't support requested feature: "
2212 "CPUID.%02XH:%s%s%s [bit %d]",
2213 kvm_enabled() ?
"host" : "TCG",
2215 f
->feat_names
[i
] ?
"." : "",
2216 f
->feat_names
[i
] ? f
->feat_names
[i
] : "", i
);
2221 static void x86_cpuid_version_get_family(Object
*obj
, Visitor
*v
,
2222 const char *name
, void *opaque
,
2225 X86CPU
*cpu
= X86_CPU(obj
);
2226 CPUX86State
*env
= &cpu
->env
;
2229 value
= (env
->cpuid_version
>> 8) & 0xf;
2231 value
+= (env
->cpuid_version
>> 20) & 0xff;
2233 visit_type_int(v
, name
, &value
, errp
);
2236 static void x86_cpuid_version_set_family(Object
*obj
, Visitor
*v
,
2237 const char *name
, void *opaque
,
2240 X86CPU
*cpu
= X86_CPU(obj
);
2241 CPUX86State
*env
= &cpu
->env
;
2242 const int64_t min
= 0;
2243 const int64_t max
= 0xff + 0xf;
2244 Error
*local_err
= NULL
;
2247 visit_type_int(v
, name
, &value
, &local_err
);
2249 error_propagate(errp
, local_err
);
2252 if (value
< min
|| value
> max
) {
2253 error_setg(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
2254 name ? name
: "null", value
, min
, max
);
2258 env
->cpuid_version
&= ~0xff00f00;
2260 env
->cpuid_version
|= 0xf00 | ((value
- 0x0f) << 20);
2262 env
->cpuid_version
|= value
<< 8;
2266 static void x86_cpuid_version_get_model(Object
*obj
, Visitor
*v
,
2267 const char *name
, void *opaque
,
2270 X86CPU
*cpu
= X86_CPU(obj
);
2271 CPUX86State
*env
= &cpu
->env
;
2274 value
= (env
->cpuid_version
>> 4) & 0xf;
2275 value
|= ((env
->cpuid_version
>> 16) & 0xf) << 4;
2276 visit_type_int(v
, name
, &value
, errp
);
2279 static void x86_cpuid_version_set_model(Object
*obj
, Visitor
*v
,
2280 const char *name
, void *opaque
,
2283 X86CPU
*cpu
= X86_CPU(obj
);
2284 CPUX86State
*env
= &cpu
->env
;
2285 const int64_t min
= 0;
2286 const int64_t max
= 0xff;
2287 Error
*local_err
= NULL
;
2290 visit_type_int(v
, name
, &value
, &local_err
);
2292 error_propagate(errp
, local_err
);
2295 if (value
< min
|| value
> max
) {
2296 error_setg(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
2297 name ? name
: "null", value
, min
, max
);
2301 env
->cpuid_version
&= ~0xf00f0;
2302 env
->cpuid_version
|= ((value
& 0xf) << 4) | ((value
>> 4) << 16);
2305 static void x86_cpuid_version_get_stepping(Object
*obj
, Visitor
*v
,
2306 const char *name
, void *opaque
,
2309 X86CPU
*cpu
= X86_CPU(obj
);
2310 CPUX86State
*env
= &cpu
->env
;
2313 value
= env
->cpuid_version
& 0xf;
2314 visit_type_int(v
, name
, &value
, errp
);
2317 static void x86_cpuid_version_set_stepping(Object
*obj
, Visitor
*v
,
2318 const char *name
, void *opaque
,
2321 X86CPU
*cpu
= X86_CPU(obj
);
2322 CPUX86State
*env
= &cpu
->env
;
2323 const int64_t min
= 0;
2324 const int64_t max
= 0xf;
2325 Error
*local_err
= NULL
;
2328 visit_type_int(v
, name
, &value
, &local_err
);
2330 error_propagate(errp
, local_err
);
2333 if (value
< min
|| value
> max
) {
2334 error_setg(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
2335 name ? name
: "null", value
, min
, max
);
2339 env
->cpuid_version
&= ~0xf;
2340 env
->cpuid_version
|= value
& 0xf;
2343 static char *x86_cpuid_get_vendor(Object
*obj
, Error
**errp
)
2345 X86CPU
*cpu
= X86_CPU(obj
);
2346 CPUX86State
*env
= &cpu
->env
;
2349 value
= g_malloc(CPUID_VENDOR_SZ
+ 1);
2350 x86_cpu_vendor_words2str(value
, env
->cpuid_vendor1
, env
->cpuid_vendor2
,
2351 env
->cpuid_vendor3
);
2355 static void x86_cpuid_set_vendor(Object
*obj
, const char *value
,
2358 X86CPU
*cpu
= X86_CPU(obj
);
2359 CPUX86State
*env
= &cpu
->env
;
2362 if (strlen(value
) != CPUID_VENDOR_SZ
) {
2363 error_setg(errp
, QERR_PROPERTY_VALUE_BAD
, "", "vendor", value
);
2367 env
->cpuid_vendor1
= 0;
2368 env
->cpuid_vendor2
= 0;
2369 env
->cpuid_vendor3
= 0;
2370 for (i
= 0; i
< 4; i
++) {
2371 env
->cpuid_vendor1
|= ((uint8_t)value
[i
]) << (8 * i
);
2372 env
->cpuid_vendor2
|= ((uint8_t)value
[i
+ 4]) << (8 * i
);
2373 env
->cpuid_vendor3
|= ((uint8_t)value
[i
+ 8]) << (8 * i
);
2377 static char *x86_cpuid_get_model_id(Object
*obj
, Error
**errp
)
2379 X86CPU
*cpu
= X86_CPU(obj
);
2380 CPUX86State
*env
= &cpu
->env
;
2384 value
= g_malloc(48 + 1);
2385 for (i
= 0; i
< 48; i
++) {
2386 value
[i
] = env
->cpuid_model
[i
>> 2] >> (8 * (i
& 3));
2392 static void x86_cpuid_set_model_id(Object
*obj
, const char *model_id
,
2395 X86CPU
*cpu
= X86_CPU(obj
);
2396 CPUX86State
*env
= &cpu
->env
;
2399 if (model_id
== NULL
) {
2402 len
= strlen(model_id
);
2403 memset(env
->cpuid_model
, 0, 48);
2404 for (i
= 0; i
< 48; i
++) {
2408 c
= (uint8_t)model_id
[i
];
2410 env
->cpuid_model
[i
>> 2] |= c
<< (8 * (i
& 3));
2414 static void x86_cpuid_get_tsc_freq(Object
*obj
, Visitor
*v
, const char *name
,
2415 void *opaque
, Error
**errp
)
2417 X86CPU
*cpu
= X86_CPU(obj
);
2420 value
= cpu
->env
.tsc_khz
* 1000;
2421 visit_type_int(v
, name
, &value
, errp
);
2424 static void x86_cpuid_set_tsc_freq(Object
*obj
, Visitor
*v
, const char *name
,
2425 void *opaque
, Error
**errp
)
2427 X86CPU
*cpu
= X86_CPU(obj
);
2428 const int64_t min
= 0;
2429 const int64_t max
= INT64_MAX
;
2430 Error
*local_err
= NULL
;
2433 visit_type_int(v
, name
, &value
, &local_err
);
2435 error_propagate(errp
, local_err
);
2438 if (value
< min
|| value
> max
) {
2439 error_setg(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
2440 name ? name
: "null", value
, min
, max
);
2444 cpu
->env
.tsc_khz
= cpu
->env
.user_tsc_khz
= value
/ 1000;
2447 /* Generic getter for "feature-words" and "filtered-features" properties */
2448 static void x86_cpu_get_feature_words(Object
*obj
, Visitor
*v
,
2449 const char *name
, void *opaque
,
2452 uint32_t *array
= (uint32_t *)opaque
;
2454 X86CPUFeatureWordInfo word_infos
[FEATURE_WORDS
] = { };
2455 X86CPUFeatureWordInfoList list_entries
[FEATURE_WORDS
] = { };
2456 X86CPUFeatureWordInfoList
*list
= NULL
;
2458 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
2459 FeatureWordInfo
*wi
= &feature_word_info
[w
];
2460 X86CPUFeatureWordInfo
*qwi
= &word_infos
[w
];
2461 qwi
->cpuid_input_eax
= wi
->cpuid_eax
;
2462 qwi
->has_cpuid_input_ecx
= wi
->cpuid_needs_ecx
;
2463 qwi
->cpuid_input_ecx
= wi
->cpuid_ecx
;
2464 qwi
->cpuid_register
= x86_reg_info_32
[wi
->cpuid_reg
].qapi_enum
;
2465 qwi
->features
= array
[w
];
2467 /* List will be in reverse order, but order shouldn't matter */
2468 list_entries
[w
].next
= list
;
2469 list_entries
[w
].value
= &word_infos
[w
];
2470 list
= &list_entries
[w
];
2473 visit_type_X86CPUFeatureWordInfoList(v
, "feature-words", &list
, errp
);
2476 static void x86_get_hv_spinlocks(Object
*obj
, Visitor
*v
, const char *name
,
2477 void *opaque
, Error
**errp
)
2479 X86CPU
*cpu
= X86_CPU(obj
);
2480 int64_t value
= cpu
->hyperv_spinlock_attempts
;
2482 visit_type_int(v
, name
, &value
, errp
);
2485 static void x86_set_hv_spinlocks(Object
*obj
, Visitor
*v
, const char *name
,
2486 void *opaque
, Error
**errp
)
2488 const int64_t min
= 0xFFF;
2489 const int64_t max
= UINT_MAX
;
2490 X86CPU
*cpu
= X86_CPU(obj
);
2494 visit_type_int(v
, name
, &value
, &err
);
2496 error_propagate(errp
, err
);
2500 if (value
< min
|| value
> max
) {
2501 error_setg(errp
, "Property %s.%s doesn't take value %" PRId64
2502 " (minimum: %" PRId64
", maximum: %" PRId64
")",
2503 object_get_typename(obj
), name ? name
: "null",
2507 cpu
->hyperv_spinlock_attempts
= value
;
2510 static const PropertyInfo qdev_prop_spinlocks
= {
2512 .get
= x86_get_hv_spinlocks
,
2513 .set
= x86_set_hv_spinlocks
,
2516 /* Convert all '_' in a feature string option name to '-', to make feature
2517 * name conform to QOM property naming rule, which uses '-' instead of '_'.
2519 static inline void feat2prop(char *s
)
2521 while ((s
= strchr(s
, '_'))) {
2526 /* Return the feature property name for a feature flag bit */
2527 static const char *x86_cpu_feature_name(FeatureWord w
, int bitnr
)
2529 /* XSAVE components are automatically enabled by other features,
2530 * so return the original feature name instead
2532 if (w
== FEAT_XSAVE_COMP_LO
|| w
== FEAT_XSAVE_COMP_HI
) {
2533 int comp
= (w
== FEAT_XSAVE_COMP_HI
) ? bitnr
+ 32 : bitnr
;
2535 if (comp
< ARRAY_SIZE(x86_ext_save_areas
) &&
2536 x86_ext_save_areas
[comp
].bits
) {
2537 w
= x86_ext_save_areas
[comp
].feature
;
2538 bitnr
= ctz32(x86_ext_save_areas
[comp
].bits
);
2543 assert(w
< FEATURE_WORDS
);
2544 return feature_word_info
[w
].feat_names
[bitnr
];
2547 /* Compatibily hack to maintain legacy +-feat semantic,
2548 * where +-feat overwrites any feature set by
2549 * feat=on|feat even if the later is parsed after +-feat
2550 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
2552 static GList
*plus_features
, *minus_features
;
2554 static gint
compare_string(gconstpointer a
, gconstpointer b
)
2556 return g_strcmp0(a
, b
);
2559 /* Parse "+feature,-feature,feature=foo" CPU feature string
2561 static void x86_cpu_parse_featurestr(const char *typename
, char *features
,
2564 char *featurestr
; /* Single 'key=value" string being parsed */
2565 static bool cpu_globals_initialized
;
2566 bool ambiguous
= false;
2568 if (cpu_globals_initialized
) {
2571 cpu_globals_initialized
= true;
2577 for (featurestr
= strtok(features
, ",");
2579 featurestr
= strtok(NULL
, ",")) {
2581 const char *val
= NULL
;
2584 GlobalProperty
*prop
;
2586 /* Compatibility syntax: */
2587 if (featurestr
[0] == '+') {
2588 plus_features
= g_list_append(plus_features
,
2589 g_strdup(featurestr
+ 1));
2591 } else if (featurestr
[0] == '-') {
2592 minus_features
= g_list_append(minus_features
,
2593 g_strdup(featurestr
+ 1));
2597 eq
= strchr(featurestr
, '=');
2605 feat2prop(featurestr
);
2608 if (g_list_find_custom(plus_features
, name
, compare_string
)) {
2609 warn_report("Ambiguous CPU model string. "
2610 "Don't mix both \"+%s\" and \"%s=%s\"",
2614 if (g_list_find_custom(minus_features
, name
, compare_string
)) {
2615 warn_report("Ambiguous CPU model string. "
2616 "Don't mix both \"-%s\" and \"%s=%s\"",
2622 if (!strcmp(name
, "tsc-freq")) {
2626 ret
= qemu_strtosz_metric(val
, NULL
, &tsc_freq
);
2627 if (ret
< 0 || tsc_freq
> INT64_MAX
) {
2628 error_setg(errp
, "bad numerical value %s", val
);
2631 snprintf(num
, sizeof(num
), "%" PRId64
, tsc_freq
);
2633 name
= "tsc-frequency";
2636 prop
= g_new0(typeof(*prop
), 1);
2637 prop
->driver
= typename
;
2638 prop
->property
= g_strdup(name
);
2639 prop
->value
= g_strdup(val
);
2640 prop
->errp
= &error_fatal
;
2641 qdev_prop_register_global(prop
);
2645 warn_report("Compatibility of ambiguous CPU model "
2646 "strings won't be kept on future QEMU versions");
2650 static void x86_cpu_expand_features(X86CPU
*cpu
, Error
**errp
);
2651 static int x86_cpu_filter_features(X86CPU
*cpu
);
2653 /* Check for missing features that may prevent the CPU class from
2654 * running using the current machine and accelerator.
2656 static void x86_cpu_class_check_missing_features(X86CPUClass
*xcc
,
2657 strList
**missing_feats
)
2662 strList
**next
= missing_feats
;
2664 if (xcc
->kvm_required
&& !kvm_enabled()) {
2665 strList
*new = g_new0(strList
, 1);
2666 new->value
= g_strdup("kvm");;
2667 *missing_feats
= new;
2671 xc
= X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc
))));
2673 x86_cpu_expand_features(xc
, &err
);
2675 /* Errors at x86_cpu_expand_features should never happen,
2676 * but in case it does, just report the model as not
2677 * runnable at all using the "type" property.
2679 strList
*new = g_new0(strList
, 1);
2680 new->value
= g_strdup("type");
2685 x86_cpu_filter_features(xc
);
2687 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
2688 uint32_t filtered
= xc
->filtered_features
[w
];
2690 for (i
= 0; i
< 32; i
++) {
2691 if (filtered
& (1UL << i
)) {
2692 strList
*new = g_new0(strList
, 1);
2693 new->value
= g_strdup(x86_cpu_feature_name(w
, i
));
2700 object_unref(OBJECT(xc
));
2703 /* Print all cpuid feature names in featureset
2705 static void listflags(FILE *f
, fprintf_function print
, const char **featureset
)
2710 for (bit
= 0; bit
< 32; bit
++) {
2711 if (featureset
[bit
]) {
2712 print(f
, "%s%s", first ?
"" : " ", featureset
[bit
]);
2718 /* Sort alphabetically by type name, respecting X86CPUClass::ordering. */
2719 static gint
x86_cpu_list_compare(gconstpointer a
, gconstpointer b
)
2721 ObjectClass
*class_a
= (ObjectClass
*)a
;
2722 ObjectClass
*class_b
= (ObjectClass
*)b
;
2723 X86CPUClass
*cc_a
= X86_CPU_CLASS(class_a
);
2724 X86CPUClass
*cc_b
= X86_CPU_CLASS(class_b
);
2725 const char *name_a
, *name_b
;
2727 if (cc_a
->ordering
!= cc_b
->ordering
) {
2728 return cc_a
->ordering
- cc_b
->ordering
;
2730 name_a
= object_class_get_name(class_a
);
2731 name_b
= object_class_get_name(class_b
);
2732 return strcmp(name_a
, name_b
);
2736 static GSList
*get_sorted_cpu_model_list(void)
2738 GSList
*list
= object_class_get_list(TYPE_X86_CPU
, false);
2739 list
= g_slist_sort(list
, x86_cpu_list_compare
);
2743 static void x86_cpu_list_entry(gpointer data
, gpointer user_data
)
2745 ObjectClass
*oc
= data
;
2746 X86CPUClass
*cc
= X86_CPU_CLASS(oc
);
2747 CPUListState
*s
= user_data
;
2748 char *name
= x86_cpu_class_get_model_name(cc
);
2749 const char *desc
= cc
->model_description
;
2750 if (!desc
&& cc
->cpu_def
) {
2751 desc
= cc
->cpu_def
->model_id
;
2754 (*s
->cpu_fprintf
)(s
->file
, "x86 %16s %-48s\n",
2759 /* list available CPU models and flags */
2760 void x86_cpu_list(FILE *f
, fprintf_function cpu_fprintf
)
2765 .cpu_fprintf
= cpu_fprintf
,
2769 (*cpu_fprintf
)(f
, "Available CPUs:\n");
2770 list
= get_sorted_cpu_model_list();
2771 g_slist_foreach(list
, x86_cpu_list_entry
, &s
);
2774 (*cpu_fprintf
)(f
, "\nRecognized CPUID flags:\n");
2775 for (i
= 0; i
< ARRAY_SIZE(feature_word_info
); i
++) {
2776 FeatureWordInfo
*fw
= &feature_word_info
[i
];
2778 (*cpu_fprintf
)(f
, " ");
2779 listflags(f
, cpu_fprintf
, fw
->feat_names
);
2780 (*cpu_fprintf
)(f
, "\n");
2784 static void x86_cpu_definition_entry(gpointer data
, gpointer user_data
)
2786 ObjectClass
*oc
= data
;
2787 X86CPUClass
*cc
= X86_CPU_CLASS(oc
);
2788 CpuDefinitionInfoList
**cpu_list
= user_data
;
2789 CpuDefinitionInfoList
*entry
;
2790 CpuDefinitionInfo
*info
;
2792 info
= g_malloc0(sizeof(*info
));
2793 info
->name
= x86_cpu_class_get_model_name(cc
);
2794 x86_cpu_class_check_missing_features(cc
, &info
->unavailable_features
);
2795 info
->has_unavailable_features
= true;
2796 info
->q_typename
= g_strdup(object_class_get_name(oc
));
2797 info
->migration_safe
= cc
->migration_safe
;
2798 info
->has_migration_safe
= true;
2799 info
->q_static
= cc
->static_model
;
2801 entry
= g_malloc0(sizeof(*entry
));
2802 entry
->value
= info
;
2803 entry
->next
= *cpu_list
;
2807 CpuDefinitionInfoList
*arch_query_cpu_definitions(Error
**errp
)
2809 CpuDefinitionInfoList
*cpu_list
= NULL
;
2810 GSList
*list
= get_sorted_cpu_model_list();
2811 g_slist_foreach(list
, x86_cpu_definition_entry
, &cpu_list
);
2816 static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w
,
2817 bool migratable_only
)
2819 FeatureWordInfo
*wi
= &feature_word_info
[w
];
2822 if (kvm_enabled()) {
2823 r
= kvm_arch_get_supported_cpuid(kvm_state
, wi
->cpuid_eax
,
2826 } else if (tcg_enabled()) {
2827 r
= wi
->tcg_features
;
2831 if (migratable_only
) {
2832 r
&= x86_cpu_get_migratable_flags(w
);
2837 static void x86_cpu_report_filtered_features(X86CPU
*cpu
)
2841 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
2842 report_unavailable_features(w
, cpu
->filtered_features
[w
]);
2846 static void x86_cpu_apply_props(X86CPU
*cpu
, PropValue
*props
)
2849 for (pv
= props
; pv
->prop
; pv
++) {
2853 object_property_parse(OBJECT(cpu
), pv
->value
, pv
->prop
,
2858 /* Load data from X86CPUDefinition into a X86CPU object
2860 static void x86_cpu_load_def(X86CPU
*cpu
, X86CPUDefinition
*def
, Error
**errp
)
2862 CPUX86State
*env
= &cpu
->env
;
2864 char host_vendor
[CPUID_VENDOR_SZ
+ 1];
2867 /*NOTE: any property set by this function should be returned by
2868 * x86_cpu_static_props(), so static expansion of
2869 * query-cpu-model-expansion is always complete.
2872 /* CPU models only set _minimum_ values for level/xlevel: */
2873 object_property_set_uint(OBJECT(cpu
), def
->level
, "min-level", errp
);
2874 object_property_set_uint(OBJECT(cpu
), def
->xlevel
, "min-xlevel", errp
);
2876 object_property_set_int(OBJECT(cpu
), def
->family
, "family", errp
);
2877 object_property_set_int(OBJECT(cpu
), def
->model
, "model", errp
);
2878 object_property_set_int(OBJECT(cpu
), def
->stepping
, "stepping", errp
);
2879 object_property_set_str(OBJECT(cpu
), def
->model_id
, "model-id", errp
);
2880 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
2881 env
->features
[w
] = def
->features
[w
];
2884 /* Special cases not set in the X86CPUDefinition structs: */
2885 if (kvm_enabled()) {
2886 if (!kvm_irqchip_in_kernel()) {
2887 x86_cpu_change_kvm_default("x2apic", "off");
2890 x86_cpu_apply_props(cpu
, kvm_default_props
);
2891 } else if (tcg_enabled()) {
2892 x86_cpu_apply_props(cpu
, tcg_default_props
);
2895 env
->features
[FEAT_1_ECX
] |= CPUID_EXT_HYPERVISOR
;
2897 /* sysenter isn't supported in compatibility mode on AMD,
2898 * syscall isn't supported in compatibility mode on Intel.
2899 * Normally we advertise the actual CPU vendor, but you can
2900 * override this using the 'vendor' property if you want to use
2901 * KVM's sysenter/syscall emulation in compatibility mode and
2902 * when doing cross vendor migration
2904 vendor
= def
->vendor
;
2905 if (kvm_enabled()) {
2906 uint32_t ebx
= 0, ecx
= 0, edx
= 0;
2907 host_cpuid(0, 0, NULL
, &ebx
, &ecx
, &edx
);
2908 x86_cpu_vendor_words2str(host_vendor
, ebx
, edx
, ecx
);
2909 vendor
= host_vendor
;
2912 object_property_set_str(OBJECT(cpu
), vendor
, "vendor", errp
);
2916 /* Return a QDict containing keys for all properties that can be included
2917 * in static expansion of CPU models. All properties set by x86_cpu_load_def()
2918 * must be included in the dictionary.
2920 static QDict
*x86_cpu_static_props(void)
2924 static const char *props
[] = {
2942 for (i
= 0; props
[i
]; i
++) {
2943 qdict_put_null(d
, props
[i
]);
2946 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
2947 FeatureWordInfo
*fi
= &feature_word_info
[w
];
2949 for (bit
= 0; bit
< 32; bit
++) {
2950 if (!fi
->feat_names
[bit
]) {
2953 qdict_put_null(d
, fi
->feat_names
[bit
]);
2960 /* Add an entry to @props dict, with the value for property. */
2961 static void x86_cpu_expand_prop(X86CPU
*cpu
, QDict
*props
, const char *prop
)
2963 QObject
*value
= object_property_get_qobject(OBJECT(cpu
), prop
,
2966 qdict_put_obj(props
, prop
, value
);
2969 /* Convert CPU model data from X86CPU object to a property dictionary
2970 * that can recreate exactly the same CPU model.
2972 static void x86_cpu_to_dict(X86CPU
*cpu
, QDict
*props
)
2974 QDict
*sprops
= x86_cpu_static_props();
2975 const QDictEntry
*e
;
2977 for (e
= qdict_first(sprops
); e
; e
= qdict_next(sprops
, e
)) {
2978 const char *prop
= qdict_entry_key(e
);
2979 x86_cpu_expand_prop(cpu
, props
, prop
);
2983 /* Convert CPU model data from X86CPU object to a property dictionary
2984 * that can recreate exactly the same CPU model, including every
2985 * writeable QOM property.
2987 static void x86_cpu_to_dict_full(X86CPU
*cpu
, QDict
*props
)
2989 ObjectPropertyIterator iter
;
2990 ObjectProperty
*prop
;
2992 object_property_iter_init(&iter
, OBJECT(cpu
));
2993 while ((prop
= object_property_iter_next(&iter
))) {
2994 /* skip read-only or write-only properties */
2995 if (!prop
->get
|| !prop
->set
) {
2999 /* "hotplugged" is the only property that is configurable
3000 * on the command-line but will be set differently on CPUs
3001 * created using "-cpu ... -smp ..." and by CPUs created
3002 * on the fly by x86_cpu_from_model() for querying. Skip it.
3004 if (!strcmp(prop
->name
, "hotplugged")) {
3007 x86_cpu_expand_prop(cpu
, props
, prop
->name
);
3011 static void object_apply_props(Object
*obj
, QDict
*props
, Error
**errp
)
3013 const QDictEntry
*prop
;
3016 for (prop
= qdict_first(props
); prop
; prop
= qdict_next(props
, prop
)) {
3017 object_property_set_qobject(obj
, qdict_entry_value(prop
),
3018 qdict_entry_key(prop
), &err
);
3024 error_propagate(errp
, err
);
3027 /* Create X86CPU object according to model+props specification */
3028 static X86CPU
*x86_cpu_from_model(const char *model
, QDict
*props
, Error
**errp
)
3034 xcc
= X86_CPU_CLASS(cpu_class_by_name(TYPE_X86_CPU
, model
));
3036 error_setg(&err
, "CPU model '%s' not found", model
);
3040 xc
= X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc
))));
3042 object_apply_props(OBJECT(xc
), props
, &err
);
3048 x86_cpu_expand_features(xc
, &err
);
3055 error_propagate(errp
, err
);
3056 object_unref(OBJECT(xc
));
3062 CpuModelExpansionInfo
*
3063 arch_query_cpu_model_expansion(CpuModelExpansionType type
,
3064 CpuModelInfo
*model
,
3069 CpuModelExpansionInfo
*ret
= g_new0(CpuModelExpansionInfo
, 1);
3070 QDict
*props
= NULL
;
3071 const char *base_name
;
3073 xc
= x86_cpu_from_model(model
->name
,
3075 qobject_to_qdict(model
->props
) :
3081 props
= qdict_new();
3084 case CPU_MODEL_EXPANSION_TYPE_STATIC
:
3085 /* Static expansion will be based on "base" only */
3087 x86_cpu_to_dict(xc
, props
);
3089 case CPU_MODEL_EXPANSION_TYPE_FULL
:
3090 /* As we don't return every single property, full expansion needs
3091 * to keep the original model name+props, and add extra
3092 * properties on top of that.
3094 base_name
= model
->name
;
3095 x86_cpu_to_dict_full(xc
, props
);
3098 error_setg(&err
, "Unsupportted expansion type");
3103 props
= qdict_new();
3105 x86_cpu_to_dict(xc
, props
);
3107 ret
->model
= g_new0(CpuModelInfo
, 1);
3108 ret
->model
->name
= g_strdup(base_name
);
3109 ret
->model
->props
= QOBJECT(props
);
3110 ret
->model
->has_props
= true;
3113 object_unref(OBJECT(xc
));
3115 error_propagate(errp
, err
);
3116 qapi_free_CpuModelExpansionInfo(ret
);
3122 static gchar
*x86_gdb_arch_name(CPUState
*cs
)
3124 #ifdef TARGET_X86_64
3125 return g_strdup("i386:x86-64");
3127 return g_strdup("i386");
3131 static void x86_cpu_cpudef_class_init(ObjectClass
*oc
, void *data
)
3133 X86CPUDefinition
*cpudef
= data
;
3134 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
3136 xcc
->cpu_def
= cpudef
;
3137 xcc
->migration_safe
= true;
3140 static void x86_register_cpudef_type(X86CPUDefinition
*def
)
3142 char *typename
= x86_cpu_type_name(def
->name
);
3145 .parent
= TYPE_X86_CPU
,
3146 .class_init
= x86_cpu_cpudef_class_init
,
3150 /* AMD aliases are handled at runtime based on CPUID vendor, so
3151 * they shouldn't be set on the CPU model table.
3153 assert(!(def
->features
[FEAT_8000_0001_EDX
] & CPUID_EXT2_AMD_ALIASES
));
3154 /* catch mistakes instead of silently truncating model_id when too long */
3155 assert(def
->model_id
&& strlen(def
->model_id
) <= 48);
3162 #if !defined(CONFIG_USER_ONLY)
3164 void cpu_clear_apic_feature(CPUX86State
*env
)
3166 env
->features
[FEAT_1_EDX
] &= ~CPUID_APIC
;
3169 #endif /* !CONFIG_USER_ONLY */
3171 void cpu_x86_cpuid(CPUX86State
*env
, uint32_t index
, uint32_t count
,
3172 uint32_t *eax
, uint32_t *ebx
,
3173 uint32_t *ecx
, uint32_t *edx
)
3175 X86CPU
*cpu
= x86_env_get_cpu(env
);
3176 CPUState
*cs
= CPU(cpu
);
3177 uint32_t pkg_offset
;
3179 uint32_t signature
[3];
3181 /* Calculate & apply limits for different index ranges */
3182 if (index
>= 0xC0000000) {
3183 limit
= env
->cpuid_xlevel2
;
3184 } else if (index
>= 0x80000000) {
3185 limit
= env
->cpuid_xlevel
;
3186 } else if (index
>= 0x40000000) {
3189 limit
= env
->cpuid_level
;
3192 if (index
> limit
) {
3193 /* Intel documentation states that invalid EAX input will
3194 * return the same information as EAX=cpuid_level
3195 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
3197 index
= env
->cpuid_level
;
3202 *eax
= env
->cpuid_level
;
3203 *ebx
= env
->cpuid_vendor1
;
3204 *edx
= env
->cpuid_vendor2
;
3205 *ecx
= env
->cpuid_vendor3
;
3208 *eax
= env
->cpuid_version
;
3209 *ebx
= (cpu
->apic_id
<< 24) |
3210 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
3211 *ecx
= env
->features
[FEAT_1_ECX
];
3212 if ((*ecx
& CPUID_EXT_XSAVE
) && (env
->cr
[4] & CR4_OSXSAVE_MASK
)) {
3213 *ecx
|= CPUID_EXT_OSXSAVE
;
3215 *edx
= env
->features
[FEAT_1_EDX
];
3216 if (cs
->nr_cores
* cs
->nr_threads
> 1) {
3217 *ebx
|= (cs
->nr_cores
* cs
->nr_threads
) << 16;
3222 /* cache info: needed for Pentium Pro compatibility */
3223 if (cpu
->cache_info_passthrough
) {
3224 host_cpuid(index
, 0, eax
, ebx
, ecx
, edx
);
3227 *eax
= 1; /* Number of CPUID[EAX=2] calls required */
3229 if (!cpu
->enable_l3_cache
) {
3232 *ecx
= L3_N_DESCRIPTOR
;
3234 *edx
= (L1D_DESCRIPTOR
<< 16) | \
3235 (L1I_DESCRIPTOR
<< 8) | \
3239 /* cache info: needed for Core compatibility */
3240 if (cpu
->cache_info_passthrough
) {
3241 host_cpuid(index
, count
, eax
, ebx
, ecx
, edx
);
3242 *eax
&= ~0xFC000000;
3246 case 0: /* L1 dcache info */
3247 *eax
|= CPUID_4_TYPE_DCACHE
| \
3248 CPUID_4_LEVEL(1) | \
3249 CPUID_4_SELF_INIT_LEVEL
;
3250 *ebx
= (L1D_LINE_SIZE
- 1) | \
3251 ((L1D_PARTITIONS
- 1) << 12) | \
3252 ((L1D_ASSOCIATIVITY
- 1) << 22);
3253 *ecx
= L1D_SETS
- 1;
3254 *edx
= CPUID_4_NO_INVD_SHARING
;
3256 case 1: /* L1 icache info */
3257 *eax
|= CPUID_4_TYPE_ICACHE
| \
3258 CPUID_4_LEVEL(1) | \
3259 CPUID_4_SELF_INIT_LEVEL
;
3260 *ebx
= (L1I_LINE_SIZE
- 1) | \
3261 ((L1I_PARTITIONS
- 1) << 12) | \
3262 ((L1I_ASSOCIATIVITY
- 1) << 22);
3263 *ecx
= L1I_SETS
- 1;
3264 *edx
= CPUID_4_NO_INVD_SHARING
;
3266 case 2: /* L2 cache info */
3267 *eax
|= CPUID_4_TYPE_UNIFIED
| \
3268 CPUID_4_LEVEL(2) | \
3269 CPUID_4_SELF_INIT_LEVEL
;
3270 if (cs
->nr_threads
> 1) {
3271 *eax
|= (cs
->nr_threads
- 1) << 14;
3273 *ebx
= (L2_LINE_SIZE
- 1) | \
3274 ((L2_PARTITIONS
- 1) << 12) | \
3275 ((L2_ASSOCIATIVITY
- 1) << 22);
3277 *edx
= CPUID_4_NO_INVD_SHARING
;
3279 case 3: /* L3 cache info */
3280 if (!cpu
->enable_l3_cache
) {
3287 *eax
|= CPUID_4_TYPE_UNIFIED
| \
3288 CPUID_4_LEVEL(3) | \
3289 CPUID_4_SELF_INIT_LEVEL
;
3290 pkg_offset
= apicid_pkg_offset(cs
->nr_cores
, cs
->nr_threads
);
3291 *eax
|= ((1 << pkg_offset
) - 1) << 14;
3292 *ebx
= (L3_N_LINE_SIZE
- 1) | \
3293 ((L3_N_PARTITIONS
- 1) << 12) | \
3294 ((L3_N_ASSOCIATIVITY
- 1) << 22);
3295 *ecx
= L3_N_SETS
- 1;
3296 *edx
= CPUID_4_INCLUSIVE
| CPUID_4_COMPLEX_IDX
;
3298 default: /* end of info */
3307 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
3308 if ((*eax
& 31) && cs
->nr_cores
> 1) {
3309 *eax
|= (cs
->nr_cores
- 1) << 26;
3313 /* mwait info: needed for Core compatibility */
3314 *eax
= 0; /* Smallest monitor-line size in bytes */
3315 *ebx
= 0; /* Largest monitor-line size in bytes */
3316 *ecx
= CPUID_MWAIT_EMX
| CPUID_MWAIT_IBE
;
3320 /* Thermal and Power Leaf */
3321 *eax
= env
->features
[FEAT_6_EAX
];
3327 /* Structured Extended Feature Flags Enumeration Leaf */
3329 *eax
= 0; /* Maximum ECX value for sub-leaves */
3330 *ebx
= env
->features
[FEAT_7_0_EBX
]; /* Feature flags */
3331 *ecx
= env
->features
[FEAT_7_0_ECX
]; /* Feature flags */
3332 if ((*ecx
& CPUID_7_0_ECX_PKU
) && env
->cr
[4] & CR4_PKE_MASK
) {
3333 *ecx
|= CPUID_7_0_ECX_OSPKE
;
3335 *edx
= env
->features
[FEAT_7_0_EDX
]; /* Feature flags */
3344 /* Direct Cache Access Information Leaf */
3345 *eax
= 0; /* Bits 0-31 in DCA_CAP MSR */
3351 /* Architectural Performance Monitoring Leaf */
3352 if (kvm_enabled() && cpu
->enable_pmu
) {
3353 KVMState
*s
= cs
->kvm_state
;
3355 *eax
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_EAX
);
3356 *ebx
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_EBX
);
3357 *ecx
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_ECX
);
3358 *edx
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_EDX
);
3367 /* Extended Topology Enumeration Leaf */
3368 if (!cpu
->enable_cpuid_0xb
) {
3369 *eax
= *ebx
= *ecx
= *edx
= 0;
3373 *ecx
= count
& 0xff;
3374 *edx
= cpu
->apic_id
;
3378 *eax
= apicid_core_offset(cs
->nr_cores
, cs
->nr_threads
);
3379 *ebx
= cs
->nr_threads
;
3380 *ecx
|= CPUID_TOPOLOGY_LEVEL_SMT
;
3383 *eax
= apicid_pkg_offset(cs
->nr_cores
, cs
->nr_threads
);
3384 *ebx
= cs
->nr_cores
* cs
->nr_threads
;
3385 *ecx
|= CPUID_TOPOLOGY_LEVEL_CORE
;
3390 *ecx
|= CPUID_TOPOLOGY_LEVEL_INVALID
;
3393 assert(!(*eax
& ~0x1f));
3394 *ebx
&= 0xffff; /* The count doesn't need to be reliable. */
3397 /* Processor Extended State */
3402 if (!(env
->features
[FEAT_1_ECX
] & CPUID_EXT_XSAVE
)) {
3407 *ecx
= xsave_area_size(x86_cpu_xsave_components(cpu
));
3408 *eax
= env
->features
[FEAT_XSAVE_COMP_LO
];
3409 *edx
= env
->features
[FEAT_XSAVE_COMP_HI
];
3411 } else if (count
== 1) {
3412 *eax
= env
->features
[FEAT_XSAVE
];
3413 } else if (count
< ARRAY_SIZE(x86_ext_save_areas
)) {
3414 if ((x86_cpu_xsave_components(cpu
) >> count
) & 1) {
3415 const ExtSaveArea
*esa
= &x86_ext_save_areas
[count
];
3424 * CPUID code in kvm_arch_init_vcpu() ignores stuff
3425 * set here, but we restrict to TCG none the less.
3427 if (tcg_enabled() && cpu
->expose_tcg
) {
3428 memcpy(signature
, "TCGTCGTCGTCG", 12);
3430 *ebx
= signature
[0];
3431 *ecx
= signature
[1];
3432 *edx
= signature
[2];
3447 *eax
= env
->cpuid_xlevel
;
3448 *ebx
= env
->cpuid_vendor1
;
3449 *edx
= env
->cpuid_vendor2
;
3450 *ecx
= env
->cpuid_vendor3
;
3453 *eax
= env
->cpuid_version
;
3455 *ecx
= env
->features
[FEAT_8000_0001_ECX
];
3456 *edx
= env
->features
[FEAT_8000_0001_EDX
];
3458 /* The Linux kernel checks for the CMPLegacy bit and
3459 * discards multiple thread information if it is set.
3460 * So don't set it here for Intel to make Linux guests happy.
3462 if (cs
->nr_cores
* cs
->nr_threads
> 1) {
3463 if (env
->cpuid_vendor1
!= CPUID_VENDOR_INTEL_1
||
3464 env
->cpuid_vendor2
!= CPUID_VENDOR_INTEL_2
||
3465 env
->cpuid_vendor3
!= CPUID_VENDOR_INTEL_3
) {
3466 *ecx
|= 1 << 1; /* CmpLegacy bit */
3473 *eax
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 0];
3474 *ebx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 1];
3475 *ecx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 2];
3476 *edx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 3];
3479 /* cache info (L1 cache) */
3480 if (cpu
->cache_info_passthrough
) {
3481 host_cpuid(index
, 0, eax
, ebx
, ecx
, edx
);
3484 *eax
= (L1_DTLB_2M_ASSOC
<< 24) | (L1_DTLB_2M_ENTRIES
<< 16) | \
3485 (L1_ITLB_2M_ASSOC
<< 8) | (L1_ITLB_2M_ENTRIES
);
3486 *ebx
= (L1_DTLB_4K_ASSOC
<< 24) | (L1_DTLB_4K_ENTRIES
<< 16) | \
3487 (L1_ITLB_4K_ASSOC
<< 8) | (L1_ITLB_4K_ENTRIES
);
3488 *ecx
= (L1D_SIZE_KB_AMD
<< 24) | (L1D_ASSOCIATIVITY_AMD
<< 16) | \
3489 (L1D_LINES_PER_TAG
<< 8) | (L1D_LINE_SIZE
);
3490 *edx
= (L1I_SIZE_KB_AMD
<< 24) | (L1I_ASSOCIATIVITY_AMD
<< 16) | \
3491 (L1I_LINES_PER_TAG
<< 8) | (L1I_LINE_SIZE
);
3494 /* cache info (L2 cache) */
3495 if (cpu
->cache_info_passthrough
) {
3496 host_cpuid(index
, 0, eax
, ebx
, ecx
, edx
);
3499 *eax
= (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC
) << 28) | \
3500 (L2_DTLB_2M_ENTRIES
<< 16) | \
3501 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC
) << 12) | \
3502 (L2_ITLB_2M_ENTRIES
);
3503 *ebx
= (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC
) << 28) | \
3504 (L2_DTLB_4K_ENTRIES
<< 16) | \
3505 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC
) << 12) | \
3506 (L2_ITLB_4K_ENTRIES
);
3507 *ecx
= (L2_SIZE_KB_AMD
<< 16) | \
3508 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY
) << 12) | \
3509 (L2_LINES_PER_TAG
<< 8) | (L2_LINE_SIZE
);
3510 if (!cpu
->enable_l3_cache
) {
3511 *edx
= ((L3_SIZE_KB
/ 512) << 18) | \
3512 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY
) << 12) | \
3513 (L3_LINES_PER_TAG
<< 8) | (L3_LINE_SIZE
);
3515 *edx
= ((L3_N_SIZE_KB_AMD
/ 512) << 18) | \
3516 (AMD_ENC_ASSOC(L3_N_ASSOCIATIVITY
) << 12) | \
3517 (L3_N_LINES_PER_TAG
<< 8) | (L3_N_LINE_SIZE
);
3524 *edx
= env
->features
[FEAT_8000_0007_EDX
];
3527 /* virtual & phys address size in low 2 bytes. */
3528 if (env
->features
[FEAT_8000_0001_EDX
] & CPUID_EXT2_LM
) {
3529 /* 64 bit processor */
3530 *eax
= cpu
->phys_bits
; /* configurable physical bits */
3531 if (env
->features
[FEAT_7_0_ECX
] & CPUID_7_0_ECX_LA57
) {
3532 *eax
|= 0x00003900; /* 57 bits virtual */
3534 *eax
|= 0x00003000; /* 48 bits virtual */
3537 *eax
= cpu
->phys_bits
;
3539 *ebx
= env
->features
[FEAT_8000_0008_EBX
];
3542 if (cs
->nr_cores
* cs
->nr_threads
> 1) {
3543 *ecx
|= (cs
->nr_cores
* cs
->nr_threads
) - 1;
3547 if (env
->features
[FEAT_8000_0001_ECX
] & CPUID_EXT3_SVM
) {
3548 *eax
= 0x00000001; /* SVM Revision */
3549 *ebx
= 0x00000010; /* nr of ASIDs */
3551 *edx
= env
->features
[FEAT_SVM
]; /* optional features */
3560 *eax
= env
->cpuid_xlevel2
;
3566 /* Support for VIA CPU's CPUID instruction */
3567 *eax
= env
->cpuid_version
;
3570 *edx
= env
->features
[FEAT_C000_0001_EDX
];
3575 /* Reserved for the future, and now filled with zero */
3582 /* reserved values: zero */
3591 /* CPUClass::reset() */
3592 static void x86_cpu_reset(CPUState
*s
)
3594 X86CPU
*cpu
= X86_CPU(s
);
3595 X86CPUClass
*xcc
= X86_CPU_GET_CLASS(cpu
);
3596 CPUX86State
*env
= &cpu
->env
;
3601 xcc
->parent_reset(s
);
3603 memset(env
, 0, offsetof(CPUX86State
, end_reset_fields
));
3605 env
->old_exception
= -1;
3607 /* init to reset state */
3609 env
->hflags2
|= HF2_GIF_MASK
;
3611 cpu_x86_update_cr0(env
, 0x60000010);
3612 env
->a20_mask
= ~0x0;
3613 env
->smbase
= 0x30000;
3615 env
->idt
.limit
= 0xffff;
3616 env
->gdt
.limit
= 0xffff;
3617 env
->ldt
.limit
= 0xffff;
3618 env
->ldt
.flags
= DESC_P_MASK
| (2 << DESC_TYPE_SHIFT
);
3619 env
->tr
.limit
= 0xffff;
3620 env
->tr
.flags
= DESC_P_MASK
| (11 << DESC_TYPE_SHIFT
);
3622 cpu_x86_load_seg_cache(env
, R_CS
, 0xf000, 0xffff0000, 0xffff,
3623 DESC_P_MASK
| DESC_S_MASK
| DESC_CS_MASK
|
3624 DESC_R_MASK
| DESC_A_MASK
);
3625 cpu_x86_load_seg_cache(env
, R_DS
, 0, 0, 0xffff,
3626 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
3628 cpu_x86_load_seg_cache(env
, R_ES
, 0, 0, 0xffff,
3629 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
3631 cpu_x86_load_seg_cache(env
, R_SS
, 0, 0, 0xffff,
3632 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
3634 cpu_x86_load_seg_cache(env
, R_FS
, 0, 0, 0xffff,
3635 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
3637 cpu_x86_load_seg_cache(env
, R_GS
, 0, 0, 0xffff,
3638 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
3642 env
->regs
[R_EDX
] = env
->cpuid_version
;
3647 for (i
= 0; i
< 8; i
++) {
3650 cpu_set_fpuc(env
, 0x37f);
3652 env
->mxcsr
= 0x1f80;
3653 /* All units are in INIT state. */
3656 env
->pat
= 0x0007040600070406ULL
;
3657 env
->msr_ia32_misc_enable
= MSR_IA32_MISC_ENABLE_DEFAULT
;
3659 memset(env
->dr
, 0, sizeof(env
->dr
));
3660 env
->dr
[6] = DR6_FIXED_1
;
3661 env
->dr
[7] = DR7_FIXED_1
;
3662 cpu_breakpoint_remove_all(s
, BP_CPU
);
3663 cpu_watchpoint_remove_all(s
, BP_CPU
);
3666 xcr0
= XSTATE_FP_MASK
;
3668 #ifdef CONFIG_USER_ONLY
3669 /* Enable all the features for user-mode. */
3670 if (env
->features
[FEAT_1_EDX
] & CPUID_SSE
) {
3671 xcr0
|= XSTATE_SSE_MASK
;
3673 for (i
= 2; i
< ARRAY_SIZE(x86_ext_save_areas
); i
++) {
3674 const ExtSaveArea
*esa
= &x86_ext_save_areas
[i
];
3675 if (env
->features
[esa
->feature
] & esa
->bits
) {
3680 if (env
->features
[FEAT_1_ECX
] & CPUID_EXT_XSAVE
) {
3681 cr4
|= CR4_OSFXSR_MASK
| CR4_OSXSAVE_MASK
;
3683 if (env
->features
[FEAT_7_0_EBX
] & CPUID_7_0_EBX_FSGSBASE
) {
3684 cr4
|= CR4_FSGSBASE_MASK
;
3689 cpu_x86_update_cr4(env
, cr4
);
3692 * SDM 11.11.5 requires:
3693 * - IA32_MTRR_DEF_TYPE MSR.E = 0
3694 * - IA32_MTRR_PHYSMASKn.V = 0
3695 * All other bits are undefined. For simplification, zero it all.
3697 env
->mtrr_deftype
= 0;
3698 memset(env
->mtrr_var
, 0, sizeof(env
->mtrr_var
));
3699 memset(env
->mtrr_fixed
, 0, sizeof(env
->mtrr_fixed
));
3701 #if !defined(CONFIG_USER_ONLY)
3702 /* We hard-wire the BSP to the first CPU. */
3703 apic_designate_bsp(cpu
->apic_state
, s
->cpu_index
== 0);
3705 s
->halted
= !cpu_is_bsp(cpu
);
3707 if (kvm_enabled()) {
3708 kvm_arch_reset_vcpu(cpu
);
3713 #ifndef CONFIG_USER_ONLY
3714 bool cpu_is_bsp(X86CPU
*cpu
)
3716 return cpu_get_apic_base(cpu
->apic_state
) & MSR_IA32_APICBASE_BSP
;
3719 /* TODO: remove me, when reset over QOM tree is implemented */
3720 static void x86_cpu_machine_reset_cb(void *opaque
)
3722 X86CPU
*cpu
= opaque
;
3723 cpu_reset(CPU(cpu
));
3727 static void mce_init(X86CPU
*cpu
)
3729 CPUX86State
*cenv
= &cpu
->env
;
3732 if (((cenv
->cpuid_version
>> 8) & 0xf) >= 6
3733 && (cenv
->features
[FEAT_1_EDX
] & (CPUID_MCE
| CPUID_MCA
)) ==
3734 (CPUID_MCE
| CPUID_MCA
)) {
3735 cenv
->mcg_cap
= MCE_CAP_DEF
| MCE_BANKS_DEF
|
3736 (cpu
->enable_lmce ? MCG_LMCE_P
: 0);
3737 cenv
->mcg_ctl
= ~(uint64_t)0;
3738 for (bank
= 0; bank
< MCE_BANKS_DEF
; bank
++) {
3739 cenv
->mce_banks
[bank
* 4] = ~(uint64_t)0;
3744 #ifndef CONFIG_USER_ONLY
3745 APICCommonClass
*apic_get_class(void)
3747 const char *apic_type
= "apic";
3749 if (kvm_apic_in_kernel()) {
3750 apic_type
= "kvm-apic";
3751 } else if (xen_enabled()) {
3752 apic_type
= "xen-apic";
3755 return APIC_COMMON_CLASS(object_class_by_name(apic_type
));
3758 static void x86_cpu_apic_create(X86CPU
*cpu
, Error
**errp
)
3760 APICCommonState
*apic
;
3761 ObjectClass
*apic_class
= OBJECT_CLASS(apic_get_class());
3763 cpu
->apic_state
= DEVICE(object_new(object_class_get_name(apic_class
)));
3765 object_property_add_child(OBJECT(cpu
), "lapic",
3766 OBJECT(cpu
->apic_state
), &error_abort
);
3767 object_unref(OBJECT(cpu
->apic_state
));
3769 qdev_prop_set_uint32(cpu
->apic_state
, "id", cpu
->apic_id
);
3770 /* TODO: convert to link<> */
3771 apic
= APIC_COMMON(cpu
->apic_state
);
3773 apic
->apicbase
= APIC_DEFAULT_ADDRESS
| MSR_IA32_APICBASE_ENABLE
;
3776 static void x86_cpu_apic_realize(X86CPU
*cpu
, Error
**errp
)
3778 APICCommonState
*apic
;
3779 static bool apic_mmio_map_once
;
3781 if (cpu
->apic_state
== NULL
) {
3784 object_property_set_bool(OBJECT(cpu
->apic_state
), true, "realized",
3787 /* Map APIC MMIO area */
3788 apic
= APIC_COMMON(cpu
->apic_state
);
3789 if (!apic_mmio_map_once
) {
3790 memory_region_add_subregion_overlap(get_system_memory(),
3792 MSR_IA32_APICBASE_BASE
,
3795 apic_mmio_map_once
= true;
3799 static void x86_cpu_machine_done(Notifier
*n
, void *unused
)
3801 X86CPU
*cpu
= container_of(n
, X86CPU
, machine_done
);
3802 MemoryRegion
*smram
=
3803 (MemoryRegion
*) object_resolve_path("/machine/smram", NULL
);
3806 cpu
->smram
= g_new(MemoryRegion
, 1);
3807 memory_region_init_alias(cpu
->smram
, OBJECT(cpu
), "smram",
3808 smram
, 0, 1ull << 32);
3809 memory_region_set_enabled(cpu
->smram
, true);
3810 memory_region_add_subregion_overlap(cpu
->cpu_as_root
, 0, cpu
->smram
, 1);
3814 static void x86_cpu_apic_realize(X86CPU
*cpu
, Error
**errp
)
3819 /* Note: Only safe for use on x86(-64) hosts */
3820 static uint32_t x86_host_phys_bits(void)
3823 uint32_t host_phys_bits
;
3825 host_cpuid(0x80000000, 0, &eax
, NULL
, NULL
, NULL
);
3826 if (eax
>= 0x80000008) {
3827 host_cpuid(0x80000008, 0, &eax
, NULL
, NULL
, NULL
);
3828 /* Note: According to AMD doc 25481 rev 2.34 they have a field
3829 * at 23:16 that can specify a maximum physical address bits for
3830 * the guest that can override this value; but I've not seen
3831 * anything with that set.
3833 host_phys_bits
= eax
& 0xff;
3835 /* It's an odd 64 bit machine that doesn't have the leaf for
3836 * physical address bits; fall back to 36 that's most older
3839 host_phys_bits
= 36;
3842 return host_phys_bits
;
3845 static void x86_cpu_adjust_level(X86CPU
*cpu
, uint32_t *min
, uint32_t value
)
3852 /* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */
3853 static void x86_cpu_adjust_feat_level(X86CPU
*cpu
, FeatureWord w
)
3855 CPUX86State
*env
= &cpu
->env
;
3856 FeatureWordInfo
*fi
= &feature_word_info
[w
];
3857 uint32_t eax
= fi
->cpuid_eax
;
3858 uint32_t region
= eax
& 0xF0000000;
3860 if (!env
->features
[w
]) {
3866 x86_cpu_adjust_level(cpu
, &env
->cpuid_min_level
, eax
);
3869 x86_cpu_adjust_level(cpu
, &env
->cpuid_min_xlevel
, eax
);
3872 x86_cpu_adjust_level(cpu
, &env
->cpuid_min_xlevel2
, eax
);
3877 /* Calculate XSAVE components based on the configured CPU feature flags */
3878 static void x86_cpu_enable_xsave_components(X86CPU
*cpu
)
3880 CPUX86State
*env
= &cpu
->env
;
3884 if (!(env
->features
[FEAT_1_ECX
] & CPUID_EXT_XSAVE
)) {
3889 for (i
= 0; i
< ARRAY_SIZE(x86_ext_save_areas
); i
++) {
3890 const ExtSaveArea
*esa
= &x86_ext_save_areas
[i
];
3891 if (env
->features
[esa
->feature
] & esa
->bits
) {
3892 mask
|= (1ULL << i
);
3896 env
->features
[FEAT_XSAVE_COMP_LO
] = mask
;
3897 env
->features
[FEAT_XSAVE_COMP_HI
] = mask
>> 32;
3900 /***** Steps involved on loading and filtering CPUID data
3902 * When initializing and realizing a CPU object, the steps
3903 * involved in setting up CPUID data are:
3905 * 1) Loading CPU model definition (X86CPUDefinition). This is
3906 * implemented by x86_cpu_load_def() and should be completely
3907 * transparent, as it is done automatically by instance_init.
3908 * No code should need to look at X86CPUDefinition structs
3909 * outside instance_init.
3911 * 2) CPU expansion. This is done by realize before CPUID
3912 * filtering, and will make sure host/accelerator data is
3913 * loaded for CPU models that depend on host capabilities
3914 * (e.g. "host"). Done by x86_cpu_expand_features().
3916 * 3) CPUID filtering. This initializes extra data related to
3917 * CPUID, and checks if the host supports all capabilities
3918 * required by the CPU. Runnability of a CPU model is
3919 * determined at this step. Done by x86_cpu_filter_features().
3921 * Some operations don't require all steps to be performed.
3924 * - CPU instance creation (instance_init) will run only CPU
3925 * model loading. CPU expansion can't run at instance_init-time
3926 * because host/accelerator data may be not available yet.
3927 * - CPU realization will perform both CPU model expansion and CPUID
3928 * filtering, and return an error in case one of them fails.
3929 * - query-cpu-definitions needs to run all 3 steps. It needs
3930 * to run CPUID filtering, as the 'unavailable-features'
3931 * field is set based on the filtering results.
3932 * - The query-cpu-model-expansion QMP command only needs to run
3933 * CPU model loading and CPU expansion. It should not filter
3934 * any CPUID data based on host capabilities.
3937 /* Expand CPU configuration data, based on configured features
3938 * and host/accelerator capabilities when appropriate.
3940 static void x86_cpu_expand_features(X86CPU
*cpu
, Error
**errp
)
3942 CPUX86State
*env
= &cpu
->env
;
3945 Error
*local_err
= NULL
;
3947 /*TODO: Now cpu->max_features doesn't overwrite features
3948 * set using QOM properties, and we can convert
3949 * plus_features & minus_features to global properties
3950 * inside x86_cpu_parse_featurestr() too.
3952 if (cpu
->max_features
) {
3953 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
3954 /* Override only features that weren't set explicitly
3958 x86_cpu_get_supported_feature_word(w
, cpu
->migratable
) &
3959 ~env
->user_features
[w
];
3963 for (l
= plus_features
; l
; l
= l
->next
) {
3964 const char *prop
= l
->data
;
3965 object_property_set_bool(OBJECT(cpu
), true, prop
, &local_err
);
3971 for (l
= minus_features
; l
; l
= l
->next
) {
3972 const char *prop
= l
->data
;
3973 object_property_set_bool(OBJECT(cpu
), false, prop
, &local_err
);
3979 if (!kvm_enabled() || !cpu
->expose_kvm
) {
3980 env
->features
[FEAT_KVM
] = 0;
3983 x86_cpu_enable_xsave_components(cpu
);
3985 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
3986 x86_cpu_adjust_feat_level(cpu
, FEAT_7_0_EBX
);
3987 if (cpu
->full_cpuid_auto_level
) {
3988 x86_cpu_adjust_feat_level(cpu
, FEAT_1_EDX
);
3989 x86_cpu_adjust_feat_level(cpu
, FEAT_1_ECX
);
3990 x86_cpu_adjust_feat_level(cpu
, FEAT_6_EAX
);
3991 x86_cpu_adjust_feat_level(cpu
, FEAT_7_0_ECX
);
3992 x86_cpu_adjust_feat_level(cpu
, FEAT_8000_0001_EDX
);
3993 x86_cpu_adjust_feat_level(cpu
, FEAT_8000_0001_ECX
);
3994 x86_cpu_adjust_feat_level(cpu
, FEAT_8000_0007_EDX
);
3995 x86_cpu_adjust_feat_level(cpu
, FEAT_8000_0008_EBX
);
3996 x86_cpu_adjust_feat_level(cpu
, FEAT_C000_0001_EDX
);
3997 x86_cpu_adjust_feat_level(cpu
, FEAT_SVM
);
3998 x86_cpu_adjust_feat_level(cpu
, FEAT_XSAVE
);
3999 /* SVM requires CPUID[0x8000000A] */
4000 if (env
->features
[FEAT_8000_0001_ECX
] & CPUID_EXT3_SVM
) {
4001 x86_cpu_adjust_level(cpu
, &env
->cpuid_min_xlevel
, 0x8000000A);