ahci: Reorder error cases in handle_cmd
[qemu.git] / target-alpha / cpu.c
1 /*
2 * QEMU Alpha CPU
3 *
4 * Copyright (c) 2007 Jocelyn Mayer
5 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see
19 * <http://www.gnu.org/licenses/lgpl-2.1.html>
20 */
21
22 #include "cpu.h"
23 #include "qemu-common.h"
24 #include "migration/vmstate.h"
25
26
27 static void alpha_cpu_set_pc(CPUState *cs, vaddr value)
28 {
29 AlphaCPU *cpu = ALPHA_CPU(cs);
30
31 cpu->env.pc = value;
32 }
33
34 static bool alpha_cpu_has_work(CPUState *cs)
35 {
36 /* Here we are checking to see if the CPU should wake up from HALT.
37 We will have gotten into this state only for WTINT from PALmode. */
38 /* ??? I'm not sure how the IPL state works with WTINT to keep a CPU
39 asleep even if (some) interrupts have been asserted. For now,
40 assume that if a CPU really wants to stay asleep, it will mask
41 interrupts at the chipset level, which will prevent these bits
42 from being set in the first place. */
43 return cs->interrupt_request & (CPU_INTERRUPT_HARD
44 | CPU_INTERRUPT_TIMER
45 | CPU_INTERRUPT_SMP
46 | CPU_INTERRUPT_MCHK);
47 }
48
49 static void alpha_cpu_realizefn(DeviceState *dev, Error **errp)
50 {
51 CPUState *cs = CPU(dev);
52 AlphaCPUClass *acc = ALPHA_CPU_GET_CLASS(dev);
53
54 qemu_init_vcpu(cs);
55
56 acc->parent_realize(dev, errp);
57 }
58
59 /* Sort alphabetically by type name. */
60 static gint alpha_cpu_list_compare(gconstpointer a, gconstpointer b)
61 {
62 ObjectClass *class_a = (ObjectClass *)a;
63 ObjectClass *class_b = (ObjectClass *)b;
64 const char *name_a, *name_b;
65
66 name_a = object_class_get_name(class_a);
67 name_b = object_class_get_name(class_b);
68 return strcmp(name_a, name_b);
69 }
70
71 static void alpha_cpu_list_entry(gpointer data, gpointer user_data)
72 {
73 ObjectClass *oc = data;
74 CPUListState *s = user_data;
75
76 (*s->cpu_fprintf)(s->file, " %s\n",
77 object_class_get_name(oc));
78 }
79
80 void alpha_cpu_list(FILE *f, fprintf_function cpu_fprintf)
81 {
82 CPUListState s = {
83 .file = f,
84 .cpu_fprintf = cpu_fprintf,
85 };
86 GSList *list;
87
88 list = object_class_get_list(TYPE_ALPHA_CPU, false);
89 list = g_slist_sort(list, alpha_cpu_list_compare);
90 (*cpu_fprintf)(f, "Available CPUs:\n");
91 g_slist_foreach(list, alpha_cpu_list_entry, &s);
92 g_slist_free(list);
93 }
94
95 /* Models */
96
97 #define TYPE(model) model "-" TYPE_ALPHA_CPU
98
99 typedef struct AlphaCPUAlias {
100 const char *alias;
101 const char *typename;
102 } AlphaCPUAlias;
103
104 static const AlphaCPUAlias alpha_cpu_aliases[] = {
105 { "21064", TYPE("ev4") },
106 { "21164", TYPE("ev5") },
107 { "21164a", TYPE("ev56") },
108 { "21164pc", TYPE("pca56") },
109 { "21264", TYPE("ev6") },
110 { "21264a", TYPE("ev67") },
111 };
112
113 static ObjectClass *alpha_cpu_class_by_name(const char *cpu_model)
114 {
115 ObjectClass *oc = NULL;
116 char *typename;
117 int i;
118
119 if (cpu_model == NULL) {
120 return NULL;
121 }
122
123 oc = object_class_by_name(cpu_model);
124 if (oc != NULL && object_class_dynamic_cast(oc, TYPE_ALPHA_CPU) != NULL &&
125 !object_class_is_abstract(oc)) {
126 return oc;
127 }
128
129 for (i = 0; i < ARRAY_SIZE(alpha_cpu_aliases); i++) {
130 if (strcmp(cpu_model, alpha_cpu_aliases[i].alias) == 0) {
131 oc = object_class_by_name(alpha_cpu_aliases[i].typename);
132 assert(oc != NULL && !object_class_is_abstract(oc));
133 return oc;
134 }
135 }
136
137 typename = g_strdup_printf("%s-" TYPE_ALPHA_CPU, cpu_model);
138 oc = object_class_by_name(typename);
139 g_free(typename);
140 if (oc != NULL && object_class_is_abstract(oc)) {
141 oc = NULL;
142 }
143 return oc;
144 }
145
146 AlphaCPU *cpu_alpha_init(const char *cpu_model)
147 {
148 AlphaCPU *cpu;
149 ObjectClass *cpu_class;
150
151 cpu_class = alpha_cpu_class_by_name(cpu_model);
152 if (cpu_class == NULL) {
153 /* Default to ev67; no reason not to emulate insns by default. */
154 cpu_class = object_class_by_name(TYPE("ev67"));
155 }
156 cpu = ALPHA_CPU(object_new(object_class_get_name(cpu_class)));
157
158 object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
159
160 return cpu;
161 }
162
163 static void ev4_cpu_initfn(Object *obj)
164 {
165 AlphaCPU *cpu = ALPHA_CPU(obj);
166 CPUAlphaState *env = &cpu->env;
167
168 env->implver = IMPLVER_2106x;
169 }
170
171 static const TypeInfo ev4_cpu_type_info = {
172 .name = TYPE("ev4"),
173 .parent = TYPE_ALPHA_CPU,
174 .instance_init = ev4_cpu_initfn,
175 };
176
177 static void ev5_cpu_initfn(Object *obj)
178 {
179 AlphaCPU *cpu = ALPHA_CPU(obj);
180 CPUAlphaState *env = &cpu->env;
181
182 env->implver = IMPLVER_21164;
183 }
184
185 static const TypeInfo ev5_cpu_type_info = {
186 .name = TYPE("ev5"),
187 .parent = TYPE_ALPHA_CPU,
188 .instance_init = ev5_cpu_initfn,
189 };
190
191 static void ev56_cpu_initfn(Object *obj)
192 {
193 AlphaCPU *cpu = ALPHA_CPU(obj);
194 CPUAlphaState *env = &cpu->env;
195
196 env->amask |= AMASK_BWX;
197 }
198
199 static const TypeInfo ev56_cpu_type_info = {
200 .name = TYPE("ev56"),
201 .parent = TYPE("ev5"),
202 .instance_init = ev56_cpu_initfn,
203 };
204
205 static void pca56_cpu_initfn(Object *obj)
206 {
207 AlphaCPU *cpu = ALPHA_CPU(obj);
208 CPUAlphaState *env = &cpu->env;
209
210 env->amask |= AMASK_MVI;
211 }
212
213 static const TypeInfo pca56_cpu_type_info = {
214 .name = TYPE("pca56"),
215 .parent = TYPE("ev56"),
216 .instance_init = pca56_cpu_initfn,
217 };
218
219 static void ev6_cpu_initfn(Object *obj)
220 {
221 AlphaCPU *cpu = ALPHA_CPU(obj);
222 CPUAlphaState *env = &cpu->env;
223
224 env->implver = IMPLVER_21264;
225 env->amask = AMASK_BWX | AMASK_FIX | AMASK_MVI | AMASK_TRAP;
226 }
227
228 static const TypeInfo ev6_cpu_type_info = {
229 .name = TYPE("ev6"),
230 .parent = TYPE_ALPHA_CPU,
231 .instance_init = ev6_cpu_initfn,
232 };
233
234 static void ev67_cpu_initfn(Object *obj)
235 {
236 AlphaCPU *cpu = ALPHA_CPU(obj);
237 CPUAlphaState *env = &cpu->env;
238
239 env->amask |= AMASK_CIX | AMASK_PREFETCH;
240 }
241
242 static const TypeInfo ev67_cpu_type_info = {
243 .name = TYPE("ev67"),
244 .parent = TYPE("ev6"),
245 .instance_init = ev67_cpu_initfn,
246 };
247
248 static const TypeInfo ev68_cpu_type_info = {
249 .name = TYPE("ev68"),
250 .parent = TYPE("ev67"),
251 };
252
253 static void alpha_cpu_initfn(Object *obj)
254 {
255 CPUState *cs = CPU(obj);
256 AlphaCPU *cpu = ALPHA_CPU(obj);
257 CPUAlphaState *env = &cpu->env;
258
259 cs->env_ptr = env;
260 cpu_exec_init(env);
261 tlb_flush(cs, 1);
262
263 alpha_translate_init();
264
265 #if defined(CONFIG_USER_ONLY)
266 env->ps = PS_USER_MODE;
267 cpu_alpha_store_fpcr(env, (FPCR_INVD | FPCR_DZED | FPCR_OVFD
268 | FPCR_UNFD | FPCR_INED | FPCR_DNOD
269 | FPCR_DYN_NORMAL));
270 #endif
271 env->lock_addr = -1;
272 env->fen = 1;
273 }
274
275 static void alpha_cpu_class_init(ObjectClass *oc, void *data)
276 {
277 DeviceClass *dc = DEVICE_CLASS(oc);
278 CPUClass *cc = CPU_CLASS(oc);
279 AlphaCPUClass *acc = ALPHA_CPU_CLASS(oc);
280
281 acc->parent_realize = dc->realize;
282 dc->realize = alpha_cpu_realizefn;
283
284 cc->class_by_name = alpha_cpu_class_by_name;
285 cc->has_work = alpha_cpu_has_work;
286 cc->do_interrupt = alpha_cpu_do_interrupt;
287 cc->cpu_exec_interrupt = alpha_cpu_exec_interrupt;
288 cc->dump_state = alpha_cpu_dump_state;
289 cc->set_pc = alpha_cpu_set_pc;
290 cc->gdb_read_register = alpha_cpu_gdb_read_register;
291 cc->gdb_write_register = alpha_cpu_gdb_write_register;
292 #ifdef CONFIG_USER_ONLY
293 cc->handle_mmu_fault = alpha_cpu_handle_mmu_fault;
294 #else
295 cc->do_unassigned_access = alpha_cpu_unassigned_access;
296 cc->do_unaligned_access = alpha_cpu_do_unaligned_access;
297 cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug;
298 dc->vmsd = &vmstate_alpha_cpu;
299 #endif
300 cc->gdb_num_core_regs = 67;
301 }
302
303 static const TypeInfo alpha_cpu_type_info = {
304 .name = TYPE_ALPHA_CPU,
305 .parent = TYPE_CPU,
306 .instance_size = sizeof(AlphaCPU),
307 .instance_init = alpha_cpu_initfn,
308 .abstract = true,
309 .class_size = sizeof(AlphaCPUClass),
310 .class_init = alpha_cpu_class_init,
311 };
312
313 static void alpha_cpu_register_types(void)
314 {
315 type_register_static(&alpha_cpu_type_info);
316 type_register_static(&ev4_cpu_type_info);
317 type_register_static(&ev5_cpu_type_info);
318 type_register_static(&ev56_cpu_type_info);
319 type_register_static(&pca56_cpu_type_info);
320 type_register_static(&ev6_cpu_type_info);
321 type_register_static(&ev67_cpu_type_info);
322 type_register_static(&ev68_cpu_type_info);
323 }
324
325 type_init(alpha_cpu_register_types)