ahci: Reorder error cases in handle_cmd
[qemu.git] / target-alpha / cpu.h
1 /*
2 * Alpha emulation cpu definitions for qemu.
3 *
4 * Copyright (c) 2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #if !defined (__CPU_ALPHA_H__)
21 #define __CPU_ALPHA_H__
22
23 #include "config.h"
24 #include "qemu-common.h"
25
26 #define TARGET_LONG_BITS 64
27 #define ALIGNED_ONLY
28
29 #define CPUArchState struct CPUAlphaState
30
31 #include "exec/cpu-defs.h"
32
33 #include "fpu/softfloat.h"
34
35 #define TARGET_HAS_ICE 1
36
37 #define ELF_MACHINE EM_ALPHA
38
39 #define ICACHE_LINE_SIZE 32
40 #define DCACHE_LINE_SIZE 32
41
42 #define TARGET_PAGE_BITS 13
43
44 #ifdef CONFIG_USER_ONLY
45 /* ??? The kernel likes to give addresses in high memory. If the host has
46 more virtual address space than the guest, this can lead to impossible
47 allocations. Honor the long-standing assumption that only kernel addrs
48 are negative, but otherwise allow allocations anywhere. This could lead
49 to tricky emulation problems for programs doing tagged addressing, but
50 that's far fewer than encounter the impossible allocation problem. */
51 #define TARGET_PHYS_ADDR_SPACE_BITS 63
52 #define TARGET_VIRT_ADDR_SPACE_BITS 63
53 #else
54 /* ??? EV4 has 34 phys addr bits, EV5 has 40, EV6 has 44. */
55 #define TARGET_PHYS_ADDR_SPACE_BITS 44
56 #define TARGET_VIRT_ADDR_SPACE_BITS (30 + TARGET_PAGE_BITS)
57 #endif
58
59 /* Alpha major type */
60 enum {
61 ALPHA_EV3 = 1,
62 ALPHA_EV4 = 2,
63 ALPHA_SIM = 3,
64 ALPHA_LCA = 4,
65 ALPHA_EV5 = 5, /* 21164 */
66 ALPHA_EV45 = 6, /* 21064A */
67 ALPHA_EV56 = 7, /* 21164A */
68 };
69
70 /* EV4 minor type */
71 enum {
72 ALPHA_EV4_2 = 0,
73 ALPHA_EV4_3 = 1,
74 };
75
76 /* LCA minor type */
77 enum {
78 ALPHA_LCA_1 = 1, /* 21066 */
79 ALPHA_LCA_2 = 2, /* 20166 */
80 ALPHA_LCA_3 = 3, /* 21068 */
81 ALPHA_LCA_4 = 4, /* 21068 */
82 ALPHA_LCA_5 = 5, /* 21066A */
83 ALPHA_LCA_6 = 6, /* 21068A */
84 };
85
86 /* EV5 minor type */
87 enum {
88 ALPHA_EV5_1 = 1, /* Rev BA, CA */
89 ALPHA_EV5_2 = 2, /* Rev DA, EA */
90 ALPHA_EV5_3 = 3, /* Pass 3 */
91 ALPHA_EV5_4 = 4, /* Pass 3.2 */
92 ALPHA_EV5_5 = 5, /* Pass 4 */
93 };
94
95 /* EV45 minor type */
96 enum {
97 ALPHA_EV45_1 = 1, /* Pass 1 */
98 ALPHA_EV45_2 = 2, /* Pass 1.1 */
99 ALPHA_EV45_3 = 3, /* Pass 2 */
100 };
101
102 /* EV56 minor type */
103 enum {
104 ALPHA_EV56_1 = 1, /* Pass 1 */
105 ALPHA_EV56_2 = 2, /* Pass 2 */
106 };
107
108 enum {
109 IMPLVER_2106x = 0, /* EV4, EV45 & LCA45 */
110 IMPLVER_21164 = 1, /* EV5, EV56 & PCA45 */
111 IMPLVER_21264 = 2, /* EV6, EV67 & EV68x */
112 IMPLVER_21364 = 3, /* EV7 & EV79 */
113 };
114
115 enum {
116 AMASK_BWX = 0x00000001,
117 AMASK_FIX = 0x00000002,
118 AMASK_CIX = 0x00000004,
119 AMASK_MVI = 0x00000100,
120 AMASK_TRAP = 0x00000200,
121 AMASK_PREFETCH = 0x00001000,
122 };
123
124 enum {
125 VAX_ROUND_NORMAL = 0,
126 VAX_ROUND_CHOPPED,
127 };
128
129 enum {
130 IEEE_ROUND_NORMAL = 0,
131 IEEE_ROUND_DYNAMIC,
132 IEEE_ROUND_PLUS,
133 IEEE_ROUND_MINUS,
134 IEEE_ROUND_CHOPPED,
135 };
136
137 /* IEEE floating-point operations encoding */
138 /* Trap mode */
139 enum {
140 FP_TRAP_I = 0x0,
141 FP_TRAP_U = 0x1,
142 FP_TRAP_S = 0x4,
143 FP_TRAP_SU = 0x5,
144 FP_TRAP_SUI = 0x7,
145 };
146
147 /* Rounding mode */
148 enum {
149 FP_ROUND_CHOPPED = 0x0,
150 FP_ROUND_MINUS = 0x1,
151 FP_ROUND_NORMAL = 0x2,
152 FP_ROUND_DYNAMIC = 0x3,
153 };
154
155 /* FPCR bits */
156 #define FPCR_SUM (1ULL << 63)
157 #define FPCR_INED (1ULL << 62)
158 #define FPCR_UNFD (1ULL << 61)
159 #define FPCR_UNDZ (1ULL << 60)
160 #define FPCR_DYN_SHIFT 58
161 #define FPCR_DYN_CHOPPED (0ULL << FPCR_DYN_SHIFT)
162 #define FPCR_DYN_MINUS (1ULL << FPCR_DYN_SHIFT)
163 #define FPCR_DYN_NORMAL (2ULL << FPCR_DYN_SHIFT)
164 #define FPCR_DYN_PLUS (3ULL << FPCR_DYN_SHIFT)
165 #define FPCR_DYN_MASK (3ULL << FPCR_DYN_SHIFT)
166 #define FPCR_IOV (1ULL << 57)
167 #define FPCR_INE (1ULL << 56)
168 #define FPCR_UNF (1ULL << 55)
169 #define FPCR_OVF (1ULL << 54)
170 #define FPCR_DZE (1ULL << 53)
171 #define FPCR_INV (1ULL << 52)
172 #define FPCR_OVFD (1ULL << 51)
173 #define FPCR_DZED (1ULL << 50)
174 #define FPCR_INVD (1ULL << 49)
175 #define FPCR_DNZ (1ULL << 48)
176 #define FPCR_DNOD (1ULL << 47)
177 #define FPCR_STATUS_MASK (FPCR_IOV | FPCR_INE | FPCR_UNF \
178 | FPCR_OVF | FPCR_DZE | FPCR_INV)
179
180 /* The silly software trap enables implemented by the kernel emulation.
181 These are more or less architecturally required, since the real hardware
182 has read-as-zero bits in the FPCR when the features aren't implemented.
183 For the purposes of QEMU, we pretend the FPCR can hold everything. */
184 #define SWCR_TRAP_ENABLE_INV (1ULL << 1)
185 #define SWCR_TRAP_ENABLE_DZE (1ULL << 2)
186 #define SWCR_TRAP_ENABLE_OVF (1ULL << 3)
187 #define SWCR_TRAP_ENABLE_UNF (1ULL << 4)
188 #define SWCR_TRAP_ENABLE_INE (1ULL << 5)
189 #define SWCR_TRAP_ENABLE_DNO (1ULL << 6)
190 #define SWCR_TRAP_ENABLE_MASK ((1ULL << 7) - (1ULL << 1))
191
192 #define SWCR_MAP_DMZ (1ULL << 12)
193 #define SWCR_MAP_UMZ (1ULL << 13)
194 #define SWCR_MAP_MASK (SWCR_MAP_DMZ | SWCR_MAP_UMZ)
195
196 #define SWCR_STATUS_INV (1ULL << 17)
197 #define SWCR_STATUS_DZE (1ULL << 18)
198 #define SWCR_STATUS_OVF (1ULL << 19)
199 #define SWCR_STATUS_UNF (1ULL << 20)
200 #define SWCR_STATUS_INE (1ULL << 21)
201 #define SWCR_STATUS_DNO (1ULL << 22)
202 #define SWCR_STATUS_MASK ((1ULL << 23) - (1ULL << 17))
203
204 #define SWCR_MASK (SWCR_TRAP_ENABLE_MASK | SWCR_MAP_MASK | SWCR_STATUS_MASK)
205
206 /* MMU modes definitions */
207
208 /* Alpha has 5 MMU modes: PALcode, kernel, executive, supervisor, and user.
209 The Unix PALcode only exposes the kernel and user modes; presumably
210 executive and supervisor are used by VMS.
211
212 PALcode itself uses physical mode for code and kernel mode for data;
213 there are PALmode instructions that can access data via physical mode
214 or via an os-installed "alternate mode", which is one of the 4 above.
215
216 QEMU does not currently properly distinguish between code/data when
217 looking up addresses. To avoid having to address this issue, our
218 emulated PALcode will cheat and use the KSEG mapping for its code+data
219 rather than physical addresses.
220
221 Moreover, we're only emulating Unix PALcode, and not attempting VMS.
222
223 All of which allows us to drop all but kernel and user modes.
224 Elide the unused MMU modes to save space. */
225
226 #define NB_MMU_MODES 2
227
228 #define MMU_MODE0_SUFFIX _kernel
229 #define MMU_MODE1_SUFFIX _user
230 #define MMU_KERNEL_IDX 0
231 #define MMU_USER_IDX 1
232
233 typedef struct CPUAlphaState CPUAlphaState;
234
235 struct CPUAlphaState {
236 uint64_t ir[31];
237 float64 fir[31];
238 uint64_t pc;
239 uint64_t unique;
240 uint64_t lock_addr;
241 uint64_t lock_st_addr;
242 uint64_t lock_value;
243 float_status fp_status;
244 /* The following fields make up the FPCR, but in FP_STATUS format. */
245 uint8_t fpcr_exc_status;
246 uint8_t fpcr_exc_mask;
247 uint8_t fpcr_dyn_round;
248 uint8_t fpcr_flush_to_zero;
249 uint8_t fpcr_dnod;
250 uint8_t fpcr_undz;
251
252 /* The Internal Processor Registers. Some of these we assume always
253 exist for use in user-mode. */
254 uint8_t ps;
255 uint8_t intr_flag;
256 uint8_t pal_mode;
257 uint8_t fen;
258
259 uint32_t pcc_ofs;
260
261 /* These pass data from the exception logic in the translator and
262 helpers to the OS entry point. This is used for both system
263 emulation and user-mode. */
264 uint64_t trap_arg0;
265 uint64_t trap_arg1;
266 uint64_t trap_arg2;
267
268 #if !defined(CONFIG_USER_ONLY)
269 /* The internal data required by our emulation of the Unix PALcode. */
270 uint64_t exc_addr;
271 uint64_t palbr;
272 uint64_t ptbr;
273 uint64_t vptptr;
274 uint64_t sysval;
275 uint64_t usp;
276 uint64_t shadow[8];
277 uint64_t scratch[24];
278 #endif
279
280 /* This alarm doesn't exist in real hardware; we wish it did. */
281 uint64_t alarm_expire;
282
283 /* Those resources are used only in QEMU core */
284 CPU_COMMON
285
286 int error_code;
287
288 uint32_t features;
289 uint32_t amask;
290 int implver;
291 };
292
293 #define cpu_list alpha_cpu_list
294 #define cpu_exec cpu_alpha_exec
295 #define cpu_gen_code cpu_alpha_gen_code
296 #define cpu_signal_handler cpu_alpha_signal_handler
297
298 #include "exec/cpu-all.h"
299 #include "cpu-qom.h"
300
301 enum {
302 FEATURE_ASN = 0x00000001,
303 FEATURE_SPS = 0x00000002,
304 FEATURE_VIRBND = 0x00000004,
305 FEATURE_TBCHK = 0x00000008,
306 };
307
308 enum {
309 EXCP_RESET,
310 EXCP_MCHK,
311 EXCP_SMP_INTERRUPT,
312 EXCP_CLK_INTERRUPT,
313 EXCP_DEV_INTERRUPT,
314 EXCP_MMFAULT,
315 EXCP_UNALIGN,
316 EXCP_OPCDEC,
317 EXCP_ARITH,
318 EXCP_FEN,
319 EXCP_CALL_PAL,
320 /* For Usermode emulation. */
321 EXCP_STL_C,
322 EXCP_STQ_C,
323 };
324
325 /* Alpha-specific interrupt pending bits. */
326 #define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_EXT_0
327 #define CPU_INTERRUPT_SMP CPU_INTERRUPT_TGT_EXT_1
328 #define CPU_INTERRUPT_MCHK CPU_INTERRUPT_TGT_EXT_2
329
330 /* OSF/1 Page table bits. */
331 enum {
332 PTE_VALID = 0x0001,
333 PTE_FOR = 0x0002, /* used for page protection (fault on read) */
334 PTE_FOW = 0x0004, /* used for page protection (fault on write) */
335 PTE_FOE = 0x0008, /* used for page protection (fault on exec) */
336 PTE_ASM = 0x0010,
337 PTE_KRE = 0x0100,
338 PTE_URE = 0x0200,
339 PTE_KWE = 0x1000,
340 PTE_UWE = 0x2000
341 };
342
343 /* Hardware interrupt (entInt) constants. */
344 enum {
345 INT_K_IP,
346 INT_K_CLK,
347 INT_K_MCHK,
348 INT_K_DEV,
349 INT_K_PERF,
350 };
351
352 /* Memory management (entMM) constants. */
353 enum {
354 MM_K_TNV,
355 MM_K_ACV,
356 MM_K_FOR,
357 MM_K_FOE,
358 MM_K_FOW
359 };
360
361 /* Arithmetic exception (entArith) constants. */
362 enum {
363 EXC_M_SWC = 1, /* Software completion */
364 EXC_M_INV = 2, /* Invalid operation */
365 EXC_M_DZE = 4, /* Division by zero */
366 EXC_M_FOV = 8, /* Overflow */
367 EXC_M_UNF = 16, /* Underflow */
368 EXC_M_INE = 32, /* Inexact result */
369 EXC_M_IOV = 64 /* Integer Overflow */
370 };
371
372 /* Processor status constants. */
373 enum {
374 /* Low 3 bits are interrupt mask level. */
375 PS_INT_MASK = 7,
376
377 /* Bits 4 and 5 are the mmu mode. The VMS PALcode uses all 4 modes;
378 The Unix PALcode only uses bit 4. */
379 PS_USER_MODE = 8
380 };
381
382 static inline int cpu_mmu_index(CPUAlphaState *env)
383 {
384 if (env->pal_mode) {
385 return MMU_KERNEL_IDX;
386 } else if (env->ps & PS_USER_MODE) {
387 return MMU_USER_IDX;
388 } else {
389 return MMU_KERNEL_IDX;
390 }
391 }
392
393 enum {
394 IR_V0 = 0,
395 IR_T0 = 1,
396 IR_T1 = 2,
397 IR_T2 = 3,
398 IR_T3 = 4,
399 IR_T4 = 5,
400 IR_T5 = 6,
401 IR_T6 = 7,
402 IR_T7 = 8,
403 IR_S0 = 9,
404 IR_S1 = 10,
405 IR_S2 = 11,
406 IR_S3 = 12,
407 IR_S4 = 13,
408 IR_S5 = 14,
409 IR_S6 = 15,
410 IR_FP = IR_S6,
411 IR_A0 = 16,
412 IR_A1 = 17,
413 IR_A2 = 18,
414 IR_A3 = 19,
415 IR_A4 = 20,
416 IR_A5 = 21,
417 IR_T8 = 22,
418 IR_T9 = 23,
419 IR_T10 = 24,
420 IR_T11 = 25,
421 IR_RA = 26,
422 IR_T12 = 27,
423 IR_PV = IR_T12,
424 IR_AT = 28,
425 IR_GP = 29,
426 IR_SP = 30,
427 IR_ZERO = 31,
428 };
429
430 void alpha_translate_init(void);
431
432 AlphaCPU *cpu_alpha_init(const char *cpu_model);
433
434 static inline CPUAlphaState *cpu_init(const char *cpu_model)
435 {
436 AlphaCPU *cpu = cpu_alpha_init(cpu_model);
437 if (cpu == NULL) {
438 return NULL;
439 }
440 return &cpu->env;
441 }
442
443 void alpha_cpu_list(FILE *f, fprintf_function cpu_fprintf);
444 int cpu_alpha_exec(CPUAlphaState *s);
445 /* you can call this signal handler from your SIGBUS and SIGSEGV
446 signal handlers to inform the virtual CPU of exceptions. non zero
447 is returned if the signal was handled by the virtual CPU. */
448 int cpu_alpha_signal_handler(int host_signum, void *pinfo,
449 void *puc);
450 int alpha_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
451 int mmu_idx);
452 void do_restore_state(CPUAlphaState *, uintptr_t retaddr);
453 void QEMU_NORETURN dynamic_excp(CPUAlphaState *, uintptr_t, int, int);
454 void QEMU_NORETURN arith_excp(CPUAlphaState *, uintptr_t, int, uint64_t);
455
456 uint64_t cpu_alpha_load_fpcr (CPUAlphaState *env);
457 void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val);
458 #ifndef CONFIG_USER_ONLY
459 void swap_shadow_regs(CPUAlphaState *env);
460 QEMU_NORETURN void alpha_cpu_unassigned_access(CPUState *cpu, hwaddr addr,
461 bool is_write, bool is_exec,
462 int unused, unsigned size);
463 #endif
464
465 /* Bits in TB->FLAGS that control how translation is processed. */
466 enum {
467 TB_FLAGS_PAL_MODE = 1,
468 TB_FLAGS_FEN = 2,
469 TB_FLAGS_USER_MODE = 8,
470
471 TB_FLAGS_AMASK_SHIFT = 4,
472 TB_FLAGS_AMASK_BWX = AMASK_BWX << TB_FLAGS_AMASK_SHIFT,
473 TB_FLAGS_AMASK_FIX = AMASK_FIX << TB_FLAGS_AMASK_SHIFT,
474 TB_FLAGS_AMASK_CIX = AMASK_CIX << TB_FLAGS_AMASK_SHIFT,
475 TB_FLAGS_AMASK_MVI = AMASK_MVI << TB_FLAGS_AMASK_SHIFT,
476 TB_FLAGS_AMASK_TRAP = AMASK_TRAP << TB_FLAGS_AMASK_SHIFT,
477 TB_FLAGS_AMASK_PREFETCH = AMASK_PREFETCH << TB_FLAGS_AMASK_SHIFT,
478 };
479
480 static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, target_ulong *pc,
481 target_ulong *cs_base, int *pflags)
482 {
483 int flags = 0;
484
485 *pc = env->pc;
486 *cs_base = 0;
487
488 if (env->pal_mode) {
489 flags = TB_FLAGS_PAL_MODE;
490 } else {
491 flags = env->ps & PS_USER_MODE;
492 }
493 if (env->fen) {
494 flags |= TB_FLAGS_FEN;
495 }
496 flags |= env->amask << TB_FLAGS_AMASK_SHIFT;
497
498 *pflags = flags;
499 }
500
501 #include "exec/exec-all.h"
502
503 #endif /* !defined (__CPU_ALPHA_H__) */