qemu-img: Omit error_report() after img_open()
[qemu.git] / target-arm / cpu-qom.h
1 /*
2 * QEMU ARM CPU
3 *
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
19 */
20 #ifndef QEMU_ARM_CPU_QOM_H
21 #define QEMU_ARM_CPU_QOM_H
22
23 #include "qom/cpu.h"
24
25 #define TYPE_ARM_CPU "arm-cpu"
26
27 #define ARM_CPU_CLASS(klass) \
28 OBJECT_CLASS_CHECK(ARMCPUClass, (klass), TYPE_ARM_CPU)
29 #define ARM_CPU(obj) \
30 OBJECT_CHECK(ARMCPU, (obj), TYPE_ARM_CPU)
31 #define ARM_CPU_GET_CLASS(obj) \
32 OBJECT_GET_CLASS(ARMCPUClass, (obj), TYPE_ARM_CPU)
33
34 /**
35 * ARMCPUClass:
36 * @parent_realize: The parent class' realize handler.
37 * @parent_reset: The parent class' reset handler.
38 *
39 * An ARM CPU model.
40 */
41 typedef struct ARMCPUClass {
42 /*< private >*/
43 CPUClass parent_class;
44 /*< public >*/
45
46 DeviceRealize parent_realize;
47 void (*parent_reset)(CPUState *cpu);
48 } ARMCPUClass;
49
50 /**
51 * ARMCPU:
52 * @env: #CPUARMState
53 *
54 * An ARM CPU core.
55 */
56 typedef struct ARMCPU {
57 /*< private >*/
58 CPUState parent_obj;
59 /*< public >*/
60
61 CPUARMState env;
62
63 /* Coprocessor information */
64 GHashTable *cp_regs;
65 /* For marshalling (mostly coprocessor) register state between the
66 * kernel and QEMU (for KVM) and between two QEMUs (for migration),
67 * we use these arrays.
68 */
69 /* List of register indexes managed via these arrays; (full KVM style
70 * 64 bit indexes, not CPRegInfo 32 bit indexes)
71 */
72 uint64_t *cpreg_indexes;
73 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */
74 uint64_t *cpreg_values;
75 /* Length of the indexes, values, reset_values arrays */
76 int32_t cpreg_array_len;
77 /* These are used only for migration: incoming data arrives in
78 * these fields and is sanity checked in post_load before copying
79 * to the working data structures above.
80 */
81 uint64_t *cpreg_vmstate_indexes;
82 uint64_t *cpreg_vmstate_values;
83 int32_t cpreg_vmstate_array_len;
84
85 /* Timers used by the generic (architected) timer */
86 QEMUTimer *gt_timer[NUM_GTIMERS];
87 /* GPIO outputs for generic timer */
88 qemu_irq gt_timer_outputs[NUM_GTIMERS];
89
90 /* 'compatible' string for this CPU for Linux device trees */
91 const char *dtb_compatible;
92
93 /* PSCI version for this CPU
94 * Bits[31:16] = Major Version
95 * Bits[15:0] = Minor Version
96 */
97 uint32_t psci_version;
98
99 /* Should CPU start in PSCI powered-off state? */
100 bool start_powered_off;
101 /* CPU currently in PSCI powered-off state */
102 bool powered_off;
103
104 /* PSCI conduit used to invoke PSCI methods
105 * 0 - disabled, 1 - smc, 2 - hvc
106 */
107 uint32_t psci_conduit;
108
109 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or
110 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type.
111 */
112 uint32_t kvm_target;
113
114 /* KVM init features for this CPU */
115 uint32_t kvm_init_features[7];
116
117 /* The instance init functions for implementation-specific subclasses
118 * set these fields to specify the implementation-dependent values of
119 * various constant registers and reset values of non-constant
120 * registers.
121 * Some of these might become QOM properties eventually.
122 * Field names match the official register names as defined in the
123 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix
124 * is used for reset values of non-constant registers; no reset_
125 * prefix means a constant register.
126 */
127 uint32_t midr;
128 uint32_t reset_fpsid;
129 uint32_t mvfr0;
130 uint32_t mvfr1;
131 uint32_t mvfr2;
132 uint32_t ctr;
133 uint32_t reset_sctlr;
134 uint32_t id_pfr0;
135 uint32_t id_pfr1;
136 uint32_t id_dfr0;
137 uint32_t id_afr0;
138 uint32_t id_mmfr0;
139 uint32_t id_mmfr1;
140 uint32_t id_mmfr2;
141 uint32_t id_mmfr3;
142 uint32_t id_isar0;
143 uint32_t id_isar1;
144 uint32_t id_isar2;
145 uint32_t id_isar3;
146 uint32_t id_isar4;
147 uint32_t id_isar5;
148 uint64_t id_aa64pfr0;
149 uint64_t id_aa64pfr1;
150 uint64_t id_aa64dfr0;
151 uint64_t id_aa64dfr1;
152 uint64_t id_aa64afr0;
153 uint64_t id_aa64afr1;
154 uint64_t id_aa64isar0;
155 uint64_t id_aa64isar1;
156 uint64_t id_aa64mmfr0;
157 uint64_t id_aa64mmfr1;
158 uint32_t dbgdidr;
159 uint32_t clidr;
160 /* The elements of this array are the CCSIDR values for each cache,
161 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
162 */
163 uint32_t ccsidr[16];
164 uint64_t reset_cbar;
165 uint32_t reset_auxcr;
166 bool reset_hivecs;
167 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */
168 uint32_t dcz_blocksize;
169 uint64_t rvbar;
170 } ARMCPU;
171
172 #define TYPE_AARCH64_CPU "aarch64-cpu"
173 #define AARCH64_CPU_CLASS(klass) \
174 OBJECT_CLASS_CHECK(AArch64CPUClass, (klass), TYPE_AARCH64_CPU)
175 #define AARCH64_CPU_GET_CLASS(obj) \
176 OBJECT_GET_CLASS(AArch64CPUClass, (obj), TYPE_AArch64_CPU)
177
178 typedef struct AArch64CPUClass {
179 /*< private >*/
180 ARMCPUClass parent_class;
181 /*< public >*/
182 } AArch64CPUClass;
183
184 static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)
185 {
186 return container_of(env, ARMCPU, env);
187 }
188
189 #define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e))
190
191 #define ENV_OFFSET offsetof(ARMCPU, env)
192
193 #ifndef CONFIG_USER_ONLY
194 extern const struct VMStateDescription vmstate_arm_cpu;
195 #endif
196
197 void register_cp_regs_for_features(ARMCPU *cpu);
198 void init_cpreg_list(ARMCPU *cpu);
199
200 void arm_cpu_do_interrupt(CPUState *cpu);
201 void arm_v7m_cpu_do_interrupt(CPUState *cpu);
202 bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req);
203
204 void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
205 int flags);
206
207 hwaddr arm_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
208
209 int arm_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
210 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
211
212 /* Callback functions for the generic timer's timers. */
213 void arm_gt_ptimer_cb(void *opaque);
214 void arm_gt_vtimer_cb(void *opaque);
215
216 #ifdef TARGET_AARCH64
217 int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
218 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
219
220 void aarch64_cpu_do_interrupt(CPUState *cs);
221 #endif
222
223 #endif