qemu-img: Omit error_report() after img_open()
[qemu.git] / target-arm / cpu.c
1 /*
2 * QEMU ARM CPU
3 *
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
19 */
20
21 #include "cpu.h"
22 #include "internals.h"
23 #include "qemu-common.h"
24 #include "hw/qdev-properties.h"
25 #include "qapi/qmp/qerror.h"
26 #if !defined(CONFIG_USER_ONLY)
27 #include "hw/loader.h"
28 #endif
29 #include "hw/arm/arm.h"
30 #include "sysemu/sysemu.h"
31 #include "sysemu/kvm.h"
32 #include "kvm_arm.h"
33
34 static void arm_cpu_set_pc(CPUState *cs, vaddr value)
35 {
36 ARMCPU *cpu = ARM_CPU(cs);
37
38 cpu->env.regs[15] = value;
39 }
40
41 static bool arm_cpu_has_work(CPUState *cs)
42 {
43 ARMCPU *cpu = ARM_CPU(cs);
44
45 return !cpu->powered_off
46 && cs->interrupt_request &
47 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
48 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ
49 | CPU_INTERRUPT_EXITTB);
50 }
51
52 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
53 {
54 /* Reset a single ARMCPRegInfo register */
55 ARMCPRegInfo *ri = value;
56 ARMCPU *cpu = opaque;
57
58 if (ri->type & ARM_CP_SPECIAL) {
59 return;
60 }
61
62 if (ri->resetfn) {
63 ri->resetfn(&cpu->env, ri);
64 return;
65 }
66
67 /* A zero offset is never possible as it would be regs[0]
68 * so we use it to indicate that reset is being handled elsewhere.
69 * This is basically only used for fields in non-core coprocessors
70 * (like the pxa2xx ones).
71 */
72 if (!ri->fieldoffset) {
73 return;
74 }
75
76 if (cpreg_field_is_64bit(ri)) {
77 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
78 } else {
79 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
80 }
81 }
82
83 /* CPUClass::reset() */
84 static void arm_cpu_reset(CPUState *s)
85 {
86 ARMCPU *cpu = ARM_CPU(s);
87 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
88 CPUARMState *env = &cpu->env;
89
90 acc->parent_reset(s);
91
92 memset(env, 0, offsetof(CPUARMState, features));
93 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
94 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
95 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
96 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
97 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2;
98
99 cpu->powered_off = cpu->start_powered_off;
100 s->halted = cpu->start_powered_off;
101
102 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
103 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
104 }
105
106 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
107 /* 64 bit CPUs always start in 64 bit mode */
108 env->aarch64 = 1;
109 #if defined(CONFIG_USER_ONLY)
110 env->pstate = PSTATE_MODE_EL0t;
111 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
112 env->cp15.c1_sys |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE;
113 /* and to the FP/Neon instructions */
114 env->cp15.c1_coproc = deposit64(env->cp15.c1_coproc, 20, 2, 3);
115 #else
116 env->pstate = PSTATE_MODE_EL1h;
117 env->pc = cpu->rvbar;
118 #endif
119 } else {
120 #if defined(CONFIG_USER_ONLY)
121 /* Userspace expects access to cp10 and cp11 for FP/Neon */
122 env->cp15.c1_coproc = deposit64(env->cp15.c1_coproc, 20, 4, 0xf);
123 #endif
124 }
125
126 #if defined(CONFIG_USER_ONLY)
127 env->uncached_cpsr = ARM_CPU_MODE_USR;
128 /* For user mode we must enable access to coprocessors */
129 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
130 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
131 env->cp15.c15_cpar = 3;
132 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
133 env->cp15.c15_cpar = 1;
134 }
135 #else
136 /* SVC mode with interrupts disabled. */
137 env->uncached_cpsr = ARM_CPU_MODE_SVC;
138 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
139 /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
140 * clear at reset. Initial SP and PC are loaded from ROM.
141 */
142 if (IS_M(env)) {
143 uint32_t initial_msp; /* Loaded from 0x0 */
144 uint32_t initial_pc; /* Loaded from 0x4 */
145 uint8_t *rom;
146
147 env->daif &= ~PSTATE_I;
148 rom = rom_ptr(0);
149 if (rom) {
150 /* Address zero is covered by ROM which hasn't yet been
151 * copied into physical memory.
152 */
153 initial_msp = ldl_p(rom);
154 initial_pc = ldl_p(rom + 4);
155 } else {
156 /* Address zero not covered by a ROM blob, or the ROM blob
157 * is in non-modifiable memory and this is a second reset after
158 * it got copied into memory. In the latter case, rom_ptr
159 * will return a NULL pointer and we should use ldl_phys instead.
160 */
161 initial_msp = ldl_phys(s->as, 0);
162 initial_pc = ldl_phys(s->as, 4);
163 }
164
165 env->regs[13] = initial_msp & 0xFFFFFFFC;
166 env->regs[15] = initial_pc & ~1;
167 env->thumb = initial_pc & 1;
168 }
169
170 if (env->cp15.c1_sys & SCTLR_V) {
171 env->regs[15] = 0xFFFF0000;
172 }
173
174 env->vfp.xregs[ARM_VFP_FPEXC] = 0;
175 #endif
176 set_flush_to_zero(1, &env->vfp.standard_fp_status);
177 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
178 set_default_nan_mode(1, &env->vfp.standard_fp_status);
179 set_float_detect_tininess(float_tininess_before_rounding,
180 &env->vfp.fp_status);
181 set_float_detect_tininess(float_tininess_before_rounding,
182 &env->vfp.standard_fp_status);
183 tlb_flush(s, 1);
184
185 #ifndef CONFIG_USER_ONLY
186 if (kvm_enabled()) {
187 kvm_arm_reset_vcpu(cpu);
188 }
189 #endif
190
191 hw_breakpoint_update_all(cpu);
192 hw_watchpoint_update_all(cpu);
193 }
194
195 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
196 {
197 CPUClass *cc = CPU_GET_CLASS(cs);
198 bool ret = false;
199
200 if (interrupt_request & CPU_INTERRUPT_FIQ
201 && arm_excp_unmasked(cs, EXCP_FIQ)) {
202 cs->exception_index = EXCP_FIQ;
203 cc->do_interrupt(cs);
204 ret = true;
205 }
206 if (interrupt_request & CPU_INTERRUPT_HARD
207 && arm_excp_unmasked(cs, EXCP_IRQ)) {
208 cs->exception_index = EXCP_IRQ;
209 cc->do_interrupt(cs);
210 ret = true;
211 }
212 if (interrupt_request & CPU_INTERRUPT_VIRQ
213 && arm_excp_unmasked(cs, EXCP_VIRQ)) {
214 cs->exception_index = EXCP_VIRQ;
215 cc->do_interrupt(cs);
216 ret = true;
217 }
218 if (interrupt_request & CPU_INTERRUPT_VFIQ
219 && arm_excp_unmasked(cs, EXCP_VFIQ)) {
220 cs->exception_index = EXCP_VFIQ;
221 cc->do_interrupt(cs);
222 ret = true;
223 }
224
225 return ret;
226 }
227
228 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
229 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
230 {
231 CPUClass *cc = CPU_GET_CLASS(cs);
232 ARMCPU *cpu = ARM_CPU(cs);
233 CPUARMState *env = &cpu->env;
234 bool ret = false;
235
236
237 if (interrupt_request & CPU_INTERRUPT_FIQ
238 && !(env->daif & PSTATE_F)) {
239 cs->exception_index = EXCP_FIQ;
240 cc->do_interrupt(cs);
241 ret = true;
242 }
243 /* ARMv7-M interrupt return works by loading a magic value
244 * into the PC. On real hardware the load causes the
245 * return to occur. The qemu implementation performs the
246 * jump normally, then does the exception return when the
247 * CPU tries to execute code at the magic address.
248 * This will cause the magic PC value to be pushed to
249 * the stack if an interrupt occurred at the wrong time.
250 * We avoid this by disabling interrupts when
251 * pc contains a magic address.
252 */
253 if (interrupt_request & CPU_INTERRUPT_HARD
254 && !(env->daif & PSTATE_I)
255 && (env->regs[15] < 0xfffffff0)) {
256 cs->exception_index = EXCP_IRQ;
257 cc->do_interrupt(cs);
258 ret = true;
259 }
260 return ret;
261 }
262 #endif
263
264 #ifndef CONFIG_USER_ONLY
265 static void arm_cpu_set_irq(void *opaque, int irq, int level)
266 {
267 ARMCPU *cpu = opaque;
268 CPUARMState *env = &cpu->env;
269 CPUState *cs = CPU(cpu);
270 static const int mask[] = {
271 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD,
272 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ,
273 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ,
274 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ
275 };
276
277 switch (irq) {
278 case ARM_CPU_VIRQ:
279 case ARM_CPU_VFIQ:
280 if (!arm_feature(env, ARM_FEATURE_EL2)) {
281 hw_error("%s: Virtual interrupt line %d with no EL2 support\n",
282 __func__, irq);
283 }
284 /* fall through */
285 case ARM_CPU_IRQ:
286 case ARM_CPU_FIQ:
287 if (level) {
288 cpu_interrupt(cs, mask[irq]);
289 } else {
290 cpu_reset_interrupt(cs, mask[irq]);
291 }
292 break;
293 default:
294 hw_error("arm_cpu_set_irq: Bad interrupt line %d\n", irq);
295 }
296 }
297
298 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
299 {
300 #ifdef CONFIG_KVM
301 ARMCPU *cpu = opaque;
302 CPUState *cs = CPU(cpu);
303 int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT;
304
305 switch (irq) {
306 case ARM_CPU_IRQ:
307 kvm_irq |= KVM_ARM_IRQ_CPU_IRQ;
308 break;
309 case ARM_CPU_FIQ:
310 kvm_irq |= KVM_ARM_IRQ_CPU_FIQ;
311 break;
312 default:
313 hw_error("arm_cpu_kvm_set_irq: Bad interrupt line %d\n", irq);
314 }
315 kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT;
316 kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0);
317 #endif
318 }
319 #endif
320
321 static inline void set_feature(CPUARMState *env, int feature)
322 {
323 env->features |= 1ULL << feature;
324 }
325
326 static void arm_cpu_initfn(Object *obj)
327 {
328 CPUState *cs = CPU(obj);
329 ARMCPU *cpu = ARM_CPU(obj);
330 static bool inited;
331
332 cs->env_ptr = &cpu->env;
333 cpu_exec_init(&cpu->env);
334 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
335 g_free, g_free);
336
337 #ifndef CONFIG_USER_ONLY
338 /* Our inbound IRQ and FIQ lines */
339 if (kvm_enabled()) {
340 /* VIRQ and VFIQ are unused with KVM but we add them to maintain
341 * the same interface as non-KVM CPUs.
342 */
343 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4);
344 } else {
345 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4);
346 }
347
348 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
349 arm_gt_ptimer_cb, cpu);
350 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
351 arm_gt_vtimer_cb, cpu);
352 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
353 ARRAY_SIZE(cpu->gt_timer_outputs));
354 #endif
355
356 /* DTB consumers generally don't in fact care what the 'compatible'
357 * string is, so always provide some string and trust that a hypothetical
358 * picky DTB consumer will also provide a helpful error message.
359 */
360 cpu->dtb_compatible = "qemu,unknown";
361 cpu->psci_version = 1; /* By default assume PSCI v0.1 */
362 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
363
364 if (tcg_enabled()) {
365 cpu->psci_version = 2; /* TCG implements PSCI 0.2 */
366 if (!inited) {
367 inited = true;
368 arm_translate_init();
369 }
370 }
371 }
372
373 static Property arm_cpu_reset_cbar_property =
374 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
375
376 static Property arm_cpu_reset_hivecs_property =
377 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
378
379 static Property arm_cpu_rvbar_property =
380 DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0);
381
382 static void arm_cpu_post_init(Object *obj)
383 {
384 ARMCPU *cpu = ARM_CPU(obj);
385
386 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
387 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
388 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property,
389 &error_abort);
390 }
391
392 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
393 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property,
394 &error_abort);
395 }
396
397 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
398 qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property,
399 &error_abort);
400 }
401 }
402
403 static void arm_cpu_finalizefn(Object *obj)
404 {
405 ARMCPU *cpu = ARM_CPU(obj);
406 g_hash_table_destroy(cpu->cp_regs);
407 }
408
409 static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
410 {
411 CPUState *cs = CPU(dev);
412 ARMCPU *cpu = ARM_CPU(dev);
413 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
414 CPUARMState *env = &cpu->env;
415
416 /* Some features automatically imply others: */
417 if (arm_feature(env, ARM_FEATURE_V8)) {
418 set_feature(env, ARM_FEATURE_V7);
419 set_feature(env, ARM_FEATURE_ARM_DIV);
420 set_feature(env, ARM_FEATURE_LPAE);
421 }
422 if (arm_feature(env, ARM_FEATURE_V7)) {
423 set_feature(env, ARM_FEATURE_VAPA);
424 set_feature(env, ARM_FEATURE_THUMB2);
425 set_feature(env, ARM_FEATURE_MPIDR);
426 if (!arm_feature(env, ARM_FEATURE_M)) {
427 set_feature(env, ARM_FEATURE_V6K);
428 } else {
429 set_feature(env, ARM_FEATURE_V6);
430 }
431 }
432 if (arm_feature(env, ARM_FEATURE_V6K)) {
433 set_feature(env, ARM_FEATURE_V6);
434 set_feature(env, ARM_FEATURE_MVFR);
435 }
436 if (arm_feature(env, ARM_FEATURE_V6)) {
437 set_feature(env, ARM_FEATURE_V5);
438 if (!arm_feature(env, ARM_FEATURE_M)) {
439 set_feature(env, ARM_FEATURE_AUXCR);
440 }
441 }
442 if (arm_feature(env, ARM_FEATURE_V5)) {
443 set_feature(env, ARM_FEATURE_V4T);
444 }
445 if (arm_feature(env, ARM_FEATURE_M)) {
446 set_feature(env, ARM_FEATURE_THUMB_DIV);
447 }
448 if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
449 set_feature(env, ARM_FEATURE_THUMB_DIV);
450 }
451 if (arm_feature(env, ARM_FEATURE_VFP4)) {
452 set_feature(env, ARM_FEATURE_VFP3);
453 set_feature(env, ARM_FEATURE_VFP_FP16);
454 }
455 if (arm_feature(env, ARM_FEATURE_VFP3)) {
456 set_feature(env, ARM_FEATURE_VFP);
457 }
458 if (arm_feature(env, ARM_FEATURE_LPAE)) {
459 set_feature(env, ARM_FEATURE_V7MP);
460 set_feature(env, ARM_FEATURE_PXN);
461 }
462 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
463 set_feature(env, ARM_FEATURE_CBAR);
464 }
465
466 if (cpu->reset_hivecs) {
467 cpu->reset_sctlr |= (1 << 13);
468 }
469
470 register_cp_regs_for_features(cpu);
471 arm_cpu_register_gdb_regs_for_features(cpu);
472
473 init_cpreg_list(cpu);
474
475 qemu_init_vcpu(cs);
476 cpu_reset(cs);
477
478 acc->parent_realize(dev, errp);
479 }
480
481 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
482 {
483 ObjectClass *oc;
484 char *typename;
485
486 if (!cpu_model) {
487 return NULL;
488 }
489
490 typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpu_model);
491 oc = object_class_by_name(typename);
492 g_free(typename);
493 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
494 object_class_is_abstract(oc)) {
495 return NULL;
496 }
497 return oc;
498 }
499
500 /* CPU models. These are not needed for the AArch64 linux-user build. */
501 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
502
503 static void arm926_initfn(Object *obj)
504 {
505 ARMCPU *cpu = ARM_CPU(obj);
506
507 cpu->dtb_compatible = "arm,arm926";
508 set_feature(&cpu->env, ARM_FEATURE_V5);
509 set_feature(&cpu->env, ARM_FEATURE_VFP);
510 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
511 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
512 cpu->midr = 0x41069265;
513 cpu->reset_fpsid = 0x41011090;
514 cpu->ctr = 0x1dd20d2;
515 cpu->reset_sctlr = 0x00090078;
516 }
517
518 static void arm946_initfn(Object *obj)
519 {
520 ARMCPU *cpu = ARM_CPU(obj);
521
522 cpu->dtb_compatible = "arm,arm946";
523 set_feature(&cpu->env, ARM_FEATURE_V5);
524 set_feature(&cpu->env, ARM_FEATURE_MPU);
525 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
526 cpu->midr = 0x41059461;
527 cpu->ctr = 0x0f004006;
528 cpu->reset_sctlr = 0x00000078;
529 }
530
531 static void arm1026_initfn(Object *obj)
532 {
533 ARMCPU *cpu = ARM_CPU(obj);
534
535 cpu->dtb_compatible = "arm,arm1026";
536 set_feature(&cpu->env, ARM_FEATURE_V5);
537 set_feature(&cpu->env, ARM_FEATURE_VFP);
538 set_feature(&cpu->env, ARM_FEATURE_AUXCR);
539 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
540 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
541 cpu->midr = 0x4106a262;
542 cpu->reset_fpsid = 0x410110a0;
543 cpu->ctr = 0x1dd20d2;
544 cpu->reset_sctlr = 0x00090078;
545 cpu->reset_auxcr = 1;
546 {
547 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
548 ARMCPRegInfo ifar = {
549 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
550 .access = PL1_RW,
551 .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[1]),
552 .resetvalue = 0
553 };
554 define_one_arm_cp_reg(cpu, &ifar);
555 }
556 }
557
558 static void arm1136_r2_initfn(Object *obj)
559 {
560 ARMCPU *cpu = ARM_CPU(obj);
561 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
562 * older core than plain "arm1136". In particular this does not
563 * have the v6K features.
564 * These ID register values are correct for 1136 but may be wrong
565 * for 1136_r2 (in particular r0p2 does not actually implement most
566 * of the ID registers).
567 */
568
569 cpu->dtb_compatible = "arm,arm1136";
570 set_feature(&cpu->env, ARM_FEATURE_V6);
571 set_feature(&cpu->env, ARM_FEATURE_VFP);
572 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
573 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
574 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
575 cpu->midr = 0x4107b362;
576 cpu->reset_fpsid = 0x410120b4;
577 cpu->mvfr0 = 0x11111111;
578 cpu->mvfr1 = 0x00000000;
579 cpu->ctr = 0x1dd20d2;
580 cpu->reset_sctlr = 0x00050078;
581 cpu->id_pfr0 = 0x111;
582 cpu->id_pfr1 = 0x1;
583 cpu->id_dfr0 = 0x2;
584 cpu->id_afr0 = 0x3;
585 cpu->id_mmfr0 = 0x01130003;
586 cpu->id_mmfr1 = 0x10030302;
587 cpu->id_mmfr2 = 0x01222110;
588 cpu->id_isar0 = 0x00140011;
589 cpu->id_isar1 = 0x12002111;
590 cpu->id_isar2 = 0x11231111;
591 cpu->id_isar3 = 0x01102131;
592 cpu->id_isar4 = 0x141;
593 cpu->reset_auxcr = 7;
594 }
595
596 static void arm1136_initfn(Object *obj)
597 {
598 ARMCPU *cpu = ARM_CPU(obj);
599
600 cpu->dtb_compatible = "arm,arm1136";
601 set_feature(&cpu->env, ARM_FEATURE_V6K);
602 set_feature(&cpu->env, ARM_FEATURE_V6);
603 set_feature(&cpu->env, ARM_FEATURE_VFP);
604 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
605 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
606 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
607 cpu->midr = 0x4117b363;
608 cpu->reset_fpsid = 0x410120b4;
609 cpu->mvfr0 = 0x11111111;
610 cpu->mvfr1 = 0x00000000;
611 cpu->ctr = 0x1dd20d2;
612 cpu->reset_sctlr = 0x00050078;
613 cpu->id_pfr0 = 0x111;
614 cpu->id_pfr1 = 0x1;
615 cpu->id_dfr0 = 0x2;
616 cpu->id_afr0 = 0x3;
617 cpu->id_mmfr0 = 0x01130003;
618 cpu->id_mmfr1 = 0x10030302;
619 cpu->id_mmfr2 = 0x01222110;
620 cpu->id_isar0 = 0x00140011;
621 cpu->id_isar1 = 0x12002111;
622 cpu->id_isar2 = 0x11231111;
623 cpu->id_isar3 = 0x01102131;
624 cpu->id_isar4 = 0x141;
625 cpu->reset_auxcr = 7;
626 }
627
628 static void arm1176_initfn(Object *obj)
629 {
630 ARMCPU *cpu = ARM_CPU(obj);
631
632 cpu->dtb_compatible = "arm,arm1176";
633 set_feature(&cpu->env, ARM_FEATURE_V6K);
634 set_feature(&cpu->env, ARM_FEATURE_VFP);
635 set_feature(&cpu->env, ARM_FEATURE_VAPA);
636 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
637 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
638 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
639 cpu->midr = 0x410fb767;
640 cpu->reset_fpsid = 0x410120b5;
641 cpu->mvfr0 = 0x11111111;
642 cpu->mvfr1 = 0x00000000;
643 cpu->ctr = 0x1dd20d2;
644 cpu->reset_sctlr = 0x00050078;
645 cpu->id_pfr0 = 0x111;
646 cpu->id_pfr1 = 0x11;
647 cpu->id_dfr0 = 0x33;
648 cpu->id_afr0 = 0;
649 cpu->id_mmfr0 = 0x01130003;
650 cpu->id_mmfr1 = 0x10030302;
651 cpu->id_mmfr2 = 0x01222100;
652 cpu->id_isar0 = 0x0140011;
653 cpu->id_isar1 = 0x12002111;
654 cpu->id_isar2 = 0x11231121;
655 cpu->id_isar3 = 0x01102131;
656 cpu->id_isar4 = 0x01141;
657 cpu->reset_auxcr = 7;
658 }
659
660 static void arm11mpcore_initfn(Object *obj)
661 {
662 ARMCPU *cpu = ARM_CPU(obj);
663
664 cpu->dtb_compatible = "arm,arm11mpcore";
665 set_feature(&cpu->env, ARM_FEATURE_V6K);
666 set_feature(&cpu->env, ARM_FEATURE_VFP);
667 set_feature(&cpu->env, ARM_FEATURE_VAPA);
668 set_feature(&cpu->env, ARM_FEATURE_MPIDR);
669 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
670 cpu->midr = 0x410fb022;
671 cpu->reset_fpsid = 0x410120b4;
672 cpu->mvfr0 = 0x11111111;
673 cpu->mvfr1 = 0x00000000;
674 cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
675 cpu->id_pfr0 = 0x111;
676 cpu->id_pfr1 = 0x1;
677 cpu->id_dfr0 = 0;
678 cpu->id_afr0 = 0x2;
679 cpu->id_mmfr0 = 0x01100103;
680 cpu->id_mmfr1 = 0x10020302;
681 cpu->id_mmfr2 = 0x01222000;
682 cpu->id_isar0 = 0x00100011;
683 cpu->id_isar1 = 0x12002111;
684 cpu->id_isar2 = 0x11221011;
685 cpu->id_isar3 = 0x01102131;
686 cpu->id_isar4 = 0x141;
687 cpu->reset_auxcr = 1;
688 }
689
690 static void cortex_m3_initfn(Object *obj)
691 {
692 ARMCPU *cpu = ARM_CPU(obj);
693 set_feature(&cpu->env, ARM_FEATURE_V7);
694 set_feature(&cpu->env, ARM_FEATURE_M);
695 cpu->midr = 0x410fc231;
696 }
697
698 static void arm_v7m_class_init(ObjectClass *oc, void *data)
699 {
700 CPUClass *cc = CPU_CLASS(oc);
701
702 #ifndef CONFIG_USER_ONLY
703 cc->do_interrupt = arm_v7m_cpu_do_interrupt;
704 #endif
705
706 cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
707 }
708
709 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
710 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
711 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
712 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
713 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
714 REGINFO_SENTINEL
715 };
716
717 static void cortex_a8_initfn(Object *obj)
718 {
719 ARMCPU *cpu = ARM_CPU(obj);
720
721 cpu->dtb_compatible = "arm,cortex-a8";
722 set_feature(&cpu->env, ARM_FEATURE_V7);
723 set_feature(&cpu->env, ARM_FEATURE_VFP3);
724 set_feature(&cpu->env, ARM_FEATURE_NEON);
725 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
726 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
727 cpu->midr = 0x410fc080;
728 cpu->reset_fpsid = 0x410330c0;
729 cpu->mvfr0 = 0x11110222;
730 cpu->mvfr1 = 0x00011100;
731 cpu->ctr = 0x82048004;
732 cpu->reset_sctlr = 0x00c50078;
733 cpu->id_pfr0 = 0x1031;
734 cpu->id_pfr1 = 0x11;
735 cpu->id_dfr0 = 0x400;
736 cpu->id_afr0 = 0;
737 cpu->id_mmfr0 = 0x31100003;
738 cpu->id_mmfr1 = 0x20000000;
739 cpu->id_mmfr2 = 0x01202000;
740 cpu->id_mmfr3 = 0x11;
741 cpu->id_isar0 = 0x00101111;
742 cpu->id_isar1 = 0x12112111;
743 cpu->id_isar2 = 0x21232031;
744 cpu->id_isar3 = 0x11112131;
745 cpu->id_isar4 = 0x00111142;
746 cpu->dbgdidr = 0x15141000;
747 cpu->clidr = (1 << 27) | (2 << 24) | 3;
748 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
749 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
750 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
751 cpu->reset_auxcr = 2;
752 define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
753 }
754
755 static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
756 /* power_control should be set to maximum latency. Again,
757 * default to 0 and set by private hook
758 */
759 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
760 .access = PL1_RW, .resetvalue = 0,
761 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
762 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
763 .access = PL1_RW, .resetvalue = 0,
764 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
765 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
766 .access = PL1_RW, .resetvalue = 0,
767 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
768 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
769 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
770 /* TLB lockdown control */
771 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
772 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
773 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
774 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
775 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
776 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
777 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
778 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
779 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
780 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
781 REGINFO_SENTINEL
782 };
783
784 static void cortex_a9_initfn(Object *obj)
785 {
786 ARMCPU *cpu = ARM_CPU(obj);
787
788 cpu->dtb_compatible = "arm,cortex-a9";
789 set_feature(&cpu->env, ARM_FEATURE_V7);
790 set_feature(&cpu->env, ARM_FEATURE_VFP3);
791 set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
792 set_feature(&cpu->env, ARM_FEATURE_NEON);
793 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
794 /* Note that A9 supports the MP extensions even for
795 * A9UP and single-core A9MP (which are both different
796 * and valid configurations; we don't model A9UP).
797 */
798 set_feature(&cpu->env, ARM_FEATURE_V7MP);
799 set_feature(&cpu->env, ARM_FEATURE_CBAR);
800 cpu->midr = 0x410fc090;
801 cpu->reset_fpsid = 0x41033090;
802 cpu->mvfr0 = 0x11110222;
803 cpu->mvfr1 = 0x01111111;
804 cpu->ctr = 0x80038003;
805 cpu->reset_sctlr = 0x00c50078;
806 cpu->id_pfr0 = 0x1031;
807 cpu->id_pfr1 = 0x11;
808 cpu->id_dfr0 = 0x000;
809 cpu->id_afr0 = 0;
810 cpu->id_mmfr0 = 0x00100103;
811 cpu->id_mmfr1 = 0x20000000;
812 cpu->id_mmfr2 = 0x01230000;
813 cpu->id_mmfr3 = 0x00002111;
814 cpu->id_isar0 = 0x00101111;
815 cpu->id_isar1 = 0x13112111;
816 cpu->id_isar2 = 0x21232041;
817 cpu->id_isar3 = 0x11112131;
818 cpu->id_isar4 = 0x00111142;
819 cpu->dbgdidr = 0x35141000;
820 cpu->clidr = (1 << 27) | (1 << 24) | 3;
821 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
822 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
823 define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
824 }
825
826 #ifndef CONFIG_USER_ONLY
827 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
828 {
829 /* Linux wants the number of processors from here.
830 * Might as well set the interrupt-controller bit too.
831 */
832 return ((smp_cpus - 1) << 24) | (1 << 23);
833 }
834 #endif
835
836 static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
837 #ifndef CONFIG_USER_ONLY
838 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
839 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
840 .writefn = arm_cp_write_ignore, },
841 #endif
842 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
843 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
844 REGINFO_SENTINEL
845 };
846
847 static void cortex_a15_initfn(Object *obj)
848 {
849 ARMCPU *cpu = ARM_CPU(obj);
850
851 cpu->dtb_compatible = "arm,cortex-a15";
852 set_feature(&cpu->env, ARM_FEATURE_V7);
853 set_feature(&cpu->env, ARM_FEATURE_VFP4);
854 set_feature(&cpu->env, ARM_FEATURE_NEON);
855 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
856 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
857 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
858 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
859 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
860 set_feature(&cpu->env, ARM_FEATURE_LPAE);
861 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
862 cpu->midr = 0x412fc0f1;
863 cpu->reset_fpsid = 0x410430f0;
864 cpu->mvfr0 = 0x10110222;
865 cpu->mvfr1 = 0x11111111;
866 cpu->ctr = 0x8444c004;
867 cpu->reset_sctlr = 0x00c50078;
868 cpu->id_pfr0 = 0x00001131;
869 cpu->id_pfr1 = 0x00011011;
870 cpu->id_dfr0 = 0x02010555;
871 cpu->id_afr0 = 0x00000000;
872 cpu->id_mmfr0 = 0x10201105;
873 cpu->id_mmfr1 = 0x20000000;
874 cpu->id_mmfr2 = 0x01240000;
875 cpu->id_mmfr3 = 0x02102211;
876 cpu->id_isar0 = 0x02101110;
877 cpu->id_isar1 = 0x13112111;
878 cpu->id_isar2 = 0x21232041;
879 cpu->id_isar3 = 0x11112131;
880 cpu->id_isar4 = 0x10011142;
881 cpu->dbgdidr = 0x3515f021;
882 cpu->clidr = 0x0a200023;
883 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
884 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
885 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
886 define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
887 }
888
889 static void ti925t_initfn(Object *obj)
890 {
891 ARMCPU *cpu = ARM_CPU(obj);
892 set_feature(&cpu->env, ARM_FEATURE_V4T);
893 set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
894 cpu->midr = ARM_CPUID_TI925T;
895 cpu->ctr = 0x5109149;
896 cpu->reset_sctlr = 0x00000070;
897 }
898
899 static void sa1100_initfn(Object *obj)
900 {
901 ARMCPU *cpu = ARM_CPU(obj);
902
903 cpu->dtb_compatible = "intel,sa1100";
904 set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
905 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
906 cpu->midr = 0x4401A11B;
907 cpu->reset_sctlr = 0x00000070;
908 }
909
910 static void sa1110_initfn(Object *obj)
911 {
912 ARMCPU *cpu = ARM_CPU(obj);
913 set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
914 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
915 cpu->midr = 0x6901B119;
916 cpu->reset_sctlr = 0x00000070;
917 }
918
919 static void pxa250_initfn(Object *obj)
920 {
921 ARMCPU *cpu = ARM_CPU(obj);
922
923 cpu->dtb_compatible = "marvell,xscale";
924 set_feature(&cpu->env, ARM_FEATURE_V5);
925 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
926 cpu->midr = 0x69052100;
927 cpu->ctr = 0xd172172;
928 cpu->reset_sctlr = 0x00000078;
929 }
930
931 static void pxa255_initfn(Object *obj)
932 {
933 ARMCPU *cpu = ARM_CPU(obj);
934
935 cpu->dtb_compatible = "marvell,xscale";
936 set_feature(&cpu->env, ARM_FEATURE_V5);
937 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
938 cpu->midr = 0x69052d00;
939 cpu->ctr = 0xd172172;
940 cpu->reset_sctlr = 0x00000078;
941 }
942
943 static void pxa260_initfn(Object *obj)
944 {
945 ARMCPU *cpu = ARM_CPU(obj);
946
947 cpu->dtb_compatible = "marvell,xscale";
948 set_feature(&cpu->env, ARM_FEATURE_V5);
949 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
950 cpu->midr = 0x69052903;
951 cpu->ctr = 0xd172172;
952 cpu->reset_sctlr = 0x00000078;
953 }
954
955 static void pxa261_initfn(Object *obj)
956 {
957 ARMCPU *cpu = ARM_CPU(obj);
958
959 cpu->dtb_compatible = "marvell,xscale";
960 set_feature(&cpu->env, ARM_FEATURE_V5);
961 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
962 cpu->midr = 0x69052d05;
963 cpu->ctr = 0xd172172;
964 cpu->reset_sctlr = 0x00000078;
965 }
966
967 static void pxa262_initfn(Object *obj)
968 {
969 ARMCPU *cpu = ARM_CPU(obj);
970
971 cpu->dtb_compatible = "marvell,xscale";
972 set_feature(&cpu->env, ARM_FEATURE_V5);
973 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
974 cpu->midr = 0x69052d06;
975 cpu->ctr = 0xd172172;
976 cpu->reset_sctlr = 0x00000078;
977 }
978
979 static void pxa270a0_initfn(Object *obj)
980 {
981 ARMCPU *cpu = ARM_CPU(obj);
982
983 cpu->dtb_compatible = "marvell,xscale";
984 set_feature(&cpu->env, ARM_FEATURE_V5);
985 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
986 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
987 cpu->midr = 0x69054110;
988 cpu->ctr = 0xd172172;
989 cpu->reset_sctlr = 0x00000078;
990 }
991
992 static void pxa270a1_initfn(Object *obj)
993 {
994 ARMCPU *cpu = ARM_CPU(obj);
995
996 cpu->dtb_compatible = "marvell,xscale";
997 set_feature(&cpu->env, ARM_FEATURE_V5);
998 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
999 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1000 cpu->midr = 0x69054111;
1001 cpu->ctr = 0xd172172;
1002 cpu->reset_sctlr = 0x00000078;
1003 }
1004
1005 static void pxa270b0_initfn(Object *obj)
1006 {
1007 ARMCPU *cpu = ARM_CPU(obj);
1008
1009 cpu->dtb_compatible = "marvell,xscale";
1010 set_feature(&cpu->env, ARM_FEATURE_V5);
1011 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1012 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1013 cpu->midr = 0x69054112;
1014 cpu->ctr = 0xd172172;
1015 cpu->reset_sctlr = 0x00000078;
1016 }
1017
1018 static void pxa270b1_initfn(Object *obj)
1019 {
1020 ARMCPU *cpu = ARM_CPU(obj);
1021
1022 cpu->dtb_compatible = "marvell,xscale";
1023 set_feature(&cpu->env, ARM_FEATURE_V5);
1024 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1025 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1026 cpu->midr = 0x69054113;
1027 cpu->ctr = 0xd172172;
1028 cpu->reset_sctlr = 0x00000078;
1029 }
1030
1031 static void pxa270c0_initfn(Object *obj)
1032 {
1033 ARMCPU *cpu = ARM_CPU(obj);
1034
1035 cpu->dtb_compatible = "marvell,xscale";
1036 set_feature(&cpu->env, ARM_FEATURE_V5);
1037 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1038 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1039 cpu->midr = 0x69054114;
1040 cpu->ctr = 0xd172172;
1041 cpu->reset_sctlr = 0x00000078;
1042 }
1043
1044 static void pxa270c5_initfn(Object *obj)
1045 {
1046 ARMCPU *cpu = ARM_CPU(obj);
1047
1048 cpu->dtb_compatible = "marvell,xscale";
1049 set_feature(&cpu->env, ARM_FEATURE_V5);
1050 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1051 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1052 cpu->midr = 0x69054117;
1053 cpu->ctr = 0xd172172;
1054 cpu->reset_sctlr = 0x00000078;
1055 }
1056
1057 #ifdef CONFIG_USER_ONLY
1058 static void arm_any_initfn(Object *obj)
1059 {
1060 ARMCPU *cpu = ARM_CPU(obj);
1061 set_feature(&cpu->env, ARM_FEATURE_V8);
1062 set_feature(&cpu->env, ARM_FEATURE_VFP4);
1063 set_feature(&cpu->env, ARM_FEATURE_NEON);
1064 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1065 set_feature(&cpu->env, ARM_FEATURE_V8_AES);
1066 set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
1067 set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
1068 set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
1069 set_feature(&cpu->env, ARM_FEATURE_CRC);
1070 cpu->midr = 0xffffffff;
1071 }
1072 #endif
1073
1074 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
1075
1076 typedef struct ARMCPUInfo {
1077 const char *name;
1078 void (*initfn)(Object *obj);
1079 void (*class_init)(ObjectClass *oc, void *data);
1080 } ARMCPUInfo;
1081
1082 static const ARMCPUInfo arm_cpus[] = {
1083 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1084 { .name = "arm926", .initfn = arm926_initfn },
1085 { .name = "arm946", .initfn = arm946_initfn },
1086 { .name = "arm1026", .initfn = arm1026_initfn },
1087 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
1088 * older core than plain "arm1136". In particular this does not
1089 * have the v6K features.
1090 */
1091 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn },
1092 { .name = "arm1136", .initfn = arm1136_initfn },
1093 { .name = "arm1176", .initfn = arm1176_initfn },
1094 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
1095 { .name = "cortex-m3", .initfn = cortex_m3_initfn,
1096 .class_init = arm_v7m_class_init },
1097 { .name = "cortex-a8", .initfn = cortex_a8_initfn },
1098 { .name = "cortex-a9", .initfn = cortex_a9_initfn },
1099 { .name = "cortex-a15", .initfn = cortex_a15_initfn },
1100 { .name = "ti925t", .initfn = ti925t_initfn },
1101 { .name = "sa1100", .initfn = sa1100_initfn },
1102 { .name = "sa1110", .initfn = sa1110_initfn },
1103 { .name = "pxa250", .initfn = pxa250_initfn },
1104 { .name = "pxa255", .initfn = pxa255_initfn },
1105 { .name = "pxa260", .initfn = pxa260_initfn },
1106 { .name = "pxa261", .initfn = pxa261_initfn },
1107 { .name = "pxa262", .initfn = pxa262_initfn },
1108 /* "pxa270" is an alias for "pxa270-a0" */
1109 { .name = "pxa270", .initfn = pxa270a0_initfn },
1110 { .name = "pxa270-a0", .initfn = pxa270a0_initfn },
1111 { .name = "pxa270-a1", .initfn = pxa270a1_initfn },
1112 { .name = "pxa270-b0", .initfn = pxa270b0_initfn },
1113 { .name = "pxa270-b1", .initfn = pxa270b1_initfn },
1114 { .name = "pxa270-c0", .initfn = pxa270c0_initfn },
1115 { .name = "pxa270-c5", .initfn = pxa270c5_initfn },
1116 #ifdef CONFIG_USER_ONLY
1117 { .name = "any", .initfn = arm_any_initfn },
1118 #endif
1119 #endif
1120 { .name = NULL }
1121 };
1122
1123 static Property arm_cpu_properties[] = {
1124 DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),
1125 DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0),
1126 DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0),
1127 DEFINE_PROP_END_OF_LIST()
1128 };
1129
1130 static void arm_cpu_class_init(ObjectClass *oc, void *data)
1131 {
1132 ARMCPUClass *acc = ARM_CPU_CLASS(oc);
1133 CPUClass *cc = CPU_CLASS(acc);
1134 DeviceClass *dc = DEVICE_CLASS(oc);
1135
1136 acc->parent_realize = dc->realize;
1137 dc->realize = arm_cpu_realizefn;
1138 dc->props = arm_cpu_properties;
1139
1140 acc->parent_reset = cc->reset;
1141 cc->reset = arm_cpu_reset;
1142
1143 cc->class_by_name = arm_cpu_class_by_name;
1144 cc->has_work = arm_cpu_has_work;
1145 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
1146 cc->dump_state = arm_cpu_dump_state;
1147 cc->set_pc = arm_cpu_set_pc;
1148 cc->gdb_read_register = arm_cpu_gdb_read_register;
1149 cc->gdb_write_register = arm_cpu_gdb_write_register;
1150 #ifdef CONFIG_USER_ONLY
1151 cc->handle_mmu_fault = arm_cpu_handle_mmu_fault;
1152 #else
1153 cc->do_interrupt = arm_cpu_do_interrupt;
1154 cc->get_phys_page_debug = arm_cpu_get_phys_page_debug;
1155 cc->vmsd = &vmstate_arm_cpu;
1156 #endif
1157 cc->gdb_num_core_regs = 26;
1158 cc->gdb_core_xml_file = "arm-core.xml";
1159 cc->gdb_stop_before_watchpoint = true;
1160 cc->debug_excp_handler = arm_debug_excp_handler;
1161 }
1162
1163 static void cpu_register(const ARMCPUInfo *info)
1164 {
1165 TypeInfo type_info = {
1166 .parent = TYPE_ARM_CPU,
1167 .instance_size = sizeof(ARMCPU),
1168 .instance_init = info->initfn,
1169 .class_size = sizeof(ARMCPUClass),
1170 .class_init = info->class_init,
1171 };
1172
1173 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
1174 type_register(&type_info);
1175 g_free((void *)type_info.name);
1176 }
1177
1178 static const TypeInfo arm_cpu_type_info = {
1179 .name = TYPE_ARM_CPU,
1180 .parent = TYPE_CPU,
1181 .instance_size = sizeof(ARMCPU),
1182 .instance_init = arm_cpu_initfn,
1183 .instance_post_init = arm_cpu_post_init,
1184 .instance_finalize = arm_cpu_finalizefn,
1185 .abstract = true,
1186 .class_size = sizeof(ARMCPUClass),
1187 .class_init = arm_cpu_class_init,
1188 };
1189
1190 static void arm_cpu_register_types(void)
1191 {
1192 const ARMCPUInfo *info = arm_cpus;
1193
1194 type_register_static(&arm_cpu_type_info);
1195
1196 while (info->name) {
1197 cpu_register(info);
1198 info++;
1199 }
1200 }
1201
1202 type_init(arm_cpu_register_types)