Add access control support to qemu bridge helper
[qemu.git] / target-arm / cpu.h
1 /*
2 * ARM virtual CPU header
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #ifndef CPU_ARM_H
20 #define CPU_ARM_H
21
22 #define TARGET_LONG_BITS 32
23
24 #define ELF_MACHINE EM_ARM
25
26 #define CPUState struct CPUARMState
27
28 #include "config.h"
29 #include "qemu-common.h"
30 #include "cpu-defs.h"
31
32 #include "softfloat.h"
33
34 #define TARGET_HAS_ICE 1
35
36 #define EXCP_UDEF 1 /* undefined instruction */
37 #define EXCP_SWI 2 /* software interrupt */
38 #define EXCP_PREFETCH_ABORT 3
39 #define EXCP_DATA_ABORT 4
40 #define EXCP_IRQ 5
41 #define EXCP_FIQ 6
42 #define EXCP_BKPT 7
43 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */
44 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */
45 #define EXCP_STREX 10
46
47 #define ARMV7M_EXCP_RESET 1
48 #define ARMV7M_EXCP_NMI 2
49 #define ARMV7M_EXCP_HARD 3
50 #define ARMV7M_EXCP_MEM 4
51 #define ARMV7M_EXCP_BUS 5
52 #define ARMV7M_EXCP_USAGE 6
53 #define ARMV7M_EXCP_SVC 11
54 #define ARMV7M_EXCP_DEBUG 12
55 #define ARMV7M_EXCP_PENDSV 14
56 #define ARMV7M_EXCP_SYSTICK 15
57
58 /* ARM-specific interrupt pending bits. */
59 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1
60
61
62 typedef void ARMWriteCPFunc(void *opaque, int cp_info,
63 int srcreg, int operand, uint32_t value);
64 typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info,
65 int dstreg, int operand);
66
67 struct arm_boot_info;
68
69 #define NB_MMU_MODES 2
70
71 /* We currently assume float and double are IEEE single and double
72 precision respectively.
73 Doing runtime conversions is tricky because VFP registers may contain
74 integer values (eg. as the result of a FTOSI instruction).
75 s<2n> maps to the least significant half of d<n>
76 s<2n+1> maps to the most significant half of d<n>
77 */
78
79 typedef struct CPUARMState {
80 /* Regs for current mode. */
81 uint32_t regs[16];
82 /* Frequently accessed CPSR bits are stored separately for efficiently.
83 This contains all the other bits. Use cpsr_{read,write} to access
84 the whole CPSR. */
85 uint32_t uncached_cpsr;
86 uint32_t spsr;
87
88 /* Banked registers. */
89 uint32_t banked_spsr[6];
90 uint32_t banked_r13[6];
91 uint32_t banked_r14[6];
92
93 /* These hold r8-r12. */
94 uint32_t usr_regs[5];
95 uint32_t fiq_regs[5];
96
97 /* cpsr flag cache for faster execution */
98 uint32_t CF; /* 0 or 1 */
99 uint32_t VF; /* V is the bit 31. All other bits are undefined */
100 uint32_t NF; /* N is bit 31. All other bits are undefined. */
101 uint32_t ZF; /* Z set if zero. */
102 uint32_t QF; /* 0 or 1 */
103 uint32_t GE; /* cpsr[19:16] */
104 uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
105 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */
106
107 /* System control coprocessor (cp15) */
108 struct {
109 uint32_t c0_cpuid;
110 uint32_t c0_cachetype;
111 uint32_t c0_ccsid[16]; /* Cache size. */
112 uint32_t c0_clid; /* Cache level. */
113 uint32_t c0_cssel; /* Cache size selection. */
114 uint32_t c0_c1[8]; /* Feature registers. */
115 uint32_t c0_c2[8]; /* Instruction set registers. */
116 uint32_t c1_sys; /* System control register. */
117 uint32_t c1_coproc; /* Coprocessor access register. */
118 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */
119 uint32_t c1_scr; /* secure config register. */
120 uint32_t c2_base0; /* MMU translation table base 0. */
121 uint32_t c2_base1; /* MMU translation table base 1. */
122 uint32_t c2_control; /* MMU translation table base control. */
123 uint32_t c2_mask; /* MMU translation table base selection mask. */
124 uint32_t c2_base_mask; /* MMU translation table base 0 mask. */
125 uint32_t c2_data; /* MPU data cachable bits. */
126 uint32_t c2_insn; /* MPU instruction cachable bits. */
127 uint32_t c3; /* MMU domain access control register
128 MPU write buffer control. */
129 uint32_t c5_insn; /* Fault status registers. */
130 uint32_t c5_data;
131 uint32_t c6_region[8]; /* MPU base/size registers. */
132 uint32_t c6_insn; /* Fault address registers. */
133 uint32_t c6_data;
134 uint32_t c7_par; /* Translation result. */
135 uint32_t c9_insn; /* Cache lockdown registers. */
136 uint32_t c9_data;
137 uint32_t c9_pmcr; /* performance monitor control register */
138 uint32_t c9_pmcnten; /* perf monitor counter enables */
139 uint32_t c9_pmovsr; /* perf monitor overflow status */
140 uint32_t c9_pmxevtyper; /* perf monitor event type */
141 uint32_t c9_pmuserenr; /* perf monitor user enable */
142 uint32_t c9_pminten; /* perf monitor interrupt enables */
143 uint32_t c13_fcse; /* FCSE PID. */
144 uint32_t c13_context; /* Context ID. */
145 uint32_t c13_tls1; /* User RW Thread register. */
146 uint32_t c13_tls2; /* User RO Thread register. */
147 uint32_t c13_tls3; /* Privileged Thread register. */
148 uint32_t c15_cpar; /* XScale Coprocessor Access Register */
149 uint32_t c15_ticonfig; /* TI925T configuration byte. */
150 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */
151 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */
152 uint32_t c15_threadid; /* TI debugger thread-ID. */
153 uint32_t c15_config_base_address; /* SCU base address. */
154 uint32_t c15_diagnostic; /* diagnostic register */
155 uint32_t c15_power_diagnostic;
156 uint32_t c15_power_control; /* power control */
157 } cp15;
158
159 struct {
160 uint32_t other_sp;
161 uint32_t vecbase;
162 uint32_t basepri;
163 uint32_t control;
164 int current_sp;
165 int exception;
166 int pending_exception;
167 } v7m;
168
169 /* Thumb-2 EE state. */
170 uint32_t teecr;
171 uint32_t teehbr;
172
173 /* Internal CPU feature flags. */
174 uint32_t features;
175
176 /* VFP coprocessor state. */
177 struct {
178 float64 regs[32];
179
180 uint32_t xregs[16];
181 /* We store these fpcsr fields separately for convenience. */
182 int vec_len;
183 int vec_stride;
184
185 /* scratch space when Tn are not sufficient. */
186 uint32_t scratch[8];
187
188 /* fp_status is the "normal" fp status. standard_fp_status retains
189 * values corresponding to the ARM "Standard FPSCR Value", ie
190 * default-NaN, flush-to-zero, round-to-nearest and is used by
191 * any operations (generally Neon) which the architecture defines
192 * as controlled by the standard FPSCR value rather than the FPSCR.
193 *
194 * To avoid having to transfer exception bits around, we simply
195 * say that the FPSCR cumulative exception flags are the logical
196 * OR of the flags in the two fp statuses. This relies on the
197 * only thing which needs to read the exception flags being
198 * an explicit FPSCR read.
199 */
200 float_status fp_status;
201 float_status standard_fp_status;
202 } vfp;
203 uint32_t exclusive_addr;
204 uint32_t exclusive_val;
205 uint32_t exclusive_high;
206 #if defined(CONFIG_USER_ONLY)
207 uint32_t exclusive_test;
208 uint32_t exclusive_info;
209 #endif
210
211 /* iwMMXt coprocessor state. */
212 struct {
213 uint64_t regs[16];
214 uint64_t val;
215
216 uint32_t cregs[16];
217 } iwmmxt;
218
219 #if defined(CONFIG_USER_ONLY)
220 /* For usermode syscall translation. */
221 int eabi;
222 #endif
223
224 CPU_COMMON
225
226 /* These fields after the common ones so they are preserved on reset. */
227
228 /* Coprocessor IO used by peripherals */
229 struct {
230 ARMReadCPFunc *cp_read;
231 ARMWriteCPFunc *cp_write;
232 void *opaque;
233 } cp[15];
234 void *nvic;
235 const struct arm_boot_info *boot_info;
236 } CPUARMState;
237
238 CPUARMState *cpu_arm_init(const char *cpu_model);
239 void arm_translate_init(void);
240 int cpu_arm_exec(CPUARMState *s);
241 void cpu_arm_close(CPUARMState *s);
242 void do_interrupt(CPUARMState *);
243 void switch_mode(CPUARMState *, int);
244 uint32_t do_arm_semihosting(CPUARMState *env);
245
246 /* you can call this signal handler from your SIGBUS and SIGSEGV
247 signal handlers to inform the virtual CPU of exceptions. non zero
248 is returned if the signal was handled by the virtual CPU. */
249 int cpu_arm_signal_handler(int host_signum, void *pinfo,
250 void *puc);
251 int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
252 int mmu_idx);
253 #define cpu_handle_mmu_fault cpu_arm_handle_mmu_fault
254
255 static inline void cpu_set_tls(CPUARMState *env, target_ulong newtls)
256 {
257 env->cp15.c13_tls2 = newtls;
258 }
259
260 #define CPSR_M (0x1f)
261 #define CPSR_T (1 << 5)
262 #define CPSR_F (1 << 6)
263 #define CPSR_I (1 << 7)
264 #define CPSR_A (1 << 8)
265 #define CPSR_E (1 << 9)
266 #define CPSR_IT_2_7 (0xfc00)
267 #define CPSR_GE (0xf << 16)
268 #define CPSR_RESERVED (0xf << 20)
269 #define CPSR_J (1 << 24)
270 #define CPSR_IT_0_1 (3 << 25)
271 #define CPSR_Q (1 << 27)
272 #define CPSR_V (1 << 28)
273 #define CPSR_C (1 << 29)
274 #define CPSR_Z (1 << 30)
275 #define CPSR_N (1 << 31)
276 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
277
278 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
279 #define CACHED_CPSR_BITS (CPSR_T | CPSR_GE | CPSR_IT | CPSR_Q | CPSR_NZCV)
280 /* Bits writable in user mode. */
281 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
282 /* Execution state bits. MRS read as zero, MSR writes ignored. */
283 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J)
284
285 /* Return the current CPSR value. */
286 uint32_t cpsr_read(CPUARMState *env);
287 /* Set the CPSR. Note that some bits of mask must be all-set or all-clear. */
288 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask);
289
290 /* Return the current xPSR value. */
291 static inline uint32_t xpsr_read(CPUARMState *env)
292 {
293 int ZF;
294 ZF = (env->ZF == 0);
295 return (env->NF & 0x80000000) | (ZF << 30)
296 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
297 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
298 | ((env->condexec_bits & 0xfc) << 8)
299 | env->v7m.exception;
300 }
301
302 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */
303 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
304 {
305 if (mask & CPSR_NZCV) {
306 env->ZF = (~val) & CPSR_Z;
307 env->NF = val;
308 env->CF = (val >> 29) & 1;
309 env->VF = (val << 3) & 0x80000000;
310 }
311 if (mask & CPSR_Q)
312 env->QF = ((val & CPSR_Q) != 0);
313 if (mask & (1 << 24))
314 env->thumb = ((val & (1 << 24)) != 0);
315 if (mask & CPSR_IT_0_1) {
316 env->condexec_bits &= ~3;
317 env->condexec_bits |= (val >> 25) & 3;
318 }
319 if (mask & CPSR_IT_2_7) {
320 env->condexec_bits &= 3;
321 env->condexec_bits |= (val >> 8) & 0xfc;
322 }
323 if (mask & 0x1ff) {
324 env->v7m.exception = val & 0x1ff;
325 }
326 }
327
328 /* Return the current FPSCR value. */
329 uint32_t vfp_get_fpscr(CPUARMState *env);
330 void vfp_set_fpscr(CPUARMState *env, uint32_t val);
331
332 enum arm_cpu_mode {
333 ARM_CPU_MODE_USR = 0x10,
334 ARM_CPU_MODE_FIQ = 0x11,
335 ARM_CPU_MODE_IRQ = 0x12,
336 ARM_CPU_MODE_SVC = 0x13,
337 ARM_CPU_MODE_ABT = 0x17,
338 ARM_CPU_MODE_UND = 0x1b,
339 ARM_CPU_MODE_SYS = 0x1f
340 };
341
342 /* VFP system registers. */
343 #define ARM_VFP_FPSID 0
344 #define ARM_VFP_FPSCR 1
345 #define ARM_VFP_MVFR1 6
346 #define ARM_VFP_MVFR0 7
347 #define ARM_VFP_FPEXC 8
348 #define ARM_VFP_FPINST 9
349 #define ARM_VFP_FPINST2 10
350
351 /* iwMMXt coprocessor control registers. */
352 #define ARM_IWMMXT_wCID 0
353 #define ARM_IWMMXT_wCon 1
354 #define ARM_IWMMXT_wCSSF 2
355 #define ARM_IWMMXT_wCASF 3
356 #define ARM_IWMMXT_wCGR0 8
357 #define ARM_IWMMXT_wCGR1 9
358 #define ARM_IWMMXT_wCGR2 10
359 #define ARM_IWMMXT_wCGR3 11
360
361 enum arm_features {
362 ARM_FEATURE_VFP,
363 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */
364 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */
365 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */
366 ARM_FEATURE_V6,
367 ARM_FEATURE_V6K,
368 ARM_FEATURE_V7,
369 ARM_FEATURE_THUMB2,
370 ARM_FEATURE_MPU, /* Only has Memory Protection Unit, not full MMU. */
371 ARM_FEATURE_VFP3,
372 ARM_FEATURE_VFP_FP16,
373 ARM_FEATURE_NEON,
374 ARM_FEATURE_THUMB_DIV, /* divide supported in Thumb encoding */
375 ARM_FEATURE_M, /* Microcontroller profile. */
376 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */
377 ARM_FEATURE_THUMB2EE,
378 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */
379 ARM_FEATURE_V4T,
380 ARM_FEATURE_V5,
381 ARM_FEATURE_STRONGARM,
382 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */
383 ARM_FEATURE_ARM_DIV, /* divide supported in ARM encoding */
384 ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */
385 ARM_FEATURE_GENERIC_TIMER,
386 };
387
388 static inline int arm_feature(CPUARMState *env, int feature)
389 {
390 return (env->features & (1u << feature)) != 0;
391 }
392
393 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf);
394
395 /* Interface between CPU and Interrupt controller. */
396 void armv7m_nvic_set_pending(void *opaque, int irq);
397 int armv7m_nvic_acknowledge_irq(void *opaque);
398 void armv7m_nvic_complete_irq(void *opaque, int irq);
399
400 void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
401 ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write,
402 void *opaque);
403
404 /* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3.
405 Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are
406 conventional cores (ie. Application or Realtime profile). */
407
408 #define IS_M(env) arm_feature(env, ARM_FEATURE_M)
409 #define ARM_CPUID(env) (env->cp15.c0_cpuid)
410
411 #define ARM_CPUID_ARM1026 0x4106a262
412 #define ARM_CPUID_ARM926 0x41069265
413 #define ARM_CPUID_ARM946 0x41059461
414 #define ARM_CPUID_TI915T 0x54029152
415 #define ARM_CPUID_TI925T 0x54029252
416 #define ARM_CPUID_SA1100 0x4401A11B
417 #define ARM_CPUID_SA1110 0x6901B119
418 #define ARM_CPUID_PXA250 0x69052100
419 #define ARM_CPUID_PXA255 0x69052d00
420 #define ARM_CPUID_PXA260 0x69052903
421 #define ARM_CPUID_PXA261 0x69052d05
422 #define ARM_CPUID_PXA262 0x69052d06
423 #define ARM_CPUID_PXA270 0x69054110
424 #define ARM_CPUID_PXA270_A0 0x69054110
425 #define ARM_CPUID_PXA270_A1 0x69054111
426 #define ARM_CPUID_PXA270_B0 0x69054112
427 #define ARM_CPUID_PXA270_B1 0x69054113
428 #define ARM_CPUID_PXA270_C0 0x69054114
429 #define ARM_CPUID_PXA270_C5 0x69054117
430 #define ARM_CPUID_ARM1136 0x4117b363
431 #define ARM_CPUID_ARM1136_R2 0x4107b362
432 #define ARM_CPUID_ARM1176 0x410fb767
433 #define ARM_CPUID_ARM11MPCORE 0x410fb022
434 #define ARM_CPUID_CORTEXA8 0x410fc080
435 #define ARM_CPUID_CORTEXA9 0x410fc090
436 #define ARM_CPUID_CORTEXA15 0x412fc0f1
437 #define ARM_CPUID_CORTEXM3 0x410fc231
438 #define ARM_CPUID_ANY 0xffffffff
439
440 #if defined(CONFIG_USER_ONLY)
441 #define TARGET_PAGE_BITS 12
442 #else
443 /* The ARM MMU allows 1k pages. */
444 /* ??? Linux doesn't actually use these, and they're deprecated in recent
445 architecture revisions. Maybe a configure option to disable them. */
446 #define TARGET_PAGE_BITS 10
447 #endif
448
449 #define TARGET_PHYS_ADDR_SPACE_BITS 32
450 #define TARGET_VIRT_ADDR_SPACE_BITS 32
451
452 #define cpu_init cpu_arm_init
453 #define cpu_exec cpu_arm_exec
454 #define cpu_gen_code cpu_arm_gen_code
455 #define cpu_signal_handler cpu_arm_signal_handler
456 #define cpu_list arm_cpu_list
457
458 #define CPU_SAVE_VERSION 6
459
460 /* MMU modes definitions */
461 #define MMU_MODE0_SUFFIX _kernel
462 #define MMU_MODE1_SUFFIX _user
463 #define MMU_USER_IDX 1
464 static inline int cpu_mmu_index (CPUState *env)
465 {
466 return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0;
467 }
468
469 #if defined(CONFIG_USER_ONLY)
470 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
471 {
472 if (newsp)
473 env->regs[13] = newsp;
474 env->regs[0] = 0;
475 }
476 #endif
477
478 #include "cpu-all.h"
479
480 /* Bit usage in the TB flags field: */
481 #define ARM_TBFLAG_THUMB_SHIFT 0
482 #define ARM_TBFLAG_THUMB_MASK (1 << ARM_TBFLAG_THUMB_SHIFT)
483 #define ARM_TBFLAG_VECLEN_SHIFT 1
484 #define ARM_TBFLAG_VECLEN_MASK (0x7 << ARM_TBFLAG_VECLEN_SHIFT)
485 #define ARM_TBFLAG_VECSTRIDE_SHIFT 4
486 #define ARM_TBFLAG_VECSTRIDE_MASK (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT)
487 #define ARM_TBFLAG_PRIV_SHIFT 6
488 #define ARM_TBFLAG_PRIV_MASK (1 << ARM_TBFLAG_PRIV_SHIFT)
489 #define ARM_TBFLAG_VFPEN_SHIFT 7
490 #define ARM_TBFLAG_VFPEN_MASK (1 << ARM_TBFLAG_VFPEN_SHIFT)
491 #define ARM_TBFLAG_CONDEXEC_SHIFT 8
492 #define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT)
493 /* Bits 31..16 are currently unused. */
494
495 /* some convenience accessor macros */
496 #define ARM_TBFLAG_THUMB(F) \
497 (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT)
498 #define ARM_TBFLAG_VECLEN(F) \
499 (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT)
500 #define ARM_TBFLAG_VECSTRIDE(F) \
501 (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT)
502 #define ARM_TBFLAG_PRIV(F) \
503 (((F) & ARM_TBFLAG_PRIV_MASK) >> ARM_TBFLAG_PRIV_SHIFT)
504 #define ARM_TBFLAG_VFPEN(F) \
505 (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT)
506 #define ARM_TBFLAG_CONDEXEC(F) \
507 (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT)
508
509 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
510 target_ulong *cs_base, int *flags)
511 {
512 int privmode;
513 *pc = env->regs[15];
514 *cs_base = 0;
515 *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT)
516 | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT)
517 | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT)
518 | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT);
519 if (arm_feature(env, ARM_FEATURE_M)) {
520 privmode = !((env->v7m.exception == 0) && (env->v7m.control & 1));
521 } else {
522 privmode = (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR;
523 }
524 if (privmode) {
525 *flags |= ARM_TBFLAG_PRIV_MASK;
526 }
527 if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) {
528 *flags |= ARM_TBFLAG_VFPEN_MASK;
529 }
530 }
531
532 static inline bool cpu_has_work(CPUState *env)
533 {
534 return env->interrupt_request &
535 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
536 }
537
538 #include "exec-all.h"
539
540 static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
541 {
542 env->regs[15] = tb->pc;
543 }
544
545 #endif