qemu-img: Omit error_report() after img_open()
[qemu.git] / target-arm / cpu.h
1 /*
2 * ARM virtual CPU header
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #ifndef CPU_ARM_H
20 #define CPU_ARM_H
21
22 #include "config.h"
23
24 #include "kvm-consts.h"
25
26 #if defined(TARGET_AARCH64)
27 /* AArch64 definitions */
28 # define TARGET_LONG_BITS 64
29 # define ELF_MACHINE EM_AARCH64
30 #else
31 # define TARGET_LONG_BITS 32
32 # define ELF_MACHINE EM_ARM
33 #endif
34
35 #define CPUArchState struct CPUARMState
36
37 #include "qemu-common.h"
38 #include "exec/cpu-defs.h"
39
40 #include "fpu/softfloat.h"
41
42 #define TARGET_HAS_ICE 1
43
44 #define EXCP_UDEF 1 /* undefined instruction */
45 #define EXCP_SWI 2 /* software interrupt */
46 #define EXCP_PREFETCH_ABORT 3
47 #define EXCP_DATA_ABORT 4
48 #define EXCP_IRQ 5
49 #define EXCP_FIQ 6
50 #define EXCP_BKPT 7
51 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */
52 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */
53 #define EXCP_STREX 10
54 #define EXCP_HVC 11 /* HyperVisor Call */
55 #define EXCP_HYP_TRAP 12
56 #define EXCP_SMC 13 /* Secure Monitor Call */
57 #define EXCP_VIRQ 14
58 #define EXCP_VFIQ 15
59
60 #define ARMV7M_EXCP_RESET 1
61 #define ARMV7M_EXCP_NMI 2
62 #define ARMV7M_EXCP_HARD 3
63 #define ARMV7M_EXCP_MEM 4
64 #define ARMV7M_EXCP_BUS 5
65 #define ARMV7M_EXCP_USAGE 6
66 #define ARMV7M_EXCP_SVC 11
67 #define ARMV7M_EXCP_DEBUG 12
68 #define ARMV7M_EXCP_PENDSV 14
69 #define ARMV7M_EXCP_SYSTICK 15
70
71 /* ARM-specific interrupt pending bits. */
72 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1
73 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2
74 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3
75
76 /* The usual mapping for an AArch64 system register to its AArch32
77 * counterpart is for the 32 bit world to have access to the lower
78 * half only (with writes leaving the upper half untouched). It's
79 * therefore useful to be able to pass TCG the offset of the least
80 * significant half of a uint64_t struct member.
81 */
82 #ifdef HOST_WORDS_BIGENDIAN
83 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t))
84 #define offsetofhigh32(S, M) offsetof(S, M)
85 #else
86 #define offsetoflow32(S, M) offsetof(S, M)
87 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t))
88 #endif
89
90 /* Meanings of the ARMCPU object's four inbound GPIO lines */
91 #define ARM_CPU_IRQ 0
92 #define ARM_CPU_FIQ 1
93 #define ARM_CPU_VIRQ 2
94 #define ARM_CPU_VFIQ 3
95
96 typedef void ARMWriteCPFunc(void *opaque, int cp_info,
97 int srcreg, int operand, uint32_t value);
98 typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info,
99 int dstreg, int operand);
100
101 struct arm_boot_info;
102
103 #define NB_MMU_MODES 4
104
105 /* We currently assume float and double are IEEE single and double
106 precision respectively.
107 Doing runtime conversions is tricky because VFP registers may contain
108 integer values (eg. as the result of a FTOSI instruction).
109 s<2n> maps to the least significant half of d<n>
110 s<2n+1> maps to the most significant half of d<n>
111 */
112
113 /* CPU state for each instance of a generic timer (in cp15 c14) */
114 typedef struct ARMGenericTimer {
115 uint64_t cval; /* Timer CompareValue register */
116 uint64_t ctl; /* Timer Control register */
117 } ARMGenericTimer;
118
119 #define GTIMER_PHYS 0
120 #define GTIMER_VIRT 1
121 #define NUM_GTIMERS 2
122
123 typedef struct CPUARMState {
124 /* Regs for current mode. */
125 uint32_t regs[16];
126
127 /* 32/64 switch only happens when taking and returning from
128 * exceptions so the overlap semantics are taken care of then
129 * instead of having a complicated union.
130 */
131 /* Regs for A64 mode. */
132 uint64_t xregs[32];
133 uint64_t pc;
134 /* PSTATE isn't an architectural register for ARMv8. However, it is
135 * convenient for us to assemble the underlying state into a 32 bit format
136 * identical to the architectural format used for the SPSR. (This is also
137 * what the Linux kernel's 'pstate' field in signal handlers and KVM's
138 * 'pstate' register are.) Of the PSTATE bits:
139 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same
140 * semantics as for AArch32, as described in the comments on each field)
141 * nRW (also known as M[4]) is kept, inverted, in env->aarch64
142 * DAIF (exception masks) are kept in env->daif
143 * all other bits are stored in their correct places in env->pstate
144 */
145 uint32_t pstate;
146 uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */
147
148 /* Frequently accessed CPSR bits are stored separately for efficiency.
149 This contains all the other bits. Use cpsr_{read,write} to access
150 the whole CPSR. */
151 uint32_t uncached_cpsr;
152 uint32_t spsr;
153
154 /* Banked registers. */
155 uint64_t banked_spsr[8];
156 uint32_t banked_r13[8];
157 uint32_t banked_r14[8];
158
159 /* These hold r8-r12. */
160 uint32_t usr_regs[5];
161 uint32_t fiq_regs[5];
162
163 /* cpsr flag cache for faster execution */
164 uint32_t CF; /* 0 or 1 */
165 uint32_t VF; /* V is the bit 31. All other bits are undefined */
166 uint32_t NF; /* N is bit 31. All other bits are undefined. */
167 uint32_t ZF; /* Z set if zero. */
168 uint32_t QF; /* 0 or 1 */
169 uint32_t GE; /* cpsr[19:16] */
170 uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
171 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */
172 uint64_t daif; /* exception masks, in the bits they are in in PSTATE */
173
174 uint64_t elr_el[4]; /* AArch64 exception link regs */
175 uint64_t sp_el[4]; /* AArch64 banked stack pointers */
176
177 /* System control coprocessor (cp15) */
178 struct {
179 uint32_t c0_cpuid;
180 uint64_t c0_cssel; /* Cache size selection. */
181 uint64_t c1_sys; /* System control register. */
182 uint64_t c1_coproc; /* Coprocessor access register. */
183 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */
184 uint64_t ttbr0_el1; /* MMU translation table base 0. */
185 uint64_t ttbr1_el1; /* MMU translation table base 1. */
186 uint64_t c2_control; /* MMU translation table base control. */
187 uint32_t c2_mask; /* MMU translation table base selection mask. */
188 uint32_t c2_base_mask; /* MMU translation table base 0 mask. */
189 uint32_t c2_data; /* MPU data cachable bits. */
190 uint32_t c2_insn; /* MPU instruction cachable bits. */
191 uint32_t c3; /* MMU domain access control register
192 MPU write buffer control. */
193 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */
194 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */
195 uint64_t hcr_el2; /* Hypervisor configuration register */
196 uint64_t scr_el3; /* Secure configuration register. */
197 uint32_t ifsr_el2; /* Fault status registers. */
198 uint64_t esr_el[4];
199 uint32_t c6_region[8]; /* MPU base/size registers. */
200 uint64_t far_el[4]; /* Fault address registers. */
201 uint64_t par_el1; /* Translation result. */
202 uint32_t c9_insn; /* Cache lockdown registers. */
203 uint32_t c9_data;
204 uint64_t c9_pmcr; /* performance monitor control register */
205 uint64_t c9_pmcnten; /* perf monitor counter enables */
206 uint32_t c9_pmovsr; /* perf monitor overflow status */
207 uint32_t c9_pmxevtyper; /* perf monitor event type */
208 uint32_t c9_pmuserenr; /* perf monitor user enable */
209 uint32_t c9_pminten; /* perf monitor interrupt enables */
210 uint64_t mair_el1;
211 uint64_t vbar_el[4]; /* vector base address register */
212 uint32_t c13_fcse; /* FCSE PID. */
213 uint64_t contextidr_el1; /* Context ID. */
214 uint64_t tpidr_el0; /* User RW Thread register. */
215 uint64_t tpidrro_el0; /* User RO Thread register. */
216 uint64_t tpidr_el1; /* Privileged Thread register. */
217 uint64_t c14_cntfrq; /* Counter Frequency register */
218 uint64_t c14_cntkctl; /* Timer Control register */
219 ARMGenericTimer c14_timer[NUM_GTIMERS];
220 uint32_t c15_cpar; /* XScale Coprocessor Access Register */
221 uint32_t c15_ticonfig; /* TI925T configuration byte. */
222 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */
223 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */
224 uint32_t c15_threadid; /* TI debugger thread-ID. */
225 uint32_t c15_config_base_address; /* SCU base address. */
226 uint32_t c15_diagnostic; /* diagnostic register */
227 uint32_t c15_power_diagnostic;
228 uint32_t c15_power_control; /* power control */
229 uint64_t dbgbvr[16]; /* breakpoint value registers */
230 uint64_t dbgbcr[16]; /* breakpoint control registers */
231 uint64_t dbgwvr[16]; /* watchpoint value registers */
232 uint64_t dbgwcr[16]; /* watchpoint control registers */
233 uint64_t mdscr_el1;
234 /* If the counter is enabled, this stores the last time the counter
235 * was reset. Otherwise it stores the counter value
236 */
237 uint64_t c15_ccnt;
238 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */
239 } cp15;
240
241 struct {
242 uint32_t other_sp;
243 uint32_t vecbase;
244 uint32_t basepri;
245 uint32_t control;
246 int current_sp;
247 int exception;
248 int pending_exception;
249 } v7m;
250
251 /* Information associated with an exception about to be taken:
252 * code which raises an exception must set cs->exception_index and
253 * the relevant parts of this structure; the cpu_do_interrupt function
254 * will then set the guest-visible registers as part of the exception
255 * entry process.
256 */
257 struct {
258 uint32_t syndrome; /* AArch64 format syndrome register */
259 uint32_t fsr; /* AArch32 format fault status register info */
260 uint64_t vaddress; /* virtual addr associated with exception, if any */
261 /* If we implement EL2 we will also need to store information
262 * about the intermediate physical address for stage 2 faults.
263 */
264 } exception;
265
266 /* Thumb-2 EE state. */
267 uint32_t teecr;
268 uint32_t teehbr;
269
270 /* VFP coprocessor state. */
271 struct {
272 /* VFP/Neon register state. Note that the mapping between S, D and Q
273 * views of the register bank differs between AArch64 and AArch32:
274 * In AArch32:
275 * Qn = regs[2n+1]:regs[2n]
276 * Dn = regs[n]
277 * Sn = regs[n/2] bits 31..0 for even n, and bits 63..32 for odd n
278 * (and regs[32] to regs[63] are inaccessible)
279 * In AArch64:
280 * Qn = regs[2n+1]:regs[2n]
281 * Dn = regs[2n]
282 * Sn = regs[2n] bits 31..0
283 * This corresponds to the architecturally defined mapping between
284 * the two execution states, and means we do not need to explicitly
285 * map these registers when changing states.
286 */
287 float64 regs[64];
288
289 uint32_t xregs[16];
290 /* We store these fpcsr fields separately for convenience. */
291 int vec_len;
292 int vec_stride;
293
294 /* scratch space when Tn are not sufficient. */
295 uint32_t scratch[8];
296
297 /* fp_status is the "normal" fp status. standard_fp_status retains
298 * values corresponding to the ARM "Standard FPSCR Value", ie
299 * default-NaN, flush-to-zero, round-to-nearest and is used by
300 * any operations (generally Neon) which the architecture defines
301 * as controlled by the standard FPSCR value rather than the FPSCR.
302 *
303 * To avoid having to transfer exception bits around, we simply
304 * say that the FPSCR cumulative exception flags are the logical
305 * OR of the flags in the two fp statuses. This relies on the
306 * only thing which needs to read the exception flags being
307 * an explicit FPSCR read.
308 */
309 float_status fp_status;
310 float_status standard_fp_status;
311 } vfp;
312 uint64_t exclusive_addr;
313 uint64_t exclusive_val;
314 uint64_t exclusive_high;
315 #if defined(CONFIG_USER_ONLY)
316 uint64_t exclusive_test;
317 uint32_t exclusive_info;
318 #endif
319
320 /* iwMMXt coprocessor state. */
321 struct {
322 uint64_t regs[16];
323 uint64_t val;
324
325 uint32_t cregs[16];
326 } iwmmxt;
327
328 /* For mixed endian mode. */
329 bool bswap_code;
330
331 #if defined(CONFIG_USER_ONLY)
332 /* For usermode syscall translation. */
333 int eabi;
334 #endif
335
336 struct CPUBreakpoint *cpu_breakpoint[16];
337 struct CPUWatchpoint *cpu_watchpoint[16];
338
339 CPU_COMMON
340
341 /* These fields after the common ones so they are preserved on reset. */
342
343 /* Internal CPU feature flags. */
344 uint64_t features;
345
346 void *nvic;
347 const struct arm_boot_info *boot_info;
348 } CPUARMState;
349
350 #include "cpu-qom.h"
351
352 ARMCPU *cpu_arm_init(const char *cpu_model);
353 int cpu_arm_exec(CPUARMState *s);
354 uint32_t do_arm_semihosting(CPUARMState *env);
355
356 static inline bool is_a64(CPUARMState *env)
357 {
358 return env->aarch64;
359 }
360
361 /* you can call this signal handler from your SIGBUS and SIGSEGV
362 signal handlers to inform the virtual CPU of exceptions. non zero
363 is returned if the signal was handled by the virtual CPU. */
364 int cpu_arm_signal_handler(int host_signum, void *pinfo,
365 void *puc);
366 int arm_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
367 int mmu_idx);
368
369 /**
370 * pmccntr_sync
371 * @env: CPUARMState
372 *
373 * Synchronises the counter in the PMCCNTR. This must always be called twice,
374 * once before any action that might affect the timer and again afterwards.
375 * The function is used to swap the state of the register if required.
376 * This only happens when not in user mode (!CONFIG_USER_ONLY)
377 */
378 void pmccntr_sync(CPUARMState *env);
379
380 /* SCTLR bit meanings. Several bits have been reused in newer
381 * versions of the architecture; in that case we define constants
382 * for both old and new bit meanings. Code which tests against those
383 * bits should probably check or otherwise arrange that the CPU
384 * is the architectural version it expects.
385 */
386 #define SCTLR_M (1U << 0)
387 #define SCTLR_A (1U << 1)
388 #define SCTLR_C (1U << 2)
389 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */
390 #define SCTLR_SA (1U << 3)
391 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */
392 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */
393 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */
394 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */
395 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */
396 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */
397 #define SCTLR_ITD (1U << 7) /* v8 onward */
398 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */
399 #define SCTLR_SED (1U << 8) /* v8 onward */
400 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */
401 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */
402 #define SCTLR_F (1U << 10) /* up to v6 */
403 #define SCTLR_SW (1U << 10) /* v7 onward */
404 #define SCTLR_Z (1U << 11)
405 #define SCTLR_I (1U << 12)
406 #define SCTLR_V (1U << 13)
407 #define SCTLR_RR (1U << 14) /* up to v7 */
408 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */
409 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */
410 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */
411 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */
412 #define SCTLR_nTWI (1U << 16) /* v8 onward */
413 #define SCTLR_HA (1U << 17)
414 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */
415 #define SCTLR_nTWE (1U << 18) /* v8 onward */
416 #define SCTLR_WXN (1U << 19)
417 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */
418 #define SCTLR_UWXN (1U << 20) /* v7 onward */
419 #define SCTLR_FI (1U << 21)
420 #define SCTLR_U (1U << 22)
421 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */
422 #define SCTLR_VE (1U << 24) /* up to v7 */
423 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */
424 #define SCTLR_EE (1U << 25)
425 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */
426 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */
427 #define SCTLR_NMFI (1U << 27)
428 #define SCTLR_TRE (1U << 28)
429 #define SCTLR_AFE (1U << 29)
430 #define SCTLR_TE (1U << 30)
431
432 #define CPSR_M (0x1fU)
433 #define CPSR_T (1U << 5)
434 #define CPSR_F (1U << 6)
435 #define CPSR_I (1U << 7)
436 #define CPSR_A (1U << 8)
437 #define CPSR_E (1U << 9)
438 #define CPSR_IT_2_7 (0xfc00U)
439 #define CPSR_GE (0xfU << 16)
440 #define CPSR_IL (1U << 20)
441 /* Note that the RESERVED bits include bit 21, which is PSTATE_SS in
442 * an AArch64 SPSR but RES0 in AArch32 SPSR and CPSR. In QEMU we use
443 * env->uncached_cpsr bit 21 to store PSTATE.SS when executing in AArch32,
444 * where it is live state but not accessible to the AArch32 code.
445 */
446 #define CPSR_RESERVED (0x7U << 21)
447 #define CPSR_J (1U << 24)
448 #define CPSR_IT_0_1 (3U << 25)
449 #define CPSR_Q (1U << 27)
450 #define CPSR_V (1U << 28)
451 #define CPSR_C (1U << 29)
452 #define CPSR_Z (1U << 30)
453 #define CPSR_N (1U << 31)
454 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
455 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F)
456
457 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
458 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
459 | CPSR_NZCV)
460 /* Bits writable in user mode. */
461 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
462 /* Execution state bits. MRS read as zero, MSR writes ignored. */
463 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL)
464 /* Mask of bits which may be set by exception return copying them from SPSR */
465 #define CPSR_ERET_MASK (~CPSR_RESERVED)
466
467 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */
468 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */
469 #define TTBCR_PD0 (1U << 4)
470 #define TTBCR_PD1 (1U << 5)
471 #define TTBCR_EPD0 (1U << 7)
472 #define TTBCR_IRGN0 (3U << 8)
473 #define TTBCR_ORGN0 (3U << 10)
474 #define TTBCR_SH0 (3U << 12)
475 #define TTBCR_T1SZ (3U << 16)
476 #define TTBCR_A1 (1U << 22)
477 #define TTBCR_EPD1 (1U << 23)
478 #define TTBCR_IRGN1 (3U << 24)
479 #define TTBCR_ORGN1 (3U << 26)
480 #define TTBCR_SH1 (1U << 28)
481 #define TTBCR_EAE (1U << 31)
482
483 /* Bit definitions for ARMv8 SPSR (PSTATE) format.
484 * Only these are valid when in AArch64 mode; in
485 * AArch32 mode SPSRs are basically CPSR-format.
486 */
487 #define PSTATE_SP (1U)
488 #define PSTATE_M (0xFU)
489 #define PSTATE_nRW (1U << 4)
490 #define PSTATE_F (1U << 6)
491 #define PSTATE_I (1U << 7)
492 #define PSTATE_A (1U << 8)
493 #define PSTATE_D (1U << 9)
494 #define PSTATE_IL (1U << 20)
495 #define PSTATE_SS (1U << 21)
496 #define PSTATE_V (1U << 28)
497 #define PSTATE_C (1U << 29)
498 #define PSTATE_Z (1U << 30)
499 #define PSTATE_N (1U << 31)
500 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V)
501 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F)
502 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF)
503 /* Mode values for AArch64 */
504 #define PSTATE_MODE_EL3h 13
505 #define PSTATE_MODE_EL3t 12
506 #define PSTATE_MODE_EL2h 9
507 #define PSTATE_MODE_EL2t 8
508 #define PSTATE_MODE_EL1h 5
509 #define PSTATE_MODE_EL1t 4
510 #define PSTATE_MODE_EL0t 0
511
512 /* Map EL and handler into a PSTATE_MODE. */
513 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler)
514 {
515 return (el << 2) | handler;
516 }
517
518 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit
519 * interprocessing, so we don't attempt to sync with the cpsr state used by
520 * the 32 bit decoder.
521 */
522 static inline uint32_t pstate_read(CPUARMState *env)
523 {
524 int ZF;
525
526 ZF = (env->ZF == 0);
527 return (env->NF & 0x80000000) | (ZF << 30)
528 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3)
529 | env->pstate | env->daif;
530 }
531
532 static inline void pstate_write(CPUARMState *env, uint32_t val)
533 {
534 env->ZF = (~val) & PSTATE_Z;
535 env->NF = val;
536 env->CF = (val >> 29) & 1;
537 env->VF = (val << 3) & 0x80000000;
538 env->daif = val & PSTATE_DAIF;
539 env->pstate = val & ~CACHED_PSTATE_BITS;
540 }
541
542 /* Return the current CPSR value. */
543 uint32_t cpsr_read(CPUARMState *env);
544 /* Set the CPSR. Note that some bits of mask must be all-set or all-clear. */
545 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask);
546
547 /* Return the current xPSR value. */
548 static inline uint32_t xpsr_read(CPUARMState *env)
549 {
550 int ZF;
551 ZF = (env->ZF == 0);
552 return (env->NF & 0x80000000) | (ZF << 30)
553 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
554 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
555 | ((env->condexec_bits & 0xfc) << 8)
556 | env->v7m.exception;
557 }
558
559 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */
560 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
561 {
562 if (mask & CPSR_NZCV) {
563 env->ZF = (~val) & CPSR_Z;
564 env->NF = val;
565 env->CF = (val >> 29) & 1;
566 env->VF = (val << 3) & 0x80000000;
567 }
568 if (mask & CPSR_Q)
569 env->QF = ((val & CPSR_Q) != 0);
570 if (mask & (1 << 24))
571 env->thumb = ((val & (1 << 24)) != 0);
572 if (mask & CPSR_IT_0_1) {
573 env->condexec_bits &= ~3;
574 env->condexec_bits |= (val >> 25) & 3;
575 }
576 if (mask & CPSR_IT_2_7) {
577 env->condexec_bits &= 3;
578 env->condexec_bits |= (val >> 8) & 0xfc;
579 }
580 if (mask & 0x1ff) {
581 env->v7m.exception = val & 0x1ff;
582 }
583 }
584
585 #define HCR_VM (1ULL << 0)
586 #define HCR_SWIO (1ULL << 1)
587 #define HCR_PTW (1ULL << 2)
588 #define HCR_FMO (1ULL << 3)
589 #define HCR_IMO (1ULL << 4)
590 #define HCR_AMO (1ULL << 5)
591 #define HCR_VF (1ULL << 6)
592 #define HCR_VI (1ULL << 7)
593 #define HCR_VSE (1ULL << 8)
594 #define HCR_FB (1ULL << 9)
595 #define HCR_BSU_MASK (3ULL << 10)
596 #define HCR_DC (1ULL << 12)
597 #define HCR_TWI (1ULL << 13)
598 #define HCR_TWE (1ULL << 14)
599 #define HCR_TID0 (1ULL << 15)
600 #define HCR_TID1 (1ULL << 16)
601 #define HCR_TID2 (1ULL << 17)
602 #define HCR_TID3 (1ULL << 18)
603 #define HCR_TSC (1ULL << 19)
604 #define HCR_TIDCP (1ULL << 20)
605 #define HCR_TACR (1ULL << 21)
606 #define HCR_TSW (1ULL << 22)
607 #define HCR_TPC (1ULL << 23)
608 #define HCR_TPU (1ULL << 24)
609 #define HCR_TTLB (1ULL << 25)
610 #define HCR_TVM (1ULL << 26)
611 #define HCR_TGE (1ULL << 27)
612 #define HCR_TDZ (1ULL << 28)
613 #define HCR_HCD (1ULL << 29)
614 #define HCR_TRVM (1ULL << 30)
615 #define HCR_RW (1ULL << 31)
616 #define HCR_CD (1ULL << 32)
617 #define HCR_ID (1ULL << 33)
618 #define HCR_MASK ((1ULL << 34) - 1)
619
620 #define SCR_NS (1U << 0)
621 #define SCR_IRQ (1U << 1)
622 #define SCR_FIQ (1U << 2)
623 #define SCR_EA (1U << 3)
624 #define SCR_FW (1U << 4)
625 #define SCR_AW (1U << 5)
626 #define SCR_NET (1U << 6)
627 #define SCR_SMD (1U << 7)
628 #define SCR_HCE (1U << 8)
629 #define SCR_SIF (1U << 9)
630 #define SCR_RW (1U << 10)
631 #define SCR_ST (1U << 11)
632 #define SCR_TWI (1U << 12)
633 #define SCR_TWE (1U << 13)
634 #define SCR_AARCH32_MASK (0x3fff & ~(SCR_RW | SCR_ST))
635 #define SCR_AARCH64_MASK (0x3fff & ~SCR_NET)
636
637 /* Return the current FPSCR value. */
638 uint32_t vfp_get_fpscr(CPUARMState *env);
639 void vfp_set_fpscr(CPUARMState *env, uint32_t val);
640
641 /* For A64 the FPSCR is split into two logically distinct registers,
642 * FPCR and FPSR. However since they still use non-overlapping bits
643 * we store the underlying state in fpscr and just mask on read/write.
644 */
645 #define FPSR_MASK 0xf800009f
646 #define FPCR_MASK 0x07f79f00
647 static inline uint32_t vfp_get_fpsr(CPUARMState *env)
648 {
649 return vfp_get_fpscr(env) & FPSR_MASK;
650 }
651
652 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val)
653 {
654 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK);
655 vfp_set_fpscr(env, new_fpscr);
656 }
657
658 static inline uint32_t vfp_get_fpcr(CPUARMState *env)
659 {
660 return vfp_get_fpscr(env) & FPCR_MASK;
661 }
662
663 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val)
664 {
665 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK);
666 vfp_set_fpscr(env, new_fpscr);
667 }
668
669 enum arm_cpu_mode {
670 ARM_CPU_MODE_USR = 0x10,
671 ARM_CPU_MODE_FIQ = 0x11,
672 ARM_CPU_MODE_IRQ = 0x12,
673 ARM_CPU_MODE_SVC = 0x13,
674 ARM_CPU_MODE_MON = 0x16,
675 ARM_CPU_MODE_ABT = 0x17,
676 ARM_CPU_MODE_HYP = 0x1a,
677 ARM_CPU_MODE_UND = 0x1b,
678 ARM_CPU_MODE_SYS = 0x1f
679 };
680
681 /* VFP system registers. */
682 #define ARM_VFP_FPSID 0
683 #define ARM_VFP_FPSCR 1
684 #define ARM_VFP_MVFR2 5
685 #define ARM_VFP_MVFR1 6
686 #define ARM_VFP_MVFR0 7
687 #define ARM_VFP_FPEXC 8
688 #define ARM_VFP_FPINST 9
689 #define ARM_VFP_FPINST2 10
690
691 /* iwMMXt coprocessor control registers. */
692 #define ARM_IWMMXT_wCID 0
693 #define ARM_IWMMXT_wCon 1
694 #define ARM_IWMMXT_wCSSF 2
695 #define ARM_IWMMXT_wCASF 3
696 #define ARM_IWMMXT_wCGR0 8
697 #define ARM_IWMMXT_wCGR1 9
698 #define ARM_IWMMXT_wCGR2 10
699 #define ARM_IWMMXT_wCGR3 11
700
701 /* If adding a feature bit which corresponds to a Linux ELF
702 * HWCAP bit, remember to update the feature-bit-to-hwcap
703 * mapping in linux-user/elfload.c:get_elf_hwcap().
704 */
705 enum arm_features {
706 ARM_FEATURE_VFP,
707 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */
708 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */
709 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */
710 ARM_FEATURE_V6,
711 ARM_FEATURE_V6K,
712 ARM_FEATURE_V7,
713 ARM_FEATURE_THUMB2,
714 ARM_FEATURE_MPU, /* Only has Memory Protection Unit, not full MMU. */
715 ARM_FEATURE_VFP3,
716 ARM_FEATURE_VFP_FP16,
717 ARM_FEATURE_NEON,
718 ARM_FEATURE_THUMB_DIV, /* divide supported in Thumb encoding */
719 ARM_FEATURE_M, /* Microcontroller profile. */
720 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */
721 ARM_FEATURE_THUMB2EE,
722 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */
723 ARM_FEATURE_V4T,
724 ARM_FEATURE_V5,
725 ARM_FEATURE_STRONGARM,
726 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */
727 ARM_FEATURE_ARM_DIV, /* divide supported in ARM encoding */
728 ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */
729 ARM_FEATURE_GENERIC_TIMER,
730 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */
731 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */
732 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */
733 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */
734 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */
735 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */
736 ARM_FEATURE_PXN, /* has Privileged Execute Never bit */
737 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */
738 ARM_FEATURE_V8,
739 ARM_FEATURE_AARCH64, /* supports 64 bit mode */
740 ARM_FEATURE_V8_AES, /* implements AES part of v8 Crypto Extensions */
741 ARM_FEATURE_CBAR, /* has cp15 CBAR */
742 ARM_FEATURE_CRC, /* ARMv8 CRC instructions */
743 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */
744 ARM_FEATURE_EL2, /* has EL2 Virtualization support */
745 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */
746 ARM_FEATURE_V8_SHA1, /* implements SHA1 part of v8 Crypto Extensions */
747 ARM_FEATURE_V8_SHA256, /* implements SHA256 part of v8 Crypto Extensions */
748 ARM_FEATURE_V8_PMULL, /* implements PMULL part of v8 Crypto Extensions */
749 };
750
751 static inline int arm_feature(CPUARMState *env, int feature)
752 {
753 return (env->features & (1ULL << feature)) != 0;
754 }
755
756 #if !defined(CONFIG_USER_ONLY)
757 /* Return true if exception levels below EL3 are in secure state,
758 * or would be following an exception return to that level.
759 * Unlike arm_is_secure() (which is always a question about the
760 * _current_ state of the CPU) this doesn't care about the current
761 * EL or mode.
762 */
763 static inline bool arm_is_secure_below_el3(CPUARMState *env)
764 {
765 if (arm_feature(env, ARM_FEATURE_EL3)) {
766 return !(env->cp15.scr_el3 & SCR_NS);
767 } else {
768 /* If EL2 is not supported then the secure state is implementation
769 * defined, in which case QEMU defaults to non-secure.
770 */
771 return false;
772 }
773 }
774
775 /* Return true if the processor is in secure state */
776 static inline bool arm_is_secure(CPUARMState *env)
777 {
778 if (arm_feature(env, ARM_FEATURE_EL3)) {
779 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) {
780 /* CPU currently in AArch64 state and EL3 */
781 return true;
782 } else if (!is_a64(env) &&
783 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
784 /* CPU currently in AArch32 state and monitor mode */
785 return true;
786 }
787 }
788 return arm_is_secure_below_el3(env);
789 }
790
791 #else
792 static inline bool arm_is_secure_below_el3(CPUARMState *env)
793 {
794 return false;
795 }
796
797 static inline bool arm_is_secure(CPUARMState *env)
798 {
799 return false;
800 }
801 #endif
802
803 /* Return true if the specified exception level is running in AArch64 state. */
804 static inline bool arm_el_is_aa64(CPUARMState *env, int el)
805 {
806 /* We don't currently support EL2, and this isn't valid for EL0
807 * (if we're in EL0, is_a64() is what you want, and if we're not in EL0
808 * then the state of EL0 isn't well defined.)
809 */
810 assert(el == 1 || el == 3);
811
812 /* AArch64-capable CPUs always run with EL1 in AArch64 mode. This
813 * is a QEMU-imposed simplification which we may wish to change later.
814 * If we in future support EL2 and/or EL3, then the state of lower
815 * exception levels is controlled by the HCR.RW and SCR.RW bits.
816 */
817 return arm_feature(env, ARM_FEATURE_AARCH64);
818 }
819
820 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf);
821 unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx);
822
823 /* Interface between CPU and Interrupt controller. */
824 void armv7m_nvic_set_pending(void *opaque, int irq);
825 int armv7m_nvic_acknowledge_irq(void *opaque);
826 void armv7m_nvic_complete_irq(void *opaque, int irq);
827
828 /* Interface for defining coprocessor registers.
829 * Registers are defined in tables of arm_cp_reginfo structs
830 * which are passed to define_arm_cp_regs().
831 */
832
833 /* When looking up a coprocessor register we look for it
834 * via an integer which encodes all of:
835 * coprocessor number
836 * Crn, Crm, opc1, opc2 fields
837 * 32 or 64 bit register (ie is it accessed via MRC/MCR
838 * or via MRRC/MCRR?)
839 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field.
840 * (In this case crn and opc2 should be zero.)
841 * For AArch64, there is no 32/64 bit size distinction;
842 * instead all registers have a 2 bit op0, 3 bit op1 and op2,
843 * and 4 bit CRn and CRm. The encoding patterns are chosen
844 * to be easy to convert to and from the KVM encodings, and also
845 * so that the hashtable can contain both AArch32 and AArch64
846 * registers (to allow for interprocessing where we might run
847 * 32 bit code on a 64 bit core).
848 */
849 /* This bit is private to our hashtable cpreg; in KVM register
850 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64
851 * in the upper bits of the 64 bit ID.
852 */
853 #define CP_REG_AA64_SHIFT 28
854 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT)
855
856 #define ENCODE_CP_REG(cp, is64, crn, crm, opc1, opc2) \
857 (((cp) << 16) | ((is64) << 15) | ((crn) << 11) | \
858 ((crm) << 7) | ((opc1) << 3) | (opc2))
859
860 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \
861 (CP_REG_AA64_MASK | \
862 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \
863 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \
864 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \
865 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \
866 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \
867 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
868
869 /* Convert a full 64 bit KVM register ID to the truncated 32 bit
870 * version used as a key for the coprocessor register hashtable
871 */
872 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid)
873 {
874 uint32_t cpregid = kvmid;
875 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) {
876 cpregid |= CP_REG_AA64_MASK;
877 } else if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) {
878 cpregid |= (1 << 15);
879 }
880 return cpregid;
881 }
882
883 /* Convert a truncated 32 bit hashtable key into the full
884 * 64 bit KVM register ID.
885 */
886 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
887 {
888 uint64_t kvmid;
889
890 if (cpregid & CP_REG_AA64_MASK) {
891 kvmid = cpregid & ~CP_REG_AA64_MASK;
892 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64;
893 } else {
894 kvmid = cpregid & ~(1 << 15);
895 if (cpregid & (1 << 15)) {
896 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM;
897 } else {
898 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM;
899 }
900 }
901 return kvmid;
902 }
903
904 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a
905 * special-behaviour cp reg and bits [15..8] indicate what behaviour
906 * it has. Otherwise it is a simple cp reg, where CONST indicates that
907 * TCG can assume the value to be constant (ie load at translate time)
908 * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END
909 * indicates that the TB should not be ended after a write to this register
910 * (the default is that the TB ends after cp writes). OVERRIDE permits
911 * a register definition to override a previous definition for the
912 * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the
913 * old must have the OVERRIDE bit set.
914 * NO_MIGRATE indicates that this register should be ignored for migration;
915 * (eg because any state is accessed via some other coprocessor register).
916 * IO indicates that this register does I/O and therefore its accesses
917 * need to be surrounded by gen_io_start()/gen_io_end(). In particular,
918 * registers which implement clocks or timers require this.
919 */
920 #define ARM_CP_SPECIAL 1
921 #define ARM_CP_CONST 2
922 #define ARM_CP_64BIT 4
923 #define ARM_CP_SUPPRESS_TB_END 8
924 #define ARM_CP_OVERRIDE 16
925 #define ARM_CP_NO_MIGRATE 32
926 #define ARM_CP_IO 64
927 #define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8))
928 #define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8))
929 #define ARM_CP_NZCV (ARM_CP_SPECIAL | (3 << 8))
930 #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | (4 << 8))
931 #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | (5 << 8))
932 #define ARM_LAST_SPECIAL ARM_CP_DC_ZVA
933 /* Used only as a terminator for ARMCPRegInfo lists */
934 #define ARM_CP_SENTINEL 0xffff
935 /* Mask of only the flag bits in a type field */
936 #define ARM_CP_FLAG_MASK 0x7f
937
938 /* Valid values for ARMCPRegInfo state field, indicating which of
939 * the AArch32 and AArch64 execution states this register is visible in.
940 * If the reginfo doesn't explicitly specify then it is AArch32 only.
941 * If the reginfo is declared to be visible in both states then a second
942 * reginfo is synthesised for the AArch32 view of the AArch64 register,
943 * such that the AArch32 view is the lower 32 bits of the AArch64 one.
944 * Note that we rely on the values of these enums as we iterate through
945 * the various states in some places.
946 */
947 enum {
948 ARM_CP_STATE_AA32 = 0,
949 ARM_CP_STATE_AA64 = 1,
950 ARM_CP_STATE_BOTH = 2,
951 };
952
953 /* Return true if cptype is a valid type field. This is used to try to
954 * catch errors where the sentinel has been accidentally left off the end
955 * of a list of registers.
956 */
957 static inline bool cptype_valid(int cptype)
958 {
959 return ((cptype & ~ARM_CP_FLAG_MASK) == 0)
960 || ((cptype & ARM_CP_SPECIAL) &&
961 ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL));
962 }
963
964 /* Access rights:
965 * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM
966 * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and
967 * PL2 (hyp). The other level which has Read and Write bits is Secure PL1
968 * (ie any of the privileged modes in Secure state, or Monitor mode).
969 * If a register is accessible in one privilege level it's always accessible
970 * in higher privilege levels too. Since "Secure PL1" also follows this rule
971 * (ie anything visible in PL2 is visible in S-PL1, some things are only
972 * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the
973 * terminology a little and call this PL3.
974 * In AArch64 things are somewhat simpler as the PLx bits line up exactly
975 * with the ELx exception levels.
976 *
977 * If access permissions for a register are more complex than can be
978 * described with these bits, then use a laxer set of restrictions, and
979 * do the more restrictive/complex check inside a helper function.
980 */
981 #define PL3_R 0x80
982 #define PL3_W 0x40
983 #define PL2_R (0x20 | PL3_R)
984 #define PL2_W (0x10 | PL3_W)
985 #define PL1_R (0x08 | PL2_R)
986 #define PL1_W (0x04 | PL2_W)
987 #define PL0_R (0x02 | PL1_R)
988 #define PL0_W (0x01 | PL1_W)
989
990 #define PL3_RW (PL3_R | PL3_W)
991 #define PL2_RW (PL2_R | PL2_W)
992 #define PL1_RW (PL1_R | PL1_W)
993 #define PL0_RW (PL0_R | PL0_W)
994
995 /* Return the current Exception Level (as per ARMv8; note that this differs
996 * from the ARMv7 Privilege Level).
997 */
998 static inline int arm_current_el(CPUARMState *env)
999 {
1000 if (is_a64(env)) {
1001 return extract32(env->pstate, 2, 2);
1002 }
1003
1004 switch (env->uncached_cpsr & 0x1f) {
1005 case ARM_CPU_MODE_USR:
1006 return 0;
1007 case ARM_CPU_MODE_HYP:
1008 return 2;
1009 case ARM_CPU_MODE_MON:
1010 return 3;
1011 default:
1012 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) {
1013 /* If EL3 is 32-bit then all secure privileged modes run in
1014 * EL3
1015 */
1016 return 3;
1017 }
1018
1019 return 1;
1020 }
1021 }
1022
1023 typedef struct ARMCPRegInfo ARMCPRegInfo;
1024
1025 typedef enum CPAccessResult {
1026 /* Access is permitted */
1027 CP_ACCESS_OK = 0,
1028 /* Access fails due to a configurable trap or enable which would
1029 * result in a categorized exception syndrome giving information about
1030 * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6,
1031 * 0xc or 0x18).
1032 */
1033 CP_ACCESS_TRAP = 1,
1034 /* Access fails and results in an exception syndrome 0x0 ("uncategorized").
1035 * Note that this is not a catch-all case -- the set of cases which may
1036 * result in this failure is specifically defined by the architecture.
1037 */
1038 CP_ACCESS_TRAP_UNCATEGORIZED = 2,
1039 } CPAccessResult;
1040
1041 /* Access functions for coprocessor registers. These cannot fail and
1042 * may not raise exceptions.
1043 */
1044 typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque);
1045 typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque,
1046 uint64_t value);
1047 /* Access permission check functions for coprocessor registers. */
1048 typedef CPAccessResult CPAccessFn(CPUARMState *env, const ARMCPRegInfo *opaque);
1049 /* Hook function for register reset */
1050 typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque);
1051
1052 #define CP_ANY 0xff
1053
1054 /* Definition of an ARM coprocessor register */
1055 struct ARMCPRegInfo {
1056 /* Name of register (useful mainly for debugging, need not be unique) */
1057 const char *name;
1058 /* Location of register: coprocessor number and (crn,crm,opc1,opc2)
1059 * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a
1060 * 'wildcard' field -- any value of that field in the MRC/MCR insn
1061 * will be decoded to this register. The register read and write
1062 * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2
1063 * used by the program, so it is possible to register a wildcard and
1064 * then behave differently on read/write if necessary.
1065 * For 64 bit registers, only crm and opc1 are relevant; crn and opc2
1066 * must both be zero.
1067 * For AArch64-visible registers, opc0 is also used.
1068 * Since there are no "coprocessors" in AArch64, cp is purely used as a
1069 * way to distinguish (for KVM's benefit) guest-visible system registers
1070 * from demuxed ones provided to preserve the "no side effects on
1071 * KVM register read/write from QEMU" semantics. cp==0x13 is guest
1072 * visible (to match KVM's encoding); cp==0 will be converted to
1073 * cp==0x13 when the ARMCPRegInfo is registered, for convenience.
1074 */
1075 uint8_t cp;
1076 uint8_t crn;
1077 uint8_t crm;
1078 uint8_t opc0;
1079 uint8_t opc1;
1080 uint8_t opc2;
1081 /* Execution state in which this register is visible: ARM_CP_STATE_* */
1082 int state;
1083 /* Register type: ARM_CP_* bits/values */
1084 int type;
1085 /* Access rights: PL*_[RW] */
1086 int access;
1087 /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when
1088 * this register was defined: can be used to hand data through to the
1089 * register read/write functions, since they are passed the ARMCPRegInfo*.
1090 */
1091 void *opaque;
1092 /* Value of this register, if it is ARM_CP_CONST. Otherwise, if
1093 * fieldoffset is non-zero, the reset value of the register.
1094 */
1095 uint64_t resetvalue;
1096 /* Offset of the field in CPUARMState for this register. This is not
1097 * needed if either:
1098 * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs
1099 * 2. both readfn and writefn are specified
1100 */
1101 ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */
1102 /* Function for making any access checks for this register in addition to
1103 * those specified by the 'access' permissions bits. If NULL, no extra
1104 * checks required. The access check is performed at runtime, not at
1105 * translate time.
1106 */
1107 CPAccessFn *accessfn;
1108 /* Function for handling reads of this register. If NULL, then reads
1109 * will be done by loading from the offset into CPUARMState specified
1110 * by fieldoffset.
1111 */
1112 CPReadFn *readfn;
1113 /* Function for handling writes of this register. If NULL, then writes
1114 * will be done by writing to the offset into CPUARMState specified
1115 * by fieldoffset.
1116 */
1117 CPWriteFn *writefn;
1118 /* Function for doing a "raw" read; used when we need to copy
1119 * coprocessor state to the kernel for KVM or out for
1120 * migration. This only needs to be provided if there is also a
1121 * readfn and it has side effects (for instance clear-on-read bits).
1122 */
1123 CPReadFn *raw_readfn;
1124 /* Function for doing a "raw" write; used when we need to copy KVM
1125 * kernel coprocessor state into userspace, or for inbound
1126 * migration. This only needs to be provided if there is also a
1127 * writefn and it masks out "unwritable" bits or has write-one-to-clear
1128 * or similar behaviour.
1129 */
1130 CPWriteFn *raw_writefn;
1131 /* Function for resetting the register. If NULL, then reset will be done
1132 * by writing resetvalue to the field specified in fieldoffset. If
1133 * fieldoffset is 0 then no reset will be done.
1134 */
1135 CPResetFn *resetfn;
1136 };
1137
1138 /* Macros which are lvalues for the field in CPUARMState for the
1139 * ARMCPRegInfo *ri.
1140 */
1141 #define CPREG_FIELD32(env, ri) \
1142 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
1143 #define CPREG_FIELD64(env, ri) \
1144 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
1145
1146 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
1147
1148 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
1149 const ARMCPRegInfo *regs, void *opaque);
1150 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
1151 const ARMCPRegInfo *regs, void *opaque);
1152 static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs)
1153 {
1154 define_arm_cp_regs_with_opaque(cpu, regs, 0);
1155 }
1156 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)
1157 {
1158 define_one_arm_cp_reg_with_opaque(cpu, regs, 0);
1159 }
1160 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp);
1161
1162 /* CPWriteFn that can be used to implement writes-ignored behaviour */
1163 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
1164 uint64_t value);
1165 /* CPReadFn that can be used for read-as-zero behaviour */
1166 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri);
1167
1168 /* CPResetFn that does nothing, for use if no reset is required even
1169 * if fieldoffset is non zero.
1170 */
1171 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque);
1172
1173 /* Return true if this reginfo struct's field in the cpu state struct
1174 * is 64 bits wide.
1175 */
1176 static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri)
1177 {
1178 return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT);
1179 }
1180
1181 static inline bool cp_access_ok(int current_el,
1182 const ARMCPRegInfo *ri, int isread)
1183 {
1184 return (ri->access >> ((current_el * 2) + isread)) & 1;
1185 }
1186
1187 /**
1188 * write_list_to_cpustate
1189 * @cpu: ARMCPU
1190 *
1191 * For each register listed in the ARMCPU cpreg_indexes list, write
1192 * its value from the cpreg_values list into the ARMCPUState structure.
1193 * This updates TCG's working data structures from KVM data or
1194 * from incoming migration state.
1195 *
1196 * Returns: true if all register values were updated correctly,
1197 * false if some register was unknown or could not be written.
1198 * Note that we do not stop early on failure -- we will attempt
1199 * writing all registers in the list.
1200 */
1201 bool write_list_to_cpustate(ARMCPU *cpu);
1202
1203 /**
1204 * write_cpustate_to_list:
1205 * @cpu: ARMCPU
1206 *
1207 * For each register listed in the ARMCPU cpreg_indexes list, write
1208 * its value from the ARMCPUState structure into the cpreg_values list.
1209 * This is used to copy info from TCG's working data structures into
1210 * KVM or for outbound migration.
1211 *
1212 * Returns: true if all register values were read correctly,
1213 * false if some register was unknown or could not be read.
1214 * Note that we do not stop early on failure -- we will attempt
1215 * reading all registers in the list.
1216 */
1217 bool write_cpustate_to_list(ARMCPU *cpu);
1218
1219 /* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3.
1220 Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are
1221 conventional cores (ie. Application or Realtime profile). */
1222
1223 #define IS_M(env) arm_feature(env, ARM_FEATURE_M)
1224
1225 #define ARM_CPUID_TI915T 0x54029152
1226 #define ARM_CPUID_TI925T 0x54029252
1227
1228 #if defined(CONFIG_USER_ONLY)
1229 #define TARGET_PAGE_BITS 12
1230 #else
1231 /* The ARM MMU allows 1k pages. */
1232 /* ??? Linux doesn't actually use these, and they're deprecated in recent
1233 architecture revisions. Maybe a configure option to disable them. */
1234 #define TARGET_PAGE_BITS 10
1235 #endif
1236
1237 #if defined(TARGET_AARCH64)
1238 # define TARGET_PHYS_ADDR_SPACE_BITS 48
1239 # define TARGET_VIRT_ADDR_SPACE_BITS 64
1240 #else
1241 # define TARGET_PHYS_ADDR_SPACE_BITS 40
1242 # define TARGET_VIRT_ADDR_SPACE_BITS 32
1243 #endif
1244
1245 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx)
1246 {
1247 CPUARMState *env = cs->env_ptr;
1248 unsigned int cur_el = arm_current_el(env);
1249 unsigned int target_el = arm_excp_target_el(cs, excp_idx);
1250 /* FIXME: Use actual secure state. */
1251 bool secure = false;
1252 /* If in EL1/0, Physical IRQ routing to EL2 only happens from NS state. */
1253 bool irq_can_hyp = !secure && cur_el < 2 && target_el == 2;
1254
1255 /* Don't take exceptions if they target a lower EL. */
1256 if (cur_el > target_el) {
1257 return false;
1258 }
1259
1260 switch (excp_idx) {
1261 case EXCP_FIQ:
1262 if (irq_can_hyp && (env->cp15.hcr_el2 & HCR_FMO)) {
1263 return true;
1264 }
1265 return !(env->daif & PSTATE_F);
1266 case EXCP_IRQ:
1267 if (irq_can_hyp && (env->cp15.hcr_el2 & HCR_IMO)) {
1268 return true;
1269 }
1270 return !(env->daif & PSTATE_I);
1271 case EXCP_VFIQ:
1272 if (secure || !(env->cp15.hcr_el2 & HCR_FMO)) {
1273 /* VFIQs are only taken when hypervized and non-secure. */
1274 return false;
1275 }
1276 return !(env->daif & PSTATE_F);
1277 case EXCP_VIRQ:
1278 if (secure || !(env->cp15.hcr_el2 & HCR_IMO)) {
1279 /* VIRQs are only taken when hypervized and non-secure. */
1280 return false;
1281 }
1282 return !(env->daif & PSTATE_I);
1283 default:
1284 g_assert_not_reached();
1285 }
1286 }
1287
1288 static inline CPUARMState *cpu_init(const char *cpu_model)
1289 {
1290 ARMCPU *cpu = cpu_arm_init(cpu_model);
1291 if (cpu) {
1292 return &cpu->env;
1293 }
1294 return NULL;
1295 }
1296
1297 #define cpu_exec cpu_arm_exec
1298 #define cpu_gen_code cpu_arm_gen_code
1299 #define cpu_signal_handler cpu_arm_signal_handler
1300 #define cpu_list arm_cpu_list
1301
1302 /* MMU modes definitions */
1303 #define MMU_MODE0_SUFFIX _user
1304 #define MMU_MODE1_SUFFIX _kernel
1305 #define MMU_USER_IDX 0
1306 static inline int cpu_mmu_index (CPUARMState *env)
1307 {
1308 return arm_current_el(env);
1309 }
1310
1311 /* Return the Exception Level targeted by debug exceptions;
1312 * currently always EL1 since we don't implement EL2 or EL3.
1313 */
1314 static inline int arm_debug_target_el(CPUARMState *env)
1315 {
1316 return 1;
1317 }
1318
1319 static inline bool aa64_generate_debug_exceptions(CPUARMState *env)
1320 {
1321 if (arm_current_el(env) == arm_debug_target_el(env)) {
1322 if ((extract32(env->cp15.mdscr_el1, 13, 1) == 0)
1323 || (env->daif & PSTATE_D)) {
1324 return false;
1325 }
1326 }
1327 return true;
1328 }
1329
1330 static inline bool aa32_generate_debug_exceptions(CPUARMState *env)
1331 {
1332 if (arm_current_el(env) == 0 && arm_el_is_aa64(env, 1)) {
1333 return aa64_generate_debug_exceptions(env);
1334 }
1335 return arm_current_el(env) != 2;
1336 }
1337
1338 /* Return true if debugging exceptions are currently enabled.
1339 * This corresponds to what in ARM ARM pseudocode would be
1340 * if UsingAArch32() then
1341 * return AArch32.GenerateDebugExceptions()
1342 * else
1343 * return AArch64.GenerateDebugExceptions()
1344 * We choose to push the if() down into this function for clarity,
1345 * since the pseudocode has it at all callsites except for the one in
1346 * CheckSoftwareStep(), where it is elided because both branches would
1347 * always return the same value.
1348 *
1349 * Parts of the pseudocode relating to EL2 and EL3 are omitted because we
1350 * don't yet implement those exception levels or their associated trap bits.
1351 */
1352 static inline bool arm_generate_debug_exceptions(CPUARMState *env)
1353 {
1354 if (env->aarch64) {
1355 return aa64_generate_debug_exceptions(env);
1356 } else {
1357 return aa32_generate_debug_exceptions(env);
1358 }
1359 }
1360
1361 /* Is single-stepping active? (Note that the "is EL_D AArch64?" check
1362 * implicitly means this always returns false in pre-v8 CPUs.)
1363 */
1364 static inline bool arm_singlestep_active(CPUARMState *env)
1365 {
1366 return extract32(env->cp15.mdscr_el1, 0, 1)
1367 && arm_el_is_aa64(env, arm_debug_target_el(env))
1368 && arm_generate_debug_exceptions(env);
1369 }
1370
1371 #include "exec/cpu-all.h"
1372
1373 /* Bit usage in the TB flags field: bit 31 indicates whether we are
1374 * in 32 or 64 bit mode. The meaning of the other bits depends on that.
1375 */
1376 #define ARM_TBFLAG_AARCH64_STATE_SHIFT 31
1377 #define ARM_TBFLAG_AARCH64_STATE_MASK (1U << ARM_TBFLAG_AARCH64_STATE_SHIFT)
1378
1379 /* Bit usage when in AArch32 state: */
1380 #define ARM_TBFLAG_THUMB_SHIFT 0
1381 #define ARM_TBFLAG_THUMB_MASK (1 << ARM_TBFLAG_THUMB_SHIFT)
1382 #define ARM_TBFLAG_VECLEN_SHIFT 1
1383 #define ARM_TBFLAG_VECLEN_MASK (0x7 << ARM_TBFLAG_VECLEN_SHIFT)
1384 #define ARM_TBFLAG_VECSTRIDE_SHIFT 4
1385 #define ARM_TBFLAG_VECSTRIDE_MASK (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT)
1386 #define ARM_TBFLAG_PRIV_SHIFT 6
1387 #define ARM_TBFLAG_PRIV_MASK (1 << ARM_TBFLAG_PRIV_SHIFT)
1388 #define ARM_TBFLAG_VFPEN_SHIFT 7
1389 #define ARM_TBFLAG_VFPEN_MASK (1 << ARM_TBFLAG_VFPEN_SHIFT)
1390 #define ARM_TBFLAG_CONDEXEC_SHIFT 8
1391 #define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT)
1392 #define ARM_TBFLAG_BSWAP_CODE_SHIFT 16
1393 #define ARM_TBFLAG_BSWAP_CODE_MASK (1 << ARM_TBFLAG_BSWAP_CODE_SHIFT)
1394 #define ARM_TBFLAG_CPACR_FPEN_SHIFT 17
1395 #define ARM_TBFLAG_CPACR_FPEN_MASK (1 << ARM_TBFLAG_CPACR_FPEN_SHIFT)
1396 #define ARM_TBFLAG_SS_ACTIVE_SHIFT 18
1397 #define ARM_TBFLAG_SS_ACTIVE_MASK (1 << ARM_TBFLAG_SS_ACTIVE_SHIFT)
1398 #define ARM_TBFLAG_PSTATE_SS_SHIFT 19
1399 #define ARM_TBFLAG_PSTATE_SS_MASK (1 << ARM_TBFLAG_PSTATE_SS_SHIFT)
1400 /* We store the bottom two bits of the CPAR as TB flags and handle
1401 * checks on the other bits at runtime
1402 */
1403 #define ARM_TBFLAG_XSCALE_CPAR_SHIFT 20
1404 #define ARM_TBFLAG_XSCALE_CPAR_MASK (3 << ARM_TBFLAG_XSCALE_CPAR_SHIFT)
1405
1406 /* Bit usage when in AArch64 state */
1407 #define ARM_TBFLAG_AA64_EL_SHIFT 0
1408 #define ARM_TBFLAG_AA64_EL_MASK (0x3 << ARM_TBFLAG_AA64_EL_SHIFT)
1409 #define ARM_TBFLAG_AA64_FPEN_SHIFT 2
1410 #define ARM_TBFLAG_AA64_FPEN_MASK (1 << ARM_TBFLAG_AA64_FPEN_SHIFT)
1411 #define ARM_TBFLAG_AA64_SS_ACTIVE_SHIFT 3
1412 #define ARM_TBFLAG_AA64_SS_ACTIVE_MASK (1 << ARM_TBFLAG_AA64_SS_ACTIVE_SHIFT)
1413 #define ARM_TBFLAG_AA64_PSTATE_SS_SHIFT 4
1414 #define ARM_TBFLAG_AA64_PSTATE_SS_MASK (1 << ARM_TBFLAG_AA64_PSTATE_SS_SHIFT)
1415
1416 /* some convenience accessor macros */
1417 #define ARM_TBFLAG_AARCH64_STATE(F) \
1418 (((F) & ARM_TBFLAG_AARCH64_STATE_MASK) >> ARM_TBFLAG_AARCH64_STATE_SHIFT)
1419 #define ARM_TBFLAG_THUMB(F) \
1420 (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT)
1421 #define ARM_TBFLAG_VECLEN(F) \
1422 (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT)
1423 #define ARM_TBFLAG_VECSTRIDE(F) \
1424 (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT)
1425 #define ARM_TBFLAG_PRIV(F) \
1426 (((F) & ARM_TBFLAG_PRIV_MASK) >> ARM_TBFLAG_PRIV_SHIFT)
1427 #define ARM_TBFLAG_VFPEN(F) \
1428 (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT)
1429 #define ARM_TBFLAG_CONDEXEC(F) \
1430 (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT)
1431 #define ARM_TBFLAG_BSWAP_CODE(F) \
1432 (((F) & ARM_TBFLAG_BSWAP_CODE_MASK) >> ARM_TBFLAG_BSWAP_CODE_SHIFT)
1433 #define ARM_TBFLAG_CPACR_FPEN(F) \
1434 (((F) & ARM_TBFLAG_CPACR_FPEN_MASK) >> ARM_TBFLAG_CPACR_FPEN_SHIFT)
1435 #define ARM_TBFLAG_SS_ACTIVE(F) \
1436 (((F) & ARM_TBFLAG_SS_ACTIVE_MASK) >> ARM_TBFLAG_SS_ACTIVE_SHIFT)
1437 #define ARM_TBFLAG_PSTATE_SS(F) \
1438 (((F) & ARM_TBFLAG_PSTATE_SS_MASK) >> ARM_TBFLAG_PSTATE_SS_SHIFT)
1439 #define ARM_TBFLAG_XSCALE_CPAR(F) \
1440 (((F) & ARM_TBFLAG_XSCALE_CPAR_MASK) >> ARM_TBFLAG_XSCALE_CPAR_SHIFT)
1441 #define ARM_TBFLAG_AA64_EL(F) \
1442 (((F) & ARM_TBFLAG_AA64_EL_MASK) >> ARM_TBFLAG_AA64_EL_SHIFT)
1443 #define ARM_TBFLAG_AA64_FPEN(F) \
1444 (((F) & ARM_TBFLAG_AA64_FPEN_MASK) >> ARM_TBFLAG_AA64_FPEN_SHIFT)
1445 #define ARM_TBFLAG_AA64_SS_ACTIVE(F) \
1446 (((F) & ARM_TBFLAG_AA64_SS_ACTIVE_MASK) >> ARM_TBFLAG_AA64_SS_ACTIVE_SHIFT)
1447 #define ARM_TBFLAG_AA64_PSTATE_SS(F) \
1448 (((F) & ARM_TBFLAG_AA64_PSTATE_SS_MASK) >> ARM_TBFLAG_AA64_PSTATE_SS_SHIFT)
1449
1450 static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
1451 target_ulong *cs_base, int *flags)
1452 {
1453 int fpen;
1454
1455 if (arm_feature(env, ARM_FEATURE_V6)) {
1456 fpen = extract32(env->cp15.c1_coproc, 20, 2);
1457 } else {
1458 /* CPACR doesn't exist before v6, so VFP is always accessible */
1459 fpen = 3;
1460 }
1461
1462 if (is_a64(env)) {
1463 *pc = env->pc;
1464 *flags = ARM_TBFLAG_AARCH64_STATE_MASK
1465 | (arm_current_el(env) << ARM_TBFLAG_AA64_EL_SHIFT);
1466 if (fpen == 3 || (fpen == 1 && arm_current_el(env) != 0)) {
1467 *flags |= ARM_TBFLAG_AA64_FPEN_MASK;
1468 }
1469 /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
1470 * states defined in the ARM ARM for software singlestep:
1471 * SS_ACTIVE PSTATE.SS State
1472 * 0 x Inactive (the TB flag for SS is always 0)
1473 * 1 0 Active-pending
1474 * 1 1 Active-not-pending
1475 */
1476 if (arm_singlestep_active(env)) {
1477 *flags |= ARM_TBFLAG_AA64_SS_ACTIVE_MASK;
1478 if (env->pstate & PSTATE_SS) {
1479 *flags |= ARM_TBFLAG_AA64_PSTATE_SS_MASK;
1480 }
1481 }
1482 } else {
1483 int privmode;
1484 *pc = env->regs[15];
1485 *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT)
1486 | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT)
1487 | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT)
1488 | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT)
1489 | (env->bswap_code << ARM_TBFLAG_BSWAP_CODE_SHIFT);
1490 if (arm_feature(env, ARM_FEATURE_M)) {
1491 privmode = !((env->v7m.exception == 0) && (env->v7m.control & 1));
1492 } else {
1493 privmode = (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR;
1494 }
1495 if (privmode) {
1496 *flags |= ARM_TBFLAG_PRIV_MASK;
1497 }
1498 if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)
1499 || arm_el_is_aa64(env, 1)) {
1500 *flags |= ARM_TBFLAG_VFPEN_MASK;
1501 }
1502 if (fpen == 3 || (fpen == 1 && arm_current_el(env) != 0)) {
1503 *flags |= ARM_TBFLAG_CPACR_FPEN_MASK;
1504 }
1505 /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
1506 * states defined in the ARM ARM for software singlestep:
1507 * SS_ACTIVE PSTATE.SS State
1508 * 0 x Inactive (the TB flag for SS is always 0)
1509 * 1 0 Active-pending
1510 * 1 1 Active-not-pending
1511 */
1512 if (arm_singlestep_active(env)) {
1513 *flags |= ARM_TBFLAG_SS_ACTIVE_MASK;
1514 if (env->uncached_cpsr & PSTATE_SS) {
1515 *flags |= ARM_TBFLAG_PSTATE_SS_MASK;
1516 }
1517 }
1518 *flags |= (extract32(env->cp15.c15_cpar, 0, 2)
1519 << ARM_TBFLAG_XSCALE_CPAR_SHIFT);
1520 }
1521
1522 *cs_base = 0;
1523 }
1524
1525 #include "exec/exec-all.h"
1526
1527 static inline void cpu_pc_from_tb(CPUARMState *env, TranslationBlock *tb)
1528 {
1529 if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) {
1530 env->pc = tb->pc;
1531 } else {
1532 env->regs[15] = tb->pc;
1533 }
1534 }
1535
1536 enum {
1537 QEMU_PSCI_CONDUIT_DISABLED = 0,
1538 QEMU_PSCI_CONDUIT_SMC = 1,
1539 QEMU_PSCI_CONDUIT_HVC = 2,
1540 };
1541
1542 #endif