migration: rename unix.c to socket.c
[qemu.git] / target-arm / cpu.h
1 /*
2 * ARM virtual CPU header
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #ifndef CPU_ARM_H
20 #define CPU_ARM_H
21
22
23 #include "kvm-consts.h"
24
25 #if defined(TARGET_AARCH64)
26 /* AArch64 definitions */
27 # define TARGET_LONG_BITS 64
28 #else
29 # define TARGET_LONG_BITS 32
30 #endif
31
32 #define TARGET_IS_BIENDIAN 1
33
34 #define CPUArchState struct CPUARMState
35
36 #include "qemu-common.h"
37 #include "cpu-qom.h"
38 #include "exec/cpu-defs.h"
39
40 #include "fpu/softfloat.h"
41
42 #define EXCP_UDEF 1 /* undefined instruction */
43 #define EXCP_SWI 2 /* software interrupt */
44 #define EXCP_PREFETCH_ABORT 3
45 #define EXCP_DATA_ABORT 4
46 #define EXCP_IRQ 5
47 #define EXCP_FIQ 6
48 #define EXCP_BKPT 7
49 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */
50 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */
51 #define EXCP_STREX 10
52 #define EXCP_HVC 11 /* HyperVisor Call */
53 #define EXCP_HYP_TRAP 12
54 #define EXCP_SMC 13 /* Secure Monitor Call */
55 #define EXCP_VIRQ 14
56 #define EXCP_VFIQ 15
57 #define EXCP_SEMIHOST 16 /* semihosting call (A64 only) */
58
59 #define ARMV7M_EXCP_RESET 1
60 #define ARMV7M_EXCP_NMI 2
61 #define ARMV7M_EXCP_HARD 3
62 #define ARMV7M_EXCP_MEM 4
63 #define ARMV7M_EXCP_BUS 5
64 #define ARMV7M_EXCP_USAGE 6
65 #define ARMV7M_EXCP_SVC 11
66 #define ARMV7M_EXCP_DEBUG 12
67 #define ARMV7M_EXCP_PENDSV 14
68 #define ARMV7M_EXCP_SYSTICK 15
69
70 /* ARM-specific interrupt pending bits. */
71 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1
72 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2
73 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3
74
75 /* The usual mapping for an AArch64 system register to its AArch32
76 * counterpart is for the 32 bit world to have access to the lower
77 * half only (with writes leaving the upper half untouched). It's
78 * therefore useful to be able to pass TCG the offset of the least
79 * significant half of a uint64_t struct member.
80 */
81 #ifdef HOST_WORDS_BIGENDIAN
82 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t))
83 #define offsetofhigh32(S, M) offsetof(S, M)
84 #else
85 #define offsetoflow32(S, M) offsetof(S, M)
86 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t))
87 #endif
88
89 /* Meanings of the ARMCPU object's four inbound GPIO lines */
90 #define ARM_CPU_IRQ 0
91 #define ARM_CPU_FIQ 1
92 #define ARM_CPU_VIRQ 2
93 #define ARM_CPU_VFIQ 3
94
95 #define NB_MMU_MODES 7
96 #define TARGET_INSN_START_EXTRA_WORDS 1
97
98 /* We currently assume float and double are IEEE single and double
99 precision respectively.
100 Doing runtime conversions is tricky because VFP registers may contain
101 integer values (eg. as the result of a FTOSI instruction).
102 s<2n> maps to the least significant half of d<n>
103 s<2n+1> maps to the most significant half of d<n>
104 */
105
106 /* CPU state for each instance of a generic timer (in cp15 c14) */
107 typedef struct ARMGenericTimer {
108 uint64_t cval; /* Timer CompareValue register */
109 uint64_t ctl; /* Timer Control register */
110 } ARMGenericTimer;
111
112 #define GTIMER_PHYS 0
113 #define GTIMER_VIRT 1
114 #define GTIMER_HYP 2
115 #define GTIMER_SEC 3
116 #define NUM_GTIMERS 4
117
118 typedef struct {
119 uint64_t raw_tcr;
120 uint32_t mask;
121 uint32_t base_mask;
122 } TCR;
123
124 typedef struct CPUARMState {
125 /* Regs for current mode. */
126 uint32_t regs[16];
127
128 /* 32/64 switch only happens when taking and returning from
129 * exceptions so the overlap semantics are taken care of then
130 * instead of having a complicated union.
131 */
132 /* Regs for A64 mode. */
133 uint64_t xregs[32];
134 uint64_t pc;
135 /* PSTATE isn't an architectural register for ARMv8. However, it is
136 * convenient for us to assemble the underlying state into a 32 bit format
137 * identical to the architectural format used for the SPSR. (This is also
138 * what the Linux kernel's 'pstate' field in signal handlers and KVM's
139 * 'pstate' register are.) Of the PSTATE bits:
140 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same
141 * semantics as for AArch32, as described in the comments on each field)
142 * nRW (also known as M[4]) is kept, inverted, in env->aarch64
143 * DAIF (exception masks) are kept in env->daif
144 * all other bits are stored in their correct places in env->pstate
145 */
146 uint32_t pstate;
147 uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */
148
149 /* Frequently accessed CPSR bits are stored separately for efficiency.
150 This contains all the other bits. Use cpsr_{read,write} to access
151 the whole CPSR. */
152 uint32_t uncached_cpsr;
153 uint32_t spsr;
154
155 /* Banked registers. */
156 uint64_t banked_spsr[8];
157 uint32_t banked_r13[8];
158 uint32_t banked_r14[8];
159
160 /* These hold r8-r12. */
161 uint32_t usr_regs[5];
162 uint32_t fiq_regs[5];
163
164 /* cpsr flag cache for faster execution */
165 uint32_t CF; /* 0 or 1 */
166 uint32_t VF; /* V is the bit 31. All other bits are undefined */
167 uint32_t NF; /* N is bit 31. All other bits are undefined. */
168 uint32_t ZF; /* Z set if zero. */
169 uint32_t QF; /* 0 or 1 */
170 uint32_t GE; /* cpsr[19:16] */
171 uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
172 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */
173 uint64_t daif; /* exception masks, in the bits they are in PSTATE */
174
175 uint64_t elr_el[4]; /* AArch64 exception link regs */
176 uint64_t sp_el[4]; /* AArch64 banked stack pointers */
177
178 /* System control coprocessor (cp15) */
179 struct {
180 uint32_t c0_cpuid;
181 union { /* Cache size selection */
182 struct {
183 uint64_t _unused_csselr0;
184 uint64_t csselr_ns;
185 uint64_t _unused_csselr1;
186 uint64_t csselr_s;
187 };
188 uint64_t csselr_el[4];
189 };
190 union { /* System control register. */
191 struct {
192 uint64_t _unused_sctlr;
193 uint64_t sctlr_ns;
194 uint64_t hsctlr;
195 uint64_t sctlr_s;
196 };
197 uint64_t sctlr_el[4];
198 };
199 uint64_t cpacr_el1; /* Architectural feature access control register */
200 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */
201 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */
202 uint64_t sder; /* Secure debug enable register. */
203 uint32_t nsacr; /* Non-secure access control register. */
204 union { /* MMU translation table base 0. */
205 struct {
206 uint64_t _unused_ttbr0_0;
207 uint64_t ttbr0_ns;
208 uint64_t _unused_ttbr0_1;
209 uint64_t ttbr0_s;
210 };
211 uint64_t ttbr0_el[4];
212 };
213 union { /* MMU translation table base 1. */
214 struct {
215 uint64_t _unused_ttbr1_0;
216 uint64_t ttbr1_ns;
217 uint64_t _unused_ttbr1_1;
218 uint64_t ttbr1_s;
219 };
220 uint64_t ttbr1_el[4];
221 };
222 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */
223 /* MMU translation table base control. */
224 TCR tcr_el[4];
225 TCR vtcr_el2; /* Virtualization Translation Control. */
226 uint32_t c2_data; /* MPU data cacheable bits. */
227 uint32_t c2_insn; /* MPU instruction cacheable bits. */
228 union { /* MMU domain access control register
229 * MPU write buffer control.
230 */
231 struct {
232 uint64_t dacr_ns;
233 uint64_t dacr_s;
234 };
235 struct {
236 uint64_t dacr32_el2;
237 };
238 };
239 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */
240 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */
241 uint64_t hcr_el2; /* Hypervisor configuration register */
242 uint64_t scr_el3; /* Secure configuration register. */
243 union { /* Fault status registers. */
244 struct {
245 uint64_t ifsr_ns;
246 uint64_t ifsr_s;
247 };
248 struct {
249 uint64_t ifsr32_el2;
250 };
251 };
252 union {
253 struct {
254 uint64_t _unused_dfsr;
255 uint64_t dfsr_ns;
256 uint64_t hsr;
257 uint64_t dfsr_s;
258 };
259 uint64_t esr_el[4];
260 };
261 uint32_t c6_region[8]; /* MPU base/size registers. */
262 union { /* Fault address registers. */
263 struct {
264 uint64_t _unused_far0;
265 #ifdef HOST_WORDS_BIGENDIAN
266 uint32_t ifar_ns;
267 uint32_t dfar_ns;
268 uint32_t ifar_s;
269 uint32_t dfar_s;
270 #else
271 uint32_t dfar_ns;
272 uint32_t ifar_ns;
273 uint32_t dfar_s;
274 uint32_t ifar_s;
275 #endif
276 uint64_t _unused_far3;
277 };
278 uint64_t far_el[4];
279 };
280 uint64_t hpfar_el2;
281 union { /* Translation result. */
282 struct {
283 uint64_t _unused_par_0;
284 uint64_t par_ns;
285 uint64_t _unused_par_1;
286 uint64_t par_s;
287 };
288 uint64_t par_el[4];
289 };
290
291 uint32_t c6_rgnr;
292
293 uint32_t c9_insn; /* Cache lockdown registers. */
294 uint32_t c9_data;
295 uint64_t c9_pmcr; /* performance monitor control register */
296 uint64_t c9_pmcnten; /* perf monitor counter enables */
297 uint32_t c9_pmovsr; /* perf monitor overflow status */
298 uint32_t c9_pmxevtyper; /* perf monitor event type */
299 uint32_t c9_pmuserenr; /* perf monitor user enable */
300 uint32_t c9_pminten; /* perf monitor interrupt enables */
301 union { /* Memory attribute redirection */
302 struct {
303 #ifdef HOST_WORDS_BIGENDIAN
304 uint64_t _unused_mair_0;
305 uint32_t mair1_ns;
306 uint32_t mair0_ns;
307 uint64_t _unused_mair_1;
308 uint32_t mair1_s;
309 uint32_t mair0_s;
310 #else
311 uint64_t _unused_mair_0;
312 uint32_t mair0_ns;
313 uint32_t mair1_ns;
314 uint64_t _unused_mair_1;
315 uint32_t mair0_s;
316 uint32_t mair1_s;
317 #endif
318 };
319 uint64_t mair_el[4];
320 };
321 union { /* vector base address register */
322 struct {
323 uint64_t _unused_vbar;
324 uint64_t vbar_ns;
325 uint64_t hvbar;
326 uint64_t vbar_s;
327 };
328 uint64_t vbar_el[4];
329 };
330 uint32_t mvbar; /* (monitor) vector base address register */
331 struct { /* FCSE PID. */
332 uint32_t fcseidr_ns;
333 uint32_t fcseidr_s;
334 };
335 union { /* Context ID. */
336 struct {
337 uint64_t _unused_contextidr_0;
338 uint64_t contextidr_ns;
339 uint64_t _unused_contextidr_1;
340 uint64_t contextidr_s;
341 };
342 uint64_t contextidr_el[4];
343 };
344 union { /* User RW Thread register. */
345 struct {
346 uint64_t tpidrurw_ns;
347 uint64_t tpidrprw_ns;
348 uint64_t htpidr;
349 uint64_t _tpidr_el3;
350 };
351 uint64_t tpidr_el[4];
352 };
353 /* The secure banks of these registers don't map anywhere */
354 uint64_t tpidrurw_s;
355 uint64_t tpidrprw_s;
356 uint64_t tpidruro_s;
357
358 union { /* User RO Thread register. */
359 uint64_t tpidruro_ns;
360 uint64_t tpidrro_el[1];
361 };
362 uint64_t c14_cntfrq; /* Counter Frequency register */
363 uint64_t c14_cntkctl; /* Timer Control register */
364 uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */
365 uint64_t cntvoff_el2; /* Counter Virtual Offset register */
366 ARMGenericTimer c14_timer[NUM_GTIMERS];
367 uint32_t c15_cpar; /* XScale Coprocessor Access Register */
368 uint32_t c15_ticonfig; /* TI925T configuration byte. */
369 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */
370 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */
371 uint32_t c15_threadid; /* TI debugger thread-ID. */
372 uint32_t c15_config_base_address; /* SCU base address. */
373 uint32_t c15_diagnostic; /* diagnostic register */
374 uint32_t c15_power_diagnostic;
375 uint32_t c15_power_control; /* power control */
376 uint64_t dbgbvr[16]; /* breakpoint value registers */
377 uint64_t dbgbcr[16]; /* breakpoint control registers */
378 uint64_t dbgwvr[16]; /* watchpoint value registers */
379 uint64_t dbgwcr[16]; /* watchpoint control registers */
380 uint64_t mdscr_el1;
381 uint64_t oslsr_el1; /* OS Lock Status */
382 uint64_t mdcr_el2;
383 uint64_t mdcr_el3;
384 /* If the counter is enabled, this stores the last time the counter
385 * was reset. Otherwise it stores the counter value
386 */
387 uint64_t c15_ccnt;
388 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */
389 uint64_t vpidr_el2; /* Virtualization Processor ID Register */
390 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */
391 } cp15;
392
393 struct {
394 uint32_t other_sp;
395 uint32_t vecbase;
396 uint32_t basepri;
397 uint32_t control;
398 int current_sp;
399 int exception;
400 } v7m;
401
402 /* Information associated with an exception about to be taken:
403 * code which raises an exception must set cs->exception_index and
404 * the relevant parts of this structure; the cpu_do_interrupt function
405 * will then set the guest-visible registers as part of the exception
406 * entry process.
407 */
408 struct {
409 uint32_t syndrome; /* AArch64 format syndrome register */
410 uint32_t fsr; /* AArch32 format fault status register info */
411 uint64_t vaddress; /* virtual addr associated with exception, if any */
412 uint32_t target_el; /* EL the exception should be targeted for */
413 /* If we implement EL2 we will also need to store information
414 * about the intermediate physical address for stage 2 faults.
415 */
416 } exception;
417
418 /* Thumb-2 EE state. */
419 uint32_t teecr;
420 uint32_t teehbr;
421
422 /* VFP coprocessor state. */
423 struct {
424 /* VFP/Neon register state. Note that the mapping between S, D and Q
425 * views of the register bank differs between AArch64 and AArch32:
426 * In AArch32:
427 * Qn = regs[2n+1]:regs[2n]
428 * Dn = regs[n]
429 * Sn = regs[n/2] bits 31..0 for even n, and bits 63..32 for odd n
430 * (and regs[32] to regs[63] are inaccessible)
431 * In AArch64:
432 * Qn = regs[2n+1]:regs[2n]
433 * Dn = regs[2n]
434 * Sn = regs[2n] bits 31..0
435 * This corresponds to the architecturally defined mapping between
436 * the two execution states, and means we do not need to explicitly
437 * map these registers when changing states.
438 */
439 float64 regs[64];
440
441 uint32_t xregs[16];
442 /* We store these fpcsr fields separately for convenience. */
443 int vec_len;
444 int vec_stride;
445
446 /* scratch space when Tn are not sufficient. */
447 uint32_t scratch[8];
448
449 /* fp_status is the "normal" fp status. standard_fp_status retains
450 * values corresponding to the ARM "Standard FPSCR Value", ie
451 * default-NaN, flush-to-zero, round-to-nearest and is used by
452 * any operations (generally Neon) which the architecture defines
453 * as controlled by the standard FPSCR value rather than the FPSCR.
454 *
455 * To avoid having to transfer exception bits around, we simply
456 * say that the FPSCR cumulative exception flags are the logical
457 * OR of the flags in the two fp statuses. This relies on the
458 * only thing which needs to read the exception flags being
459 * an explicit FPSCR read.
460 */
461 float_status fp_status;
462 float_status standard_fp_status;
463 } vfp;
464 uint64_t exclusive_addr;
465 uint64_t exclusive_val;
466 uint64_t exclusive_high;
467 #if defined(CONFIG_USER_ONLY)
468 uint64_t exclusive_test;
469 uint32_t exclusive_info;
470 #endif
471
472 /* iwMMXt coprocessor state. */
473 struct {
474 uint64_t regs[16];
475 uint64_t val;
476
477 uint32_t cregs[16];
478 } iwmmxt;
479
480 #if defined(CONFIG_USER_ONLY)
481 /* For usermode syscall translation. */
482 int eabi;
483 #endif
484
485 struct CPUBreakpoint *cpu_breakpoint[16];
486 struct CPUWatchpoint *cpu_watchpoint[16];
487
488 CPU_COMMON
489
490 /* These fields after the common ones so they are preserved on reset. */
491
492 /* Internal CPU feature flags. */
493 uint64_t features;
494
495 /* PMSAv7 MPU */
496 struct {
497 uint32_t *drbar;
498 uint32_t *drsr;
499 uint32_t *dracr;
500 } pmsav7;
501
502 void *nvic;
503 const struct arm_boot_info *boot_info;
504 } CPUARMState;
505
506 /**
507 * ARMCPU:
508 * @env: #CPUARMState
509 *
510 * An ARM CPU core.
511 */
512 struct ARMCPU {
513 /*< private >*/
514 CPUState parent_obj;
515 /*< public >*/
516
517 CPUARMState env;
518
519 /* Coprocessor information */
520 GHashTable *cp_regs;
521 /* For marshalling (mostly coprocessor) register state between the
522 * kernel and QEMU (for KVM) and between two QEMUs (for migration),
523 * we use these arrays.
524 */
525 /* List of register indexes managed via these arrays; (full KVM style
526 * 64 bit indexes, not CPRegInfo 32 bit indexes)
527 */
528 uint64_t *cpreg_indexes;
529 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */
530 uint64_t *cpreg_values;
531 /* Length of the indexes, values, reset_values arrays */
532 int32_t cpreg_array_len;
533 /* These are used only for migration: incoming data arrives in
534 * these fields and is sanity checked in post_load before copying
535 * to the working data structures above.
536 */
537 uint64_t *cpreg_vmstate_indexes;
538 uint64_t *cpreg_vmstate_values;
539 int32_t cpreg_vmstate_array_len;
540
541 /* Timers used by the generic (architected) timer */
542 QEMUTimer *gt_timer[NUM_GTIMERS];
543 /* GPIO outputs for generic timer */
544 qemu_irq gt_timer_outputs[NUM_GTIMERS];
545
546 /* MemoryRegion to use for secure physical accesses */
547 MemoryRegion *secure_memory;
548
549 /* 'compatible' string for this CPU for Linux device trees */
550 const char *dtb_compatible;
551
552 /* PSCI version for this CPU
553 * Bits[31:16] = Major Version
554 * Bits[15:0] = Minor Version
555 */
556 uint32_t psci_version;
557
558 /* Should CPU start in PSCI powered-off state? */
559 bool start_powered_off;
560 /* CPU currently in PSCI powered-off state */
561 bool powered_off;
562 /* CPU has security extension */
563 bool has_el3;
564
565 /* CPU has memory protection unit */
566 bool has_mpu;
567 /* PMSAv7 MPU number of supported regions */
568 uint32_t pmsav7_dregion;
569
570 /* PSCI conduit used to invoke PSCI methods
571 * 0 - disabled, 1 - smc, 2 - hvc
572 */
573 uint32_t psci_conduit;
574
575 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or
576 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type.
577 */
578 uint32_t kvm_target;
579
580 /* KVM init features for this CPU */
581 uint32_t kvm_init_features[7];
582
583 /* Uniprocessor system with MP extensions */
584 bool mp_is_up;
585
586 /* The instance init functions for implementation-specific subclasses
587 * set these fields to specify the implementation-dependent values of
588 * various constant registers and reset values of non-constant
589 * registers.
590 * Some of these might become QOM properties eventually.
591 * Field names match the official register names as defined in the
592 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix
593 * is used for reset values of non-constant registers; no reset_
594 * prefix means a constant register.
595 */
596 uint32_t midr;
597 uint32_t revidr;
598 uint32_t reset_fpsid;
599 uint32_t mvfr0;
600 uint32_t mvfr1;
601 uint32_t mvfr2;
602 uint32_t ctr;
603 uint32_t reset_sctlr;
604 uint32_t id_pfr0;
605 uint32_t id_pfr1;
606 uint32_t id_dfr0;
607 uint32_t pmceid0;
608 uint32_t pmceid1;
609 uint32_t id_afr0;
610 uint32_t id_mmfr0;
611 uint32_t id_mmfr1;
612 uint32_t id_mmfr2;
613 uint32_t id_mmfr3;
614 uint32_t id_mmfr4;
615 uint32_t id_isar0;
616 uint32_t id_isar1;
617 uint32_t id_isar2;
618 uint32_t id_isar3;
619 uint32_t id_isar4;
620 uint32_t id_isar5;
621 uint64_t id_aa64pfr0;
622 uint64_t id_aa64pfr1;
623 uint64_t id_aa64dfr0;
624 uint64_t id_aa64dfr1;
625 uint64_t id_aa64afr0;
626 uint64_t id_aa64afr1;
627 uint64_t id_aa64isar0;
628 uint64_t id_aa64isar1;
629 uint64_t id_aa64mmfr0;
630 uint64_t id_aa64mmfr1;
631 uint32_t dbgdidr;
632 uint32_t clidr;
633 uint64_t mp_affinity; /* MP ID without feature bits */
634 /* The elements of this array are the CCSIDR values for each cache,
635 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
636 */
637 uint32_t ccsidr[16];
638 uint64_t reset_cbar;
639 uint32_t reset_auxcr;
640 bool reset_hivecs;
641 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */
642 uint32_t dcz_blocksize;
643 uint64_t rvbar;
644 };
645
646 static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)
647 {
648 return container_of(env, ARMCPU, env);
649 }
650
651 #define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e))
652
653 #define ENV_OFFSET offsetof(ARMCPU, env)
654
655 #ifndef CONFIG_USER_ONLY
656 extern const struct VMStateDescription vmstate_arm_cpu;
657 #endif
658
659 void arm_cpu_do_interrupt(CPUState *cpu);
660 void arm_v7m_cpu_do_interrupt(CPUState *cpu);
661 bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req);
662
663 void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
664 int flags);
665
666 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
667 MemTxAttrs *attrs);
668
669 int arm_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
670 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
671
672 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
673 int cpuid, void *opaque);
674 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
675 int cpuid, void *opaque);
676
677 #ifdef TARGET_AARCH64
678 int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
679 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
680 #endif
681
682 ARMCPU *cpu_arm_init(const char *cpu_model);
683 int cpu_arm_exec(CPUState *cpu);
684 target_ulong do_arm_semihosting(CPUARMState *env);
685 void aarch64_sync_32_to_64(CPUARMState *env);
686 void aarch64_sync_64_to_32(CPUARMState *env);
687
688 static inline bool is_a64(CPUARMState *env)
689 {
690 return env->aarch64;
691 }
692
693 /* you can call this signal handler from your SIGBUS and SIGSEGV
694 signal handlers to inform the virtual CPU of exceptions. non zero
695 is returned if the signal was handled by the virtual CPU. */
696 int cpu_arm_signal_handler(int host_signum, void *pinfo,
697 void *puc);
698
699 /**
700 * pmccntr_sync
701 * @env: CPUARMState
702 *
703 * Synchronises the counter in the PMCCNTR. This must always be called twice,
704 * once before any action that might affect the timer and again afterwards.
705 * The function is used to swap the state of the register if required.
706 * This only happens when not in user mode (!CONFIG_USER_ONLY)
707 */
708 void pmccntr_sync(CPUARMState *env);
709
710 /* SCTLR bit meanings. Several bits have been reused in newer
711 * versions of the architecture; in that case we define constants
712 * for both old and new bit meanings. Code which tests against those
713 * bits should probably check or otherwise arrange that the CPU
714 * is the architectural version it expects.
715 */
716 #define SCTLR_M (1U << 0)
717 #define SCTLR_A (1U << 1)
718 #define SCTLR_C (1U << 2)
719 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */
720 #define SCTLR_SA (1U << 3)
721 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */
722 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */
723 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */
724 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */
725 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */
726 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */
727 #define SCTLR_ITD (1U << 7) /* v8 onward */
728 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */
729 #define SCTLR_SED (1U << 8) /* v8 onward */
730 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */
731 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */
732 #define SCTLR_F (1U << 10) /* up to v6 */
733 #define SCTLR_SW (1U << 10) /* v7 onward */
734 #define SCTLR_Z (1U << 11)
735 #define SCTLR_I (1U << 12)
736 #define SCTLR_V (1U << 13)
737 #define SCTLR_RR (1U << 14) /* up to v7 */
738 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */
739 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */
740 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */
741 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */
742 #define SCTLR_nTWI (1U << 16) /* v8 onward */
743 #define SCTLR_HA (1U << 17)
744 #define SCTLR_BR (1U << 17) /* PMSA only */
745 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */
746 #define SCTLR_nTWE (1U << 18) /* v8 onward */
747 #define SCTLR_WXN (1U << 19)
748 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */
749 #define SCTLR_UWXN (1U << 20) /* v7 onward */
750 #define SCTLR_FI (1U << 21)
751 #define SCTLR_U (1U << 22)
752 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */
753 #define SCTLR_VE (1U << 24) /* up to v7 */
754 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */
755 #define SCTLR_EE (1U << 25)
756 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */
757 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */
758 #define SCTLR_NMFI (1U << 27)
759 #define SCTLR_TRE (1U << 28)
760 #define SCTLR_AFE (1U << 29)
761 #define SCTLR_TE (1U << 30)
762
763 #define CPTR_TCPAC (1U << 31)
764 #define CPTR_TTA (1U << 20)
765 #define CPTR_TFP (1U << 10)
766
767 #define MDCR_EPMAD (1U << 21)
768 #define MDCR_EDAD (1U << 20)
769 #define MDCR_SPME (1U << 17)
770 #define MDCR_SDD (1U << 16)
771 #define MDCR_SPD (3U << 14)
772 #define MDCR_TDRA (1U << 11)
773 #define MDCR_TDOSA (1U << 10)
774 #define MDCR_TDA (1U << 9)
775 #define MDCR_TDE (1U << 8)
776 #define MDCR_HPME (1U << 7)
777 #define MDCR_TPM (1U << 6)
778 #define MDCR_TPMCR (1U << 5)
779
780 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */
781 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD)
782
783 #define CPSR_M (0x1fU)
784 #define CPSR_T (1U << 5)
785 #define CPSR_F (1U << 6)
786 #define CPSR_I (1U << 7)
787 #define CPSR_A (1U << 8)
788 #define CPSR_E (1U << 9)
789 #define CPSR_IT_2_7 (0xfc00U)
790 #define CPSR_GE (0xfU << 16)
791 #define CPSR_IL (1U << 20)
792 /* Note that the RESERVED bits include bit 21, which is PSTATE_SS in
793 * an AArch64 SPSR but RES0 in AArch32 SPSR and CPSR. In QEMU we use
794 * env->uncached_cpsr bit 21 to store PSTATE.SS when executing in AArch32,
795 * where it is live state but not accessible to the AArch32 code.
796 */
797 #define CPSR_RESERVED (0x7U << 21)
798 #define CPSR_J (1U << 24)
799 #define CPSR_IT_0_1 (3U << 25)
800 #define CPSR_Q (1U << 27)
801 #define CPSR_V (1U << 28)
802 #define CPSR_C (1U << 29)
803 #define CPSR_Z (1U << 30)
804 #define CPSR_N (1U << 31)
805 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
806 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F)
807
808 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
809 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
810 | CPSR_NZCV)
811 /* Bits writable in user mode. */
812 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
813 /* Execution state bits. MRS read as zero, MSR writes ignored. */
814 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL)
815 /* Mask of bits which may be set by exception return copying them from SPSR */
816 #define CPSR_ERET_MASK (~CPSR_RESERVED)
817
818 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */
819 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */
820 #define TTBCR_PD0 (1U << 4)
821 #define TTBCR_PD1 (1U << 5)
822 #define TTBCR_EPD0 (1U << 7)
823 #define TTBCR_IRGN0 (3U << 8)
824 #define TTBCR_ORGN0 (3U << 10)
825 #define TTBCR_SH0 (3U << 12)
826 #define TTBCR_T1SZ (3U << 16)
827 #define TTBCR_A1 (1U << 22)
828 #define TTBCR_EPD1 (1U << 23)
829 #define TTBCR_IRGN1 (3U << 24)
830 #define TTBCR_ORGN1 (3U << 26)
831 #define TTBCR_SH1 (1U << 28)
832 #define TTBCR_EAE (1U << 31)
833
834 /* Bit definitions for ARMv8 SPSR (PSTATE) format.
835 * Only these are valid when in AArch64 mode; in
836 * AArch32 mode SPSRs are basically CPSR-format.
837 */
838 #define PSTATE_SP (1U)
839 #define PSTATE_M (0xFU)
840 #define PSTATE_nRW (1U << 4)
841 #define PSTATE_F (1U << 6)
842 #define PSTATE_I (1U << 7)
843 #define PSTATE_A (1U << 8)
844 #define PSTATE_D (1U << 9)
845 #define PSTATE_IL (1U << 20)
846 #define PSTATE_SS (1U << 21)
847 #define PSTATE_V (1U << 28)
848 #define PSTATE_C (1U << 29)
849 #define PSTATE_Z (1U << 30)
850 #define PSTATE_N (1U << 31)
851 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V)
852 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F)
853 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF)
854 /* Mode values for AArch64 */
855 #define PSTATE_MODE_EL3h 13
856 #define PSTATE_MODE_EL3t 12
857 #define PSTATE_MODE_EL2h 9
858 #define PSTATE_MODE_EL2t 8
859 #define PSTATE_MODE_EL1h 5
860 #define PSTATE_MODE_EL1t 4
861 #define PSTATE_MODE_EL0t 0
862
863 /* Map EL and handler into a PSTATE_MODE. */
864 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler)
865 {
866 return (el << 2) | handler;
867 }
868
869 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit
870 * interprocessing, so we don't attempt to sync with the cpsr state used by
871 * the 32 bit decoder.
872 */
873 static inline uint32_t pstate_read(CPUARMState *env)
874 {
875 int ZF;
876
877 ZF = (env->ZF == 0);
878 return (env->NF & 0x80000000) | (ZF << 30)
879 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3)
880 | env->pstate | env->daif;
881 }
882
883 static inline void pstate_write(CPUARMState *env, uint32_t val)
884 {
885 env->ZF = (~val) & PSTATE_Z;
886 env->NF = val;
887 env->CF = (val >> 29) & 1;
888 env->VF = (val << 3) & 0x80000000;
889 env->daif = val & PSTATE_DAIF;
890 env->pstate = val & ~CACHED_PSTATE_BITS;
891 }
892
893 /* Return the current CPSR value. */
894 uint32_t cpsr_read(CPUARMState *env);
895
896 typedef enum CPSRWriteType {
897 CPSRWriteByInstr = 0, /* from guest MSR or CPS */
898 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */
899 CPSRWriteRaw = 2, /* trust values, do not switch reg banks */
900 CPSRWriteByGDBStub = 3, /* from the GDB stub */
901 } CPSRWriteType;
902
903 /* Set the CPSR. Note that some bits of mask must be all-set or all-clear.*/
904 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
905 CPSRWriteType write_type);
906
907 /* Return the current xPSR value. */
908 static inline uint32_t xpsr_read(CPUARMState *env)
909 {
910 int ZF;
911 ZF = (env->ZF == 0);
912 return (env->NF & 0x80000000) | (ZF << 30)
913 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
914 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
915 | ((env->condexec_bits & 0xfc) << 8)
916 | env->v7m.exception;
917 }
918
919 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */
920 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
921 {
922 if (mask & CPSR_NZCV) {
923 env->ZF = (~val) & CPSR_Z;
924 env->NF = val;
925 env->CF = (val >> 29) & 1;
926 env->VF = (val << 3) & 0x80000000;
927 }
928 if (mask & CPSR_Q)
929 env->QF = ((val & CPSR_Q) != 0);
930 if (mask & (1 << 24))
931 env->thumb = ((val & (1 << 24)) != 0);
932 if (mask & CPSR_IT_0_1) {
933 env->condexec_bits &= ~3;
934 env->condexec_bits |= (val >> 25) & 3;
935 }
936 if (mask & CPSR_IT_2_7) {
937 env->condexec_bits &= 3;
938 env->condexec_bits |= (val >> 8) & 0xfc;
939 }
940 if (mask & 0x1ff) {
941 env->v7m.exception = val & 0x1ff;
942 }
943 }
944
945 #define HCR_VM (1ULL << 0)
946 #define HCR_SWIO (1ULL << 1)
947 #define HCR_PTW (1ULL << 2)
948 #define HCR_FMO (1ULL << 3)
949 #define HCR_IMO (1ULL << 4)
950 #define HCR_AMO (1ULL << 5)
951 #define HCR_VF (1ULL << 6)
952 #define HCR_VI (1ULL << 7)
953 #define HCR_VSE (1ULL << 8)
954 #define HCR_FB (1ULL << 9)
955 #define HCR_BSU_MASK (3ULL << 10)
956 #define HCR_DC (1ULL << 12)
957 #define HCR_TWI (1ULL << 13)
958 #define HCR_TWE (1ULL << 14)
959 #define HCR_TID0 (1ULL << 15)
960 #define HCR_TID1 (1ULL << 16)
961 #define HCR_TID2 (1ULL << 17)
962 #define HCR_TID3 (1ULL << 18)
963 #define HCR_TSC (1ULL << 19)
964 #define HCR_TIDCP (1ULL << 20)
965 #define HCR_TACR (1ULL << 21)
966 #define HCR_TSW (1ULL << 22)
967 #define HCR_TPC (1ULL << 23)
968 #define HCR_TPU (1ULL << 24)
969 #define HCR_TTLB (1ULL << 25)
970 #define HCR_TVM (1ULL << 26)
971 #define HCR_TGE (1ULL << 27)
972 #define HCR_TDZ (1ULL << 28)
973 #define HCR_HCD (1ULL << 29)
974 #define HCR_TRVM (1ULL << 30)
975 #define HCR_RW (1ULL << 31)
976 #define HCR_CD (1ULL << 32)
977 #define HCR_ID (1ULL << 33)
978 #define HCR_MASK ((1ULL << 34) - 1)
979
980 #define SCR_NS (1U << 0)
981 #define SCR_IRQ (1U << 1)
982 #define SCR_FIQ (1U << 2)
983 #define SCR_EA (1U << 3)
984 #define SCR_FW (1U << 4)
985 #define SCR_AW (1U << 5)
986 #define SCR_NET (1U << 6)
987 #define SCR_SMD (1U << 7)
988 #define SCR_HCE (1U << 8)
989 #define SCR_SIF (1U << 9)
990 #define SCR_RW (1U << 10)
991 #define SCR_ST (1U << 11)
992 #define SCR_TWI (1U << 12)
993 #define SCR_TWE (1U << 13)
994 #define SCR_AARCH32_MASK (0x3fff & ~(SCR_RW | SCR_ST))
995 #define SCR_AARCH64_MASK (0x3fff & ~SCR_NET)
996
997 /* Return the current FPSCR value. */
998 uint32_t vfp_get_fpscr(CPUARMState *env);
999 void vfp_set_fpscr(CPUARMState *env, uint32_t val);
1000
1001 /* For A64 the FPSCR is split into two logically distinct registers,
1002 * FPCR and FPSR. However since they still use non-overlapping bits
1003 * we store the underlying state in fpscr and just mask on read/write.
1004 */
1005 #define FPSR_MASK 0xf800009f
1006 #define FPCR_MASK 0x07f79f00
1007 static inline uint32_t vfp_get_fpsr(CPUARMState *env)
1008 {
1009 return vfp_get_fpscr(env) & FPSR_MASK;
1010 }
1011
1012 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val)
1013 {
1014 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK);
1015 vfp_set_fpscr(env, new_fpscr);
1016 }
1017
1018 static inline uint32_t vfp_get_fpcr(CPUARMState *env)
1019 {
1020 return vfp_get_fpscr(env) & FPCR_MASK;
1021 }
1022
1023 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val)
1024 {
1025 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK);
1026 vfp_set_fpscr(env, new_fpscr);
1027 }
1028
1029 enum arm_cpu_mode {
1030 ARM_CPU_MODE_USR = 0x10,
1031 ARM_CPU_MODE_FIQ = 0x11,
1032 ARM_CPU_MODE_IRQ = 0x12,
1033 ARM_CPU_MODE_SVC = 0x13,
1034 ARM_CPU_MODE_MON = 0x16,
1035 ARM_CPU_MODE_ABT = 0x17,
1036 ARM_CPU_MODE_HYP = 0x1a,
1037 ARM_CPU_MODE_UND = 0x1b,
1038 ARM_CPU_MODE_SYS = 0x1f
1039 };
1040
1041 /* VFP system registers. */
1042 #define ARM_VFP_FPSID 0
1043 #define ARM_VFP_FPSCR 1
1044 #define ARM_VFP_MVFR2 5
1045 #define ARM_VFP_MVFR1 6
1046 #define ARM_VFP_MVFR0 7
1047 #define ARM_VFP_FPEXC 8
1048 #define ARM_VFP_FPINST 9
1049 #define ARM_VFP_FPINST2 10
1050
1051 /* iwMMXt coprocessor control registers. */
1052 #define ARM_IWMMXT_wCID 0
1053 #define ARM_IWMMXT_wCon 1
1054 #define ARM_IWMMXT_wCSSF 2
1055 #define ARM_IWMMXT_wCASF 3
1056 #define ARM_IWMMXT_wCGR0 8
1057 #define ARM_IWMMXT_wCGR1 9
1058 #define ARM_IWMMXT_wCGR2 10
1059 #define ARM_IWMMXT_wCGR3 11
1060
1061 /* If adding a feature bit which corresponds to a Linux ELF
1062 * HWCAP bit, remember to update the feature-bit-to-hwcap
1063 * mapping in linux-user/elfload.c:get_elf_hwcap().
1064 */
1065 enum arm_features {
1066 ARM_FEATURE_VFP,
1067 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */
1068 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */
1069 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */
1070 ARM_FEATURE_V6,
1071 ARM_FEATURE_V6K,
1072 ARM_FEATURE_V7,
1073 ARM_FEATURE_THUMB2,
1074 ARM_FEATURE_MPU, /* Only has Memory Protection Unit, not full MMU. */
1075 ARM_FEATURE_VFP3,
1076 ARM_FEATURE_VFP_FP16,
1077 ARM_FEATURE_NEON,
1078 ARM_FEATURE_THUMB_DIV, /* divide supported in Thumb encoding */
1079 ARM_FEATURE_M, /* Microcontroller profile. */
1080 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */
1081 ARM_FEATURE_THUMB2EE,
1082 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */
1083 ARM_FEATURE_V4T,
1084 ARM_FEATURE_V5,
1085 ARM_FEATURE_STRONGARM,
1086 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */
1087 ARM_FEATURE_ARM_DIV, /* divide supported in ARM encoding */
1088 ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */
1089 ARM_FEATURE_GENERIC_TIMER,
1090 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */
1091 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */
1092 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */
1093 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */
1094 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */
1095 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */
1096 ARM_FEATURE_PXN, /* has Privileged Execute Never bit */
1097 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */
1098 ARM_FEATURE_V8,
1099 ARM_FEATURE_AARCH64, /* supports 64 bit mode */
1100 ARM_FEATURE_V8_AES, /* implements AES part of v8 Crypto Extensions */
1101 ARM_FEATURE_CBAR, /* has cp15 CBAR */
1102 ARM_FEATURE_CRC, /* ARMv8 CRC instructions */
1103 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */
1104 ARM_FEATURE_EL2, /* has EL2 Virtualization support */
1105 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */
1106 ARM_FEATURE_V8_SHA1, /* implements SHA1 part of v8 Crypto Extensions */
1107 ARM_FEATURE_V8_SHA256, /* implements SHA256 part of v8 Crypto Extensions */
1108 ARM_FEATURE_V8_PMULL, /* implements PMULL part of v8 Crypto Extensions */
1109 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */
1110 };
1111
1112 static inline int arm_feature(CPUARMState *env, int feature)
1113 {
1114 return (env->features & (1ULL << feature)) != 0;
1115 }
1116
1117 #if !defined(CONFIG_USER_ONLY)
1118 /* Return true if exception levels below EL3 are in secure state,
1119 * or would be following an exception return to that level.
1120 * Unlike arm_is_secure() (which is always a question about the
1121 * _current_ state of the CPU) this doesn't care about the current
1122 * EL or mode.
1123 */
1124 static inline bool arm_is_secure_below_el3(CPUARMState *env)
1125 {
1126 if (arm_feature(env, ARM_FEATURE_EL3)) {
1127 return !(env->cp15.scr_el3 & SCR_NS);
1128 } else {
1129 /* If EL3 is not supported then the secure state is implementation
1130 * defined, in which case QEMU defaults to non-secure.
1131 */
1132 return false;
1133 }
1134 }
1135
1136 /* Return true if the processor is in secure state */
1137 static inline bool arm_is_secure(CPUARMState *env)
1138 {
1139 if (arm_feature(env, ARM_FEATURE_EL3)) {
1140 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) {
1141 /* CPU currently in AArch64 state and EL3 */
1142 return true;
1143 } else if (!is_a64(env) &&
1144 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
1145 /* CPU currently in AArch32 state and monitor mode */
1146 return true;
1147 }
1148 }
1149 return arm_is_secure_below_el3(env);
1150 }
1151
1152 #else
1153 static inline bool arm_is_secure_below_el3(CPUARMState *env)
1154 {
1155 return false;
1156 }
1157
1158 static inline bool arm_is_secure(CPUARMState *env)
1159 {
1160 return false;
1161 }
1162 #endif
1163
1164 /* Return true if the specified exception level is running in AArch64 state. */
1165 static inline bool arm_el_is_aa64(CPUARMState *env, int el)
1166 {
1167 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want,
1168 * and if we're not in EL0 then the state of EL0 isn't well defined.)
1169 */
1170 assert(el >= 1 && el <= 3);
1171 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64);
1172
1173 /* The highest exception level is always at the maximum supported
1174 * register width, and then lower levels have a register width controlled
1175 * by bits in the SCR or HCR registers.
1176 */
1177 if (el == 3) {
1178 return aa64;
1179 }
1180
1181 if (arm_feature(env, ARM_FEATURE_EL3)) {
1182 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW);
1183 }
1184
1185 if (el == 2) {
1186 return aa64;
1187 }
1188
1189 if (arm_feature(env, ARM_FEATURE_EL2) && !arm_is_secure_below_el3(env)) {
1190 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW);
1191 }
1192
1193 return aa64;
1194 }
1195
1196 /* Function for determing whether guest cp register reads and writes should
1197 * access the secure or non-secure bank of a cp register. When EL3 is
1198 * operating in AArch32 state, the NS-bit determines whether the secure
1199 * instance of a cp register should be used. When EL3 is AArch64 (or if
1200 * it doesn't exist at all) then there is no register banking, and all
1201 * accesses are to the non-secure version.
1202 */
1203 static inline bool access_secure_reg(CPUARMState *env)
1204 {
1205 bool ret = (arm_feature(env, ARM_FEATURE_EL3) &&
1206 !arm_el_is_aa64(env, 3) &&
1207 !(env->cp15.scr_el3 & SCR_NS));
1208
1209 return ret;
1210 }
1211
1212 /* Macros for accessing a specified CP register bank */
1213 #define A32_BANKED_REG_GET(_env, _regname, _secure) \
1214 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns)
1215
1216 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \
1217 do { \
1218 if (_secure) { \
1219 (_env)->cp15._regname##_s = (_val); \
1220 } else { \
1221 (_env)->cp15._regname##_ns = (_val); \
1222 } \
1223 } while (0)
1224
1225 /* Macros for automatically accessing a specific CP register bank depending on
1226 * the current secure state of the system. These macros are not intended for
1227 * supporting instruction translation reads/writes as these are dependent
1228 * solely on the SCR.NS bit and not the mode.
1229 */
1230 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \
1231 A32_BANKED_REG_GET((_env), _regname, \
1232 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)))
1233
1234 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \
1235 A32_BANKED_REG_SET((_env), _regname, \
1236 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \
1237 (_val))
1238
1239 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf);
1240 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
1241 uint32_t cur_el, bool secure);
1242
1243 /* Interface between CPU and Interrupt controller. */
1244 void armv7m_nvic_set_pending(void *opaque, int irq);
1245 int armv7m_nvic_acknowledge_irq(void *opaque);
1246 void armv7m_nvic_complete_irq(void *opaque, int irq);
1247
1248 /* Interface for defining coprocessor registers.
1249 * Registers are defined in tables of arm_cp_reginfo structs
1250 * which are passed to define_arm_cp_regs().
1251 */
1252
1253 /* When looking up a coprocessor register we look for it
1254 * via an integer which encodes all of:
1255 * coprocessor number
1256 * Crn, Crm, opc1, opc2 fields
1257 * 32 or 64 bit register (ie is it accessed via MRC/MCR
1258 * or via MRRC/MCRR?)
1259 * non-secure/secure bank (AArch32 only)
1260 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field.
1261 * (In this case crn and opc2 should be zero.)
1262 * For AArch64, there is no 32/64 bit size distinction;
1263 * instead all registers have a 2 bit op0, 3 bit op1 and op2,
1264 * and 4 bit CRn and CRm. The encoding patterns are chosen
1265 * to be easy to convert to and from the KVM encodings, and also
1266 * so that the hashtable can contain both AArch32 and AArch64
1267 * registers (to allow for interprocessing where we might run
1268 * 32 bit code on a 64 bit core).
1269 */
1270 /* This bit is private to our hashtable cpreg; in KVM register
1271 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64
1272 * in the upper bits of the 64 bit ID.
1273 */
1274 #define CP_REG_AA64_SHIFT 28
1275 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT)
1276
1277 /* To enable banking of coprocessor registers depending on ns-bit we
1278 * add a bit to distinguish between secure and non-secure cpregs in the
1279 * hashtable.
1280 */
1281 #define CP_REG_NS_SHIFT 29
1282 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT)
1283
1284 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \
1285 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \
1286 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
1287
1288 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \
1289 (CP_REG_AA64_MASK | \
1290 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \
1291 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \
1292 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \
1293 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \
1294 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \
1295 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
1296
1297 /* Convert a full 64 bit KVM register ID to the truncated 32 bit
1298 * version used as a key for the coprocessor register hashtable
1299 */
1300 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid)
1301 {
1302 uint32_t cpregid = kvmid;
1303 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) {
1304 cpregid |= CP_REG_AA64_MASK;
1305 } else {
1306 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) {
1307 cpregid |= (1 << 15);
1308 }
1309
1310 /* KVM is always non-secure so add the NS flag on AArch32 register
1311 * entries.
1312 */
1313 cpregid |= 1 << CP_REG_NS_SHIFT;
1314 }
1315 return cpregid;
1316 }
1317
1318 /* Convert a truncated 32 bit hashtable key into the full
1319 * 64 bit KVM register ID.
1320 */
1321 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
1322 {
1323 uint64_t kvmid;
1324
1325 if (cpregid & CP_REG_AA64_MASK) {
1326 kvmid = cpregid & ~CP_REG_AA64_MASK;
1327 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64;
1328 } else {
1329 kvmid = cpregid & ~(1 << 15);
1330 if (cpregid & (1 << 15)) {
1331 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM;
1332 } else {
1333 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM;
1334 }
1335 }
1336 return kvmid;
1337 }
1338
1339 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a
1340 * special-behaviour cp reg and bits [15..8] indicate what behaviour
1341 * it has. Otherwise it is a simple cp reg, where CONST indicates that
1342 * TCG can assume the value to be constant (ie load at translate time)
1343 * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END
1344 * indicates that the TB should not be ended after a write to this register
1345 * (the default is that the TB ends after cp writes). OVERRIDE permits
1346 * a register definition to override a previous definition for the
1347 * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the
1348 * old must have the OVERRIDE bit set.
1349 * ALIAS indicates that this register is an alias view of some underlying
1350 * state which is also visible via another register, and that the other
1351 * register is handling migration and reset; registers marked ALIAS will not be
1352 * migrated but may have their state set by syncing of register state from KVM.
1353 * NO_RAW indicates that this register has no underlying state and does not
1354 * support raw access for state saving/loading; it will not be used for either
1355 * migration or KVM state synchronization. (Typically this is for "registers"
1356 * which are actually used as instructions for cache maintenance and so on.)
1357 * IO indicates that this register does I/O and therefore its accesses
1358 * need to be surrounded by gen_io_start()/gen_io_end(). In particular,
1359 * registers which implement clocks or timers require this.
1360 */
1361 #define ARM_CP_SPECIAL 1
1362 #define ARM_CP_CONST 2
1363 #define ARM_CP_64BIT 4
1364 #define ARM_CP_SUPPRESS_TB_END 8
1365 #define ARM_CP_OVERRIDE 16
1366 #define ARM_CP_ALIAS 32
1367 #define ARM_CP_IO 64
1368 #define ARM_CP_NO_RAW 128
1369 #define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8))
1370 #define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8))
1371 #define ARM_CP_NZCV (ARM_CP_SPECIAL | (3 << 8))
1372 #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | (4 << 8))
1373 #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | (5 << 8))
1374 #define ARM_LAST_SPECIAL ARM_CP_DC_ZVA
1375 /* Used only as a terminator for ARMCPRegInfo lists */
1376 #define ARM_CP_SENTINEL 0xffff
1377 /* Mask of only the flag bits in a type field */
1378 #define ARM_CP_FLAG_MASK 0xff
1379
1380 /* Valid values for ARMCPRegInfo state field, indicating which of
1381 * the AArch32 and AArch64 execution states this register is visible in.
1382 * If the reginfo doesn't explicitly specify then it is AArch32 only.
1383 * If the reginfo is declared to be visible in both states then a second
1384 * reginfo is synthesised for the AArch32 view of the AArch64 register,
1385 * such that the AArch32 view is the lower 32 bits of the AArch64 one.
1386 * Note that we rely on the values of these enums as we iterate through
1387 * the various states in some places.
1388 */
1389 enum {
1390 ARM_CP_STATE_AA32 = 0,
1391 ARM_CP_STATE_AA64 = 1,
1392 ARM_CP_STATE_BOTH = 2,
1393 };
1394
1395 /* ARM CP register secure state flags. These flags identify security state
1396 * attributes for a given CP register entry.
1397 * The existence of both or neither secure and non-secure flags indicates that
1398 * the register has both a secure and non-secure hash entry. A single one of
1399 * these flags causes the register to only be hashed for the specified
1400 * security state.
1401 * Although definitions may have any combination of the S/NS bits, each
1402 * registered entry will only have one to identify whether the entry is secure
1403 * or non-secure.
1404 */
1405 enum {
1406 ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */
1407 ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */
1408 };
1409
1410 /* Return true if cptype is a valid type field. This is used to try to
1411 * catch errors where the sentinel has been accidentally left off the end
1412 * of a list of registers.
1413 */
1414 static inline bool cptype_valid(int cptype)
1415 {
1416 return ((cptype & ~ARM_CP_FLAG_MASK) == 0)
1417 || ((cptype & ARM_CP_SPECIAL) &&
1418 ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL));
1419 }
1420
1421 /* Access rights:
1422 * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM
1423 * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and
1424 * PL2 (hyp). The other level which has Read and Write bits is Secure PL1
1425 * (ie any of the privileged modes in Secure state, or Monitor mode).
1426 * If a register is accessible in one privilege level it's always accessible
1427 * in higher privilege levels too. Since "Secure PL1" also follows this rule
1428 * (ie anything visible in PL2 is visible in S-PL1, some things are only
1429 * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the
1430 * terminology a little and call this PL3.
1431 * In AArch64 things are somewhat simpler as the PLx bits line up exactly
1432 * with the ELx exception levels.
1433 *
1434 * If access permissions for a register are more complex than can be
1435 * described with these bits, then use a laxer set of restrictions, and
1436 * do the more restrictive/complex check inside a helper function.
1437 */
1438 #define PL3_R 0x80
1439 #define PL3_W 0x40
1440 #define PL2_R (0x20 | PL3_R)
1441 #define PL2_W (0x10 | PL3_W)
1442 #define PL1_R (0x08 | PL2_R)
1443 #define PL1_W (0x04 | PL2_W)
1444 #define PL0_R (0x02 | PL1_R)
1445 #define PL0_W (0x01 | PL1_W)
1446
1447 #define PL3_RW (PL3_R | PL3_W)
1448 #define PL2_RW (PL2_R | PL2_W)
1449 #define PL1_RW (PL1_R | PL1_W)
1450 #define PL0_RW (PL0_R | PL0_W)
1451
1452 /* Return the highest implemented Exception Level */
1453 static inline int arm_highest_el(CPUARMState *env)
1454 {
1455 if (arm_feature(env, ARM_FEATURE_EL3)) {
1456 return 3;
1457 }
1458 if (arm_feature(env, ARM_FEATURE_EL2)) {
1459 return 2;
1460 }
1461 return 1;
1462 }
1463
1464 /* Return the current Exception Level (as per ARMv8; note that this differs
1465 * from the ARMv7 Privilege Level).
1466 */
1467 static inline int arm_current_el(CPUARMState *env)
1468 {
1469 if (arm_feature(env, ARM_FEATURE_M)) {
1470 return !((env->v7m.exception == 0) && (env->v7m.control & 1));
1471 }
1472
1473 if (is_a64(env)) {
1474 return extract32(env->pstate, 2, 2);
1475 }
1476
1477 switch (env->uncached_cpsr & 0x1f) {
1478 case ARM_CPU_MODE_USR:
1479 return 0;
1480 case ARM_CPU_MODE_HYP:
1481 return 2;
1482 case ARM_CPU_MODE_MON:
1483 return 3;
1484 default:
1485 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) {
1486 /* If EL3 is 32-bit then all secure privileged modes run in
1487 * EL3
1488 */
1489 return 3;
1490 }
1491
1492 return 1;
1493 }
1494 }
1495
1496 typedef struct ARMCPRegInfo ARMCPRegInfo;
1497
1498 typedef enum CPAccessResult {
1499 /* Access is permitted */
1500 CP_ACCESS_OK = 0,
1501 /* Access fails due to a configurable trap or enable which would
1502 * result in a categorized exception syndrome giving information about
1503 * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6,
1504 * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or
1505 * PL1 if in EL0, otherwise to the current EL).
1506 */
1507 CP_ACCESS_TRAP = 1,
1508 /* Access fails and results in an exception syndrome 0x0 ("uncategorized").
1509 * Note that this is not a catch-all case -- the set of cases which may
1510 * result in this failure is specifically defined by the architecture.
1511 */
1512 CP_ACCESS_TRAP_UNCATEGORIZED = 2,
1513 /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */
1514 CP_ACCESS_TRAP_EL2 = 3,
1515 CP_ACCESS_TRAP_EL3 = 4,
1516 /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */
1517 CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5,
1518 CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6,
1519 /* Access fails and results in an exception syndrome for an FP access,
1520 * trapped directly to EL2 or EL3
1521 */
1522 CP_ACCESS_TRAP_FP_EL2 = 7,
1523 CP_ACCESS_TRAP_FP_EL3 = 8,
1524 } CPAccessResult;
1525
1526 /* Access functions for coprocessor registers. These cannot fail and
1527 * may not raise exceptions.
1528 */
1529 typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque);
1530 typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque,
1531 uint64_t value);
1532 /* Access permission check functions for coprocessor registers. */
1533 typedef CPAccessResult CPAccessFn(CPUARMState *env,
1534 const ARMCPRegInfo *opaque,
1535 bool isread);
1536 /* Hook function for register reset */
1537 typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque);
1538
1539 #define CP_ANY 0xff
1540
1541 /* Definition of an ARM coprocessor register */
1542 struct ARMCPRegInfo {
1543 /* Name of register (useful mainly for debugging, need not be unique) */
1544 const char *name;
1545 /* Location of register: coprocessor number and (crn,crm,opc1,opc2)
1546 * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a
1547 * 'wildcard' field -- any value of that field in the MRC/MCR insn
1548 * will be decoded to this register. The register read and write
1549 * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2
1550 * used by the program, so it is possible to register a wildcard and
1551 * then behave differently on read/write if necessary.
1552 * For 64 bit registers, only crm and opc1 are relevant; crn and opc2
1553 * must both be zero.
1554 * For AArch64-visible registers, opc0 is also used.
1555 * Since there are no "coprocessors" in AArch64, cp is purely used as a
1556 * way to distinguish (for KVM's benefit) guest-visible system registers
1557 * from demuxed ones provided to preserve the "no side effects on
1558 * KVM register read/write from QEMU" semantics. cp==0x13 is guest
1559 * visible (to match KVM's encoding); cp==0 will be converted to
1560 * cp==0x13 when the ARMCPRegInfo is registered, for convenience.
1561 */
1562 uint8_t cp;
1563 uint8_t crn;
1564 uint8_t crm;
1565 uint8_t opc0;
1566 uint8_t opc1;
1567 uint8_t opc2;
1568 /* Execution state in which this register is visible: ARM_CP_STATE_* */
1569 int state;
1570 /* Register type: ARM_CP_* bits/values */
1571 int type;
1572 /* Access rights: PL*_[RW] */
1573 int access;
1574 /* Security state: ARM_CP_SECSTATE_* bits/values */
1575 int secure;
1576 /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when
1577 * this register was defined: can be used to hand data through to the
1578 * register read/write functions, since they are passed the ARMCPRegInfo*.
1579 */
1580 void *opaque;
1581 /* Value of this register, if it is ARM_CP_CONST. Otherwise, if
1582 * fieldoffset is non-zero, the reset value of the register.
1583 */
1584 uint64_t resetvalue;
1585 /* Offset of the field in CPUARMState for this register.
1586 *
1587 * This is not needed if either:
1588 * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs
1589 * 2. both readfn and writefn are specified
1590 */
1591 ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */
1592
1593 /* Offsets of the secure and non-secure fields in CPUARMState for the
1594 * register if it is banked. These fields are only used during the static
1595 * registration of a register. During hashing the bank associated
1596 * with a given security state is copied to fieldoffset which is used from
1597 * there on out.
1598 *
1599 * It is expected that register definitions use either fieldoffset or
1600 * bank_fieldoffsets in the definition but not both. It is also expected
1601 * that both bank offsets are set when defining a banked register. This
1602 * use indicates that a register is banked.
1603 */
1604 ptrdiff_t bank_fieldoffsets[2];
1605
1606 /* Function for making any access checks for this register in addition to
1607 * those specified by the 'access' permissions bits. If NULL, no extra
1608 * checks required. The access check is performed at runtime, not at
1609 * translate time.
1610 */
1611 CPAccessFn *accessfn;
1612 /* Function for handling reads of this register. If NULL, then reads
1613 * will be done by loading from the offset into CPUARMState specified
1614 * by fieldoffset.
1615 */
1616 CPReadFn *readfn;
1617 /* Function for handling writes of this register. If NULL, then writes
1618 * will be done by writing to the offset into CPUARMState specified
1619 * by fieldoffset.
1620 */
1621 CPWriteFn *writefn;
1622 /* Function for doing a "raw" read; used when we need to copy
1623 * coprocessor state to the kernel for KVM or out for
1624 * migration. This only needs to be provided if there is also a
1625 * readfn and it has side effects (for instance clear-on-read bits).
1626 */
1627 CPReadFn *raw_readfn;
1628 /* Function for doing a "raw" write; used when we need to copy KVM
1629 * kernel coprocessor state into userspace, or for inbound
1630 * migration. This only needs to be provided if there is also a
1631 * writefn and it masks out "unwritable" bits or has write-one-to-clear
1632 * or similar behaviour.
1633 */
1634 CPWriteFn *raw_writefn;
1635 /* Function for resetting the register. If NULL, then reset will be done
1636 * by writing resetvalue to the field specified in fieldoffset. If
1637 * fieldoffset is 0 then no reset will be done.
1638 */
1639 CPResetFn *resetfn;
1640 };
1641
1642 /* Macros which are lvalues for the field in CPUARMState for the
1643 * ARMCPRegInfo *ri.
1644 */
1645 #define CPREG_FIELD32(env, ri) \
1646 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
1647 #define CPREG_FIELD64(env, ri) \
1648 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
1649
1650 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
1651
1652 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
1653 const ARMCPRegInfo *regs, void *opaque);
1654 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
1655 const ARMCPRegInfo *regs, void *opaque);
1656 static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs)
1657 {
1658 define_arm_cp_regs_with_opaque(cpu, regs, 0);
1659 }
1660 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)
1661 {
1662 define_one_arm_cp_reg_with_opaque(cpu, regs, 0);
1663 }
1664 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp);
1665
1666 /* CPWriteFn that can be used to implement writes-ignored behaviour */
1667 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
1668 uint64_t value);
1669 /* CPReadFn that can be used for read-as-zero behaviour */
1670 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri);
1671
1672 /* CPResetFn that does nothing, for use if no reset is required even
1673 * if fieldoffset is non zero.
1674 */
1675 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque);
1676
1677 /* Return true if this reginfo struct's field in the cpu state struct
1678 * is 64 bits wide.
1679 */
1680 static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri)
1681 {
1682 return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT);
1683 }
1684
1685 static inline bool cp_access_ok(int current_el,
1686 const ARMCPRegInfo *ri, int isread)
1687 {
1688 return (ri->access >> ((current_el * 2) + isread)) & 1;
1689 }
1690
1691 /* Raw read of a coprocessor register (as needed for migration, etc) */
1692 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri);
1693
1694 /**
1695 * write_list_to_cpustate
1696 * @cpu: ARMCPU
1697 *
1698 * For each register listed in the ARMCPU cpreg_indexes list, write
1699 * its value from the cpreg_values list into the ARMCPUState structure.
1700 * This updates TCG's working data structures from KVM data or
1701 * from incoming migration state.
1702 *
1703 * Returns: true if all register values were updated correctly,
1704 * false if some register was unknown or could not be written.
1705 * Note that we do not stop early on failure -- we will attempt
1706 * writing all registers in the list.
1707 */
1708 bool write_list_to_cpustate(ARMCPU *cpu);
1709
1710 /**
1711 * write_cpustate_to_list:
1712 * @cpu: ARMCPU
1713 *
1714 * For each register listed in the ARMCPU cpreg_indexes list, write
1715 * its value from the ARMCPUState structure into the cpreg_values list.
1716 * This is used to copy info from TCG's working data structures into
1717 * KVM or for outbound migration.
1718 *
1719 * Returns: true if all register values were read correctly,
1720 * false if some register was unknown or could not be read.
1721 * Note that we do not stop early on failure -- we will attempt
1722 * reading all registers in the list.
1723 */
1724 bool write_cpustate_to_list(ARMCPU *cpu);
1725
1726 /* Does the core conform to the "MicroController" profile. e.g. Cortex-M3.
1727 Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are
1728 conventional cores (ie. Application or Realtime profile). */
1729
1730 #define IS_M(env) arm_feature(env, ARM_FEATURE_M)
1731
1732 #define ARM_CPUID_TI915T 0x54029152
1733 #define ARM_CPUID_TI925T 0x54029252
1734
1735 #if defined(CONFIG_USER_ONLY)
1736 #define TARGET_PAGE_BITS 12
1737 #else
1738 /* The ARM MMU allows 1k pages. */
1739 /* ??? Linux doesn't actually use these, and they're deprecated in recent
1740 architecture revisions. Maybe a configure option to disable them. */
1741 #define TARGET_PAGE_BITS 10
1742 #endif
1743
1744 #if defined(TARGET_AARCH64)
1745 # define TARGET_PHYS_ADDR_SPACE_BITS 48
1746 # define TARGET_VIRT_ADDR_SPACE_BITS 64
1747 #else
1748 # define TARGET_PHYS_ADDR_SPACE_BITS 40
1749 # define TARGET_VIRT_ADDR_SPACE_BITS 32
1750 #endif
1751
1752 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
1753 unsigned int target_el)
1754 {
1755 CPUARMState *env = cs->env_ptr;
1756 unsigned int cur_el = arm_current_el(env);
1757 bool secure = arm_is_secure(env);
1758 bool pstate_unmasked;
1759 int8_t unmasked = 0;
1760
1761 /* Don't take exceptions if they target a lower EL.
1762 * This check should catch any exceptions that would not be taken but left
1763 * pending.
1764 */
1765 if (cur_el > target_el) {
1766 return false;
1767 }
1768
1769 switch (excp_idx) {
1770 case EXCP_FIQ:
1771 pstate_unmasked = !(env->daif & PSTATE_F);
1772 break;
1773
1774 case EXCP_IRQ:
1775 pstate_unmasked = !(env->daif & PSTATE_I);
1776 break;
1777
1778 case EXCP_VFIQ:
1779 if (secure || !(env->cp15.hcr_el2 & HCR_FMO)) {
1780 /* VFIQs are only taken when hypervized and non-secure. */
1781 return false;
1782 }
1783 return !(env->daif & PSTATE_F);
1784 case EXCP_VIRQ:
1785 if (secure || !(env->cp15.hcr_el2 & HCR_IMO)) {
1786 /* VIRQs are only taken when hypervized and non-secure. */
1787 return false;
1788 }
1789 return !(env->daif & PSTATE_I);
1790 default:
1791 g_assert_not_reached();
1792 }
1793
1794 /* Use the target EL, current execution state and SCR/HCR settings to
1795 * determine whether the corresponding CPSR bit is used to mask the
1796 * interrupt.
1797 */
1798 if ((target_el > cur_el) && (target_el != 1)) {
1799 /* Exceptions targeting a higher EL may not be maskable */
1800 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
1801 /* 64-bit masking rules are simple: exceptions to EL3
1802 * can't be masked, and exceptions to EL2 can only be
1803 * masked from Secure state. The HCR and SCR settings
1804 * don't affect the masking logic, only the interrupt routing.
1805 */
1806 if (target_el == 3 || !secure) {
1807 unmasked = 1;
1808 }
1809 } else {
1810 /* The old 32-bit-only environment has a more complicated
1811 * masking setup. HCR and SCR bits not only affect interrupt
1812 * routing but also change the behaviour of masking.
1813 */
1814 bool hcr, scr;
1815
1816 switch (excp_idx) {
1817 case EXCP_FIQ:
1818 /* If FIQs are routed to EL3 or EL2 then there are cases where
1819 * we override the CPSR.F in determining if the exception is
1820 * masked or not. If neither of these are set then we fall back
1821 * to the CPSR.F setting otherwise we further assess the state
1822 * below.
1823 */
1824 hcr = (env->cp15.hcr_el2 & HCR_FMO);
1825 scr = (env->cp15.scr_el3 & SCR_FIQ);
1826
1827 /* When EL3 is 32-bit, the SCR.FW bit controls whether the
1828 * CPSR.F bit masks FIQ interrupts when taken in non-secure
1829 * state. If SCR.FW is set then FIQs can be masked by CPSR.F
1830 * when non-secure but only when FIQs are only routed to EL3.
1831 */
1832 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr);
1833 break;
1834 case EXCP_IRQ:
1835 /* When EL3 execution state is 32-bit, if HCR.IMO is set then
1836 * we may override the CPSR.I masking when in non-secure state.
1837 * The SCR.IRQ setting has already been taken into consideration
1838 * when setting the target EL, so it does not have a further
1839 * affect here.
1840 */
1841 hcr = (env->cp15.hcr_el2 & HCR_IMO);
1842 scr = false;
1843 break;
1844 default:
1845 g_assert_not_reached();
1846 }
1847
1848 if ((scr || hcr) && !secure) {
1849 unmasked = 1;
1850 }
1851 }
1852 }
1853
1854 /* The PSTATE bits only mask the interrupt if we have not overriden the
1855 * ability above.
1856 */
1857 return unmasked || pstate_unmasked;
1858 }
1859
1860 #define cpu_init(cpu_model) CPU(cpu_arm_init(cpu_model))
1861
1862 #define cpu_exec cpu_arm_exec
1863 #define cpu_signal_handler cpu_arm_signal_handler
1864 #define cpu_list arm_cpu_list
1865
1866 /* ARM has the following "translation regimes" (as the ARM ARM calls them):
1867 *
1868 * If EL3 is 64-bit:
1869 * + NonSecure EL1 & 0 stage 1
1870 * + NonSecure EL1 & 0 stage 2
1871 * + NonSecure EL2
1872 * + Secure EL1 & EL0
1873 * + Secure EL3
1874 * If EL3 is 32-bit:
1875 * + NonSecure PL1 & 0 stage 1
1876 * + NonSecure PL1 & 0 stage 2
1877 * + NonSecure PL2
1878 * + Secure PL0 & PL1
1879 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.)
1880 *
1881 * For QEMU, an mmu_idx is not quite the same as a translation regime because:
1882 * 1. we need to split the "EL1 & 0" regimes into two mmu_idxes, because they
1883 * may differ in access permissions even if the VA->PA map is the same
1884 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2
1885 * translation, which means that we have one mmu_idx that deals with two
1886 * concatenated translation regimes [this sort of combined s1+2 TLB is
1887 * architecturally permitted]
1888 * 3. we don't need to allocate an mmu_idx to translations that we won't be
1889 * handling via the TLB. The only way to do a stage 1 translation without
1890 * the immediate stage 2 translation is via the ATS or AT system insns,
1891 * which can be slow-pathed and always do a page table walk.
1892 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3"
1893 * translation regimes, because they map reasonably well to each other
1894 * and they can't both be active at the same time.
1895 * This gives us the following list of mmu_idx values:
1896 *
1897 * NS EL0 (aka NS PL0) stage 1+2
1898 * NS EL1 (aka NS PL1) stage 1+2
1899 * NS EL2 (aka NS PL2)
1900 * S EL3 (aka S PL1)
1901 * S EL0 (aka S PL0)
1902 * S EL1 (not used if EL3 is 32 bit)
1903 * NS EL0+1 stage 2
1904 *
1905 * (The last of these is an mmu_idx because we want to be able to use the TLB
1906 * for the accesses done as part of a stage 1 page table walk, rather than
1907 * having to walk the stage 2 page table over and over.)
1908 *
1909 * Our enumeration includes at the end some entries which are not "true"
1910 * mmu_idx values in that they don't have corresponding TLBs and are only
1911 * valid for doing slow path page table walks.
1912 *
1913 * The constant names here are patterned after the general style of the names
1914 * of the AT/ATS operations.
1915 * The values used are carefully arranged to make mmu_idx => EL lookup easy.
1916 */
1917 typedef enum ARMMMUIdx {
1918 ARMMMUIdx_S12NSE0 = 0,
1919 ARMMMUIdx_S12NSE1 = 1,
1920 ARMMMUIdx_S1E2 = 2,
1921 ARMMMUIdx_S1E3 = 3,
1922 ARMMMUIdx_S1SE0 = 4,
1923 ARMMMUIdx_S1SE1 = 5,
1924 ARMMMUIdx_S2NS = 6,
1925 /* Indexes below here don't have TLBs and are used only for AT system
1926 * instructions or for the first stage of an S12 page table walk.
1927 */
1928 ARMMMUIdx_S1NSE0 = 7,
1929 ARMMMUIdx_S1NSE1 = 8,
1930 } ARMMMUIdx;
1931
1932 #define MMU_USER_IDX 0
1933
1934 /* Return the exception level we're running at if this is our mmu_idx */
1935 static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx)
1936 {
1937 assert(mmu_idx < ARMMMUIdx_S2NS);
1938 return mmu_idx & 3;
1939 }
1940
1941 /* Determine the current mmu_idx to use for normal loads/stores */
1942 static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)
1943 {
1944 int el = arm_current_el(env);
1945
1946 if (el < 2 && arm_is_secure_below_el3(env)) {
1947 return ARMMMUIdx_S1SE0 + el;
1948 }
1949 return el;
1950 }
1951
1952 /* Indexes used when registering address spaces with cpu_address_space_init */
1953 typedef enum ARMASIdx {
1954 ARMASIdx_NS = 0,
1955 ARMASIdx_S = 1,
1956 } ARMASIdx;
1957
1958 /* Return the Exception Level targeted by debug exceptions. */
1959 static inline int arm_debug_target_el(CPUARMState *env)
1960 {
1961 bool secure = arm_is_secure(env);
1962 bool route_to_el2 = false;
1963
1964 if (arm_feature(env, ARM_FEATURE_EL2) && !secure) {
1965 route_to_el2 = env->cp15.hcr_el2 & HCR_TGE ||
1966 env->cp15.mdcr_el2 & (1 << 8);
1967 }
1968
1969 if (route_to_el2) {
1970 return 2;
1971 } else if (arm_feature(env, ARM_FEATURE_EL3) &&
1972 !arm_el_is_aa64(env, 3) && secure) {
1973 return 3;
1974 } else {
1975 return 1;
1976 }
1977 }
1978
1979 static inline bool aa64_generate_debug_exceptions(CPUARMState *env)
1980 {
1981 if (arm_is_secure(env)) {
1982 /* MDCR_EL3.SDD disables debug events from Secure state */
1983 if (extract32(env->cp15.mdcr_el3, 16, 1) != 0
1984 || arm_current_el(env) == 3) {
1985 return false;
1986 }
1987 }
1988
1989 if (arm_current_el(env) == arm_debug_target_el(env)) {
1990 if ((extract32(env->cp15.mdscr_el1, 13, 1) == 0)
1991 || (env->daif & PSTATE_D)) {
1992 return false;
1993 }
1994 }
1995 return true;
1996 }
1997
1998 static inline bool aa32_generate_debug_exceptions(CPUARMState *env)
1999 {
2000 int el = arm_current_el(env);
2001
2002 if (el == 0 && arm_el_is_aa64(env, 1)) {
2003 return aa64_generate_debug_exceptions(env);
2004 }
2005
2006 if (arm_is_secure(env)) {
2007 int spd;
2008
2009 if (el == 0 && (env->cp15.sder & 1)) {
2010 /* SDER.SUIDEN means debug exceptions from Secure EL0
2011 * are always enabled. Otherwise they are controlled by
2012 * SDCR.SPD like those from other Secure ELs.
2013 */
2014 return true;
2015 }
2016
2017 spd = extract32(env->cp15.mdcr_el3, 14, 2);
2018 switch (spd) {
2019 case 1:
2020 /* SPD == 0b01 is reserved, but behaves as 0b00. */
2021 case 0:
2022 /* For 0b00 we return true if external secure invasive debug
2023 * is enabled. On real hardware this is controlled by external
2024 * signals to the core. QEMU always permits debug, and behaves
2025 * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high.
2026 */
2027 return true;
2028 case 2:
2029 return false;
2030 case 3:
2031 return true;
2032 }
2033 }
2034
2035 return el != 2;
2036 }
2037
2038 /* Return true if debugging exceptions are currently enabled.
2039 * This corresponds to what in ARM ARM pseudocode would be
2040 * if UsingAArch32() then
2041 * return AArch32.GenerateDebugExceptions()
2042 * else
2043 * return AArch64.GenerateDebugExceptions()
2044 * We choose to push the if() down into this function for clarity,
2045 * since the pseudocode has it at all callsites except for the one in
2046 * CheckSoftwareStep(), where it is elided because both branches would
2047 * always return the same value.
2048 *
2049 * Parts of the pseudocode relating to EL2 and EL3 are omitted because we
2050 * don't yet implement those exception levels or their associated trap bits.
2051 */
2052 static inline bool arm_generate_debug_exceptions(CPUARMState *env)
2053 {
2054 if (env->aarch64) {
2055 return aa64_generate_debug_exceptions(env);
2056 } else {
2057 return aa32_generate_debug_exceptions(env);
2058 }
2059 }
2060
2061 /* Is single-stepping active? (Note that the "is EL_D AArch64?" check
2062 * implicitly means this always returns false in pre-v8 CPUs.)
2063 */
2064 static inline bool arm_singlestep_active(CPUARMState *env)
2065 {
2066 return extract32(env->cp15.mdscr_el1, 0, 1)
2067 && arm_el_is_aa64(env, arm_debug_target_el(env))
2068 && arm_generate_debug_exceptions(env);
2069 }
2070
2071 static inline bool arm_sctlr_b(CPUARMState *env)
2072 {
2073 return
2074 /* We need not implement SCTLR.ITD in user-mode emulation, so
2075 * let linux-user ignore the fact that it conflicts with SCTLR_B.
2076 * This lets people run BE32 binaries with "-cpu any".
2077 */
2078 #ifndef CONFIG_USER_ONLY
2079 !arm_feature(env, ARM_FEATURE_V7) &&
2080 #endif
2081 (env->cp15.sctlr_el[1] & SCTLR_B) != 0;
2082 }
2083
2084 /* Return true if the processor is in big-endian mode. */
2085 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
2086 {
2087 int cur_el;
2088
2089 /* In 32bit endianness is determined by looking at CPSR's E bit */
2090 if (!is_a64(env)) {
2091 return
2092 #ifdef CONFIG_USER_ONLY
2093 /* In system mode, BE32 is modelled in line with the
2094 * architecture (as word-invariant big-endianness), where loads
2095 * and stores are done little endian but from addresses which
2096 * are adjusted by XORing with the appropriate constant. So the
2097 * endianness to use for the raw data access is not affected by
2098 * SCTLR.B.
2099 * In user mode, however, we model BE32 as byte-invariant
2100 * big-endianness (because user-only code cannot tell the
2101 * difference), and so we need to use a data access endianness
2102 * that depends on SCTLR.B.
2103 */
2104 arm_sctlr_b(env) ||
2105 #endif
2106 ((env->uncached_cpsr & CPSR_E) ? 1 : 0);
2107 }
2108
2109 cur_el = arm_current_el(env);
2110
2111 if (cur_el == 0) {
2112 return (env->cp15.sctlr_el[1] & SCTLR_E0E) != 0;
2113 }
2114
2115 return (env->cp15.sctlr_el[cur_el] & SCTLR_EE) != 0;
2116 }
2117
2118 #include "exec/cpu-all.h"
2119
2120 /* Bit usage in the TB flags field: bit 31 indicates whether we are
2121 * in 32 or 64 bit mode. The meaning of the other bits depends on that.
2122 * We put flags which are shared between 32 and 64 bit mode at the top
2123 * of the word, and flags which apply to only one mode at the bottom.
2124 */
2125 #define ARM_TBFLAG_AARCH64_STATE_SHIFT 31
2126 #define ARM_TBFLAG_AARCH64_STATE_MASK (1U << ARM_TBFLAG_AARCH64_STATE_SHIFT)
2127 #define ARM_TBFLAG_MMUIDX_SHIFT 28
2128 #define ARM_TBFLAG_MMUIDX_MASK (0x7 << ARM_TBFLAG_MMUIDX_SHIFT)
2129 #define ARM_TBFLAG_SS_ACTIVE_SHIFT 27
2130 #define ARM_TBFLAG_SS_ACTIVE_MASK (1 << ARM_TBFLAG_SS_ACTIVE_SHIFT)
2131 #define ARM_TBFLAG_PSTATE_SS_SHIFT 26
2132 #define ARM_TBFLAG_PSTATE_SS_MASK (1 << ARM_TBFLAG_PSTATE_SS_SHIFT)
2133 /* Target EL if we take a floating-point-disabled exception */
2134 #define ARM_TBFLAG_FPEXC_EL_SHIFT 24
2135 #define ARM_TBFLAG_FPEXC_EL_MASK (0x3 << ARM_TBFLAG_FPEXC_EL_SHIFT)
2136
2137 /* Bit usage when in AArch32 state: */
2138 #define ARM_TBFLAG_THUMB_SHIFT 0
2139 #define ARM_TBFLAG_THUMB_MASK (1 << ARM_TBFLAG_THUMB_SHIFT)
2140 #define ARM_TBFLAG_VECLEN_SHIFT 1
2141 #define ARM_TBFLAG_VECLEN_MASK (0x7 << ARM_TBFLAG_VECLEN_SHIFT)
2142 #define ARM_TBFLAG_VECSTRIDE_SHIFT 4
2143 #define ARM_TBFLAG_VECSTRIDE_MASK (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT)
2144 #define ARM_TBFLAG_VFPEN_SHIFT 7
2145 #define ARM_TBFLAG_VFPEN_MASK (1 << ARM_TBFLAG_VFPEN_SHIFT)
2146 #define ARM_TBFLAG_CONDEXEC_SHIFT 8
2147 #define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT)
2148 #define ARM_TBFLAG_SCTLR_B_SHIFT 16
2149 #define ARM_TBFLAG_SCTLR_B_MASK (1 << ARM_TBFLAG_SCTLR_B_SHIFT)
2150 /* We store the bottom two bits of the CPAR as TB flags and handle
2151 * checks on the other bits at runtime
2152 */
2153 #define ARM_TBFLAG_XSCALE_CPAR_SHIFT 17
2154 #define ARM_TBFLAG_XSCALE_CPAR_MASK (3 << ARM_TBFLAG_XSCALE_CPAR_SHIFT)
2155 /* Indicates whether cp register reads and writes by guest code should access
2156 * the secure or nonsecure bank of banked registers; note that this is not
2157 * the same thing as the current security state of the processor!
2158 */
2159 #define ARM_TBFLAG_NS_SHIFT 19
2160 #define ARM_TBFLAG_NS_MASK (1 << ARM_TBFLAG_NS_SHIFT)
2161 #define ARM_TBFLAG_BE_DATA_SHIFT 20
2162 #define ARM_TBFLAG_BE_DATA_MASK (1 << ARM_TBFLAG_BE_DATA_SHIFT)
2163
2164 /* Bit usage when in AArch64 state: currently we have no A64 specific bits */
2165
2166 /* some convenience accessor macros */
2167 #define ARM_TBFLAG_AARCH64_STATE(F) \
2168 (((F) & ARM_TBFLAG_AARCH64_STATE_MASK) >> ARM_TBFLAG_AARCH64_STATE_SHIFT)
2169 #define ARM_TBFLAG_MMUIDX(F) \
2170 (((F) & ARM_TBFLAG_MMUIDX_MASK) >> ARM_TBFLAG_MMUIDX_SHIFT)
2171 #define ARM_TBFLAG_SS_ACTIVE(F) \
2172 (((F) & ARM_TBFLAG_SS_ACTIVE_MASK) >> ARM_TBFLAG_SS_ACTIVE_SHIFT)
2173 #define ARM_TBFLAG_PSTATE_SS(F) \
2174 (((F) & ARM_TBFLAG_PSTATE_SS_MASK) >> ARM_TBFLAG_PSTATE_SS_SHIFT)
2175 #define ARM_TBFLAG_FPEXC_EL(F) \
2176 (((F) & ARM_TBFLAG_FPEXC_EL_MASK) >> ARM_TBFLAG_FPEXC_EL_SHIFT)
2177 #define ARM_TBFLAG_THUMB(F) \
2178 (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT)
2179 #define ARM_TBFLAG_VECLEN(F) \
2180 (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT)
2181 #define ARM_TBFLAG_VECSTRIDE(F) \
2182 (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT)
2183 #define ARM_TBFLAG_VFPEN(F) \
2184 (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT)
2185 #define ARM_TBFLAG_CONDEXEC(F) \
2186 (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT)
2187 #define ARM_TBFLAG_SCTLR_B(F) \
2188 (((F) & ARM_TBFLAG_SCTLR_B_MASK) >> ARM_TBFLAG_SCTLR_B_SHIFT)
2189 #define ARM_TBFLAG_XSCALE_CPAR(F) \
2190 (((F) & ARM_TBFLAG_XSCALE_CPAR_MASK) >> ARM_TBFLAG_XSCALE_CPAR_SHIFT)
2191 #define ARM_TBFLAG_NS(F) \
2192 (((F) & ARM_TBFLAG_NS_MASK) >> ARM_TBFLAG_NS_SHIFT)
2193 #define ARM_TBFLAG_BE_DATA(F) \
2194 (((F) & ARM_TBFLAG_BE_DATA_MASK) >> ARM_TBFLAG_BE_DATA_SHIFT)
2195
2196 static inline bool bswap_code(bool sctlr_b)
2197 {
2198 #ifdef CONFIG_USER_ONLY
2199 /* BE8 (SCTLR.B = 0, TARGET_WORDS_BIGENDIAN = 1) is mixed endian.
2200 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_WORDS_BIGENDIAN=0
2201 * would also end up as a mixed-endian mode with BE code, LE data.
2202 */
2203 return
2204 #ifdef TARGET_WORDS_BIGENDIAN
2205 1 ^
2206 #endif
2207 sctlr_b;
2208 #else
2209 /* All code access in ARM is little endian, and there are no loaders
2210 * doing swaps that need to be reversed
2211 */
2212 return 0;
2213 #endif
2214 }
2215
2216 /* Return the exception level to which FP-disabled exceptions should
2217 * be taken, or 0 if FP is enabled.
2218 */
2219 static inline int fp_exception_el(CPUARMState *env)
2220 {
2221 int fpen;
2222 int cur_el = arm_current_el(env);
2223
2224 /* CPACR and the CPTR registers don't exist before v6, so FP is
2225 * always accessible
2226 */
2227 if (!arm_feature(env, ARM_FEATURE_V6)) {
2228 return 0;
2229 }
2230
2231 /* The CPACR controls traps to EL1, or PL1 if we're 32 bit:
2232 * 0, 2 : trap EL0 and EL1/PL1 accesses
2233 * 1 : trap only EL0 accesses
2234 * 3 : trap no accesses
2235 */
2236 fpen = extract32(env->cp15.cpacr_el1, 20, 2);
2237 switch (fpen) {
2238 case 0:
2239 case 2:
2240 if (cur_el == 0 || cur_el == 1) {
2241 /* Trap to PL1, which might be EL1 or EL3 */
2242 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) {
2243 return 3;
2244 }
2245 return 1;
2246 }
2247 if (cur_el == 3 && !is_a64(env)) {
2248 /* Secure PL1 running at EL3 */
2249 return 3;
2250 }
2251 break;
2252 case 1:
2253 if (cur_el == 0) {
2254 return 1;
2255 }
2256 break;
2257 case 3:
2258 break;
2259 }
2260
2261 /* For the CPTR registers we don't need to guard with an ARM_FEATURE
2262 * check because zero bits in the registers mean "don't trap".
2263 */
2264
2265 /* CPTR_EL2 : present in v7VE or v8 */
2266 if (cur_el <= 2 && extract32(env->cp15.cptr_el[2], 10, 1)
2267 && !arm_is_secure_below_el3(env)) {
2268 /* Trap FP ops at EL2, NS-EL1 or NS-EL0 to EL2 */
2269 return 2;
2270 }
2271
2272 /* CPTR_EL3 : present in v8 */
2273 if (extract32(env->cp15.cptr_el[3], 10, 1)) {
2274 /* Trap all FP ops to EL3 */
2275 return 3;
2276 }
2277
2278 return 0;
2279 }
2280
2281 #ifdef CONFIG_USER_ONLY
2282 static inline bool arm_cpu_bswap_data(CPUARMState *env)
2283 {
2284 return
2285 #ifdef TARGET_WORDS_BIGENDIAN
2286 1 ^
2287 #endif
2288 arm_cpu_data_is_big_endian(env);
2289 }
2290 #endif
2291
2292 static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
2293 target_ulong *cs_base, uint32_t *flags)
2294 {
2295 if (is_a64(env)) {
2296 *pc = env->pc;
2297 *flags = ARM_TBFLAG_AARCH64_STATE_MASK;
2298 } else {
2299 *pc = env->regs[15];
2300 *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT)
2301 | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT)
2302 | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT)
2303 | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT)
2304 | (arm_sctlr_b(env) << ARM_TBFLAG_SCTLR_B_SHIFT);
2305 if (!(access_secure_reg(env))) {
2306 *flags |= ARM_TBFLAG_NS_MASK;
2307 }
2308 if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)
2309 || arm_el_is_aa64(env, 1)) {
2310 *flags |= ARM_TBFLAG_VFPEN_MASK;
2311 }
2312 *flags |= (extract32(env->cp15.c15_cpar, 0, 2)
2313 << ARM_TBFLAG_XSCALE_CPAR_SHIFT);
2314 }
2315
2316 *flags |= (cpu_mmu_index(env, false) << ARM_TBFLAG_MMUIDX_SHIFT);
2317 /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
2318 * states defined in the ARM ARM for software singlestep:
2319 * SS_ACTIVE PSTATE.SS State
2320 * 0 x Inactive (the TB flag for SS is always 0)
2321 * 1 0 Active-pending
2322 * 1 1 Active-not-pending
2323 */
2324 if (arm_singlestep_active(env)) {
2325 *flags |= ARM_TBFLAG_SS_ACTIVE_MASK;
2326 if (is_a64(env)) {
2327 if (env->pstate & PSTATE_SS) {
2328 *flags |= ARM_TBFLAG_PSTATE_SS_MASK;
2329 }
2330 } else {
2331 if (env->uncached_cpsr & PSTATE_SS) {
2332 *flags |= ARM_TBFLAG_PSTATE_SS_MASK;
2333 }
2334 }
2335 }
2336 if (arm_cpu_data_is_big_endian(env)) {
2337 *flags |= ARM_TBFLAG_BE_DATA_MASK;
2338 }
2339 *flags |= fp_exception_el(env) << ARM_TBFLAG_FPEXC_EL_SHIFT;
2340
2341 *cs_base = 0;
2342 }
2343
2344 enum {
2345 QEMU_PSCI_CONDUIT_DISABLED = 0,
2346 QEMU_PSCI_CONDUIT_SMC = 1,
2347 QEMU_PSCI_CONDUIT_HVC = 2,
2348 };
2349
2350 #ifndef CONFIG_USER_ONLY
2351 /* Return the address space index to use for a memory access */
2352 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs)
2353 {
2354 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS;
2355 }
2356
2357 /* Return the AddressSpace to use for a memory access
2358 * (which depends on whether the access is S or NS, and whether
2359 * the board gave us a separate AddressSpace for S accesses).
2360 */
2361 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs)
2362 {
2363 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs));
2364 }
2365 #endif
2366
2367 #endif