qemu-img: Omit error_report() after img_open()
[qemu.git] / target-arm / cpu64.c
1 /*
2 * QEMU AArch64 CPU
3 *
4 * Copyright (c) 2013 Linaro Ltd
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
19 */
20
21 #include "cpu.h"
22 #include "qemu-common.h"
23 #if !defined(CONFIG_USER_ONLY)
24 #include "hw/loader.h"
25 #endif
26 #include "hw/arm/arm.h"
27 #include "sysemu/sysemu.h"
28 #include "sysemu/kvm.h"
29
30 static inline void set_feature(CPUARMState *env, int feature)
31 {
32 env->features |= 1ULL << feature;
33 }
34
35 #ifndef CONFIG_USER_ONLY
36 static uint64_t a57_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
37 {
38 /* Number of processors is in [25:24]; otherwise we RAZ */
39 return (smp_cpus - 1) << 24;
40 }
41 #endif
42
43 static const ARMCPRegInfo cortexa57_cp_reginfo[] = {
44 #ifndef CONFIG_USER_ONLY
45 { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
46 .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
47 .access = PL1_RW, .readfn = a57_l2ctlr_read,
48 .writefn = arm_cp_write_ignore },
49 { .name = "L2CTLR",
50 .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
51 .access = PL1_RW, .readfn = a57_l2ctlr_read,
52 .writefn = arm_cp_write_ignore },
53 #endif
54 { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
55 .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
56 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
57 { .name = "L2ECTLR",
58 .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
59 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
60 { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
61 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
62 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
63 { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
64 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
65 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
66 { .name = "CPUACTLR",
67 .cp = 15, .opc1 = 0, .crm = 15,
68 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
69 { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
70 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
71 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
72 { .name = "CPUECTLR",
73 .cp = 15, .opc1 = 1, .crm = 15,
74 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
75 { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
76 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
77 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
78 { .name = "CPUMERRSR",
79 .cp = 15, .opc1 = 2, .crm = 15,
80 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
81 { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
82 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
83 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
84 { .name = "L2MERRSR",
85 .cp = 15, .opc1 = 3, .crm = 15,
86 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
87 REGINFO_SENTINEL
88 };
89
90 static void aarch64_a57_initfn(Object *obj)
91 {
92 ARMCPU *cpu = ARM_CPU(obj);
93
94 set_feature(&cpu->env, ARM_FEATURE_V8);
95 set_feature(&cpu->env, ARM_FEATURE_VFP4);
96 set_feature(&cpu->env, ARM_FEATURE_NEON);
97 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
98 set_feature(&cpu->env, ARM_FEATURE_AARCH64);
99 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
100 set_feature(&cpu->env, ARM_FEATURE_V8_AES);
101 set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
102 set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
103 set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
104 set_feature(&cpu->env, ARM_FEATURE_CRC);
105 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
106 cpu->midr = 0x411fd070;
107 cpu->reset_fpsid = 0x41034070;
108 cpu->mvfr0 = 0x10110222;
109 cpu->mvfr1 = 0x12111111;
110 cpu->mvfr2 = 0x00000043;
111 cpu->ctr = 0x8444c004;
112 cpu->reset_sctlr = 0x00c50838;
113 cpu->id_pfr0 = 0x00000131;
114 cpu->id_pfr1 = 0x00011011;
115 cpu->id_dfr0 = 0x03010066;
116 cpu->id_afr0 = 0x00000000;
117 cpu->id_mmfr0 = 0x10101105;
118 cpu->id_mmfr1 = 0x40000000;
119 cpu->id_mmfr2 = 0x01260000;
120 cpu->id_mmfr3 = 0x02102211;
121 cpu->id_isar0 = 0x02101110;
122 cpu->id_isar1 = 0x13112111;
123 cpu->id_isar2 = 0x21232042;
124 cpu->id_isar3 = 0x01112131;
125 cpu->id_isar4 = 0x00011142;
126 cpu->id_isar5 = 0x00011121;
127 cpu->id_aa64pfr0 = 0x00002222;
128 cpu->id_aa64dfr0 = 0x10305106;
129 cpu->id_aa64isar0 = 0x00011120;
130 cpu->id_aa64mmfr0 = 0x00001124;
131 cpu->dbgdidr = 0x3516d000;
132 cpu->clidr = 0x0a200023;
133 cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
134 cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
135 cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
136 cpu->dcz_blocksize = 4; /* 64 bytes */
137 define_arm_cp_regs(cpu, cortexa57_cp_reginfo);
138 }
139
140 #ifdef CONFIG_USER_ONLY
141 static void aarch64_any_initfn(Object *obj)
142 {
143 ARMCPU *cpu = ARM_CPU(obj);
144
145 set_feature(&cpu->env, ARM_FEATURE_V8);
146 set_feature(&cpu->env, ARM_FEATURE_VFP4);
147 set_feature(&cpu->env, ARM_FEATURE_NEON);
148 set_feature(&cpu->env, ARM_FEATURE_AARCH64);
149 set_feature(&cpu->env, ARM_FEATURE_V8_AES);
150 set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
151 set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
152 set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
153 set_feature(&cpu->env, ARM_FEATURE_CRC);
154 cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
155 cpu->dcz_blocksize = 7; /* 512 bytes */
156 }
157 #endif
158
159 typedef struct ARMCPUInfo {
160 const char *name;
161 void (*initfn)(Object *obj);
162 void (*class_init)(ObjectClass *oc, void *data);
163 } ARMCPUInfo;
164
165 static const ARMCPUInfo aarch64_cpus[] = {
166 { .name = "cortex-a57", .initfn = aarch64_a57_initfn },
167 #ifdef CONFIG_USER_ONLY
168 { .name = "any", .initfn = aarch64_any_initfn },
169 #endif
170 { .name = NULL }
171 };
172
173 static void aarch64_cpu_initfn(Object *obj)
174 {
175 }
176
177 static void aarch64_cpu_finalizefn(Object *obj)
178 {
179 }
180
181 static void aarch64_cpu_set_pc(CPUState *cs, vaddr value)
182 {
183 ARMCPU *cpu = ARM_CPU(cs);
184 /* It's OK to look at env for the current mode here, because it's
185 * never possible for an AArch64 TB to chain to an AArch32 TB.
186 * (Otherwise we would need to use synchronize_from_tb instead.)
187 */
188 if (is_a64(&cpu->env)) {
189 cpu->env.pc = value;
190 } else {
191 cpu->env.regs[15] = value;
192 }
193 }
194
195 static void aarch64_cpu_class_init(ObjectClass *oc, void *data)
196 {
197 CPUClass *cc = CPU_CLASS(oc);
198
199 #if !defined(CONFIG_USER_ONLY)
200 cc->do_interrupt = aarch64_cpu_do_interrupt;
201 #endif
202 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
203 cc->set_pc = aarch64_cpu_set_pc;
204 cc->gdb_read_register = aarch64_cpu_gdb_read_register;
205 cc->gdb_write_register = aarch64_cpu_gdb_write_register;
206 cc->gdb_num_core_regs = 34;
207 cc->gdb_core_xml_file = "aarch64-core.xml";
208 }
209
210 static void aarch64_cpu_register(const ARMCPUInfo *info)
211 {
212 TypeInfo type_info = {
213 .parent = TYPE_AARCH64_CPU,
214 .instance_size = sizeof(ARMCPU),
215 .instance_init = info->initfn,
216 .class_size = sizeof(ARMCPUClass),
217 .class_init = info->class_init,
218 };
219
220 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
221 type_register(&type_info);
222 g_free((void *)type_info.name);
223 }
224
225 static const TypeInfo aarch64_cpu_type_info = {
226 .name = TYPE_AARCH64_CPU,
227 .parent = TYPE_ARM_CPU,
228 .instance_size = sizeof(ARMCPU),
229 .instance_init = aarch64_cpu_initfn,
230 .instance_finalize = aarch64_cpu_finalizefn,
231 .abstract = true,
232 .class_size = sizeof(AArch64CPUClass),
233 .class_init = aarch64_cpu_class_init,
234 };
235
236 static void aarch64_cpu_register_types(void)
237 {
238 const ARMCPUInfo *info = aarch64_cpus;
239
240 type_register_static(&aarch64_cpu_type_info);
241
242 while (info->name) {
243 aarch64_cpu_register(info);
244 info++;
245 }
246 }
247
248 type_init(aarch64_cpu_register_types)