linux-user: Support for restarting system calls for OpenRISC targets
[qemu.git] / target-arm / helper-a64.c
1 /*
2 * AArch64 specific helpers
3 *
4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "cpu.h"
22 #include "exec/gdbstub.h"
23 #include "exec/helper-proto.h"
24 #include "qemu/host-utils.h"
25 #include "qemu/log.h"
26 #include "sysemu/sysemu.h"
27 #include "qemu/bitops.h"
28 #include "internals.h"
29 #include "qemu/crc32c.h"
30 #include <zlib.h> /* For crc32 */
31
32 /* C2.4.7 Multiply and divide */
33 /* special cases for 0 and LLONG_MIN are mandated by the standard */
34 uint64_t HELPER(udiv64)(uint64_t num, uint64_t den)
35 {
36 if (den == 0) {
37 return 0;
38 }
39 return num / den;
40 }
41
42 int64_t HELPER(sdiv64)(int64_t num, int64_t den)
43 {
44 if (den == 0) {
45 return 0;
46 }
47 if (num == LLONG_MIN && den == -1) {
48 return LLONG_MIN;
49 }
50 return num / den;
51 }
52
53 uint64_t HELPER(clz64)(uint64_t x)
54 {
55 return clz64(x);
56 }
57
58 uint64_t HELPER(cls64)(uint64_t x)
59 {
60 return clrsb64(x);
61 }
62
63 uint32_t HELPER(cls32)(uint32_t x)
64 {
65 return clrsb32(x);
66 }
67
68 uint32_t HELPER(clz32)(uint32_t x)
69 {
70 return clz32(x);
71 }
72
73 uint64_t HELPER(rbit64)(uint64_t x)
74 {
75 return revbit64(x);
76 }
77
78 /* Convert a softfloat float_relation_ (as returned by
79 * the float*_compare functions) to the correct ARM
80 * NZCV flag state.
81 */
82 static inline uint32_t float_rel_to_flags(int res)
83 {
84 uint64_t flags;
85 switch (res) {
86 case float_relation_equal:
87 flags = PSTATE_Z | PSTATE_C;
88 break;
89 case float_relation_less:
90 flags = PSTATE_N;
91 break;
92 case float_relation_greater:
93 flags = PSTATE_C;
94 break;
95 case float_relation_unordered:
96 default:
97 flags = PSTATE_C | PSTATE_V;
98 break;
99 }
100 return flags;
101 }
102
103 uint64_t HELPER(vfp_cmps_a64)(float32 x, float32 y, void *fp_status)
104 {
105 return float_rel_to_flags(float32_compare_quiet(x, y, fp_status));
106 }
107
108 uint64_t HELPER(vfp_cmpes_a64)(float32 x, float32 y, void *fp_status)
109 {
110 return float_rel_to_flags(float32_compare(x, y, fp_status));
111 }
112
113 uint64_t HELPER(vfp_cmpd_a64)(float64 x, float64 y, void *fp_status)
114 {
115 return float_rel_to_flags(float64_compare_quiet(x, y, fp_status));
116 }
117
118 uint64_t HELPER(vfp_cmped_a64)(float64 x, float64 y, void *fp_status)
119 {
120 return float_rel_to_flags(float64_compare(x, y, fp_status));
121 }
122
123 float32 HELPER(vfp_mulxs)(float32 a, float32 b, void *fpstp)
124 {
125 float_status *fpst = fpstp;
126
127 a = float32_squash_input_denormal(a, fpst);
128 b = float32_squash_input_denormal(b, fpst);
129
130 if ((float32_is_zero(a) && float32_is_infinity(b)) ||
131 (float32_is_infinity(a) && float32_is_zero(b))) {
132 /* 2.0 with the sign bit set to sign(A) XOR sign(B) */
133 return make_float32((1U << 30) |
134 ((float32_val(a) ^ float32_val(b)) & (1U << 31)));
135 }
136 return float32_mul(a, b, fpst);
137 }
138
139 float64 HELPER(vfp_mulxd)(float64 a, float64 b, void *fpstp)
140 {
141 float_status *fpst = fpstp;
142
143 a = float64_squash_input_denormal(a, fpst);
144 b = float64_squash_input_denormal(b, fpst);
145
146 if ((float64_is_zero(a) && float64_is_infinity(b)) ||
147 (float64_is_infinity(a) && float64_is_zero(b))) {
148 /* 2.0 with the sign bit set to sign(A) XOR sign(B) */
149 return make_float64((1ULL << 62) |
150 ((float64_val(a) ^ float64_val(b)) & (1ULL << 63)));
151 }
152 return float64_mul(a, b, fpst);
153 }
154
155 uint64_t HELPER(simd_tbl)(CPUARMState *env, uint64_t result, uint64_t indices,
156 uint32_t rn, uint32_t numregs)
157 {
158 /* Helper function for SIMD TBL and TBX. We have to do the table
159 * lookup part for the 64 bits worth of indices we're passed in.
160 * result is the initial results vector (either zeroes for TBL
161 * or some guest values for TBX), rn the register number where
162 * the table starts, and numregs the number of registers in the table.
163 * We return the results of the lookups.
164 */
165 int shift;
166
167 for (shift = 0; shift < 64; shift += 8) {
168 int index = extract64(indices, shift, 8);
169 if (index < 16 * numregs) {
170 /* Convert index (a byte offset into the virtual table
171 * which is a series of 128-bit vectors concatenated)
172 * into the correct vfp.regs[] element plus a bit offset
173 * into that element, bearing in mind that the table
174 * can wrap around from V31 to V0.
175 */
176 int elt = (rn * 2 + (index >> 3)) % 64;
177 int bitidx = (index & 7) * 8;
178 uint64_t val = extract64(env->vfp.regs[elt], bitidx, 8);
179
180 result = deposit64(result, shift, 8, val);
181 }
182 }
183 return result;
184 }
185
186 /* 64bit/double versions of the neon float compare functions */
187 uint64_t HELPER(neon_ceq_f64)(float64 a, float64 b, void *fpstp)
188 {
189 float_status *fpst = fpstp;
190 return -float64_eq_quiet(a, b, fpst);
191 }
192
193 uint64_t HELPER(neon_cge_f64)(float64 a, float64 b, void *fpstp)
194 {
195 float_status *fpst = fpstp;
196 return -float64_le(b, a, fpst);
197 }
198
199 uint64_t HELPER(neon_cgt_f64)(float64 a, float64 b, void *fpstp)
200 {
201 float_status *fpst = fpstp;
202 return -float64_lt(b, a, fpst);
203 }
204
205 /* Reciprocal step and sqrt step. Note that unlike the A32/T32
206 * versions, these do a fully fused multiply-add or
207 * multiply-add-and-halve.
208 */
209 #define float32_two make_float32(0x40000000)
210 #define float32_three make_float32(0x40400000)
211 #define float32_one_point_five make_float32(0x3fc00000)
212
213 #define float64_two make_float64(0x4000000000000000ULL)
214 #define float64_three make_float64(0x4008000000000000ULL)
215 #define float64_one_point_five make_float64(0x3FF8000000000000ULL)
216
217 float32 HELPER(recpsf_f32)(float32 a, float32 b, void *fpstp)
218 {
219 float_status *fpst = fpstp;
220
221 a = float32_squash_input_denormal(a, fpst);
222 b = float32_squash_input_denormal(b, fpst);
223
224 a = float32_chs(a);
225 if ((float32_is_infinity(a) && float32_is_zero(b)) ||
226 (float32_is_infinity(b) && float32_is_zero(a))) {
227 return float32_two;
228 }
229 return float32_muladd(a, b, float32_two, 0, fpst);
230 }
231
232 float64 HELPER(recpsf_f64)(float64 a, float64 b, void *fpstp)
233 {
234 float_status *fpst = fpstp;
235
236 a = float64_squash_input_denormal(a, fpst);
237 b = float64_squash_input_denormal(b, fpst);
238
239 a = float64_chs(a);
240 if ((float64_is_infinity(a) && float64_is_zero(b)) ||
241 (float64_is_infinity(b) && float64_is_zero(a))) {
242 return float64_two;
243 }
244 return float64_muladd(a, b, float64_two, 0, fpst);
245 }
246
247 float32 HELPER(rsqrtsf_f32)(float32 a, float32 b, void *fpstp)
248 {
249 float_status *fpst = fpstp;
250
251 a = float32_squash_input_denormal(a, fpst);
252 b = float32_squash_input_denormal(b, fpst);
253
254 a = float32_chs(a);
255 if ((float32_is_infinity(a) && float32_is_zero(b)) ||
256 (float32_is_infinity(b) && float32_is_zero(a))) {
257 return float32_one_point_five;
258 }
259 return float32_muladd(a, b, float32_three, float_muladd_halve_result, fpst);
260 }
261
262 float64 HELPER(rsqrtsf_f64)(float64 a, float64 b, void *fpstp)
263 {
264 float_status *fpst = fpstp;
265
266 a = float64_squash_input_denormal(a, fpst);
267 b = float64_squash_input_denormal(b, fpst);
268
269 a = float64_chs(a);
270 if ((float64_is_infinity(a) && float64_is_zero(b)) ||
271 (float64_is_infinity(b) && float64_is_zero(a))) {
272 return float64_one_point_five;
273 }
274 return float64_muladd(a, b, float64_three, float_muladd_halve_result, fpst);
275 }
276
277 /* Pairwise long add: add pairs of adjacent elements into
278 * double-width elements in the result (eg _s8 is an 8x8->16 op)
279 */
280 uint64_t HELPER(neon_addlp_s8)(uint64_t a)
281 {
282 uint64_t nsignmask = 0x0080008000800080ULL;
283 uint64_t wsignmask = 0x8000800080008000ULL;
284 uint64_t elementmask = 0x00ff00ff00ff00ffULL;
285 uint64_t tmp1, tmp2;
286 uint64_t res, signres;
287
288 /* Extract odd elements, sign extend each to a 16 bit field */
289 tmp1 = a & elementmask;
290 tmp1 ^= nsignmask;
291 tmp1 |= wsignmask;
292 tmp1 = (tmp1 - nsignmask) ^ wsignmask;
293 /* Ditto for the even elements */
294 tmp2 = (a >> 8) & elementmask;
295 tmp2 ^= nsignmask;
296 tmp2 |= wsignmask;
297 tmp2 = (tmp2 - nsignmask) ^ wsignmask;
298
299 /* calculate the result by summing bits 0..14, 16..22, etc,
300 * and then adjusting the sign bits 15, 23, etc manually.
301 * This ensures the addition can't overflow the 16 bit field.
302 */
303 signres = (tmp1 ^ tmp2) & wsignmask;
304 res = (tmp1 & ~wsignmask) + (tmp2 & ~wsignmask);
305 res ^= signres;
306
307 return res;
308 }
309
310 uint64_t HELPER(neon_addlp_u8)(uint64_t a)
311 {
312 uint64_t tmp;
313
314 tmp = a & 0x00ff00ff00ff00ffULL;
315 tmp += (a >> 8) & 0x00ff00ff00ff00ffULL;
316 return tmp;
317 }
318
319 uint64_t HELPER(neon_addlp_s16)(uint64_t a)
320 {
321 int32_t reslo, reshi;
322
323 reslo = (int32_t)(int16_t)a + (int32_t)(int16_t)(a >> 16);
324 reshi = (int32_t)(int16_t)(a >> 32) + (int32_t)(int16_t)(a >> 48);
325
326 return (uint32_t)reslo | (((uint64_t)reshi) << 32);
327 }
328
329 uint64_t HELPER(neon_addlp_u16)(uint64_t a)
330 {
331 uint64_t tmp;
332
333 tmp = a & 0x0000ffff0000ffffULL;
334 tmp += (a >> 16) & 0x0000ffff0000ffffULL;
335 return tmp;
336 }
337
338 /* Floating-point reciprocal exponent - see FPRecpX in ARM ARM */
339 float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
340 {
341 float_status *fpst = fpstp;
342 uint32_t val32, sbit;
343 int32_t exp;
344
345 if (float32_is_any_nan(a)) {
346 float32 nan = a;
347 if (float32_is_signaling_nan(a)) {
348 float_raise(float_flag_invalid, fpst);
349 nan = float32_maybe_silence_nan(a);
350 }
351 if (fpst->default_nan_mode) {
352 nan = float32_default_nan;
353 }
354 return nan;
355 }
356
357 val32 = float32_val(a);
358 sbit = 0x80000000ULL & val32;
359 exp = extract32(val32, 23, 8);
360
361 if (exp == 0) {
362 return make_float32(sbit | (0xfe << 23));
363 } else {
364 return make_float32(sbit | (~exp & 0xff) << 23);
365 }
366 }
367
368 float64 HELPER(frecpx_f64)(float64 a, void *fpstp)
369 {
370 float_status *fpst = fpstp;
371 uint64_t val64, sbit;
372 int64_t exp;
373
374 if (float64_is_any_nan(a)) {
375 float64 nan = a;
376 if (float64_is_signaling_nan(a)) {
377 float_raise(float_flag_invalid, fpst);
378 nan = float64_maybe_silence_nan(a);
379 }
380 if (fpst->default_nan_mode) {
381 nan = float64_default_nan;
382 }
383 return nan;
384 }
385
386 val64 = float64_val(a);
387 sbit = 0x8000000000000000ULL & val64;
388 exp = extract64(float64_val(a), 52, 11);
389
390 if (exp == 0) {
391 return make_float64(sbit | (0x7feULL << 52));
392 } else {
393 return make_float64(sbit | (~exp & 0x7ffULL) << 52);
394 }
395 }
396
397 float32 HELPER(fcvtx_f64_to_f32)(float64 a, CPUARMState *env)
398 {
399 /* Von Neumann rounding is implemented by using round-to-zero
400 * and then setting the LSB of the result if Inexact was raised.
401 */
402 float32 r;
403 float_status *fpst = &env->vfp.fp_status;
404 float_status tstat = *fpst;
405 int exflags;
406
407 set_float_rounding_mode(float_round_to_zero, &tstat);
408 set_float_exception_flags(0, &tstat);
409 r = float64_to_float32(a, &tstat);
410 r = float32_maybe_silence_nan(r);
411 exflags = get_float_exception_flags(&tstat);
412 if (exflags & float_flag_inexact) {
413 r = make_float32(float32_val(r) | 1);
414 }
415 exflags |= get_float_exception_flags(fpst);
416 set_float_exception_flags(exflags, fpst);
417 return r;
418 }
419
420 /* 64-bit versions of the CRC helpers. Note that although the operation
421 * (and the prototypes of crc32c() and crc32() mean that only the bottom
422 * 32 bits of the accumulator and result are used, we pass and return
423 * uint64_t for convenience of the generated code. Unlike the 32-bit
424 * instruction set versions, val may genuinely have 64 bits of data in it.
425 * The upper bytes of val (above the number specified by 'bytes') must have
426 * been zeroed out by the caller.
427 */
428 uint64_t HELPER(crc32_64)(uint64_t acc, uint64_t val, uint32_t bytes)
429 {
430 uint8_t buf[8];
431
432 stq_le_p(buf, val);
433
434 /* zlib crc32 converts the accumulator and output to one's complement. */
435 return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff;
436 }
437
438 uint64_t HELPER(crc32c_64)(uint64_t acc, uint64_t val, uint32_t bytes)
439 {
440 uint8_t buf[8];
441
442 stq_le_p(buf, val);
443
444 /* Linux crc32c converts the output to one's complement. */
445 return crc32c(acc, buf, bytes) ^ 0xffffffff;
446 }