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exec: Make ldl_*_phys input an AddressSpace
[qemu.git] / target-arm / helper.c
1 #include "cpu.h"
2 #include "exec/gdbstub.h"
3 #include "helper.h"
4 #include "qemu/host-utils.h"
5 #include "sysemu/arch_init.h"
6 #include "sysemu/sysemu.h"
7 #include "qemu/bitops.h"
8
9 #ifndef CONFIG_USER_ONLY
10 static inline int get_phys_addr(CPUARMState *env, uint32_t address,
11 int access_type, int is_user,
12 hwaddr *phys_ptr, int *prot,
13 target_ulong *page_size);
14 #endif
15
16 static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
17 {
18 int nregs;
19
20 /* VFP data registers are always little-endian. */
21 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
22 if (reg < nregs) {
23 stfq_le_p(buf, env->vfp.regs[reg]);
24 return 8;
25 }
26 if (arm_feature(env, ARM_FEATURE_NEON)) {
27 /* Aliases for Q regs. */
28 nregs += 16;
29 if (reg < nregs) {
30 stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
31 stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
32 return 16;
33 }
34 }
35 switch (reg - nregs) {
36 case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
37 case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
38 case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
39 }
40 return 0;
41 }
42
43 static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
44 {
45 int nregs;
46
47 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
48 if (reg < nregs) {
49 env->vfp.regs[reg] = ldfq_le_p(buf);
50 return 8;
51 }
52 if (arm_feature(env, ARM_FEATURE_NEON)) {
53 nregs += 16;
54 if (reg < nregs) {
55 env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
56 env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
57 return 16;
58 }
59 }
60 switch (reg - nregs) {
61 case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
62 case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
63 case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
64 }
65 return 0;
66 }
67
68 static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
69 {
70 switch (reg) {
71 case 0 ... 31:
72 /* 128 bit FP register */
73 stfq_le_p(buf, env->vfp.regs[reg * 2]);
74 stfq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]);
75 return 16;
76 case 32:
77 /* FPSR */
78 stl_p(buf, vfp_get_fpsr(env));
79 return 4;
80 case 33:
81 /* FPCR */
82 stl_p(buf, vfp_get_fpcr(env));
83 return 4;
84 default:
85 return 0;
86 }
87 }
88
89 static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
90 {
91 switch (reg) {
92 case 0 ... 31:
93 /* 128 bit FP register */
94 env->vfp.regs[reg * 2] = ldfq_le_p(buf);
95 env->vfp.regs[reg * 2 + 1] = ldfq_le_p(buf + 8);
96 return 16;
97 case 32:
98 /* FPSR */
99 vfp_set_fpsr(env, ldl_p(buf));
100 return 4;
101 case 33:
102 /* FPCR */
103 vfp_set_fpcr(env, ldl_p(buf));
104 return 4;
105 default:
106 return 0;
107 }
108 }
109
110 static int raw_read(CPUARMState *env, const ARMCPRegInfo *ri,
111 uint64_t *value)
112 {
113 if (ri->type & ARM_CP_64BIT) {
114 *value = CPREG_FIELD64(env, ri);
115 } else {
116 *value = CPREG_FIELD32(env, ri);
117 }
118 return 0;
119 }
120
121 static int raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
122 uint64_t value)
123 {
124 if (ri->type & ARM_CP_64BIT) {
125 CPREG_FIELD64(env, ri) = value;
126 } else {
127 CPREG_FIELD32(env, ri) = value;
128 }
129 return 0;
130 }
131
132 static bool read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
133 uint64_t *v)
134 {
135 /* Raw read of a coprocessor register (as needed for migration, etc)
136 * return true on success, false if the read is impossible for some reason.
137 */
138 if (ri->type & ARM_CP_CONST) {
139 *v = ri->resetvalue;
140 } else if (ri->raw_readfn) {
141 return (ri->raw_readfn(env, ri, v) == 0);
142 } else if (ri->readfn) {
143 return (ri->readfn(env, ri, v) == 0);
144 } else {
145 raw_read(env, ri, v);
146 }
147 return true;
148 }
149
150 static bool write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
151 int64_t v)
152 {
153 /* Raw write of a coprocessor register (as needed for migration, etc).
154 * Return true on success, false if the write is impossible for some reason.
155 * Note that constant registers are treated as write-ignored; the
156 * caller should check for success by whether a readback gives the
157 * value written.
158 */
159 if (ri->type & ARM_CP_CONST) {
160 return true;
161 } else if (ri->raw_writefn) {
162 return (ri->raw_writefn(env, ri, v) == 0);
163 } else if (ri->writefn) {
164 return (ri->writefn(env, ri, v) == 0);
165 } else {
166 raw_write(env, ri, v);
167 }
168 return true;
169 }
170
171 bool write_cpustate_to_list(ARMCPU *cpu)
172 {
173 /* Write the coprocessor state from cpu->env to the (index,value) list. */
174 int i;
175 bool ok = true;
176
177 for (i = 0; i < cpu->cpreg_array_len; i++) {
178 uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
179 const ARMCPRegInfo *ri;
180 uint64_t v;
181 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
182 if (!ri) {
183 ok = false;
184 continue;
185 }
186 if (ri->type & ARM_CP_NO_MIGRATE) {
187 continue;
188 }
189 if (!read_raw_cp_reg(&cpu->env, ri, &v)) {
190 ok = false;
191 continue;
192 }
193 cpu->cpreg_values[i] = v;
194 }
195 return ok;
196 }
197
198 bool write_list_to_cpustate(ARMCPU *cpu)
199 {
200 int i;
201 bool ok = true;
202
203 for (i = 0; i < cpu->cpreg_array_len; i++) {
204 uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
205 uint64_t v = cpu->cpreg_values[i];
206 uint64_t readback;
207 const ARMCPRegInfo *ri;
208
209 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
210 if (!ri) {
211 ok = false;
212 continue;
213 }
214 if (ri->type & ARM_CP_NO_MIGRATE) {
215 continue;
216 }
217 /* Write value and confirm it reads back as written
218 * (to catch read-only registers and partially read-only
219 * registers where the incoming migration value doesn't match)
220 */
221 if (!write_raw_cp_reg(&cpu->env, ri, v) ||
222 !read_raw_cp_reg(&cpu->env, ri, &readback) ||
223 readback != v) {
224 ok = false;
225 }
226 }
227 return ok;
228 }
229
230 static void add_cpreg_to_list(gpointer key, gpointer opaque)
231 {
232 ARMCPU *cpu = opaque;
233 uint64_t regidx;
234 const ARMCPRegInfo *ri;
235
236 regidx = *(uint32_t *)key;
237 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
238
239 if (!(ri->type & ARM_CP_NO_MIGRATE)) {
240 cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
241 /* The value array need not be initialized at this point */
242 cpu->cpreg_array_len++;
243 }
244 }
245
246 static void count_cpreg(gpointer key, gpointer opaque)
247 {
248 ARMCPU *cpu = opaque;
249 uint64_t regidx;
250 const ARMCPRegInfo *ri;
251
252 regidx = *(uint32_t *)key;
253 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
254
255 if (!(ri->type & ARM_CP_NO_MIGRATE)) {
256 cpu->cpreg_array_len++;
257 }
258 }
259
260 static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
261 {
262 uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a);
263 uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b);
264
265 if (aidx > bidx) {
266 return 1;
267 }
268 if (aidx < bidx) {
269 return -1;
270 }
271 return 0;
272 }
273
274 static void cpreg_make_keylist(gpointer key, gpointer value, gpointer udata)
275 {
276 GList **plist = udata;
277
278 *plist = g_list_prepend(*plist, key);
279 }
280
281 void init_cpreg_list(ARMCPU *cpu)
282 {
283 /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
284 * Note that we require cpreg_tuples[] to be sorted by key ID.
285 */
286 GList *keys = NULL;
287 int arraylen;
288
289 g_hash_table_foreach(cpu->cp_regs, cpreg_make_keylist, &keys);
290
291 keys = g_list_sort(keys, cpreg_key_compare);
292
293 cpu->cpreg_array_len = 0;
294
295 g_list_foreach(keys, count_cpreg, cpu);
296
297 arraylen = cpu->cpreg_array_len;
298 cpu->cpreg_indexes = g_new(uint64_t, arraylen);
299 cpu->cpreg_values = g_new(uint64_t, arraylen);
300 cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen);
301 cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen);
302 cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
303 cpu->cpreg_array_len = 0;
304
305 g_list_foreach(keys, add_cpreg_to_list, cpu);
306
307 assert(cpu->cpreg_array_len == arraylen);
308
309 g_list_free(keys);
310 }
311
312 static int dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
313 {
314 env->cp15.c3 = value;
315 tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */
316 return 0;
317 }
318
319 static int fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
320 {
321 if (env->cp15.c13_fcse != value) {
322 /* Unlike real hardware the qemu TLB uses virtual addresses,
323 * not modified virtual addresses, so this causes a TLB flush.
324 */
325 tlb_flush(env, 1);
326 env->cp15.c13_fcse = value;
327 }
328 return 0;
329 }
330 static int contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
331 uint64_t value)
332 {
333 if (env->cp15.c13_context != value && !arm_feature(env, ARM_FEATURE_MPU)) {
334 /* For VMSA (when not using the LPAE long descriptor page table
335 * format) this register includes the ASID, so do a TLB flush.
336 * For PMSA it is purely a process ID and no action is needed.
337 */
338 tlb_flush(env, 1);
339 }
340 env->cp15.c13_context = value;
341 return 0;
342 }
343
344 static int tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
345 uint64_t value)
346 {
347 /* Invalidate all (TLBIALL) */
348 tlb_flush(env, 1);
349 return 0;
350 }
351
352 static int tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
353 uint64_t value)
354 {
355 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
356 tlb_flush_page(env, value & TARGET_PAGE_MASK);
357 return 0;
358 }
359
360 static int tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
361 uint64_t value)
362 {
363 /* Invalidate by ASID (TLBIASID) */
364 tlb_flush(env, value == 0);
365 return 0;
366 }
367
368 static int tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
369 uint64_t value)
370 {
371 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
372 tlb_flush_page(env, value & TARGET_PAGE_MASK);
373 return 0;
374 }
375
376 static const ARMCPRegInfo cp_reginfo[] = {
377 /* DBGDIDR: just RAZ. In particular this means the "debug architecture
378 * version" bits will read as a reserved value, which should cause
379 * Linux to not try to use the debug hardware.
380 */
381 { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
382 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
383 /* MMU Domain access control / MPU write buffer control */
384 { .name = "DACR", .cp = 15,
385 .crn = 3, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
386 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3),
387 .resetvalue = 0, .writefn = dacr_write, .raw_writefn = raw_write, },
388 { .name = "FCSEIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 0,
389 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
390 .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
391 { .name = "CONTEXTIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 1,
392 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_context),
393 .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
394 /* ??? This covers not just the impdef TLB lockdown registers but also
395 * some v7VMSA registers relating to TEX remap, so it is overly broad.
396 */
397 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = CP_ANY,
398 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
399 /* MMU TLB control. Note that the wildcarding means we cover not just
400 * the unified TLB ops but also the dside/iside/inner-shareable variants.
401 */
402 { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
403 .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write,
404 .type = ARM_CP_NO_MIGRATE },
405 { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY,
406 .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write,
407 .type = ARM_CP_NO_MIGRATE },
408 { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY,
409 .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write,
410 .type = ARM_CP_NO_MIGRATE },
411 { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY,
412 .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write,
413 .type = ARM_CP_NO_MIGRATE },
414 /* Cache maintenance ops; some of this space may be overridden later. */
415 { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
416 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
417 .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
418 REGINFO_SENTINEL
419 };
420
421 static const ARMCPRegInfo not_v6_cp_reginfo[] = {
422 /* Not all pre-v6 cores implemented this WFI, so this is slightly
423 * over-broad.
424 */
425 { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
426 .access = PL1_W, .type = ARM_CP_WFI },
427 REGINFO_SENTINEL
428 };
429
430 static const ARMCPRegInfo not_v7_cp_reginfo[] = {
431 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
432 * is UNPREDICTABLE; we choose to NOP as most implementations do).
433 */
434 { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
435 .access = PL1_W, .type = ARM_CP_WFI },
436 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
437 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
438 * OMAPCP will override this space.
439 */
440 { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0,
441 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data),
442 .resetvalue = 0 },
443 { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1,
444 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn),
445 .resetvalue = 0 },
446 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
447 { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
448 .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
449 .resetvalue = 0 },
450 REGINFO_SENTINEL
451 };
452
453 static int cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
454 {
455 if (env->cp15.c1_coproc != value) {
456 env->cp15.c1_coproc = value;
457 /* ??? Is this safe when called from within a TB? */
458 tb_flush(env);
459 }
460 return 0;
461 }
462
463 static const ARMCPRegInfo v6_cp_reginfo[] = {
464 /* prefetch by MVA in v6, NOP in v7 */
465 { .name = "MVA_prefetch",
466 .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
467 .access = PL1_W, .type = ARM_CP_NOP },
468 { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
469 .access = PL0_W, .type = ARM_CP_NOP },
470 { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
471 .access = PL0_W, .type = ARM_CP_NOP },
472 { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
473 .access = PL0_W, .type = ARM_CP_NOP },
474 { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
475 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_insn),
476 .resetvalue = 0, },
477 /* Watchpoint Fault Address Register : should actually only be present
478 * for 1136, 1176, 11MPCore.
479 */
480 { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
481 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
482 { .name = "CPACR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2,
483 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_coproc),
484 .resetvalue = 0, .writefn = cpacr_write },
485 REGINFO_SENTINEL
486 };
487
488
489 static int pmreg_read(CPUARMState *env, const ARMCPRegInfo *ri,
490 uint64_t *value)
491 {
492 /* Generic performance monitor register read function for where
493 * user access may be allowed by PMUSERENR.
494 */
495 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
496 return EXCP_UDEF;
497 }
498 *value = CPREG_FIELD32(env, ri);
499 return 0;
500 }
501
502 static int pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
503 uint64_t value)
504 {
505 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
506 return EXCP_UDEF;
507 }
508 /* only the DP, X, D and E bits are writable */
509 env->cp15.c9_pmcr &= ~0x39;
510 env->cp15.c9_pmcr |= (value & 0x39);
511 return 0;
512 }
513
514 static int pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
515 uint64_t value)
516 {
517 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
518 return EXCP_UDEF;
519 }
520 value &= (1 << 31);
521 env->cp15.c9_pmcnten |= value;
522 return 0;
523 }
524
525 static int pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
526 uint64_t value)
527 {
528 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
529 return EXCP_UDEF;
530 }
531 value &= (1 << 31);
532 env->cp15.c9_pmcnten &= ~value;
533 return 0;
534 }
535
536 static int pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
537 uint64_t value)
538 {
539 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
540 return EXCP_UDEF;
541 }
542 env->cp15.c9_pmovsr &= ~value;
543 return 0;
544 }
545
546 static int pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
547 uint64_t value)
548 {
549 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
550 return EXCP_UDEF;
551 }
552 env->cp15.c9_pmxevtyper = value & 0xff;
553 return 0;
554 }
555
556 static int pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
557 uint64_t value)
558 {
559 env->cp15.c9_pmuserenr = value & 1;
560 return 0;
561 }
562
563 static int pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
564 uint64_t value)
565 {
566 /* We have no event counters so only the C bit can be changed */
567 value &= (1 << 31);
568 env->cp15.c9_pminten |= value;
569 return 0;
570 }
571
572 static int pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
573 uint64_t value)
574 {
575 value &= (1 << 31);
576 env->cp15.c9_pminten &= ~value;
577 return 0;
578 }
579
580 static int vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
581 uint64_t value)
582 {
583 env->cp15.c12_vbar = value & ~0x1Ful;
584 return 0;
585 }
586
587 static int ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri,
588 uint64_t *value)
589 {
590 ARMCPU *cpu = arm_env_get_cpu(env);
591 *value = cpu->ccsidr[env->cp15.c0_cssel];
592 return 0;
593 }
594
595 static int csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
596 uint64_t value)
597 {
598 env->cp15.c0_cssel = value & 0xf;
599 return 0;
600 }
601
602 static const ARMCPRegInfo v7_cp_reginfo[] = {
603 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
604 * debug components
605 */
606 { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
607 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
608 { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
609 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
610 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
611 { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
612 .access = PL1_W, .type = ARM_CP_NOP },
613 /* Performance monitors are implementation defined in v7,
614 * but with an ARM recommended set of registers, which we
615 * follow (although we don't actually implement any counters)
616 *
617 * Performance registers fall into three categories:
618 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
619 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
620 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
621 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
622 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
623 */
624 { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
625 .access = PL0_RW, .resetvalue = 0,
626 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
627 .readfn = pmreg_read, .writefn = pmcntenset_write,
628 .raw_readfn = raw_read, .raw_writefn = raw_write },
629 { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
630 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
631 .readfn = pmreg_read, .writefn = pmcntenclr_write,
632 .type = ARM_CP_NO_MIGRATE },
633 { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
634 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
635 .readfn = pmreg_read, .writefn = pmovsr_write,
636 .raw_readfn = raw_read, .raw_writefn = raw_write },
637 /* Unimplemented so WI. Strictly speaking write accesses in PL0 should
638 * respect PMUSERENR.
639 */
640 { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
641 .access = PL0_W, .type = ARM_CP_NOP },
642 /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
643 * We choose to RAZ/WI. XXX should respect PMUSERENR.
644 */
645 { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
646 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
647 /* Unimplemented, RAZ/WI. XXX PMUSERENR */
648 { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
649 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
650 { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
651 .access = PL0_RW,
652 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
653 .readfn = pmreg_read, .writefn = pmxevtyper_write,
654 .raw_readfn = raw_read, .raw_writefn = raw_write },
655 /* Unimplemented, RAZ/WI. XXX PMUSERENR */
656 { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
657 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
658 { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
659 .access = PL0_R | PL1_RW,
660 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
661 .resetvalue = 0,
662 .writefn = pmuserenr_write, .raw_writefn = raw_write },
663 { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
664 .access = PL1_RW,
665 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
666 .resetvalue = 0,
667 .writefn = pmintenset_write, .raw_writefn = raw_write },
668 { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
669 .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
670 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
671 .resetvalue = 0, .writefn = pmintenclr_write, },
672 { .name = "VBAR", .cp = 15, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
673 .access = PL1_RW, .writefn = vbar_write,
674 .fieldoffset = offsetof(CPUARMState, cp15.c12_vbar),
675 .resetvalue = 0 },
676 { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
677 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr),
678 .resetvalue = 0, },
679 { .name = "CCSIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
680 .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE },
681 { .name = "CSSELR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
682 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c0_cssel),
683 .writefn = csselr_write, .resetvalue = 0 },
684 /* Auxiliary ID register: this actually has an IMPDEF value but for now
685 * just RAZ for all cores:
686 */
687 { .name = "AIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 7,
688 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
689 REGINFO_SENTINEL
690 };
691
692 static int teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
693 {
694 value &= 1;
695 env->teecr = value;
696 return 0;
697 }
698
699 static int teehbr_read(CPUARMState *env, const ARMCPRegInfo *ri,
700 uint64_t *value)
701 {
702 /* This is a helper function because the user access rights
703 * depend on the value of the TEECR.
704 */
705 if (arm_current_pl(env) == 0 && (env->teecr & 1)) {
706 return EXCP_UDEF;
707 }
708 *value = env->teehbr;
709 return 0;
710 }
711
712 static int teehbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
713 uint64_t value)
714 {
715 if (arm_current_pl(env) == 0 && (env->teecr & 1)) {
716 return EXCP_UDEF;
717 }
718 env->teehbr = value;
719 return 0;
720 }
721
722 static const ARMCPRegInfo t2ee_cp_reginfo[] = {
723 { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
724 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
725 .resetvalue = 0,
726 .writefn = teecr_write },
727 { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
728 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
729 .resetvalue = 0, .raw_readfn = raw_read, .raw_writefn = raw_write,
730 .readfn = teehbr_read, .writefn = teehbr_write },
731 REGINFO_SENTINEL
732 };
733
734 static const ARMCPRegInfo v6k_cp_reginfo[] = {
735 { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64,
736 .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0,
737 .access = PL0_RW,
738 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el0), .resetvalue = 0 },
739 { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
740 .access = PL0_RW,
741 .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidr_el0),
742 .resetfn = arm_cp_reset_ignore },
743 { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64,
744 .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
745 .access = PL0_R|PL1_W,
746 .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el0), .resetvalue = 0 },
747 { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
748 .access = PL0_R|PL1_W,
749 .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidrro_el0),
750 .resetfn = arm_cp_reset_ignore },
751 { .name = "TPIDR_EL1", .state = ARM_CP_STATE_BOTH,
752 .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0,
753 .access = PL1_RW,
754 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el1), .resetvalue = 0 },
755 REGINFO_SENTINEL
756 };
757
758 #ifndef CONFIG_USER_ONLY
759
760 static uint64_t gt_get_countervalue(CPUARMState *env)
761 {
762 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE;
763 }
764
765 static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
766 {
767 ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
768
769 if (gt->ctl & 1) {
770 /* Timer enabled: calculate and set current ISTATUS, irq, and
771 * reset timer to when ISTATUS next has to change
772 */
773 uint64_t count = gt_get_countervalue(&cpu->env);
774 /* Note that this must be unsigned 64 bit arithmetic: */
775 int istatus = count >= gt->cval;
776 uint64_t nexttick;
777
778 gt->ctl = deposit32(gt->ctl, 2, 1, istatus);
779 qemu_set_irq(cpu->gt_timer_outputs[timeridx],
780 (istatus && !(gt->ctl & 2)));
781 if (istatus) {
782 /* Next transition is when count rolls back over to zero */
783 nexttick = UINT64_MAX;
784 } else {
785 /* Next transition is when we hit cval */
786 nexttick = gt->cval;
787 }
788 /* Note that the desired next expiry time might be beyond the
789 * signed-64-bit range of a QEMUTimer -- in this case we just
790 * set the timer for as far in the future as possible. When the
791 * timer expires we will reset the timer for any remaining period.
792 */
793 if (nexttick > INT64_MAX / GTIMER_SCALE) {
794 nexttick = INT64_MAX / GTIMER_SCALE;
795 }
796 timer_mod(cpu->gt_timer[timeridx], nexttick);
797 } else {
798 /* Timer disabled: ISTATUS and timer output always clear */
799 gt->ctl &= ~4;
800 qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0);
801 timer_del(cpu->gt_timer[timeridx]);
802 }
803 }
804
805 static int gt_cntfrq_read(CPUARMState *env, const ARMCPRegInfo *ri,
806 uint64_t *value)
807 {
808 /* Not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero */
809 if (arm_current_pl(env) == 0 && !extract32(env->cp15.c14_cntkctl, 0, 2)) {
810 return EXCP_UDEF;
811 }
812 *value = env->cp15.c14_cntfrq;
813 return 0;
814 }
815
816 static void gt_cnt_reset(CPUARMState *env, const ARMCPRegInfo *ri)
817 {
818 ARMCPU *cpu = arm_env_get_cpu(env);
819 int timeridx = ri->opc1 & 1;
820
821 timer_del(cpu->gt_timer[timeridx]);
822 }
823
824 static int gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri,
825 uint64_t *value)
826 {
827 int timeridx = ri->opc1 & 1;
828
829 if (arm_current_pl(env) == 0 &&
830 !extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
831 return EXCP_UDEF;
832 }
833 *value = gt_get_countervalue(env);
834 return 0;
835 }
836
837 static int gt_cval_read(CPUARMState *env, const ARMCPRegInfo *ri,
838 uint64_t *value)
839 {
840 int timeridx = ri->opc1 & 1;
841
842 if (arm_current_pl(env) == 0 &&
843 !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
844 return EXCP_UDEF;
845 }
846 *value = env->cp15.c14_timer[timeridx].cval;
847 return 0;
848 }
849
850 static int gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
851 uint64_t value)
852 {
853 int timeridx = ri->opc1 & 1;
854
855 env->cp15.c14_timer[timeridx].cval = value;
856 gt_recalc_timer(arm_env_get_cpu(env), timeridx);
857 return 0;
858 }
859 static int gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri,
860 uint64_t *value)
861 {
862 int timeridx = ri->crm & 1;
863
864 if (arm_current_pl(env) == 0 &&
865 !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
866 return EXCP_UDEF;
867 }
868 *value = (uint32_t)(env->cp15.c14_timer[timeridx].cval -
869 gt_get_countervalue(env));
870 return 0;
871 }
872
873 static int gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
874 uint64_t value)
875 {
876 int timeridx = ri->crm & 1;
877
878 env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) +
879 + sextract64(value, 0, 32);
880 gt_recalc_timer(arm_env_get_cpu(env), timeridx);
881 return 0;
882 }
883
884 static int gt_ctl_read(CPUARMState *env, const ARMCPRegInfo *ri,
885 uint64_t *value)
886 {
887 int timeridx = ri->crm & 1;
888
889 if (arm_current_pl(env) == 0 &&
890 !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
891 return EXCP_UDEF;
892 }
893 *value = env->cp15.c14_timer[timeridx].ctl;
894 return 0;
895 }
896
897 static int gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
898 uint64_t value)
899 {
900 ARMCPU *cpu = arm_env_get_cpu(env);
901 int timeridx = ri->crm & 1;
902 uint32_t oldval = env->cp15.c14_timer[timeridx].ctl;
903
904 env->cp15.c14_timer[timeridx].ctl = value & 3;
905 if ((oldval ^ value) & 1) {
906 /* Enable toggled */
907 gt_recalc_timer(cpu, timeridx);
908 } else if ((oldval & value) & 2) {
909 /* IMASK toggled: don't need to recalculate,
910 * just set the interrupt line based on ISTATUS
911 */
912 qemu_set_irq(cpu->gt_timer_outputs[timeridx],
913 (oldval & 4) && (value & 2));
914 }
915 return 0;
916 }
917
918 void arm_gt_ptimer_cb(void *opaque)
919 {
920 ARMCPU *cpu = opaque;
921
922 gt_recalc_timer(cpu, GTIMER_PHYS);
923 }
924
925 void arm_gt_vtimer_cb(void *opaque)
926 {
927 ARMCPU *cpu = opaque;
928
929 gt_recalc_timer(cpu, GTIMER_VIRT);
930 }
931
932 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
933 /* Note that CNTFRQ is purely reads-as-written for the benefit
934 * of software; writing it doesn't actually change the timer frequency.
935 * Our reset value matches the fixed frequency we implement the timer at.
936 */
937 { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0,
938 .access = PL1_RW | PL0_R,
939 .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq),
940 .resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE,
941 .readfn = gt_cntfrq_read, .raw_readfn = raw_read,
942 },
943 /* overall control: mostly access permissions */
944 { .name = "CNTKCTL", .cp = 15, .crn = 14, .crm = 1, .opc1 = 0, .opc2 = 0,
945 .access = PL1_RW,
946 .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl),
947 .resetvalue = 0,
948 },
949 /* per-timer control */
950 { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
951 .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
952 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
953 .resetvalue = 0,
954 .readfn = gt_ctl_read, .writefn = gt_ctl_write,
955 .raw_readfn = raw_read, .raw_writefn = raw_write,
956 },
957 { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1,
958 .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
959 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
960 .resetvalue = 0,
961 .readfn = gt_ctl_read, .writefn = gt_ctl_write,
962 .raw_readfn = raw_read, .raw_writefn = raw_write,
963 },
964 /* TimerValue views: a 32 bit downcounting view of the underlying state */
965 { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
966 .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
967 .readfn = gt_tval_read, .writefn = gt_tval_write,
968 },
969 { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0,
970 .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
971 .readfn = gt_tval_read, .writefn = gt_tval_write,
972 },
973 /* The counter itself */
974 { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0,
975 .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO,
976 .readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
977 },
978 { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1,
979 .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO,
980 .readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
981 },
982 /* Comparison value, indicating when the timer goes off */
983 { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2,
984 .access = PL1_RW | PL0_R,
985 .type = ARM_CP_64BIT | ARM_CP_IO,
986 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
987 .resetvalue = 0,
988 .readfn = gt_cval_read, .writefn = gt_cval_write,
989 .raw_readfn = raw_read, .raw_writefn = raw_write,
990 },
991 { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3,
992 .access = PL1_RW | PL0_R,
993 .type = ARM_CP_64BIT | ARM_CP_IO,
994 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
995 .resetvalue = 0,
996 .readfn = gt_cval_read, .writefn = gt_cval_write,
997 .raw_readfn = raw_read, .raw_writefn = raw_write,
998 },
999 REGINFO_SENTINEL
1000 };
1001
1002 #else
1003 /* In user-mode none of the generic timer registers are accessible,
1004 * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs,
1005 * so instead just don't register any of them.
1006 */
1007 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1008 REGINFO_SENTINEL
1009 };
1010
1011 #endif
1012
1013 static int par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1014 {
1015 if (arm_feature(env, ARM_FEATURE_LPAE)) {
1016 env->cp15.c7_par = value;
1017 } else if (arm_feature(env, ARM_FEATURE_V7)) {
1018 env->cp15.c7_par = value & 0xfffff6ff;
1019 } else {
1020 env->cp15.c7_par = value & 0xfffff1ff;
1021 }
1022 return 0;
1023 }
1024
1025 #ifndef CONFIG_USER_ONLY
1026 /* get_phys_addr() isn't present for user-mode-only targets */
1027
1028 /* Return true if extended addresses are enabled, ie this is an
1029 * LPAE implementation and we are using the long-descriptor translation
1030 * table format because the TTBCR EAE bit is set.
1031 */
1032 static inline bool extended_addresses_enabled(CPUARMState *env)
1033 {
1034 return arm_feature(env, ARM_FEATURE_LPAE)
1035 && (env->cp15.c2_control & (1U << 31));
1036 }
1037
1038 static int ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1039 {
1040 hwaddr phys_addr;
1041 target_ulong page_size;
1042 int prot;
1043 int ret, is_user = ri->opc2 & 2;
1044 int access_type = ri->opc2 & 1;
1045
1046 if (ri->opc2 & 4) {
1047 /* Other states are only available with TrustZone */
1048 return EXCP_UDEF;
1049 }
1050 ret = get_phys_addr(env, value, access_type, is_user,
1051 &phys_addr, &prot, &page_size);
1052 if (extended_addresses_enabled(env)) {
1053 /* ret is a DFSR/IFSR value for the long descriptor
1054 * translation table format, but with WnR always clear.
1055 * Convert it to a 64-bit PAR.
1056 */
1057 uint64_t par64 = (1 << 11); /* LPAE bit always set */
1058 if (ret == 0) {
1059 par64 |= phys_addr & ~0xfffULL;
1060 /* We don't set the ATTR or SH fields in the PAR. */
1061 } else {
1062 par64 |= 1; /* F */
1063 par64 |= (ret & 0x3f) << 1; /* FS */
1064 /* Note that S2WLK and FSTAGE are always zero, because we don't
1065 * implement virtualization and therefore there can't be a stage 2
1066 * fault.
1067 */
1068 }
1069 env->cp15.c7_par = par64;
1070 env->cp15.c7_par_hi = par64 >> 32;
1071 } else {
1072 /* ret is a DFSR/IFSR value for the short descriptor
1073 * translation table format (with WnR always clear).
1074 * Convert it to a 32-bit PAR.
1075 */
1076 if (ret == 0) {
1077 /* We do not set any attribute bits in the PAR */
1078 if (page_size == (1 << 24)
1079 && arm_feature(env, ARM_FEATURE_V7)) {
1080 env->cp15.c7_par = (phys_addr & 0xff000000) | 1 << 1;
1081 } else {
1082 env->cp15.c7_par = phys_addr & 0xfffff000;
1083 }
1084 } else {
1085 env->cp15.c7_par = ((ret & (10 << 1)) >> 5) |
1086 ((ret & (12 << 1)) >> 6) |
1087 ((ret & 0xf) << 1) | 1;
1088 }
1089 env->cp15.c7_par_hi = 0;
1090 }
1091 return 0;
1092 }
1093 #endif
1094
1095 static const ARMCPRegInfo vapa_cp_reginfo[] = {
1096 { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
1097 .access = PL1_RW, .resetvalue = 0,
1098 .fieldoffset = offsetof(CPUARMState, cp15.c7_par),
1099 .writefn = par_write },
1100 #ifndef CONFIG_USER_ONLY
1101 { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
1102 .access = PL1_W, .writefn = ats_write, .type = ARM_CP_NO_MIGRATE },
1103 #endif
1104 REGINFO_SENTINEL
1105 };
1106
1107 /* Return basic MPU access permission bits. */
1108 static uint32_t simple_mpu_ap_bits(uint32_t val)
1109 {
1110 uint32_t ret;
1111 uint32_t mask;
1112 int i;
1113 ret = 0;
1114 mask = 3;
1115 for (i = 0; i < 16; i += 2) {
1116 ret |= (val >> i) & mask;
1117 mask <<= 2;
1118 }
1119 return ret;
1120 }
1121
1122 /* Pad basic MPU access permission bits to extended format. */
1123 static uint32_t extended_mpu_ap_bits(uint32_t val)
1124 {
1125 uint32_t ret;
1126 uint32_t mask;
1127 int i;
1128 ret = 0;
1129 mask = 3;
1130 for (i = 0; i < 16; i += 2) {
1131 ret |= (val & mask) << i;
1132 mask <<= 2;
1133 }
1134 return ret;
1135 }
1136
1137 static int pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
1138 uint64_t value)
1139 {
1140 env->cp15.c5_data = extended_mpu_ap_bits(value);
1141 return 0;
1142 }
1143
1144 static int pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri,
1145 uint64_t *value)
1146 {
1147 *value = simple_mpu_ap_bits(env->cp15.c5_data);
1148 return 0;
1149 }
1150
1151 static int pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
1152 uint64_t value)
1153 {
1154 env->cp15.c5_insn = extended_mpu_ap_bits(value);
1155 return 0;
1156 }
1157
1158 static int pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri,
1159 uint64_t *value)
1160 {
1161 *value = simple_mpu_ap_bits(env->cp15.c5_insn);
1162 return 0;
1163 }
1164
1165 static int arm946_prbs_read(CPUARMState *env, const ARMCPRegInfo *ri,
1166 uint64_t *value)
1167 {
1168 if (ri->crm >= 8) {
1169 return EXCP_UDEF;
1170 }
1171 *value = env->cp15.c6_region[ri->crm];
1172 return 0;
1173 }
1174
1175 static int arm946_prbs_write(CPUARMState *env, const ARMCPRegInfo *ri,
1176 uint64_t value)
1177 {
1178 if (ri->crm >= 8) {
1179 return EXCP_UDEF;
1180 }
1181 env->cp15.c6_region[ri->crm] = value;
1182 return 0;
1183 }
1184
1185 static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
1186 { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
1187 .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
1188 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0,
1189 .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
1190 { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
1191 .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
1192 .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0,
1193 .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
1194 { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
1195 .access = PL1_RW,
1196 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
1197 { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
1198 .access = PL1_RW,
1199 .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, },
1200 { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
1201 .access = PL1_RW,
1202 .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
1203 { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
1204 .access = PL1_RW,
1205 .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
1206 /* Protection region base and size registers */
1207 { .name = "946_PRBS", .cp = 15, .crn = 6, .crm = CP_ANY, .opc1 = 0,
1208 .opc2 = CP_ANY, .access = PL1_RW,
1209 .readfn = arm946_prbs_read, .writefn = arm946_prbs_write, },
1210 REGINFO_SENTINEL
1211 };
1212
1213 static int vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
1214 uint64_t value)
1215 {
1216 int maskshift = extract32(value, 0, 3);
1217
1218 if (arm_feature(env, ARM_FEATURE_LPAE) && (value & (1 << 31))) {
1219 value &= ~((7 << 19) | (3 << 14) | (0xf << 3));
1220 } else {
1221 value &= 7;
1222 }
1223 /* Note that we always calculate c2_mask and c2_base_mask, but
1224 * they are only used for short-descriptor tables (ie if EAE is 0);
1225 * for long-descriptor tables the TTBCR fields are used differently
1226 * and the c2_mask and c2_base_mask values are meaningless.
1227 */
1228 env->cp15.c2_control = value;
1229 env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> maskshift);
1230 env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> maskshift);
1231 return 0;
1232 }
1233
1234 static int vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1235 uint64_t value)
1236 {
1237 if (arm_feature(env, ARM_FEATURE_LPAE)) {
1238 /* With LPAE the TTBCR could result in a change of ASID
1239 * via the TTBCR.A1 bit, so do a TLB flush.
1240 */
1241 tlb_flush(env, 1);
1242 }
1243 return vmsa_ttbcr_raw_write(env, ri, value);
1244 }
1245
1246 static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1247 {
1248 env->cp15.c2_base_mask = 0xffffc000u;
1249 env->cp15.c2_control = 0;
1250 env->cp15.c2_mask = 0;
1251 }
1252
1253 static const ARMCPRegInfo vmsa_cp_reginfo[] = {
1254 { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
1255 .access = PL1_RW,
1256 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
1257 { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
1258 .access = PL1_RW,
1259 .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, },
1260 { .name = "TTBR0", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
1261 .access = PL1_RW,
1262 .fieldoffset = offsetof(CPUARMState, cp15.c2_base0), .resetvalue = 0, },
1263 { .name = "TTBR1", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
1264 .access = PL1_RW,
1265 .fieldoffset = offsetof(CPUARMState, cp15.c2_base1), .resetvalue = 0, },
1266 { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
1267 .access = PL1_RW, .writefn = vmsa_ttbcr_write,
1268 .resetfn = vmsa_ttbcr_reset, .raw_writefn = vmsa_ttbcr_raw_write,
1269 .fieldoffset = offsetof(CPUARMState, cp15.c2_control) },
1270 { .name = "DFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
1271 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_data),
1272 .resetvalue = 0, },
1273 REGINFO_SENTINEL
1274 };
1275
1276 static int omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
1277 uint64_t value)
1278 {
1279 env->cp15.c15_ticonfig = value & 0xe7;
1280 /* The OS_TYPE bit in this register changes the reported CPUID! */
1281 env->cp15.c0_cpuid = (value & (1 << 5)) ?
1282 ARM_CPUID_TI915T : ARM_CPUID_TI925T;
1283 return 0;
1284 }
1285
1286 static int omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,
1287 uint64_t value)
1288 {
1289 env->cp15.c15_threadid = value & 0xffff;
1290 return 0;
1291 }
1292
1293 static int omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
1294 uint64_t value)
1295 {
1296 /* Wait-for-interrupt (deprecated) */
1297 cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT);
1298 return 0;
1299 }
1300
1301 static int omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
1302 uint64_t value)
1303 {
1304 /* On OMAP there are registers indicating the max/min index of dcache lines
1305 * containing a dirty line; cache flush operations have to reset these.
1306 */
1307 env->cp15.c15_i_max = 0x000;
1308 env->cp15.c15_i_min = 0xff0;
1309 return 0;
1310 }
1311
1312 static const ARMCPRegInfo omap_cp_reginfo[] = {
1313 { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
1314 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
1315 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
1316 { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
1317 .access = PL1_RW, .type = ARM_CP_NOP },
1318 { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
1319 .access = PL1_RW,
1320 .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
1321 .writefn = omap_ticonfig_write },
1322 { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,
1323 .access = PL1_RW,
1324 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
1325 { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
1326 .access = PL1_RW, .resetvalue = 0xff0,
1327 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },
1328 { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,
1329 .access = PL1_RW,
1330 .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
1331 .writefn = omap_threadid_write },
1332 { .name = "TI925T_STATUS", .cp = 15, .crn = 15,
1333 .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
1334 .type = ARM_CP_NO_MIGRATE,
1335 .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
1336 /* TODO: Peripheral port remap register:
1337 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
1338 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
1339 * when MMU is off.
1340 */
1341 { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
1342 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
1343 .type = ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE,
1344 .writefn = omap_cachemaint_write },
1345 { .name = "C9", .cp = 15, .crn = 9,
1346 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
1347 .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
1348 REGINFO_SENTINEL
1349 };
1350
1351 static int xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
1352 uint64_t value)
1353 {
1354 value &= 0x3fff;
1355 if (env->cp15.c15_cpar != value) {
1356 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
1357 tb_flush(env);
1358 env->cp15.c15_cpar = value;
1359 }
1360 return 0;
1361 }
1362
1363 static const ARMCPRegInfo xscale_cp_reginfo[] = {
1364 { .name = "XSCALE_CPAR",
1365 .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
1366 .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
1367 .writefn = xscale_cpar_write, },
1368 { .name = "XSCALE_AUXCR",
1369 .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
1370 .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
1371 .resetvalue = 0, },
1372 REGINFO_SENTINEL
1373 };
1374
1375 static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
1376 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
1377 * implementation of this implementation-defined space.
1378 * Ideally this should eventually disappear in favour of actually
1379 * implementing the correct behaviour for all cores.
1380 */
1381 { .name = "C15_IMPDEF", .cp = 15, .crn = 15,
1382 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
1383 .access = PL1_RW,
1384 .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE | ARM_CP_OVERRIDE,
1385 .resetvalue = 0 },
1386 REGINFO_SENTINEL
1387 };
1388
1389 static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
1390 /* Cache status: RAZ because we have no cache so it's always clean */
1391 { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
1392 .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1393 .resetvalue = 0 },
1394 REGINFO_SENTINEL
1395 };
1396
1397 static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
1398 /* We never have a a block transfer operation in progress */
1399 { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
1400 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1401 .resetvalue = 0 },
1402 /* The cache ops themselves: these all NOP for QEMU */
1403 { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
1404 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1405 { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
1406 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1407 { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
1408 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1409 { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
1410 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1411 { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
1412 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1413 { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
1414 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1415 REGINFO_SENTINEL
1416 };
1417
1418 static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
1419 /* The cache test-and-clean instructions always return (1 << 30)
1420 * to indicate that there are no dirty cache lines.
1421 */
1422 { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
1423 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1424 .resetvalue = (1 << 30) },
1425 { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
1426 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1427 .resetvalue = (1 << 30) },
1428 REGINFO_SENTINEL
1429 };
1430
1431 static const ARMCPRegInfo strongarm_cp_reginfo[] = {
1432 /* Ignore ReadBuffer accesses */
1433 { .name = "C9_READBUFFER", .cp = 15, .crn = 9,
1434 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
1435 .access = PL1_RW, .resetvalue = 0,
1436 .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE },
1437 REGINFO_SENTINEL
1438 };
1439
1440 static int mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri,
1441 uint64_t *value)
1442 {
1443 CPUState *cs = CPU(arm_env_get_cpu(env));
1444 uint32_t mpidr = cs->cpu_index;
1445 /* We don't support setting cluster ID ([8..11])
1446 * so these bits always RAZ.
1447 */
1448 if (arm_feature(env, ARM_FEATURE_V7MP)) {
1449 mpidr |= (1U << 31);
1450 /* Cores which are uniprocessor (non-coherent)
1451 * but still implement the MP extensions set
1452 * bit 30. (For instance, A9UP.) However we do
1453 * not currently model any of those cores.
1454 */
1455 }
1456 *value = mpidr;
1457 return 0;
1458 }
1459
1460 static const ARMCPRegInfo mpidr_cp_reginfo[] = {
1461 { .name = "MPIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
1462 .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_MIGRATE },
1463 REGINFO_SENTINEL
1464 };
1465
1466 static int par64_read(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value)
1467 {
1468 *value = ((uint64_t)env->cp15.c7_par_hi << 32) | env->cp15.c7_par;
1469 return 0;
1470 }
1471
1472 static int par64_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1473 {
1474 env->cp15.c7_par_hi = value >> 32;
1475 env->cp15.c7_par = value;
1476 return 0;
1477 }
1478
1479 static void par64_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1480 {
1481 env->cp15.c7_par_hi = 0;
1482 env->cp15.c7_par = 0;
1483 }
1484
1485 static int ttbr064_read(CPUARMState *env, const ARMCPRegInfo *ri,
1486 uint64_t *value)
1487 {
1488 *value = ((uint64_t)env->cp15.c2_base0_hi << 32) | env->cp15.c2_base0;
1489 return 0;
1490 }
1491
1492 static int ttbr064_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
1493 uint64_t value)
1494 {
1495 env->cp15.c2_base0_hi = value >> 32;
1496 env->cp15.c2_base0 = value;
1497 return 0;
1498 }
1499
1500 static int ttbr064_write(CPUARMState *env, const ARMCPRegInfo *ri,
1501 uint64_t value)
1502 {
1503 /* Writes to the 64 bit format TTBRs may change the ASID */
1504 tlb_flush(env, 1);
1505 return ttbr064_raw_write(env, ri, value);
1506 }
1507
1508 static void ttbr064_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1509 {
1510 env->cp15.c2_base0_hi = 0;
1511 env->cp15.c2_base0 = 0;
1512 }
1513
1514 static int ttbr164_read(CPUARMState *env, const ARMCPRegInfo *ri,
1515 uint64_t *value)
1516 {
1517 *value = ((uint64_t)env->cp15.c2_base1_hi << 32) | env->cp15.c2_base1;
1518 return 0;
1519 }
1520
1521 static int ttbr164_write(CPUARMState *env, const ARMCPRegInfo *ri,
1522 uint64_t value)
1523 {
1524 env->cp15.c2_base1_hi = value >> 32;
1525 env->cp15.c2_base1 = value;
1526 return 0;
1527 }
1528
1529 static void ttbr164_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1530 {
1531 env->cp15.c2_base1_hi = 0;
1532 env->cp15.c2_base1 = 0;
1533 }
1534
1535 static const ARMCPRegInfo lpae_cp_reginfo[] = {
1536 /* NOP AMAIR0/1: the override is because these clash with the rather
1537 * broadly specified TLB_LOCKDOWN entry in the generic cp_reginfo.
1538 */
1539 { .name = "AMAIR0", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
1540 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
1541 .resetvalue = 0 },
1542 { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
1543 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
1544 .resetvalue = 0 },
1545 /* 64 bit access versions of the (dummy) debug registers */
1546 { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
1547 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
1548 { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
1549 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
1550 { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0,
1551 .access = PL1_RW, .type = ARM_CP_64BIT,
1552 .readfn = par64_read, .writefn = par64_write, .resetfn = par64_reset },
1553 { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0,
1554 .access = PL1_RW, .type = ARM_CP_64BIT, .readfn = ttbr064_read,
1555 .writefn = ttbr064_write, .raw_writefn = ttbr064_raw_write,
1556 .resetfn = ttbr064_reset },
1557 { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
1558 .access = PL1_RW, .type = ARM_CP_64BIT, .readfn = ttbr164_read,
1559 .writefn = ttbr164_write, .resetfn = ttbr164_reset },
1560 REGINFO_SENTINEL
1561 };
1562
1563 static int aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri,
1564 uint64_t *value)
1565 {
1566 *value = vfp_get_fpcr(env);
1567 return 0;
1568 }
1569
1570 static int aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1571 uint64_t value)
1572 {
1573 vfp_set_fpcr(env, value);
1574 return 0;
1575 }
1576
1577 static int aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri,
1578 uint64_t *value)
1579 {
1580 *value = vfp_get_fpsr(env);
1581 return 0;
1582 }
1583
1584 static int aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1585 uint64_t value)
1586 {
1587 vfp_set_fpsr(env, value);
1588 return 0;
1589 }
1590
1591 static const ARMCPRegInfo v8_cp_reginfo[] = {
1592 /* Minimal set of EL0-visible registers. This will need to be expanded
1593 * significantly for system emulation of AArch64 CPUs.
1594 */
1595 { .name = "NZCV", .state = ARM_CP_STATE_AA64,
1596 .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2,
1597 .access = PL0_RW, .type = ARM_CP_NZCV },
1598 { .name = "FPCR", .state = ARM_CP_STATE_AA64,
1599 .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4,
1600 .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write },
1601 { .name = "FPSR", .state = ARM_CP_STATE_AA64,
1602 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4,
1603 .access = PL0_RW, .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write },
1604 /* This claims a 32 byte cacheline size for icache and dcache, VIPT icache.
1605 * It will eventually need to have a CPU-specified reset value.
1606 */
1607 { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64,
1608 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0,
1609 .access = PL0_R, .type = ARM_CP_CONST,
1610 .resetvalue = 0x80030003 },
1611 /* Prohibit use of DC ZVA. OPTME: implement DC ZVA and allow its use.
1612 * For system mode the DZP bit here will need to be computed, not constant.
1613 */
1614 { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64,
1615 .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0,
1616 .access = PL0_R, .type = ARM_CP_CONST,
1617 .resetvalue = 0x10 },
1618 REGINFO_SENTINEL
1619 };
1620
1621 static int sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1622 {
1623 env->cp15.c1_sys = value;
1624 /* ??? Lots of these bits are not implemented. */
1625 /* This may enable/disable the MMU, so do a TLB flush. */
1626 tlb_flush(env, 1);
1627 return 0;
1628 }
1629
1630 void register_cp_regs_for_features(ARMCPU *cpu)
1631 {
1632 /* Register all the coprocessor registers based on feature bits */
1633 CPUARMState *env = &cpu->env;
1634 if (arm_feature(env, ARM_FEATURE_M)) {
1635 /* M profile has no coprocessor registers */
1636 return;
1637 }
1638
1639 define_arm_cp_regs(cpu, cp_reginfo);
1640 if (arm_feature(env, ARM_FEATURE_V6)) {
1641 /* The ID registers all have impdef reset values */
1642 ARMCPRegInfo v6_idregs[] = {
1643 { .name = "ID_PFR0", .cp = 15, .crn = 0, .crm = 1,
1644 .opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST,
1645 .resetvalue = cpu->id_pfr0 },
1646 { .name = "ID_PFR1", .cp = 15, .crn = 0, .crm = 1,
1647 .opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST,
1648 .resetvalue = cpu->id_pfr1 },
1649 { .name = "ID_DFR0", .cp = 15, .crn = 0, .crm = 1,
1650 .opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST,
1651 .resetvalue = cpu->id_dfr0 },
1652 { .name = "ID_AFR0", .cp = 15, .crn = 0, .crm = 1,
1653 .opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST,
1654 .resetvalue = cpu->id_afr0 },
1655 { .name = "ID_MMFR0", .cp = 15, .crn = 0, .crm = 1,
1656 .opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST,
1657 .resetvalue = cpu->id_mmfr0 },
1658 { .name = "ID_MMFR1", .cp = 15, .crn = 0, .crm = 1,
1659 .opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST,
1660 .resetvalue = cpu->id_mmfr1 },
1661 { .name = "ID_MMFR2", .cp = 15, .crn = 0, .crm = 1,
1662 .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
1663 .resetvalue = cpu->id_mmfr2 },
1664 { .name = "ID_MMFR3", .cp = 15, .crn = 0, .crm = 1,
1665 .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
1666 .resetvalue = cpu->id_mmfr3 },
1667 { .name = "ID_ISAR0", .cp = 15, .crn = 0, .crm = 2,
1668 .opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST,
1669 .resetvalue = cpu->id_isar0 },
1670 { .name = "ID_ISAR1", .cp = 15, .crn = 0, .crm = 2,
1671 .opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST,
1672 .resetvalue = cpu->id_isar1 },
1673 { .name = "ID_ISAR2", .cp = 15, .crn = 0, .crm = 2,
1674 .opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST,
1675 .resetvalue = cpu->id_isar2 },
1676 { .name = "ID_ISAR3", .cp = 15, .crn = 0, .crm = 2,
1677 .opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST,
1678 .resetvalue = cpu->id_isar3 },
1679 { .name = "ID_ISAR4", .cp = 15, .crn = 0, .crm = 2,
1680 .opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST,
1681 .resetvalue = cpu->id_isar4 },
1682 { .name = "ID_ISAR5", .cp = 15, .crn = 0, .crm = 2,
1683 .opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST,
1684 .resetvalue = cpu->id_isar5 },
1685 /* 6..7 are as yet unallocated and must RAZ */
1686 { .name = "ID_ISAR6", .cp = 15, .crn = 0, .crm = 2,
1687 .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
1688 .resetvalue = 0 },
1689 { .name = "ID_ISAR7", .cp = 15, .crn = 0, .crm = 2,
1690 .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
1691 .resetvalue = 0 },
1692 REGINFO_SENTINEL
1693 };
1694 define_arm_cp_regs(cpu, v6_idregs);
1695 define_arm_cp_regs(cpu, v6_cp_reginfo);
1696 } else {
1697 define_arm_cp_regs(cpu, not_v6_cp_reginfo);
1698 }
1699 if (arm_feature(env, ARM_FEATURE_V6K)) {
1700 define_arm_cp_regs(cpu, v6k_cp_reginfo);
1701 }
1702 if (arm_feature(env, ARM_FEATURE_V7)) {
1703 /* v7 performance monitor control register: same implementor
1704 * field as main ID register, and we implement no event counters.
1705 */
1706 ARMCPRegInfo pmcr = {
1707 .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
1708 .access = PL0_RW, .resetvalue = cpu->midr & 0xff000000,
1709 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
1710 .readfn = pmreg_read, .writefn = pmcr_write,
1711 .raw_readfn = raw_read, .raw_writefn = raw_write,
1712 };
1713 ARMCPRegInfo clidr = {
1714 .name = "CLIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
1715 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr
1716 };
1717 define_one_arm_cp_reg(cpu, &pmcr);
1718 define_one_arm_cp_reg(cpu, &clidr);
1719 define_arm_cp_regs(cpu, v7_cp_reginfo);
1720 } else {
1721 define_arm_cp_regs(cpu, not_v7_cp_reginfo);
1722 }
1723 if (arm_feature(env, ARM_FEATURE_V8)) {
1724 define_arm_cp_regs(cpu, v8_cp_reginfo);
1725 }
1726 if (arm_feature(env, ARM_FEATURE_MPU)) {
1727 /* These are the MPU registers prior to PMSAv6. Any new
1728 * PMSA core later than the ARM946 will require that we
1729 * implement the PMSAv6 or PMSAv7 registers, which are
1730 * completely different.
1731 */
1732 assert(!arm_feature(env, ARM_FEATURE_V6));
1733 define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
1734 } else {
1735 define_arm_cp_regs(cpu, vmsa_cp_reginfo);
1736 }
1737 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
1738 define_arm_cp_regs(cpu, t2ee_cp_reginfo);
1739 }
1740 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
1741 define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
1742 }
1743 if (arm_feature(env, ARM_FEATURE_VAPA)) {
1744 define_arm_cp_regs(cpu, vapa_cp_reginfo);
1745 }
1746 if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) {
1747 define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo);
1748 }
1749 if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) {
1750 define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo);
1751 }
1752 if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) {
1753 define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo);
1754 }
1755 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
1756 define_arm_cp_regs(cpu, omap_cp_reginfo);
1757 }
1758 if (arm_feature(env, ARM_FEATURE_STRONGARM)) {
1759 define_arm_cp_regs(cpu, strongarm_cp_reginfo);
1760 }
1761 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1762 define_arm_cp_regs(cpu, xscale_cp_reginfo);
1763 }
1764 if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
1765 define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
1766 }
1767 if (arm_feature(env, ARM_FEATURE_LPAE)) {
1768 define_arm_cp_regs(cpu, lpae_cp_reginfo);
1769 }
1770 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
1771 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
1772 * be read-only (ie write causes UNDEF exception).
1773 */
1774 {
1775 ARMCPRegInfo id_cp_reginfo[] = {
1776 /* Note that the MIDR isn't a simple constant register because
1777 * of the TI925 behaviour where writes to another register can
1778 * cause the MIDR value to change.
1779 *
1780 * Unimplemented registers in the c15 0 0 0 space default to
1781 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
1782 * and friends override accordingly.
1783 */
1784 { .name = "MIDR",
1785 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY,
1786 .access = PL1_R, .resetvalue = cpu->midr,
1787 .writefn = arm_cp_write_ignore, .raw_writefn = raw_write,
1788 .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
1789 .type = ARM_CP_OVERRIDE },
1790 { .name = "CTR",
1791 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
1792 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
1793 { .name = "TCMTR",
1794 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2,
1795 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1796 { .name = "TLBTR",
1797 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
1798 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1799 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
1800 { .name = "DUMMY",
1801 .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY,
1802 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1803 { .name = "DUMMY",
1804 .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY,
1805 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1806 { .name = "DUMMY",
1807 .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY,
1808 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1809 { .name = "DUMMY",
1810 .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY,
1811 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1812 { .name = "DUMMY",
1813 .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
1814 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1815 REGINFO_SENTINEL
1816 };
1817 ARMCPRegInfo crn0_wi_reginfo = {
1818 .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
1819 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
1820 .type = ARM_CP_NOP | ARM_CP_OVERRIDE
1821 };
1822 if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
1823 arm_feature(env, ARM_FEATURE_STRONGARM)) {
1824 ARMCPRegInfo *r;
1825 /* Register the blanket "writes ignored" value first to cover the
1826 * whole space. Then update the specific ID registers to allow write
1827 * access, so that they ignore writes rather than causing them to
1828 * UNDEF.
1829 */
1830 define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
1831 for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
1832 r->access = PL1_RW;
1833 }
1834 }
1835 define_arm_cp_regs(cpu, id_cp_reginfo);
1836 }
1837
1838 if (arm_feature(env, ARM_FEATURE_MPIDR)) {
1839 define_arm_cp_regs(cpu, mpidr_cp_reginfo);
1840 }
1841
1842 if (arm_feature(env, ARM_FEATURE_AUXCR)) {
1843 ARMCPRegInfo auxcr = {
1844 .name = "AUXCR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1,
1845 .access = PL1_RW, .type = ARM_CP_CONST,
1846 .resetvalue = cpu->reset_auxcr
1847 };
1848 define_one_arm_cp_reg(cpu, &auxcr);
1849 }
1850
1851 if (arm_feature(env, ARM_FEATURE_CBAR)) {
1852 ARMCPRegInfo cbar = {
1853 .name = "CBAR", .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
1854 .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
1855 .fieldoffset = offsetof(CPUARMState, cp15.c15_config_base_address)
1856 };
1857 define_one_arm_cp_reg(cpu, &cbar);
1858 }
1859
1860 /* Generic registers whose values depend on the implementation */
1861 {
1862 ARMCPRegInfo sctlr = {
1863 .name = "SCTLR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
1864 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_sys),
1865 .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
1866 .raw_writefn = raw_write,
1867 };
1868 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1869 /* Normally we would always end the TB on an SCTLR write, but Linux
1870 * arch/arm/mach-pxa/sleep.S expects two instructions following
1871 * an MMU enable to execute from cache. Imitate this behaviour.
1872 */
1873 sctlr.type |= ARM_CP_SUPPRESS_TB_END;
1874 }
1875 define_one_arm_cp_reg(cpu, &sctlr);
1876 }
1877 }
1878
1879 ARMCPU *cpu_arm_init(const char *cpu_model)
1880 {
1881 ARMCPU *cpu;
1882 ObjectClass *oc;
1883
1884 oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
1885 if (!oc) {
1886 return NULL;
1887 }
1888 cpu = ARM_CPU(object_new(object_class_get_name(oc)));
1889
1890 /* TODO this should be set centrally, once possible */
1891 object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
1892
1893 return cpu;
1894 }
1895
1896 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
1897 {
1898 CPUState *cs = CPU(cpu);
1899 CPUARMState *env = &cpu->env;
1900
1901 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
1902 gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
1903 aarch64_fpu_gdb_set_reg,
1904 34, "aarch64-fpu.xml", 0);
1905 } else if (arm_feature(env, ARM_FEATURE_NEON)) {
1906 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
1907 51, "arm-neon.xml", 0);
1908 } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
1909 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
1910 35, "arm-vfp3.xml", 0);
1911 } else if (arm_feature(env, ARM_FEATURE_VFP)) {
1912 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
1913 19, "arm-vfp.xml", 0);
1914 }
1915 }
1916
1917 /* Sort alphabetically by type name, except for "any". */
1918 static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
1919 {
1920 ObjectClass *class_a = (ObjectClass *)a;
1921 ObjectClass *class_b = (ObjectClass *)b;
1922 const char *name_a, *name_b;
1923
1924 name_a = object_class_get_name(class_a);
1925 name_b = object_class_get_name(class_b);
1926 if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) {
1927 return 1;
1928 } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) {
1929 return -1;
1930 } else {
1931 return strcmp(name_a, name_b);
1932 }
1933 }
1934
1935 static void arm_cpu_list_entry(gpointer data, gpointer user_data)
1936 {
1937 ObjectClass *oc = data;
1938 CPUListState *s = user_data;
1939 const char *typename;
1940 char *name;
1941
1942 typename = object_class_get_name(oc);
1943 name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU));
1944 (*s->cpu_fprintf)(s->file, " %s\n",
1945 name);
1946 g_free(name);
1947 }
1948
1949 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1950 {
1951 CPUListState s = {
1952 .file = f,
1953 .cpu_fprintf = cpu_fprintf,
1954 };
1955 GSList *list;
1956
1957 list = object_class_get_list(TYPE_ARM_CPU, false);
1958 list = g_slist_sort(list, arm_cpu_list_compare);
1959 (*cpu_fprintf)(f, "Available CPUs:\n");
1960 g_slist_foreach(list, arm_cpu_list_entry, &s);
1961 g_slist_free(list);
1962 #ifdef CONFIG_KVM
1963 /* The 'host' CPU type is dynamically registered only if KVM is
1964 * enabled, so we have to special-case it here:
1965 */
1966 (*cpu_fprintf)(f, " host (only available in KVM mode)\n");
1967 #endif
1968 }
1969
1970 static void arm_cpu_add_definition(gpointer data, gpointer user_data)
1971 {
1972 ObjectClass *oc = data;
1973 CpuDefinitionInfoList **cpu_list = user_data;
1974 CpuDefinitionInfoList *entry;
1975 CpuDefinitionInfo *info;
1976 const char *typename;
1977
1978 typename = object_class_get_name(oc);
1979 info = g_malloc0(sizeof(*info));
1980 info->name = g_strndup(typename,
1981 strlen(typename) - strlen("-" TYPE_ARM_CPU));
1982
1983 entry = g_malloc0(sizeof(*entry));
1984 entry->value = info;
1985 entry->next = *cpu_list;
1986 *cpu_list = entry;
1987 }
1988
1989 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
1990 {
1991 CpuDefinitionInfoList *cpu_list = NULL;
1992 GSList *list;
1993
1994 list = object_class_get_list(TYPE_ARM_CPU, false);
1995 g_slist_foreach(list, arm_cpu_add_definition, &cpu_list);
1996 g_slist_free(list);
1997
1998 return cpu_list;
1999 }
2000
2001 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
2002 void *opaque, int state,
2003 int crm, int opc1, int opc2)
2004 {
2005 /* Private utility function for define_one_arm_cp_reg_with_opaque():
2006 * add a single reginfo struct to the hash table.
2007 */
2008 uint32_t *key = g_new(uint32_t, 1);
2009 ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
2010 int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
2011 if (r->state == ARM_CP_STATE_BOTH && state == ARM_CP_STATE_AA32) {
2012 /* The AArch32 view of a shared register sees the lower 32 bits
2013 * of a 64 bit backing field. It is not migratable as the AArch64
2014 * view handles that. AArch64 also handles reset.
2015 * We assume it is a cp15 register.
2016 */
2017 r2->cp = 15;
2018 r2->type |= ARM_CP_NO_MIGRATE;
2019 r2->resetfn = arm_cp_reset_ignore;
2020 #ifdef HOST_WORDS_BIGENDIAN
2021 if (r2->fieldoffset) {
2022 r2->fieldoffset += sizeof(uint32_t);
2023 }
2024 #endif
2025 }
2026 if (state == ARM_CP_STATE_AA64) {
2027 /* To allow abbreviation of ARMCPRegInfo
2028 * definitions, we treat cp == 0 as equivalent to
2029 * the value for "standard guest-visible sysreg".
2030 */
2031 if (r->cp == 0) {
2032 r2->cp = CP_REG_ARM64_SYSREG_CP;
2033 }
2034 *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
2035 r2->opc0, opc1, opc2);
2036 } else {
2037 *key = ENCODE_CP_REG(r2->cp, is64, r2->crn, crm, opc1, opc2);
2038 }
2039 if (opaque) {
2040 r2->opaque = opaque;
2041 }
2042 /* Make sure reginfo passed to helpers for wildcarded regs
2043 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
2044 */
2045 r2->crm = crm;
2046 r2->opc1 = opc1;
2047 r2->opc2 = opc2;
2048 /* By convention, for wildcarded registers only the first
2049 * entry is used for migration; the others are marked as
2050 * NO_MIGRATE so we don't try to transfer the register
2051 * multiple times. Special registers (ie NOP/WFI) are
2052 * never migratable.
2053 */
2054 if ((r->type & ARM_CP_SPECIAL) ||
2055 ((r->crm == CP_ANY) && crm != 0) ||
2056 ((r->opc1 == CP_ANY) && opc1 != 0) ||
2057 ((r->opc2 == CP_ANY) && opc2 != 0)) {
2058 r2->type |= ARM_CP_NO_MIGRATE;
2059 }
2060
2061 /* Overriding of an existing definition must be explicitly
2062 * requested.
2063 */
2064 if (!(r->type & ARM_CP_OVERRIDE)) {
2065 ARMCPRegInfo *oldreg;
2066 oldreg = g_hash_table_lookup(cpu->cp_regs, key);
2067 if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
2068 fprintf(stderr, "Register redefined: cp=%d %d bit "
2069 "crn=%d crm=%d opc1=%d opc2=%d, "
2070 "was %s, now %s\n", r2->cp, 32 + 32 * is64,
2071 r2->crn, r2->crm, r2->opc1, r2->opc2,
2072 oldreg->name, r2->name);
2073 g_assert_not_reached();
2074 }
2075 }
2076 g_hash_table_insert(cpu->cp_regs, key, r2);
2077 }
2078
2079
2080 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
2081 const ARMCPRegInfo *r, void *opaque)
2082 {
2083 /* Define implementations of coprocessor registers.
2084 * We store these in a hashtable because typically
2085 * there are less than 150 registers in a space which
2086 * is 16*16*16*8*8 = 262144 in size.
2087 * Wildcarding is supported for the crm, opc1 and opc2 fields.
2088 * If a register is defined twice then the second definition is
2089 * used, so this can be used to define some generic registers and
2090 * then override them with implementation specific variations.
2091 * At least one of the original and the second definition should
2092 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
2093 * against accidental use.
2094 *
2095 * The state field defines whether the register is to be
2096 * visible in the AArch32 or AArch64 execution state. If the
2097 * state is set to ARM_CP_STATE_BOTH then we synthesise a
2098 * reginfo structure for the AArch32 view, which sees the lower
2099 * 32 bits of the 64 bit register.
2100 *
2101 * Only registers visible in AArch64 may set r->opc0; opc0 cannot
2102 * be wildcarded. AArch64 registers are always considered to be 64
2103 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
2104 * the register, if any.
2105 */
2106 int crm, opc1, opc2, state;
2107 int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
2108 int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
2109 int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
2110 int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
2111 int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
2112 int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
2113 /* 64 bit registers have only CRm and Opc1 fields */
2114 assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
2115 /* op0 only exists in the AArch64 encodings */
2116 assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0));
2117 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
2118 assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT));
2119 /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
2120 * encodes a minimum access level for the register. We roll this
2121 * runtime check into our general permission check code, so check
2122 * here that the reginfo's specified permissions are strict enough
2123 * to encompass the generic architectural permission check.
2124 */
2125 if (r->state != ARM_CP_STATE_AA32) {
2126 int mask = 0;
2127 switch (r->opc1) {
2128 case 0: case 1: case 2:
2129 /* min_EL EL1 */
2130 mask = PL1_RW;
2131 break;
2132 case 3:
2133 /* min_EL EL0 */
2134 mask = PL0_RW;
2135 break;
2136 case 4:
2137 /* min_EL EL2 */
2138 mask = PL2_RW;
2139 break;
2140 case 5:
2141 /* unallocated encoding, so not possible */
2142 assert(false);
2143 break;
2144 case 6:
2145 /* min_EL EL3 */
2146 mask = PL3_RW;
2147 break;
2148 case 7:
2149 /* min_EL EL1, secure mode only (we don't check the latter) */
2150 mask = PL1_RW;
2151 break;
2152 default:
2153 /* broken reginfo with out-of-range opc1 */
2154 assert(false);
2155 break;
2156 }
2157 /* assert our permissions are not too lax (stricter is fine) */
2158 assert((r->access & ~mask) == 0);
2159 }
2160
2161 /* Check that the register definition has enough info to handle
2162 * reads and writes if they are permitted.
2163 */
2164 if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
2165 if (r->access & PL3_R) {
2166 assert(r->fieldoffset || r->readfn);
2167 }
2168 if (r->access & PL3_W) {
2169 assert(r->fieldoffset || r->writefn);
2170 }
2171 }
2172 /* Bad type field probably means missing sentinel at end of reg list */
2173 assert(cptype_valid(r->type));
2174 for (crm = crmmin; crm <= crmmax; crm++) {
2175 for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
2176 for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
2177 for (state = ARM_CP_STATE_AA32;
2178 state <= ARM_CP_STATE_AA64; state++) {
2179 if (r->state != state && r->state != ARM_CP_STATE_BOTH) {
2180 continue;
2181 }
2182 add_cpreg_to_hashtable(cpu, r, opaque, state,
2183 crm, opc1, opc2);
2184 }
2185 }
2186 }
2187 }
2188 }
2189
2190 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
2191 const ARMCPRegInfo *regs, void *opaque)
2192 {
2193 /* Define a whole list of registers */
2194 const ARMCPRegInfo *r;
2195 for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
2196 define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
2197 }
2198 }
2199
2200 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp)
2201 {
2202 return g_hash_table_lookup(cpregs, &encoded_cp);
2203 }
2204
2205 int arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
2206 uint64_t value)
2207 {
2208 /* Helper coprocessor write function for write-ignore registers */
2209 return 0;
2210 }
2211
2212 int arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value)
2213 {
2214 /* Helper coprocessor write function for read-as-zero registers */
2215 *value = 0;
2216 return 0;
2217 }
2218
2219 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque)
2220 {
2221 /* Helper coprocessor reset function for do-nothing-on-reset registers */
2222 }
2223
2224 static int bad_mode_switch(CPUARMState *env, int mode)
2225 {
2226 /* Return true if it is not valid for us to switch to
2227 * this CPU mode (ie all the UNPREDICTABLE cases in
2228 * the ARM ARM CPSRWriteByInstr pseudocode).
2229 */
2230 switch (mode) {
2231 case ARM_CPU_MODE_USR:
2232 case ARM_CPU_MODE_SYS:
2233 case ARM_CPU_MODE_SVC:
2234 case ARM_CPU_MODE_ABT:
2235 case ARM_CPU_MODE_UND:
2236 case ARM_CPU_MODE_IRQ:
2237 case ARM_CPU_MODE_FIQ:
2238 return 0;
2239 default:
2240 return 1;
2241 }
2242 }
2243
2244 uint32_t cpsr_read(CPUARMState *env)
2245 {
2246 int ZF;
2247 ZF = (env->ZF == 0);
2248 return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
2249 (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
2250 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
2251 | ((env->condexec_bits & 0xfc) << 8)
2252 | (env->GE << 16);
2253 }
2254
2255 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
2256 {
2257 if (mask & CPSR_NZCV) {
2258 env->ZF = (~val) & CPSR_Z;
2259 env->NF = val;
2260 env->CF = (val >> 29) & 1;
2261 env->VF = (val << 3) & 0x80000000;
2262 }
2263 if (mask & CPSR_Q)
2264 env->QF = ((val & CPSR_Q) != 0);
2265 if (mask & CPSR_T)
2266 env->thumb = ((val & CPSR_T) != 0);
2267 if (mask & CPSR_IT_0_1) {
2268 env->condexec_bits &= ~3;
2269 env->condexec_bits |= (val >> 25) & 3;
2270 }
2271 if (mask & CPSR_IT_2_7) {
2272 env->condexec_bits &= 3;
2273 env->condexec_bits |= (val >> 8) & 0xfc;
2274 }
2275 if (mask & CPSR_GE) {
2276 env->GE = (val >> 16) & 0xf;
2277 }
2278
2279 if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
2280 if (bad_mode_switch(env, val & CPSR_M)) {
2281 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
2282 * We choose to ignore the attempt and leave the CPSR M field
2283 * untouched.
2284 */
2285 mask &= ~CPSR_M;
2286 } else {
2287 switch_mode(env, val & CPSR_M);
2288 }
2289 }
2290 mask &= ~CACHED_CPSR_BITS;
2291 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
2292 }
2293
2294 /* Sign/zero extend */
2295 uint32_t HELPER(sxtb16)(uint32_t x)
2296 {
2297 uint32_t res;
2298 res = (uint16_t)(int8_t)x;
2299 res |= (uint32_t)(int8_t)(x >> 16) << 16;
2300 return res;
2301 }
2302
2303 uint32_t HELPER(uxtb16)(uint32_t x)
2304 {
2305 uint32_t res;
2306 res = (uint16_t)(uint8_t)x;
2307 res |= (uint32_t)(uint8_t)(x >> 16) << 16;
2308 return res;
2309 }
2310
2311 uint32_t HELPER(clz)(uint32_t x)
2312 {
2313 return clz32(x);
2314 }
2315
2316 int32_t HELPER(sdiv)(int32_t num, int32_t den)
2317 {
2318 if (den == 0)
2319 return 0;
2320 if (num == INT_MIN && den == -1)
2321 return INT_MIN;
2322 return num / den;
2323 }
2324
2325 uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
2326 {
2327 if (den == 0)
2328 return 0;
2329 return num / den;
2330 }
2331
2332 uint32_t HELPER(rbit)(uint32_t x)
2333 {
2334 x = ((x & 0xff000000) >> 24)
2335 | ((x & 0x00ff0000) >> 8)
2336 | ((x & 0x0000ff00) << 8)
2337 | ((x & 0x000000ff) << 24);
2338 x = ((x & 0xf0f0f0f0) >> 4)
2339 | ((x & 0x0f0f0f0f) << 4);
2340 x = ((x & 0x88888888) >> 3)
2341 | ((x & 0x44444444) >> 1)
2342 | ((x & 0x22222222) << 1)
2343 | ((x & 0x11111111) << 3);
2344 return x;
2345 }
2346
2347 #if defined(CONFIG_USER_ONLY)
2348
2349 void arm_cpu_do_interrupt(CPUState *cs)
2350 {
2351 ARMCPU *cpu = ARM_CPU(cs);
2352 CPUARMState *env = &cpu->env;
2353
2354 env->exception_index = -1;
2355 }
2356
2357 int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
2358 int mmu_idx)
2359 {
2360 if (rw == 2) {
2361 env->exception_index = EXCP_PREFETCH_ABORT;
2362 env->cp15.c6_insn = address;
2363 } else {
2364 env->exception_index = EXCP_DATA_ABORT;
2365 env->cp15.c6_data = address;
2366 }
2367 return 1;
2368 }
2369
2370 /* These should probably raise undefined insn exceptions. */
2371 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
2372 {
2373 cpu_abort(env, "v7m_mrs %d\n", reg);
2374 }
2375
2376 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
2377 {
2378 cpu_abort(env, "v7m_mrs %d\n", reg);
2379 return 0;
2380 }
2381
2382 void switch_mode(CPUARMState *env, int mode)
2383 {
2384 if (mode != ARM_CPU_MODE_USR)
2385 cpu_abort(env, "Tried to switch out of user mode\n");
2386 }
2387
2388 void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
2389 {
2390 cpu_abort(env, "banked r13 write\n");
2391 }
2392
2393 uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
2394 {
2395 cpu_abort(env, "banked r13 read\n");
2396 return 0;
2397 }
2398
2399 #else
2400
2401 /* Map CPU modes onto saved register banks. */
2402 int bank_number(int mode)
2403 {
2404 switch (mode) {
2405 case ARM_CPU_MODE_USR:
2406 case ARM_CPU_MODE_SYS:
2407 return 0;
2408 case ARM_CPU_MODE_SVC:
2409 return 1;
2410 case ARM_CPU_MODE_ABT:
2411 return 2;
2412 case ARM_CPU_MODE_UND:
2413 return 3;
2414 case ARM_CPU_MODE_IRQ:
2415 return 4;
2416 case ARM_CPU_MODE_FIQ:
2417 return 5;
2418 }
2419 hw_error("bank number requested for bad CPSR mode value 0x%x\n", mode);
2420 }
2421
2422 void switch_mode(CPUARMState *env, int mode)
2423 {
2424 int old_mode;
2425 int i;
2426
2427 old_mode = env->uncached_cpsr & CPSR_M;
2428 if (mode == old_mode)
2429 return;
2430
2431 if (old_mode == ARM_CPU_MODE_FIQ) {
2432 memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
2433 memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
2434 } else if (mode == ARM_CPU_MODE_FIQ) {
2435 memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
2436 memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
2437 }
2438
2439 i = bank_number(old_mode);
2440 env->banked_r13[i] = env->regs[13];
2441 env->banked_r14[i] = env->regs[14];
2442 env->banked_spsr[i] = env->spsr;
2443
2444 i = bank_number(mode);
2445 env->regs[13] = env->banked_r13[i];
2446 env->regs[14] = env->banked_r14[i];
2447 env->spsr = env->banked_spsr[i];
2448 }
2449
2450 static void v7m_push(CPUARMState *env, uint32_t val)
2451 {
2452 env->regs[13] -= 4;
2453 stl_phys(env->regs[13], val);
2454 }
2455
2456 static uint32_t v7m_pop(CPUARMState *env)
2457 {
2458 CPUState *cs = ENV_GET_CPU(env);
2459 uint32_t val;
2460 val = ldl_phys(cs->as, env->regs[13]);
2461 env->regs[13] += 4;
2462 return val;
2463 }
2464
2465 /* Switch to V7M main or process stack pointer. */
2466 static void switch_v7m_sp(CPUARMState *env, int process)
2467 {
2468 uint32_t tmp;
2469 if (env->v7m.current_sp != process) {
2470 tmp = env->v7m.other_sp;
2471 env->v7m.other_sp = env->regs[13];
2472 env->regs[13] = tmp;
2473 env->v7m.current_sp = process;
2474 }
2475 }
2476
2477 static void do_v7m_exception_exit(CPUARMState *env)
2478 {
2479 uint32_t type;
2480 uint32_t xpsr;
2481
2482 type = env->regs[15];
2483 if (env->v7m.exception != 0)
2484 armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
2485
2486 /* Switch to the target stack. */
2487 switch_v7m_sp(env, (type & 4) != 0);
2488 /* Pop registers. */
2489 env->regs[0] = v7m_pop(env);
2490 env->regs[1] = v7m_pop(env);
2491 env->regs[2] = v7m_pop(env);
2492 env->regs[3] = v7m_pop(env);
2493 env->regs[12] = v7m_pop(env);
2494 env->regs[14] = v7m_pop(env);
2495 env->regs[15] = v7m_pop(env);
2496 xpsr = v7m_pop(env);
2497 xpsr_write(env, xpsr, 0xfffffdff);
2498 /* Undo stack alignment. */
2499 if (xpsr & 0x200)
2500 env->regs[13] |= 4;
2501 /* ??? The exception return type specifies Thread/Handler mode. However
2502 this is also implied by the xPSR value. Not sure what to do
2503 if there is a mismatch. */
2504 /* ??? Likewise for mismatches between the CONTROL register and the stack
2505 pointer. */
2506 }
2507
2508 /* Exception names for debug logging; note that not all of these
2509 * precisely correspond to architectural exceptions.
2510 */
2511 static const char * const excnames[] = {
2512 [EXCP_UDEF] = "Undefined Instruction",
2513 [EXCP_SWI] = "SVC",
2514 [EXCP_PREFETCH_ABORT] = "Prefetch Abort",
2515 [EXCP_DATA_ABORT] = "Data Abort",
2516 [EXCP_IRQ] = "IRQ",
2517 [EXCP_FIQ] = "FIQ",
2518 [EXCP_BKPT] = "Breakpoint",
2519 [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit",
2520 [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage",
2521 [EXCP_STREX] = "QEMU intercept of STREX",
2522 };
2523
2524 static inline void arm_log_exception(int idx)
2525 {
2526 if (qemu_loglevel_mask(CPU_LOG_INT)) {
2527 const char *exc = NULL;
2528
2529 if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
2530 exc = excnames[idx];
2531 }
2532 if (!exc) {
2533 exc = "unknown";
2534 }
2535 qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc);
2536 }
2537 }
2538
2539 void arm_v7m_cpu_do_interrupt(CPUState *cs)
2540 {
2541 ARMCPU *cpu = ARM_CPU(cs);
2542 CPUARMState *env = &cpu->env;
2543 uint32_t xpsr = xpsr_read(env);
2544 uint32_t lr;
2545 uint32_t addr;
2546
2547 arm_log_exception(env->exception_index);
2548
2549 lr = 0xfffffff1;
2550 if (env->v7m.current_sp)
2551 lr |= 4;
2552 if (env->v7m.exception == 0)
2553 lr |= 8;
2554
2555 /* For exceptions we just mark as pending on the NVIC, and let that
2556 handle it. */
2557 /* TODO: Need to escalate if the current priority is higher than the
2558 one we're raising. */
2559 switch (env->exception_index) {
2560 case EXCP_UDEF:
2561 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
2562 return;
2563 case EXCP_SWI:
2564 /* The PC already points to the next instruction. */
2565 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
2566 return;
2567 case EXCP_PREFETCH_ABORT:
2568 case EXCP_DATA_ABORT:
2569 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
2570 return;
2571 case EXCP_BKPT:
2572 if (semihosting_enabled) {
2573 int nr;
2574 nr = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
2575 if (nr == 0xab) {
2576 env->regs[15] += 2;
2577 env->regs[0] = do_arm_semihosting(env);
2578 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
2579 return;
2580 }
2581 }
2582 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
2583 return;
2584 case EXCP_IRQ:
2585 env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
2586 break;
2587 case EXCP_EXCEPTION_EXIT:
2588 do_v7m_exception_exit(env);
2589 return;
2590 default:
2591 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
2592 return; /* Never happens. Keep compiler happy. */
2593 }
2594
2595 /* Align stack pointer. */
2596 /* ??? Should only do this if Configuration Control Register
2597 STACKALIGN bit is set. */
2598 if (env->regs[13] & 4) {
2599 env->regs[13] -= 4;
2600 xpsr |= 0x200;
2601 }
2602 /* Switch to the handler mode. */
2603 v7m_push(env, xpsr);
2604 v7m_push(env, env->regs[15]);
2605 v7m_push(env, env->regs[14]);
2606 v7m_push(env, env->regs[12]);
2607 v7m_push(env, env->regs[3]);
2608 v7m_push(env, env->regs[2]);
2609 v7m_push(env, env->regs[1]);
2610 v7m_push(env, env->regs[0]);
2611 switch_v7m_sp(env, 0);
2612 /* Clear IT bits */
2613 env->condexec_bits = 0;
2614 env->regs[14] = lr;
2615 addr = ldl_phys(cs->as, env->v7m.vecbase + env->v7m.exception * 4);
2616 env->regs[15] = addr & 0xfffffffe;
2617 env->thumb = addr & 1;
2618 }
2619
2620 /* Handle a CPU exception. */
2621 void arm_cpu_do_interrupt(CPUState *cs)
2622 {
2623 ARMCPU *cpu = ARM_CPU(cs);
2624 CPUARMState *env = &cpu->env;
2625 uint32_t addr;
2626 uint32_t mask;
2627 int new_mode;
2628 uint32_t offset;
2629
2630 assert(!IS_M(env));
2631
2632 arm_log_exception(env->exception_index);
2633
2634 /* TODO: Vectored interrupt controller. */
2635 switch (env->exception_index) {
2636 case EXCP_UDEF:
2637 new_mode = ARM_CPU_MODE_UND;
2638 addr = 0x04;
2639 mask = CPSR_I;
2640 if (env->thumb)
2641 offset = 2;
2642 else
2643 offset = 4;
2644 break;
2645 case EXCP_SWI:
2646 if (semihosting_enabled) {
2647 /* Check for semihosting interrupt. */
2648 if (env->thumb) {
2649 mask = arm_lduw_code(env, env->regs[15] - 2, env->bswap_code)
2650 & 0xff;
2651 } else {
2652 mask = arm_ldl_code(env, env->regs[15] - 4, env->bswap_code)
2653 & 0xffffff;
2654 }
2655 /* Only intercept calls from privileged modes, to provide some
2656 semblance of security. */
2657 if (((mask == 0x123456 && !env->thumb)
2658 || (mask == 0xab && env->thumb))
2659 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
2660 env->regs[0] = do_arm_semihosting(env);
2661 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
2662 return;
2663 }
2664 }
2665 new_mode = ARM_CPU_MODE_SVC;
2666 addr = 0x08;
2667 mask = CPSR_I;
2668 /* The PC already points to the next instruction. */
2669 offset = 0;
2670 break;
2671 case EXCP_BKPT:
2672 /* See if this is a semihosting syscall. */
2673 if (env->thumb && semihosting_enabled) {
2674 mask = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
2675 if (mask == 0xab
2676 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
2677 env->regs[15] += 2;
2678 env->regs[0] = do_arm_semihosting(env);
2679 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
2680 return;
2681 }
2682 }
2683 env->cp15.c5_insn = 2;
2684 /* Fall through to prefetch abort. */
2685 case EXCP_PREFETCH_ABORT:
2686 qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n",
2687 env->cp15.c5_insn, env->cp15.c6_insn);
2688 new_mode = ARM_CPU_MODE_ABT;
2689 addr = 0x0c;
2690 mask = CPSR_A | CPSR_I;
2691 offset = 4;
2692 break;
2693 case EXCP_DATA_ABORT:
2694 qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n",
2695 env->cp15.c5_data, env->cp15.c6_data);
2696 new_mode = ARM_CPU_MODE_ABT;
2697 addr = 0x10;
2698 mask = CPSR_A | CPSR_I;
2699 offset = 8;
2700 break;
2701 case EXCP_IRQ:
2702 new_mode = ARM_CPU_MODE_IRQ;
2703 addr = 0x18;
2704 /* Disable IRQ and imprecise data aborts. */
2705 mask = CPSR_A | CPSR_I;
2706 offset = 4;
2707 break;
2708 case EXCP_FIQ:
2709 new_mode = ARM_CPU_MODE_FIQ;
2710 addr = 0x1c;
2711 /* Disable FIQ, IRQ and imprecise data aborts. */
2712 mask = CPSR_A | CPSR_I | CPSR_F;
2713 offset = 4;
2714 break;
2715 default:
2716 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
2717 return; /* Never happens. Keep compiler happy. */
2718 }
2719 /* High vectors. */
2720 if (env->cp15.c1_sys & (1 << 13)) {
2721 /* when enabled, base address cannot be remapped. */
2722 addr += 0xffff0000;
2723 } else {
2724 /* ARM v7 architectures provide a vector base address register to remap
2725 * the interrupt vector table.
2726 * This register is only followed in non-monitor mode, and has a secure
2727 * and un-secure copy. Since the cpu is always in a un-secure operation
2728 * and is never in monitor mode this feature is always active.
2729 * Note: only bits 31:5 are valid.
2730 */
2731 addr += env->cp15.c12_vbar;
2732 }
2733 switch_mode (env, new_mode);
2734 env->spsr = cpsr_read(env);
2735 /* Clear IT bits. */
2736 env->condexec_bits = 0;
2737 /* Switch to the new mode, and to the correct instruction set. */
2738 env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
2739 env->uncached_cpsr |= mask;
2740 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
2741 * and we should just guard the thumb mode on V4 */
2742 if (arm_feature(env, ARM_FEATURE_V4T)) {
2743 env->thumb = (env->cp15.c1_sys & (1 << 30)) != 0;
2744 }
2745 env->regs[14] = env->regs[15] + offset;
2746 env->regs[15] = addr;
2747 cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
2748 }
2749
2750 /* Check section/page access permissions.
2751 Returns the page protection flags, or zero if the access is not
2752 permitted. */
2753 static inline int check_ap(CPUARMState *env, int ap, int domain_prot,
2754 int access_type, int is_user)
2755 {
2756 int prot_ro;
2757
2758 if (domain_prot == 3) {
2759 return PAGE_READ | PAGE_WRITE;
2760 }
2761
2762 if (access_type == 1)
2763 prot_ro = 0;
2764 else
2765 prot_ro = PAGE_READ;
2766
2767 switch (ap) {
2768 case 0:
2769 if (access_type == 1)
2770 return 0;
2771 switch ((env->cp15.c1_sys >> 8) & 3) {
2772 case 1:
2773 return is_user ? 0 : PAGE_READ;
2774 case 2:
2775 return PAGE_READ;
2776 default:
2777 return 0;
2778 }
2779 case 1:
2780 return is_user ? 0 : PAGE_READ | PAGE_WRITE;
2781 case 2:
2782 if (is_user)
2783 return prot_ro;
2784 else
2785 return PAGE_READ | PAGE_WRITE;
2786 case 3:
2787 return PAGE_READ | PAGE_WRITE;
2788 case 4: /* Reserved. */
2789 return 0;
2790 case 5:
2791 return is_user ? 0 : prot_ro;
2792 case 6:
2793 return prot_ro;
2794 case 7:
2795 if (!arm_feature (env, ARM_FEATURE_V6K))
2796 return 0;
2797 return prot_ro;
2798 default:
2799 abort();
2800 }
2801 }
2802
2803 static uint32_t get_level1_table_address(CPUARMState *env, uint32_t address)
2804 {
2805 uint32_t table;
2806
2807 if (address & env->cp15.c2_mask)
2808 table = env->cp15.c2_base1 & 0xffffc000;
2809 else
2810 table = env->cp15.c2_base0 & env->cp15.c2_base_mask;
2811
2812 table |= (address >> 18) & 0x3ffc;
2813 return table;
2814 }
2815
2816 static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type,
2817 int is_user, hwaddr *phys_ptr,
2818 int *prot, target_ulong *page_size)
2819 {
2820 CPUState *cs = ENV_GET_CPU(env);
2821 int code;
2822 uint32_t table;
2823 uint32_t desc;
2824 int type;
2825 int ap;
2826 int domain;
2827 int domain_prot;
2828 hwaddr phys_addr;
2829
2830 /* Pagetable walk. */
2831 /* Lookup l1 descriptor. */
2832 table = get_level1_table_address(env, address);
2833 desc = ldl_phys(cs->as, table);
2834 type = (desc & 3);
2835 domain = (desc >> 5) & 0x0f;
2836 domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
2837 if (type == 0) {
2838 /* Section translation fault. */
2839 code = 5;
2840 goto do_fault;
2841 }
2842 if (domain_prot == 0 || domain_prot == 2) {
2843 if (type == 2)
2844 code = 9; /* Section domain fault. */
2845 else
2846 code = 11; /* Page domain fault. */
2847 goto do_fault;
2848 }
2849 if (type == 2) {
2850 /* 1Mb section. */
2851 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
2852 ap = (desc >> 10) & 3;
2853 code = 13;
2854 *page_size = 1024 * 1024;
2855 } else {
2856 /* Lookup l2 entry. */
2857 if (type == 1) {
2858 /* Coarse pagetable. */
2859 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
2860 } else {
2861 /* Fine pagetable. */
2862 table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
2863 }
2864 desc = ldl_phys(cs->as, table);
2865 switch (desc & 3) {
2866 case 0: /* Page translation fault. */
2867 code = 7;
2868 goto do_fault;
2869 case 1: /* 64k page. */
2870 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
2871 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
2872 *page_size = 0x10000;
2873 break;
2874 case 2: /* 4k page. */
2875 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
2876 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
2877 *page_size = 0x1000;
2878 break;
2879 case 3: /* 1k page. */
2880 if (type == 1) {
2881 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
2882 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
2883 } else {
2884 /* Page translation fault. */
2885 code = 7;
2886 goto do_fault;
2887 }
2888 } else {
2889 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
2890 }
2891 ap = (desc >> 4) & 3;
2892 *page_size = 0x400;
2893 break;
2894 default:
2895 /* Never happens, but compiler isn't smart enough to tell. */
2896 abort();
2897 }
2898 code = 15;
2899 }
2900 *prot = check_ap(env, ap, domain_prot, access_type, is_user);
2901 if (!*prot) {
2902 /* Access permission fault. */
2903 goto do_fault;
2904 }
2905 *prot |= PAGE_EXEC;
2906 *phys_ptr = phys_addr;
2907 return 0;
2908 do_fault:
2909 return code | (domain << 4);
2910 }
2911
2912 static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type,
2913 int is_user, hwaddr *phys_ptr,
2914 int *prot, target_ulong *page_size)
2915 {
2916 CPUState *cs = ENV_GET_CPU(env);
2917 int code;
2918 uint32_t table;
2919 uint32_t desc;
2920 uint32_t xn;
2921 uint32_t pxn = 0;
2922 int type;
2923 int ap;
2924 int domain = 0;
2925 int domain_prot;
2926 hwaddr phys_addr;
2927
2928 /* Pagetable walk. */
2929 /* Lookup l1 descriptor. */
2930 table = get_level1_table_address(env, address);
2931 desc = ldl_phys(cs->as, table);
2932 type = (desc & 3);
2933 if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
2934 /* Section translation fault, or attempt to use the encoding
2935 * which is Reserved on implementations without PXN.
2936 */
2937 code = 5;
2938 goto do_fault;
2939 }
2940 if ((type == 1) || !(desc & (1 << 18))) {
2941 /* Page or Section. */
2942 domain = (desc >> 5) & 0x0f;
2943 }
2944 domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
2945 if (domain_prot == 0 || domain_prot == 2) {
2946 if (type != 1) {
2947 code = 9; /* Section domain fault. */
2948 } else {
2949 code = 11; /* Page domain fault. */
2950 }
2951 goto do_fault;
2952 }
2953 if (type != 1) {
2954 if (desc & (1 << 18)) {
2955 /* Supersection. */
2956 phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
2957 *page_size = 0x1000000;
2958 } else {
2959 /* Section. */
2960 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
2961 *page_size = 0x100000;
2962 }
2963 ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
2964 xn = desc & (1 << 4);
2965 pxn = desc & 1;
2966 code = 13;
2967 } else {
2968 if (arm_feature(env, ARM_FEATURE_PXN)) {
2969 pxn = (desc >> 2) & 1;
2970 }
2971 /* Lookup l2 entry. */
2972 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
2973 desc = ldl_phys(cs->as, table);
2974 ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
2975 switch (desc & 3) {
2976 case 0: /* Page translation fault. */
2977 code = 7;
2978 goto do_fault;
2979 case 1: /* 64k page. */
2980 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
2981 xn = desc & (1 << 15);
2982 *page_size = 0x10000;
2983 break;
2984 case 2: case 3: /* 4k page. */
2985 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
2986 xn = desc & 1<