target-arm: A64: Implement AdvSIMD reciprocal estimate insns URECPE, FRECPE
[qemu.git] / target-arm / helper.c
1 #include "cpu.h"
2 #include "exec/gdbstub.h"
3 #include "helper.h"
4 #include "qemu/host-utils.h"
5 #include "sysemu/arch_init.h"
6 #include "sysemu/sysemu.h"
7 #include "qemu/bitops.h"
8 #include "qemu/crc32c.h"
9 #include <zlib.h> /* For crc32 */
10
11 #ifndef CONFIG_USER_ONLY
12 static inline int get_phys_addr(CPUARMState *env, uint32_t address,
13 int access_type, int is_user,
14 hwaddr *phys_ptr, int *prot,
15 target_ulong *page_size);
16
17 /* Definitions for the PMCCNTR and PMCR registers */
18 #define PMCRD 0x8
19 #define PMCRC 0x4
20 #define PMCRE 0x1
21 #endif
22
23 static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
24 {
25 int nregs;
26
27 /* VFP data registers are always little-endian. */
28 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
29 if (reg < nregs) {
30 stfq_le_p(buf, env->vfp.regs[reg]);
31 return 8;
32 }
33 if (arm_feature(env, ARM_FEATURE_NEON)) {
34 /* Aliases for Q regs. */
35 nregs += 16;
36 if (reg < nregs) {
37 stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
38 stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
39 return 16;
40 }
41 }
42 switch (reg - nregs) {
43 case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
44 case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
45 case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
46 }
47 return 0;
48 }
49
50 static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
51 {
52 int nregs;
53
54 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
55 if (reg < nregs) {
56 env->vfp.regs[reg] = ldfq_le_p(buf);
57 return 8;
58 }
59 if (arm_feature(env, ARM_FEATURE_NEON)) {
60 nregs += 16;
61 if (reg < nregs) {
62 env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
63 env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
64 return 16;
65 }
66 }
67 switch (reg - nregs) {
68 case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
69 case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
70 case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
71 }
72 return 0;
73 }
74
75 static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
76 {
77 switch (reg) {
78 case 0 ... 31:
79 /* 128 bit FP register */
80 stfq_le_p(buf, env->vfp.regs[reg * 2]);
81 stfq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]);
82 return 16;
83 case 32:
84 /* FPSR */
85 stl_p(buf, vfp_get_fpsr(env));
86 return 4;
87 case 33:
88 /* FPCR */
89 stl_p(buf, vfp_get_fpcr(env));
90 return 4;
91 default:
92 return 0;
93 }
94 }
95
96 static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
97 {
98 switch (reg) {
99 case 0 ... 31:
100 /* 128 bit FP register */
101 env->vfp.regs[reg * 2] = ldfq_le_p(buf);
102 env->vfp.regs[reg * 2 + 1] = ldfq_le_p(buf + 8);
103 return 16;
104 case 32:
105 /* FPSR */
106 vfp_set_fpsr(env, ldl_p(buf));
107 return 4;
108 case 33:
109 /* FPCR */
110 vfp_set_fpcr(env, ldl_p(buf));
111 return 4;
112 default:
113 return 0;
114 }
115 }
116
117 static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri)
118 {
119 if (cpreg_field_is_64bit(ri)) {
120 return CPREG_FIELD64(env, ri);
121 } else {
122 return CPREG_FIELD32(env, ri);
123 }
124 }
125
126 static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
127 uint64_t value)
128 {
129 if (cpreg_field_is_64bit(ri)) {
130 CPREG_FIELD64(env, ri) = value;
131 } else {
132 CPREG_FIELD32(env, ri) = value;
133 }
134 }
135
136 static uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri)
137 {
138 /* Raw read of a coprocessor register (as needed for migration, etc). */
139 if (ri->type & ARM_CP_CONST) {
140 return ri->resetvalue;
141 } else if (ri->raw_readfn) {
142 return ri->raw_readfn(env, ri);
143 } else if (ri->readfn) {
144 return ri->readfn(env, ri);
145 } else {
146 return raw_read(env, ri);
147 }
148 }
149
150 static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
151 uint64_t v)
152 {
153 /* Raw write of a coprocessor register (as needed for migration, etc).
154 * Note that constant registers are treated as write-ignored; the
155 * caller should check for success by whether a readback gives the
156 * value written.
157 */
158 if (ri->type & ARM_CP_CONST) {
159 return;
160 } else if (ri->raw_writefn) {
161 ri->raw_writefn(env, ri, v);
162 } else if (ri->writefn) {
163 ri->writefn(env, ri, v);
164 } else {
165 raw_write(env, ri, v);
166 }
167 }
168
169 bool write_cpustate_to_list(ARMCPU *cpu)
170 {
171 /* Write the coprocessor state from cpu->env to the (index,value) list. */
172 int i;
173 bool ok = true;
174
175 for (i = 0; i < cpu->cpreg_array_len; i++) {
176 uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
177 const ARMCPRegInfo *ri;
178
179 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
180 if (!ri) {
181 ok = false;
182 continue;
183 }
184 if (ri->type & ARM_CP_NO_MIGRATE) {
185 continue;
186 }
187 cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri);
188 }
189 return ok;
190 }
191
192 bool write_list_to_cpustate(ARMCPU *cpu)
193 {
194 int i;
195 bool ok = true;
196
197 for (i = 0; i < cpu->cpreg_array_len; i++) {
198 uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
199 uint64_t v = cpu->cpreg_values[i];
200 const ARMCPRegInfo *ri;
201
202 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
203 if (!ri) {
204 ok = false;
205 continue;
206 }
207 if (ri->type & ARM_CP_NO_MIGRATE) {
208 continue;
209 }
210 /* Write value and confirm it reads back as written
211 * (to catch read-only registers and partially read-only
212 * registers where the incoming migration value doesn't match)
213 */
214 write_raw_cp_reg(&cpu->env, ri, v);
215 if (read_raw_cp_reg(&cpu->env, ri) != v) {
216 ok = false;
217 }
218 }
219 return ok;
220 }
221
222 static void add_cpreg_to_list(gpointer key, gpointer opaque)
223 {
224 ARMCPU *cpu = opaque;
225 uint64_t regidx;
226 const ARMCPRegInfo *ri;
227
228 regidx = *(uint32_t *)key;
229 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
230
231 if (!(ri->type & ARM_CP_NO_MIGRATE)) {
232 cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
233 /* The value array need not be initialized at this point */
234 cpu->cpreg_array_len++;
235 }
236 }
237
238 static void count_cpreg(gpointer key, gpointer opaque)
239 {
240 ARMCPU *cpu = opaque;
241 uint64_t regidx;
242 const ARMCPRegInfo *ri;
243
244 regidx = *(uint32_t *)key;
245 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
246
247 if (!(ri->type & ARM_CP_NO_MIGRATE)) {
248 cpu->cpreg_array_len++;
249 }
250 }
251
252 static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
253 {
254 uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a);
255 uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b);
256
257 if (aidx > bidx) {
258 return 1;
259 }
260 if (aidx < bidx) {
261 return -1;
262 }
263 return 0;
264 }
265
266 static void cpreg_make_keylist(gpointer key, gpointer value, gpointer udata)
267 {
268 GList **plist = udata;
269
270 *plist = g_list_prepend(*plist, key);
271 }
272
273 void init_cpreg_list(ARMCPU *cpu)
274 {
275 /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
276 * Note that we require cpreg_tuples[] to be sorted by key ID.
277 */
278 GList *keys = NULL;
279 int arraylen;
280
281 g_hash_table_foreach(cpu->cp_regs, cpreg_make_keylist, &keys);
282
283 keys = g_list_sort(keys, cpreg_key_compare);
284
285 cpu->cpreg_array_len = 0;
286
287 g_list_foreach(keys, count_cpreg, cpu);
288
289 arraylen = cpu->cpreg_array_len;
290 cpu->cpreg_indexes = g_new(uint64_t, arraylen);
291 cpu->cpreg_values = g_new(uint64_t, arraylen);
292 cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen);
293 cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen);
294 cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
295 cpu->cpreg_array_len = 0;
296
297 g_list_foreach(keys, add_cpreg_to_list, cpu);
298
299 assert(cpu->cpreg_array_len == arraylen);
300
301 g_list_free(keys);
302 }
303
304 static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
305 {
306 ARMCPU *cpu = arm_env_get_cpu(env);
307
308 env->cp15.c3 = value;
309 tlb_flush(CPU(cpu), 1); /* Flush TLB as domain not tracked in TLB */
310 }
311
312 static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
313 {
314 ARMCPU *cpu = arm_env_get_cpu(env);
315
316 if (env->cp15.c13_fcse != value) {
317 /* Unlike real hardware the qemu TLB uses virtual addresses,
318 * not modified virtual addresses, so this causes a TLB flush.
319 */
320 tlb_flush(CPU(cpu), 1);
321 env->cp15.c13_fcse = value;
322 }
323 }
324
325 static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
326 uint64_t value)
327 {
328 ARMCPU *cpu = arm_env_get_cpu(env);
329
330 if (env->cp15.c13_context != value && !arm_feature(env, ARM_FEATURE_MPU)) {
331 /* For VMSA (when not using the LPAE long descriptor page table
332 * format) this register includes the ASID, so do a TLB flush.
333 * For PMSA it is purely a process ID and no action is needed.
334 */
335 tlb_flush(CPU(cpu), 1);
336 }
337 env->cp15.c13_context = value;
338 }
339
340 static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
341 uint64_t value)
342 {
343 /* Invalidate all (TLBIALL) */
344 ARMCPU *cpu = arm_env_get_cpu(env);
345
346 tlb_flush(CPU(cpu), 1);
347 }
348
349 static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
350 uint64_t value)
351 {
352 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
353 ARMCPU *cpu = arm_env_get_cpu(env);
354
355 tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
356 }
357
358 static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
359 uint64_t value)
360 {
361 /* Invalidate by ASID (TLBIASID) */
362 ARMCPU *cpu = arm_env_get_cpu(env);
363
364 tlb_flush(CPU(cpu), value == 0);
365 }
366
367 static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
368 uint64_t value)
369 {
370 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
371 ARMCPU *cpu = arm_env_get_cpu(env);
372
373 tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
374 }
375
376 static const ARMCPRegInfo cp_reginfo[] = {
377 /* DBGDIDR: just RAZ. In particular this means the "debug architecture
378 * version" bits will read as a reserved value, which should cause
379 * Linux to not try to use the debug hardware.
380 */
381 { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
382 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
383 /* MMU Domain access control / MPU write buffer control */
384 { .name = "DACR", .cp = 15,
385 .crn = 3, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
386 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3),
387 .resetvalue = 0, .writefn = dacr_write, .raw_writefn = raw_write, },
388 { .name = "FCSEIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 0,
389 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
390 .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
391 { .name = "CONTEXTIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 1,
392 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_context),
393 .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
394 /* ??? This covers not just the impdef TLB lockdown registers but also
395 * some v7VMSA registers relating to TEX remap, so it is overly broad.
396 */
397 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = CP_ANY,
398 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
399 /* MMU TLB control. Note that the wildcarding means we cover not just
400 * the unified TLB ops but also the dside/iside/inner-shareable variants.
401 */
402 { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
403 .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write,
404 .type = ARM_CP_NO_MIGRATE },
405 { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY,
406 .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write,
407 .type = ARM_CP_NO_MIGRATE },
408 { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY,
409 .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write,
410 .type = ARM_CP_NO_MIGRATE },
411 { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY,
412 .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write,
413 .type = ARM_CP_NO_MIGRATE },
414 /* Cache maintenance ops; some of this space may be overridden later. */
415 { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
416 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
417 .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
418 REGINFO_SENTINEL
419 };
420
421 static const ARMCPRegInfo not_v6_cp_reginfo[] = {
422 /* Not all pre-v6 cores implemented this WFI, so this is slightly
423 * over-broad.
424 */
425 { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
426 .access = PL1_W, .type = ARM_CP_WFI },
427 REGINFO_SENTINEL
428 };
429
430 static const ARMCPRegInfo not_v7_cp_reginfo[] = {
431 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
432 * is UNPREDICTABLE; we choose to NOP as most implementations do).
433 */
434 { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
435 .access = PL1_W, .type = ARM_CP_WFI },
436 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
437 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
438 * OMAPCP will override this space.
439 */
440 { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0,
441 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data),
442 .resetvalue = 0 },
443 { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1,
444 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn),
445 .resetvalue = 0 },
446 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
447 { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
448 .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
449 .resetvalue = 0 },
450 REGINFO_SENTINEL
451 };
452
453 static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
454 uint64_t value)
455 {
456 if (env->cp15.c1_coproc != value) {
457 env->cp15.c1_coproc = value;
458 /* ??? Is this safe when called from within a TB? */
459 tb_flush(env);
460 }
461 }
462
463 static const ARMCPRegInfo v6_cp_reginfo[] = {
464 /* prefetch by MVA in v6, NOP in v7 */
465 { .name = "MVA_prefetch",
466 .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
467 .access = PL1_W, .type = ARM_CP_NOP },
468 { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
469 .access = PL0_W, .type = ARM_CP_NOP },
470 { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
471 .access = PL0_W, .type = ARM_CP_NOP },
472 { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
473 .access = PL0_W, .type = ARM_CP_NOP },
474 { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
475 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_insn),
476 .resetvalue = 0, },
477 /* Watchpoint Fault Address Register : should actually only be present
478 * for 1136, 1176, 11MPCore.
479 */
480 { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
481 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
482 { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
483 .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2,
484 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_coproc),
485 .resetvalue = 0, .writefn = cpacr_write },
486 REGINFO_SENTINEL
487 };
488
489 static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri)
490 {
491 /* Performance monitor registers user accessibility is controlled
492 * by PMUSERENR.
493 */
494 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
495 return CP_ACCESS_TRAP;
496 }
497 return CP_ACCESS_OK;
498 }
499
500 #ifndef CONFIG_USER_ONLY
501 static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
502 uint64_t value)
503 {
504 /* Don't computer the number of ticks in user mode */
505 uint32_t temp_ticks;
506
507 temp_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) *
508 get_ticks_per_sec() / 1000000;
509
510 if (env->cp15.c9_pmcr & PMCRE) {
511 /* If the counter is enabled */
512 if (env->cp15.c9_pmcr & PMCRD) {
513 /* Increment once every 64 processor clock cycles */
514 env->cp15.c15_ccnt = (temp_ticks/64) - env->cp15.c15_ccnt;
515 } else {
516 env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
517 }
518 }
519
520 if (value & PMCRC) {
521 /* The counter has been reset */
522 env->cp15.c15_ccnt = 0;
523 }
524
525 /* only the DP, X, D and E bits are writable */
526 env->cp15.c9_pmcr &= ~0x39;
527 env->cp15.c9_pmcr |= (value & 0x39);
528
529 if (env->cp15.c9_pmcr & PMCRE) {
530 if (env->cp15.c9_pmcr & PMCRD) {
531 /* Increment once every 64 processor clock cycles */
532 temp_ticks /= 64;
533 }
534 env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
535 }
536 }
537
538 static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
539 {
540 uint32_t total_ticks;
541
542 if (!(env->cp15.c9_pmcr & PMCRE)) {
543 /* Counter is disabled, do not change value */
544 return env->cp15.c15_ccnt;
545 }
546
547 total_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) *
548 get_ticks_per_sec() / 1000000;
549
550 if (env->cp15.c9_pmcr & PMCRD) {
551 /* Increment once every 64 processor clock cycles */
552 total_ticks /= 64;
553 }
554 return total_ticks - env->cp15.c15_ccnt;
555 }
556
557 static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
558 uint64_t value)
559 {
560 uint32_t total_ticks;
561
562 if (!(env->cp15.c9_pmcr & PMCRE)) {
563 /* Counter is disabled, set the absolute value */
564 env->cp15.c15_ccnt = value;
565 return;
566 }
567
568 total_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) *
569 get_ticks_per_sec() / 1000000;
570
571 if (env->cp15.c9_pmcr & PMCRD) {
572 /* Increment once every 64 processor clock cycles */
573 total_ticks /= 64;
574 }
575 env->cp15.c15_ccnt = total_ticks - value;
576 }
577 #endif
578
579 static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
580 uint64_t value)
581 {
582 value &= (1 << 31);
583 env->cp15.c9_pmcnten |= value;
584 }
585
586 static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
587 uint64_t value)
588 {
589 value &= (1 << 31);
590 env->cp15.c9_pmcnten &= ~value;
591 }
592
593 static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
594 uint64_t value)
595 {
596 env->cp15.c9_pmovsr &= ~value;
597 }
598
599 static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
600 uint64_t value)
601 {
602 env->cp15.c9_pmxevtyper = value & 0xff;
603 }
604
605 static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
606 uint64_t value)
607 {
608 env->cp15.c9_pmuserenr = value & 1;
609 }
610
611 static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
612 uint64_t value)
613 {
614 /* We have no event counters so only the C bit can be changed */
615 value &= (1 << 31);
616 env->cp15.c9_pminten |= value;
617 }
618
619 static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
620 uint64_t value)
621 {
622 value &= (1 << 31);
623 env->cp15.c9_pminten &= ~value;
624 }
625
626 static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
627 uint64_t value)
628 {
629 /* Note that even though the AArch64 view of this register has bits
630 * [10:0] all RES0 we can only mask the bottom 5, to comply with the
631 * architectural requirements for bits which are RES0 only in some
632 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
633 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
634 */
635 env->cp15.c12_vbar = value & ~0x1Ful;
636 }
637
638 static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
639 {
640 ARMCPU *cpu = arm_env_get_cpu(env);
641 return cpu->ccsidr[env->cp15.c0_cssel];
642 }
643
644 static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
645 uint64_t value)
646 {
647 env->cp15.c0_cssel = value & 0xf;
648 }
649
650 static const ARMCPRegInfo v7_cp_reginfo[] = {
651 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
652 * debug components
653 */
654 { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
655 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
656 { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
657 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
658 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
659 { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
660 .access = PL1_W, .type = ARM_CP_NOP },
661 /* Performance monitors are implementation defined in v7,
662 * but with an ARM recommended set of registers, which we
663 * follow (although we don't actually implement any counters)
664 *
665 * Performance registers fall into three categories:
666 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
667 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
668 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
669 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
670 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
671 */
672 { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
673 .access = PL0_RW, .resetvalue = 0,
674 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
675 .writefn = pmcntenset_write,
676 .accessfn = pmreg_access,
677 .raw_writefn = raw_write },
678 { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
679 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
680 .accessfn = pmreg_access,
681 .writefn = pmcntenclr_write,
682 .type = ARM_CP_NO_MIGRATE },
683 { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
684 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
685 .accessfn = pmreg_access,
686 .writefn = pmovsr_write,
687 .raw_writefn = raw_write },
688 /* Unimplemented so WI. */
689 { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
690 .access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP },
691 /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
692 * We choose to RAZ/WI.
693 */
694 { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
695 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
696 .accessfn = pmreg_access },
697 #ifndef CONFIG_USER_ONLY
698 { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
699 .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO,
700 .readfn = pmccntr_read, .writefn = pmccntr_write,
701 .accessfn = pmreg_access },
702 #endif
703 { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
704 .access = PL0_RW,
705 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
706 .accessfn = pmreg_access, .writefn = pmxevtyper_write,
707 .raw_writefn = raw_write },
708 /* Unimplemented, RAZ/WI. */
709 { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
710 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
711 .accessfn = pmreg_access },
712 { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
713 .access = PL0_R | PL1_RW,
714 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
715 .resetvalue = 0,
716 .writefn = pmuserenr_write, .raw_writefn = raw_write },
717 { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
718 .access = PL1_RW,
719 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
720 .resetvalue = 0,
721 .writefn = pmintenset_write, .raw_writefn = raw_write },
722 { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
723 .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
724 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
725 .resetvalue = 0, .writefn = pmintenclr_write, },
726 { .name = "VBAR", .state = ARM_CP_STATE_BOTH,
727 .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
728 .access = PL1_RW, .writefn = vbar_write,
729 .fieldoffset = offsetof(CPUARMState, cp15.c12_vbar),
730 .resetvalue = 0 },
731 { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
732 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr),
733 .resetvalue = 0, },
734 { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
735 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
736 .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE },
737 { .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
738 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
739 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c0_cssel),
740 .writefn = csselr_write, .resetvalue = 0 },
741 /* Auxiliary ID register: this actually has an IMPDEF value but for now
742 * just RAZ for all cores:
743 */
744 { .name = "AIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 7,
745 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
746 /* MAIR can just read-as-written because we don't implement caches
747 * and so don't need to care about memory attributes.
748 */
749 { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64,
750 .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0,
751 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el1),
752 .resetvalue = 0 },
753 /* For non-long-descriptor page tables these are PRRR and NMRR;
754 * regardless they still act as reads-as-written for QEMU.
755 * The override is necessary because of the overly-broad TLB_LOCKDOWN
756 * definition.
757 */
758 { .name = "MAIR0", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE,
759 .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW,
760 .fieldoffset = offsetoflow32(CPUARMState, cp15.mair_el1),
761 .resetfn = arm_cp_reset_ignore },
762 { .name = "MAIR1", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE,
763 .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW,
764 .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el1),
765 .resetfn = arm_cp_reset_ignore },
766 REGINFO_SENTINEL
767 };
768
769 static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri,
770 uint64_t value)
771 {
772 value &= 1;
773 env->teecr = value;
774 }
775
776 static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri)
777 {
778 if (arm_current_pl(env) == 0 && (env->teecr & 1)) {
779 return CP_ACCESS_TRAP;
780 }
781 return CP_ACCESS_OK;
782 }
783
784 static const ARMCPRegInfo t2ee_cp_reginfo[] = {
785 { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
786 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
787 .resetvalue = 0,
788 .writefn = teecr_write },
789 { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
790 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
791 .accessfn = teehbr_access, .resetvalue = 0 },
792 REGINFO_SENTINEL
793 };
794
795 static const ARMCPRegInfo v6k_cp_reginfo[] = {
796 { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64,
797 .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0,
798 .access = PL0_RW,
799 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el0), .resetvalue = 0 },
800 { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
801 .access = PL0_RW,
802 .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidr_el0),
803 .resetfn = arm_cp_reset_ignore },
804 { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64,
805 .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
806 .access = PL0_R|PL1_W,
807 .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el0), .resetvalue = 0 },
808 { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
809 .access = PL0_R|PL1_W,
810 .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidrro_el0),
811 .resetfn = arm_cp_reset_ignore },
812 { .name = "TPIDR_EL1", .state = ARM_CP_STATE_BOTH,
813 .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0,
814 .access = PL1_RW,
815 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el1), .resetvalue = 0 },
816 REGINFO_SENTINEL
817 };
818
819 #ifndef CONFIG_USER_ONLY
820
821 static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri)
822 {
823 /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero */
824 if (arm_current_pl(env) == 0 && !extract32(env->cp15.c14_cntkctl, 0, 2)) {
825 return CP_ACCESS_TRAP;
826 }
827 return CP_ACCESS_OK;
828 }
829
830 static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx)
831 {
832 /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
833 if (arm_current_pl(env) == 0 &&
834 !extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
835 return CP_ACCESS_TRAP;
836 }
837 return CP_ACCESS_OK;
838 }
839
840 static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx)
841 {
842 /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
843 * EL0[PV]TEN is zero.
844 */
845 if (arm_current_pl(env) == 0 &&
846 !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
847 return CP_ACCESS_TRAP;
848 }
849 return CP_ACCESS_OK;
850 }
851
852 static CPAccessResult gt_pct_access(CPUARMState *env,
853 const ARMCPRegInfo *ri)
854 {
855 return gt_counter_access(env, GTIMER_PHYS);
856 }
857
858 static CPAccessResult gt_vct_access(CPUARMState *env,
859 const ARMCPRegInfo *ri)
860 {
861 return gt_counter_access(env, GTIMER_VIRT);
862 }
863
864 static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri)
865 {
866 return gt_timer_access(env, GTIMER_PHYS);
867 }
868
869 static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri)
870 {
871 return gt_timer_access(env, GTIMER_VIRT);
872 }
873
874 static uint64_t gt_get_countervalue(CPUARMState *env)
875 {
876 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE;
877 }
878
879 static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
880 {
881 ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
882
883 if (gt->ctl & 1) {
884 /* Timer enabled: calculate and set current ISTATUS, irq, and
885 * reset timer to when ISTATUS next has to change
886 */
887 uint64_t count = gt_get_countervalue(&cpu->env);
888 /* Note that this must be unsigned 64 bit arithmetic: */
889 int istatus = count >= gt->cval;
890 uint64_t nexttick;
891
892 gt->ctl = deposit32(gt->ctl, 2, 1, istatus);
893 qemu_set_irq(cpu->gt_timer_outputs[timeridx],
894 (istatus && !(gt->ctl & 2)));
895 if (istatus) {
896 /* Next transition is when count rolls back over to zero */
897 nexttick = UINT64_MAX;
898 } else {
899 /* Next transition is when we hit cval */
900 nexttick = gt->cval;
901 }
902 /* Note that the desired next expiry time might be beyond the
903 * signed-64-bit range of a QEMUTimer -- in this case we just
904 * set the timer for as far in the future as possible. When the
905 * timer expires we will reset the timer for any remaining period.
906 */
907 if (nexttick > INT64_MAX / GTIMER_SCALE) {
908 nexttick = INT64_MAX / GTIMER_SCALE;
909 }
910 timer_mod(cpu->gt_timer[timeridx], nexttick);
911 } else {
912 /* Timer disabled: ISTATUS and timer output always clear */
913 gt->ctl &= ~4;
914 qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0);
915 timer_del(cpu->gt_timer[timeridx]);
916 }
917 }
918
919 static void gt_cnt_reset(CPUARMState *env, const ARMCPRegInfo *ri)
920 {
921 ARMCPU *cpu = arm_env_get_cpu(env);
922 int timeridx = ri->opc1 & 1;
923
924 timer_del(cpu->gt_timer[timeridx]);
925 }
926
927 static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
928 {
929 return gt_get_countervalue(env);
930 }
931
932 static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
933 uint64_t value)
934 {
935 int timeridx = ri->opc1 & 1;
936
937 env->cp15.c14_timer[timeridx].cval = value;
938 gt_recalc_timer(arm_env_get_cpu(env), timeridx);
939 }
940
941 static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
942 {
943 int timeridx = ri->crm & 1;
944
945 return (uint32_t)(env->cp15.c14_timer[timeridx].cval -
946 gt_get_countervalue(env));
947 }
948
949 static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
950 uint64_t value)
951 {
952 int timeridx = ri->crm & 1;
953
954 env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) +
955 + sextract64(value, 0, 32);
956 gt_recalc_timer(arm_env_get_cpu(env), timeridx);
957 }
958
959 static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
960 uint64_t value)
961 {
962 ARMCPU *cpu = arm_env_get_cpu(env);
963 int timeridx = ri->crm & 1;
964 uint32_t oldval = env->cp15.c14_timer[timeridx].ctl;
965
966 env->cp15.c14_timer[timeridx].ctl = value & 3;
967 if ((oldval ^ value) & 1) {
968 /* Enable toggled */
969 gt_recalc_timer(cpu, timeridx);
970 } else if ((oldval & value) & 2) {
971 /* IMASK toggled: don't need to recalculate,
972 * just set the interrupt line based on ISTATUS
973 */
974 qemu_set_irq(cpu->gt_timer_outputs[timeridx],
975 (oldval & 4) && (value & 2));
976 }
977 }
978
979 void arm_gt_ptimer_cb(void *opaque)
980 {
981 ARMCPU *cpu = opaque;
982
983 gt_recalc_timer(cpu, GTIMER_PHYS);
984 }
985
986 void arm_gt_vtimer_cb(void *opaque)
987 {
988 ARMCPU *cpu = opaque;
989
990 gt_recalc_timer(cpu, GTIMER_VIRT);
991 }
992
993 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
994 /* Note that CNTFRQ is purely reads-as-written for the benefit
995 * of software; writing it doesn't actually change the timer frequency.
996 * Our reset value matches the fixed frequency we implement the timer at.
997 */
998 { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0,
999 .type = ARM_CP_NO_MIGRATE,
1000 .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
1001 .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq),
1002 .resetfn = arm_cp_reset_ignore,
1003 },
1004 { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64,
1005 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0,
1006 .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
1007 .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq),
1008 .resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE,
1009 },
1010 /* overall control: mostly access permissions */
1011 { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH,
1012 .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0,
1013 .access = PL1_RW,
1014 .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl),
1015 .resetvalue = 0,
1016 },
1017 /* per-timer control */
1018 { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
1019 .type = ARM_CP_IO | ARM_CP_NO_MIGRATE, .access = PL1_RW | PL0_R,
1020 .accessfn = gt_ptimer_access,
1021 .fieldoffset = offsetoflow32(CPUARMState,
1022 cp15.c14_timer[GTIMER_PHYS].ctl),
1023 .resetfn = arm_cp_reset_ignore,
1024 .writefn = gt_ctl_write, .raw_writefn = raw_write,
1025 },
1026 { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64,
1027 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1,
1028 .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1029 .accessfn = gt_ptimer_access,
1030 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
1031 .resetvalue = 0,
1032 .writefn = gt_ctl_write, .raw_writefn = raw_write,
1033 },
1034 { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1,
1035 .type = ARM_CP_IO | ARM_CP_NO_MIGRATE, .access = PL1_RW | PL0_R,
1036 .accessfn = gt_vtimer_access,
1037 .fieldoffset = offsetoflow32(CPUARMState,
1038 cp15.c14_timer[GTIMER_VIRT].ctl),
1039 .resetfn = arm_cp_reset_ignore,
1040 .writefn = gt_ctl_write, .raw_writefn = raw_write,
1041 },
1042 { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64,
1043 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1,
1044 .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1045 .accessfn = gt_vtimer_access,
1046 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
1047 .resetvalue = 0,
1048 .writefn = gt_ctl_write, .raw_writefn = raw_write,
1049 },
1050 /* TimerValue views: a 32 bit downcounting view of the underlying state */
1051 { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
1052 .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
1053 .accessfn = gt_ptimer_access,
1054 .readfn = gt_tval_read, .writefn = gt_tval_write,
1055 },
1056 { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64,
1057 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0,
1058 .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
1059 .readfn = gt_tval_read, .writefn = gt_tval_write,
1060 },
1061 { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0,
1062 .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
1063 .accessfn = gt_vtimer_access,
1064 .readfn = gt_tval_read, .writefn = gt_tval_write,
1065 },
1066 { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64,
1067 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0,
1068 .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
1069 .readfn = gt_tval_read, .writefn = gt_tval_write,
1070 },
1071 /* The counter itself */
1072 { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0,
1073 .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO,
1074 .accessfn = gt_pct_access,
1075 .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
1076 },
1077 { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64,
1078 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1,
1079 .access = PL0_R, .type = ARM_CP_NO_MIGRATE | ARM_CP_IO,
1080 .accessfn = gt_pct_access,
1081 .readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
1082 },
1083 { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1,
1084 .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO,
1085 .accessfn = gt_vct_access,
1086 .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
1087 },
1088 { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64,
1089 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2,
1090 .access = PL0_R, .type = ARM_CP_NO_MIGRATE | ARM_CP_IO,
1091 .accessfn = gt_vct_access,
1092 .readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
1093 },
1094 /* Comparison value, indicating when the timer goes off */
1095 { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2,
1096 .access = PL1_RW | PL0_R,
1097 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_MIGRATE,
1098 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1099 .accessfn = gt_ptimer_access, .resetfn = arm_cp_reset_ignore,
1100 .writefn = gt_cval_write, .raw_writefn = raw_write,
1101 },
1102 { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64,
1103 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2,
1104 .access = PL1_RW | PL0_R,
1105 .type = ARM_CP_IO,
1106 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1107 .resetvalue = 0, .accessfn = gt_vtimer_access,
1108 .writefn = gt_cval_write, .raw_writefn = raw_write,
1109 },
1110 { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3,
1111 .access = PL1_RW | PL0_R,
1112 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_MIGRATE,
1113 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1114 .accessfn = gt_vtimer_access, .resetfn = arm_cp_reset_ignore,
1115 .writefn = gt_cval_write, .raw_writefn = raw_write,
1116 },
1117 { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64,
1118 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2,
1119 .access = PL1_RW | PL0_R,
1120 .type = ARM_CP_IO,
1121 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1122 .resetvalue = 0, .accessfn = gt_vtimer_access,
1123 .writefn = gt_cval_write, .raw_writefn = raw_write,
1124 },
1125 REGINFO_SENTINEL
1126 };
1127
1128 #else
1129 /* In user-mode none of the generic timer registers are accessible,
1130 * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs,
1131 * so instead just don't register any of them.
1132 */
1133 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1134 REGINFO_SENTINEL
1135 };
1136
1137 #endif
1138
1139 static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1140 {
1141 if (arm_feature(env, ARM_FEATURE_LPAE)) {
1142 env->cp15.c7_par = value;
1143 } else if (arm_feature(env, ARM_FEATURE_V7)) {
1144 env->cp15.c7_par = value & 0xfffff6ff;
1145 } else {
1146 env->cp15.c7_par = value & 0xfffff1ff;
1147 }
1148 }
1149
1150 #ifndef CONFIG_USER_ONLY
1151 /* get_phys_addr() isn't present for user-mode-only targets */
1152
1153 /* Return true if extended addresses are enabled, ie this is an
1154 * LPAE implementation and we are using the long-descriptor translation
1155 * table format because the TTBCR EAE bit is set.
1156 */
1157 static inline bool extended_addresses_enabled(CPUARMState *env)
1158 {
1159 return arm_feature(env, ARM_FEATURE_LPAE)
1160 && (env->cp15.c2_control & (1U << 31));
1161 }
1162
1163 static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri)
1164 {
1165 if (ri->opc2 & 4) {
1166 /* Other states are only available with TrustZone; in
1167 * a non-TZ implementation these registers don't exist
1168 * at all, which is an Uncategorized trap. This underdecoding
1169 * is safe because the reginfo is NO_MIGRATE.
1170 */
1171 return CP_ACCESS_TRAP_UNCATEGORIZED;
1172 }
1173 return CP_ACCESS_OK;
1174 }
1175
1176 static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1177 {
1178 hwaddr phys_addr;
1179 target_ulong page_size;
1180 int prot;
1181 int ret, is_user = ri->opc2 & 2;
1182 int access_type = ri->opc2 & 1;
1183
1184 ret = get_phys_addr(env, value, access_type, is_user,
1185 &phys_addr, &prot, &page_size);
1186 if (extended_addresses_enabled(env)) {
1187 /* ret is a DFSR/IFSR value for the long descriptor
1188 * translation table format, but with WnR always clear.
1189 * Convert it to a 64-bit PAR.
1190 */
1191 uint64_t par64 = (1 << 11); /* LPAE bit always set */
1192 if (ret == 0) {
1193 par64 |= phys_addr & ~0xfffULL;
1194 /* We don't set the ATTR or SH fields in the PAR. */
1195 } else {
1196 par64 |= 1; /* F */
1197 par64 |= (ret & 0x3f) << 1; /* FS */
1198 /* Note that S2WLK and FSTAGE are always zero, because we don't
1199 * implement virtualization and therefore there can't be a stage 2
1200 * fault.
1201 */
1202 }
1203 env->cp15.c7_par = par64;
1204 env->cp15.c7_par_hi = par64 >> 32;
1205 } else {
1206 /* ret is a DFSR/IFSR value for the short descriptor
1207 * translation table format (with WnR always clear).
1208 * Convert it to a 32-bit PAR.
1209 */
1210 if (ret == 0) {
1211 /* We do not set any attribute bits in the PAR */
1212 if (page_size == (1 << 24)
1213 && arm_feature(env, ARM_FEATURE_V7)) {
1214 env->cp15.c7_par = (phys_addr & 0xff000000) | 1 << 1;
1215 } else {
1216 env->cp15.c7_par = phys_addr & 0xfffff000;
1217 }
1218 } else {
1219 env->cp15.c7_par = ((ret & (1 << 10)) >> 5) |
1220 ((ret & (1 << 12)) >> 6) |
1221 ((ret & 0xf) << 1) | 1;
1222 }
1223 env->cp15.c7_par_hi = 0;
1224 }
1225 }
1226 #endif
1227
1228 static const ARMCPRegInfo vapa_cp_reginfo[] = {
1229 { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
1230 .access = PL1_RW, .resetvalue = 0,
1231 .fieldoffset = offsetof(CPUARMState, cp15.c7_par),
1232 .writefn = par_write },
1233 #ifndef CONFIG_USER_ONLY
1234 { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
1235 .access = PL1_W, .accessfn = ats_access,
1236 .writefn = ats_write, .type = ARM_CP_NO_MIGRATE },
1237 #endif
1238 REGINFO_SENTINEL
1239 };
1240
1241 /* Return basic MPU access permission bits. */
1242 static uint32_t simple_mpu_ap_bits(uint32_t val)
1243 {
1244 uint32_t ret;
1245 uint32_t mask;
1246 int i;
1247 ret = 0;
1248 mask = 3;
1249 for (i = 0; i < 16; i += 2) {
1250 ret |= (val >> i) & mask;
1251 mask <<= 2;
1252 }
1253 return ret;
1254 }
1255
1256 /* Pad basic MPU access permission bits to extended format. */
1257 static uint32_t extended_mpu_ap_bits(uint32_t val)
1258 {
1259 uint32_t ret;
1260 uint32_t mask;
1261 int i;
1262 ret = 0;
1263 mask = 3;
1264 for (i = 0; i < 16; i += 2) {
1265 ret |= (val & mask) << i;
1266 mask <<= 2;
1267 }
1268 return ret;
1269 }
1270
1271 static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
1272 uint64_t value)
1273 {
1274 env->cp15.c5_data = extended_mpu_ap_bits(value);
1275 }
1276
1277 static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
1278 {
1279 return simple_mpu_ap_bits(env->cp15.c5_data);
1280 }
1281
1282 static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
1283 uint64_t value)
1284 {
1285 env->cp15.c5_insn = extended_mpu_ap_bits(value);
1286 }
1287
1288 static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
1289 {
1290 return simple_mpu_ap_bits(env->cp15.c5_insn);
1291 }
1292
1293 static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
1294 { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
1295 .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
1296 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0,
1297 .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
1298 { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
1299 .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
1300 .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0,
1301 .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
1302 { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
1303 .access = PL1_RW,
1304 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
1305 { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
1306 .access = PL1_RW,
1307 .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, },
1308 { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
1309 .access = PL1_RW,
1310 .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
1311 { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
1312 .access = PL1_RW,
1313 .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
1314 /* Protection region base and size registers */
1315 { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0,
1316 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1317 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) },
1318 { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0,
1319 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1320 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) },
1321 { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0,
1322 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1323 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) },
1324 { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0,
1325 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1326 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) },
1327 { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0,
1328 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1329 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) },
1330 { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0,
1331 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1332 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) },
1333 { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0,
1334 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1335 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) },
1336 { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0,
1337 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1338 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) },
1339 REGINFO_SENTINEL
1340 };
1341
1342 static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
1343 uint64_t value)
1344 {
1345 int maskshift = extract32(value, 0, 3);
1346
1347 if (arm_feature(env, ARM_FEATURE_LPAE) && (value & (1 << 31))) {
1348 value &= ~((7 << 19) | (3 << 14) | (0xf << 3));
1349 } else {
1350 value &= 7;
1351 }
1352 /* Note that we always calculate c2_mask and c2_base_mask, but
1353 * they are only used for short-descriptor tables (ie if EAE is 0);
1354 * for long-descriptor tables the TTBCR fields are used differently
1355 * and the c2_mask and c2_base_mask values are meaningless.
1356 */
1357 env->cp15.c2_control = value;
1358 env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> maskshift);
1359 env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> maskshift);
1360 }
1361
1362 static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1363 uint64_t value)
1364 {
1365 ARMCPU *cpu = arm_env_get_cpu(env);
1366
1367 if (arm_feature(env, ARM_FEATURE_LPAE)) {
1368 /* With LPAE the TTBCR could result in a change of ASID
1369 * via the TTBCR.A1 bit, so do a TLB flush.
1370 */
1371 tlb_flush(CPU(cpu), 1);
1372 }
1373 vmsa_ttbcr_raw_write(env, ri, value);
1374 }
1375
1376 static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1377 {
1378 env->cp15.c2_base_mask = 0xffffc000u;
1379 env->cp15.c2_control = 0;
1380 env->cp15.c2_mask = 0;
1381 }
1382
1383 static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
1384 uint64_t value)
1385 {
1386 ARMCPU *cpu = arm_env_get_cpu(env);
1387
1388 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
1389 tlb_flush(CPU(cpu), 1);
1390 env->cp15.c2_control = value;
1391 }
1392
1393 static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1394 uint64_t value)
1395 {
1396 /* 64 bit accesses to the TTBRs can change the ASID and so we
1397 * must flush the TLB.
1398 */
1399 if (cpreg_field_is_64bit(ri)) {
1400 ARMCPU *cpu = arm_env_get_cpu(env);
1401
1402 tlb_flush(CPU(cpu), 1);
1403 }
1404 raw_write(env, ri, value);
1405 }
1406
1407 static const ARMCPRegInfo vmsa_cp_reginfo[] = {
1408 { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
1409 .access = PL1_RW,
1410 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
1411 { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
1412 .access = PL1_RW,
1413 .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, },
1414 { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
1415 .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
1416 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el1),
1417 .writefn = vmsa_ttbr_write, .resetvalue = 0 },
1418 { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH,
1419 .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
1420 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el1),
1421 .writefn = vmsa_ttbr_write, .resetvalue = 0 },
1422 { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64,
1423 .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
1424 .access = PL1_RW, .writefn = vmsa_tcr_el1_write,
1425 .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
1426 .fieldoffset = offsetof(CPUARMState, cp15.c2_control) },
1427 { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
1428 .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, .writefn = vmsa_ttbcr_write,
1429 .resetfn = arm_cp_reset_ignore, .raw_writefn = vmsa_ttbcr_raw_write,
1430 .fieldoffset = offsetoflow32(CPUARMState, cp15.c2_control) },
1431 { .name = "DFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
1432 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_data),
1433 .resetvalue = 0, },
1434 REGINFO_SENTINEL
1435 };
1436
1437 static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
1438 uint64_t value)
1439 {
1440 env->cp15.c15_ticonfig = value & 0xe7;
1441 /* The OS_TYPE bit in this register changes the reported CPUID! */
1442 env->cp15.c0_cpuid = (value & (1 << 5)) ?
1443 ARM_CPUID_TI915T : ARM_CPUID_TI925T;
1444 }
1445
1446 static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,
1447 uint64_t value)
1448 {
1449 env->cp15.c15_threadid = value & 0xffff;
1450 }
1451
1452 static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
1453 uint64_t value)
1454 {
1455 /* Wait-for-interrupt (deprecated) */
1456 cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT);
1457 }
1458
1459 static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
1460 uint64_t value)
1461 {
1462 /* On OMAP there are registers indicating the max/min index of dcache lines
1463 * containing a dirty line; cache flush operations have to reset these.
1464 */
1465 env->cp15.c15_i_max = 0x000;
1466 env->cp15.c15_i_min = 0xff0;
1467 }
1468
1469 static const ARMCPRegInfo omap_cp_reginfo[] = {
1470 { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
1471 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
1472 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
1473 { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
1474 .access = PL1_RW, .type = ARM_CP_NOP },
1475 { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
1476 .access = PL1_RW,
1477 .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
1478 .writefn = omap_ticonfig_write },
1479 { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,
1480 .access = PL1_RW,
1481 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
1482 { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
1483 .access = PL1_RW, .resetvalue = 0xff0,
1484 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },
1485 { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,
1486 .access = PL1_RW,
1487 .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
1488 .writefn = omap_threadid_write },
1489 { .name = "TI925T_STATUS", .cp = 15, .crn = 15,
1490 .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
1491 .type = ARM_CP_NO_MIGRATE,
1492 .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
1493 /* TODO: Peripheral port remap register:
1494 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
1495 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
1496 * when MMU is off.
1497 */
1498 { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
1499 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
1500 .type = ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE,
1501 .writefn = omap_cachemaint_write },
1502 { .name = "C9", .cp = 15, .crn = 9,
1503 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
1504 .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
1505 REGINFO_SENTINEL
1506 };
1507
1508 static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
1509 uint64_t value)
1510 {
1511 value &= 0x3fff;
1512 if (env->cp15.c15_cpar != value) {
1513 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
1514 tb_flush(env);
1515 env->cp15.c15_cpar = value;
1516 }
1517 }
1518
1519 static const ARMCPRegInfo xscale_cp_reginfo[] = {
1520 { .name = "XSCALE_CPAR",
1521 .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
1522 .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
1523 .writefn = xscale_cpar_write, },
1524 { .name = "XSCALE_AUXCR",
1525 .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
1526 .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
1527 .resetvalue = 0, },
1528 REGINFO_SENTINEL
1529 };
1530
1531 static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
1532 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
1533 * implementation of this implementation-defined space.
1534 * Ideally this should eventually disappear in favour of actually
1535 * implementing the correct behaviour for all cores.
1536 */
1537 { .name = "C15_IMPDEF", .cp = 15, .crn = 15,
1538 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
1539 .access = PL1_RW,
1540 .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE | ARM_CP_OVERRIDE,
1541 .resetvalue = 0 },
1542 REGINFO_SENTINEL
1543 };
1544
1545 static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
1546 /* Cache status: RAZ because we have no cache so it's always clean */
1547 { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
1548 .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1549 .resetvalue = 0 },
1550 REGINFO_SENTINEL
1551 };
1552
1553 static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
1554 /* We never have a a block transfer operation in progress */
1555 { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
1556 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1557 .resetvalue = 0 },
1558 /* The cache ops themselves: these all NOP for QEMU */
1559 { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
1560 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1561 { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
1562 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1563 { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
1564 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1565 { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
1566 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1567 { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
1568 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1569 { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
1570 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1571 REGINFO_SENTINEL
1572 };
1573
1574 static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
1575 /* The cache test-and-clean instructions always return (1 << 30)
1576 * to indicate that there are no dirty cache lines.
1577 */
1578 { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
1579 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1580 .resetvalue = (1 << 30) },
1581 { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
1582 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1583 .resetvalue = (1 << 30) },
1584 REGINFO_SENTINEL
1585 };
1586
1587 static const ARMCPRegInfo strongarm_cp_reginfo[] = {
1588 /* Ignore ReadBuffer accesses */
1589 { .name = "C9_READBUFFER", .cp = 15, .crn = 9,
1590 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
1591 .access = PL1_RW, .resetvalue = 0,
1592 .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE },
1593 REGINFO_SENTINEL
1594 };
1595
1596 static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1597 {
1598 CPUState *cs = CPU(arm_env_get_cpu(env));
1599 uint32_t mpidr = cs->cpu_index;
1600 /* We don't support setting cluster ID ([8..11]) (known as Aff1
1601 * in later ARM ARM versions), or any of the higher affinity level fields,
1602 * so these bits always RAZ.
1603 */
1604 if (arm_feature(env, ARM_FEATURE_V7MP)) {
1605 mpidr |= (1U << 31);
1606 /* Cores which are uniprocessor (non-coherent)
1607 * but still implement the MP extensions set
1608 * bit 30. (For instance, A9UP.) However we do
1609 * not currently model any of those cores.
1610 */
1611 }
1612 return mpidr;
1613 }
1614
1615 static const ARMCPRegInfo mpidr_cp_reginfo[] = {
1616 { .name = "MPIDR", .state = ARM_CP_STATE_BOTH,
1617 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
1618 .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_MIGRATE },
1619 REGINFO_SENTINEL
1620 };
1621
1622 static uint64_t par64_read(CPUARMState *env, const ARMCPRegInfo *ri)
1623 {
1624 return ((uint64_t)env->cp15.c7_par_hi << 32) | env->cp15.c7_par;
1625 }
1626
1627 static void par64_write(CPUARMState *env, const ARMCPRegInfo *ri,
1628 uint64_t value)
1629 {
1630 env->cp15.c7_par_hi = value >> 32;
1631 env->cp15.c7_par = value;
1632 }
1633
1634 static void par64_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1635 {
1636 env->cp15.c7_par_hi = 0;
1637 env->cp15.c7_par = 0;
1638 }
1639
1640 static const ARMCPRegInfo lpae_cp_reginfo[] = {
1641 /* NOP AMAIR0/1: the override is because these clash with the rather
1642 * broadly specified TLB_LOCKDOWN entry in the generic cp_reginfo.
1643 */
1644 { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH,
1645 .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
1646 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
1647 .resetvalue = 0 },
1648 /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
1649 { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
1650 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
1651 .resetvalue = 0 },
1652 /* 64 bit access versions of the (dummy) debug registers */
1653 { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
1654 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
1655 { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
1656 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
1657 { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0,
1658 .access = PL1_RW, .type = ARM_CP_64BIT,
1659 .readfn = par64_read, .writefn = par64_write, .resetfn = par64_reset },
1660 { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0,
1661 .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE,
1662 .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el1),
1663 .writefn = vmsa_ttbr_write, .resetfn = arm_cp_reset_ignore },
1664 { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
1665 .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE,
1666 .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el1),
1667 .writefn = vmsa_ttbr_write, .resetfn = arm_cp_reset_ignore },
1668 REGINFO_SENTINEL
1669 };
1670
1671 static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1672 {
1673 return vfp_get_fpcr(env);
1674 }
1675
1676 static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1677 uint64_t value)
1678 {
1679 vfp_set_fpcr(env, value);
1680 }
1681
1682 static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1683 {
1684 return vfp_get_fpsr(env);
1685 }
1686
1687 static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1688 uint64_t value)
1689 {
1690 vfp_set_fpsr(env, value);
1691 }
1692
1693 static CPAccessResult aa64_cacheop_access(CPUARMState *env,
1694 const ARMCPRegInfo *ri)
1695 {
1696 /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless
1697 * SCTLR_EL1.UCI is set.
1698 */
1699 if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UCI)) {
1700 return CP_ACCESS_TRAP;
1701 }
1702 return CP_ACCESS_OK;
1703 }
1704
1705 static void tlbi_aa64_va_write(CPUARMState *env, const ARMCPRegInfo *ri,
1706 uint64_t value)
1707 {
1708 /* Invalidate by VA (AArch64 version) */
1709 ARMCPU *cpu = arm_env_get_cpu(env);
1710 uint64_t pageaddr = value << 12;
1711 tlb_flush_page(CPU(cpu), pageaddr);
1712 }
1713
1714 static void tlbi_aa64_vaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
1715 uint64_t value)
1716 {
1717 /* Invalidate by VA, all ASIDs (AArch64 version) */
1718 ARMCPU *cpu = arm_env_get_cpu(env);
1719 uint64_t pageaddr = value << 12;
1720 tlb_flush_page(CPU(cpu), pageaddr);
1721 }
1722
1723 static void tlbi_aa64_asid_write(CPUARMState *env, const ARMCPRegInfo *ri,
1724 uint64_t value)
1725 {
1726 /* Invalidate by ASID (AArch64 version) */
1727 ARMCPU *cpu = arm_env_get_cpu(env);
1728 int asid = extract64(value, 48, 16);
1729 tlb_flush(CPU(cpu), asid == 0);
1730 }
1731
1732 static const ARMCPRegInfo v8_cp_reginfo[] = {
1733 /* Minimal set of EL0-visible registers. This will need to be expanded
1734 * significantly for system emulation of AArch64 CPUs.
1735 */
1736 { .name = "NZCV", .state = ARM_CP_STATE_AA64,
1737 .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2,
1738 .access = PL0_RW, .type = ARM_CP_NZCV },
1739 { .name = "FPCR", .state = ARM_CP_STATE_AA64,
1740 .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4,
1741 .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write },
1742 { .name = "FPSR", .state = ARM_CP_STATE_AA64,
1743 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4,
1744 .access = PL0_RW, .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write },
1745 /* Prohibit use of DC ZVA. OPTME: implement DC ZVA and allow its use.
1746 * For system mode the DZP bit here will need to be computed, not constant.
1747 */
1748 { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64,
1749 .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0,
1750 .access = PL0_R, .type = ARM_CP_CONST,
1751 .resetvalue = 0x10 },
1752 { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64,
1753 .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2,
1754 .access = PL1_R, .type = ARM_CP_CURRENTEL },
1755 /* Cache ops: all NOPs since we don't emulate caches */
1756 { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64,
1757 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
1758 .access = PL1_W, .type = ARM_CP_NOP },
1759 { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64,
1760 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
1761 .access = PL1_W, .type = ARM_CP_NOP },
1762 { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64,
1763 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1,
1764 .access = PL0_W, .type = ARM_CP_NOP,
1765 .accessfn = aa64_cacheop_access },
1766 { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64,
1767 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
1768 .access = PL1_W, .type = ARM_CP_NOP },
1769 { .name = "DC_ISW", .state = ARM_CP_STATE_AA64,
1770 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
1771 .access = PL1_W, .type = ARM_CP_NOP },
1772 { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64,
1773 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1,
1774 .access = PL0_W, .type = ARM_CP_NOP,
1775 .accessfn = aa64_cacheop_access },
1776 { .name = "DC_CSW", .state = ARM_CP_STATE_AA64,
1777 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
1778 .access = PL1_W, .type = ARM_CP_NOP },
1779 { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64,
1780 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1,
1781 .access = PL0_W, .type = ARM_CP_NOP,
1782 .accessfn = aa64_cacheop_access },
1783 { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64,
1784 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1,
1785 .access = PL0_W, .type = ARM_CP_NOP,
1786 .accessfn = aa64_cacheop_access },
1787 { .name = "DC_CISW", .state = ARM_CP_STATE_AA64,
1788 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
1789 .access = PL1_W, .type = ARM_CP_NOP },
1790 /* TLBI operations */
1791 { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
1792 .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 0,
1793 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1794 .writefn = tlbiall_write },
1795 { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
1796 .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 1,
1797 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1798 .writefn = tlbi_aa64_va_write },
1799 { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
1800 .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 2,
1801 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1802 .writefn = tlbi_aa64_asid_write },
1803 { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
1804 .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 3,
1805 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1806 .writefn = tlbi_aa64_vaa_write },
1807 { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
1808 .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 5,
1809 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1810 .writefn = tlbi_aa64_va_write },
1811 { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
1812 .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 7,
1813 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1814 .writefn = tlbi_aa64_vaa_write },
1815 { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
1816 .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 0,
1817 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1818 .writefn = tlbiall_write },
1819 { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64,
1820 .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 1,
1821 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1822 .writefn = tlbi_aa64_va_write },
1823 { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64,
1824 .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 2,
1825 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1826 .writefn = tlbi_aa64_asid_write },
1827 { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64,
1828 .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 3,
1829 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1830 .writefn = tlbi_aa64_vaa_write },
1831 { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64,
1832 .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 5,
1833 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1834 .writefn = tlbi_aa64_va_write },
1835 { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64,
1836 .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 7,
1837 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1838 .writefn = tlbi_aa64_vaa_write },
1839 /* Dummy implementation of monitor debug system control register:
1840 * we don't support debug.
1841 */
1842 { .name = "MDSCR_EL1", .state = ARM_CP_STATE_AA64,
1843 .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
1844 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1845 /* We define a dummy WI OSLAR_EL1, because Linux writes to it. */
1846 { .name = "OSLAR_EL1", .state = ARM_CP_STATE_AA64,
1847 .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
1848 .access = PL1_W, .type = ARM_CP_NOP },
1849 REGINFO_SENTINEL
1850 };
1851
1852 static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1853 uint64_t value)
1854 {
1855 ARMCPU *cpu = arm_env_get_cpu(env);
1856
1857 env->cp15.c1_sys = value;
1858 /* ??? Lots of these bits are not implemented. */
1859 /* This may enable/disable the MMU, so do a TLB flush. */
1860 tlb_flush(CPU(cpu), 1);
1861 }
1862
1863 static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri)
1864 {
1865 /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64,
1866 * but the AArch32 CTR has its own reginfo struct)
1867 */
1868 if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UCT)) {
1869 return CP_ACCESS_TRAP;
1870 }
1871 return CP_ACCESS_OK;
1872 }
1873
1874 static void define_aarch64_debug_regs(ARMCPU *cpu)
1875 {
1876 /* Define breakpoint and watchpoint registers. These do nothing
1877 * but read as written, for now.
1878 */
1879 int i;
1880
1881 for (i = 0; i < 16; i++) {
1882 ARMCPRegInfo dbgregs[] = {
1883 { .name = "DBGBVR", .state = ARM_CP_STATE_AA64,
1884 .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4,
1885 .access = PL1_RW,
1886 .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]) },
1887 { .name = "DBGBCR", .state = ARM_CP_STATE_AA64,
1888 .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5,
1889 .access = PL1_RW,
1890 .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]) },
1891 { .name = "DBGWVR", .state = ARM_CP_STATE_AA64,
1892 .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6,
1893 .access = PL1_RW,
1894 .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]) },
1895 { .name = "DBGWCR", .state = ARM_CP_STATE_AA64,
1896 .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7,
1897 .access = PL1_RW,
1898 .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]) },
1899 REGINFO_SENTINEL
1900 };
1901 define_arm_cp_regs(cpu, dbgregs);
1902 }
1903 }
1904
1905 void register_cp_regs_for_features(ARMCPU *cpu)
1906 {
1907 /* Register all the coprocessor registers based on feature bits */
1908 CPUARMState *env = &cpu->env;
1909 if (arm_feature(env, ARM_FEATURE_M)) {
1910 /* M profile has no coprocessor registers */
1911 return;
1912 }
1913
1914 define_arm_cp_regs(cpu, cp_reginfo);
1915 if (arm_feature(env, ARM_FEATURE_V6)) {
1916 /* The ID registers all have impdef reset values */
1917 ARMCPRegInfo v6_idregs[] = {
1918 { .name = "ID_PFR0", .cp = 15, .crn = 0, .crm = 1,
1919 .opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST,
1920 .resetvalue = cpu->id_pfr0 },
1921 { .name = "ID_PFR1", .cp = 15, .crn = 0, .crm = 1,
1922 .opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST,
1923 .resetvalue = cpu->id_pfr1 },
1924 { .name = "ID_DFR0", .cp = 15, .crn = 0, .crm = 1,
1925 .opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST,
1926 .resetvalue = cpu->id_dfr0 },
1927 { .name = "ID_AFR0", .cp = 15, .crn = 0, .crm = 1,
1928 .opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST,
1929 .resetvalue = cpu->id_afr0 },
1930 { .name = "ID_MMFR0", .cp = 15, .crn = 0, .crm = 1,
1931 .opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST,
1932 .resetvalue = cpu->id_mmfr0 },
1933 { .name = "ID_MMFR1", .cp = 15, .crn = 0, .crm = 1,
1934 .opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST,
1935 .resetvalue = cpu->id_mmfr1 },
1936 { .name = "ID_MMFR2", .cp = 15, .crn = 0, .crm = 1,
1937 .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
1938 .resetvalue = cpu->id_mmfr2 },
1939 { .name = "ID_MMFR3", .cp = 15, .crn = 0, .crm = 1,
1940 .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
1941 .resetvalue = cpu->id_mmfr3 },
1942 { .name = "ID_ISAR0", .cp = 15, .crn = 0, .crm = 2,
1943 .opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST,
1944 .resetvalue = cpu->id_isar0 },
1945 { .name = "ID_ISAR1", .cp = 15, .crn = 0, .crm = 2,
1946 .opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST,
1947 .resetvalue = cpu->id_isar1 },
1948 { .name = "ID_ISAR2", .cp = 15, .crn = 0, .crm = 2,
1949 .opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST,
1950 .resetvalue = cpu->id_isar2 },
1951 { .name = "ID_ISAR3", .cp = 15, .crn = 0, .crm = 2,
1952 .opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST,
1953 .resetvalue = cpu->id_isar3 },
1954 { .name = "ID_ISAR4", .cp = 15, .crn = 0, .crm = 2,
1955 .opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST,
1956 .resetvalue = cpu->id_isar4 },
1957 { .name = "ID_ISAR5", .cp = 15, .crn = 0, .crm = 2,
1958 .opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST,
1959 .resetvalue = cpu->id_isar5 },
1960 /* 6..7 are as yet unallocated and must RAZ */
1961 { .name = "ID_ISAR6", .cp = 15, .crn = 0, .crm = 2,
1962 .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
1963 .resetvalue = 0 },
1964 { .name = "ID_ISAR7", .cp = 15, .crn = 0, .crm = 2,
1965 .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
1966 .resetvalue = 0 },
1967 REGINFO_SENTINEL
1968 };
1969 define_arm_cp_regs(cpu, v6_idregs);
1970 define_arm_cp_regs(cpu, v6_cp_reginfo);
1971 } else {
1972 define_arm_cp_regs(cpu, not_v6_cp_reginfo);
1973 }
1974 if (arm_feature(env, ARM_FEATURE_V6K)) {
1975 define_arm_cp_regs(cpu, v6k_cp_reginfo);
1976 }
1977 if (arm_feature(env, ARM_FEATURE_V7)) {
1978 /* v7 performance monitor control register: same implementor
1979 * field as main ID register, and we implement only the cycle
1980 * count register.
1981 */
1982 #ifndef CONFIG_USER_ONLY
1983 ARMCPRegInfo pmcr = {
1984 .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
1985 .access = PL0_RW, .resetvalue = cpu->midr & 0xff000000,
1986 .type = ARM_CP_IO,
1987 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
1988 .accessfn = pmreg_access, .writefn = pmcr_write,
1989 .raw_writefn = raw_write,
1990 };
1991 define_one_arm_cp_reg(cpu, &pmcr);
1992 #endif
1993 ARMCPRegInfo clidr = {
1994 .name = "CLIDR", .state = ARM_CP_STATE_BOTH,
1995 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
1996 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr
1997 };
1998 define_one_arm_cp_reg(cpu, &clidr);
1999 define_arm_cp_regs(cpu, v7_cp_reginfo);
2000 } else {
2001 define_arm_cp_regs(cpu, not_v7_cp_reginfo);
2002 }
2003 if (arm_feature(env, ARM_FEATURE_V8)) {
2004 /* AArch64 ID registers, which all have impdef reset values */
2005 ARMCPRegInfo v8_idregs[] = {
2006 { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64,
2007 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0,
2008 .access = PL1_R, .type = ARM_CP_CONST,
2009 .resetvalue = cpu->id_aa64pfr0 },
2010 { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64,
2011 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1,
2012 .access = PL1_R, .type = ARM_CP_CONST,
2013 .resetvalue = cpu->id_aa64pfr1},
2014 { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
2015 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
2016 .access = PL1_R, .type = ARM_CP_CONST,
2017 .resetvalue = cpu->id_aa64dfr0 },
2018 { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
2019 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
2020 .access = PL1_R, .type = ARM_CP_CONST,
2021 .resetvalue = cpu->id_aa64dfr1 },
2022 { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64,
2023 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4,
2024 .access = PL1_R, .type = ARM_CP_CONST,
2025 .resetvalue = cpu->id_aa64afr0 },
2026 { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64,
2027 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5,
2028 .access = PL1_R, .type = ARM_CP_CONST,
2029 .resetvalue = cpu->id_aa64afr1 },
2030 { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64,
2031 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0,
2032 .access = PL1_R, .type = ARM_CP_CONST,
2033 .resetvalue = cpu->id_aa64isar0 },
2034 { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64,
2035 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1,
2036 .access = PL1_R, .type = ARM_CP_CONST,
2037 .resetvalue = cpu->id_aa64isar1 },
2038 { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64,
2039 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
2040 .access = PL1_R, .type = ARM_CP_CONST,
2041 .resetvalue = cpu->id_aa64mmfr0 },
2042 { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64,
2043 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1,
2044 .access = PL1_R, .type = ARM_CP_CONST,
2045 .resetvalue = cpu->id_aa64mmfr1 },
2046 REGINFO_SENTINEL
2047 };
2048 define_arm_cp_regs(cpu, v8_idregs);
2049 define_arm_cp_regs(cpu, v8_cp_reginfo);
2050 define_aarch64_debug_regs(cpu);
2051 }
2052 if (arm_feature(env, ARM_FEATURE_MPU)) {
2053 /* These are the MPU registers prior to PMSAv6. Any new
2054 * PMSA core later than the ARM946 will require that we
2055 * implement the PMSAv6 or PMSAv7 registers, which are
2056 * completely different.
2057 */
2058 assert(!arm_feature(env, ARM_FEATURE_V6));
2059 define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
2060 } else {
2061 define_arm_cp_regs(cpu, vmsa_cp_reginfo);
2062 }
2063 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
2064 define_arm_cp_regs(cpu, t2ee_cp_reginfo);
2065 }
2066 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
2067 define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
2068 }
2069 if (arm_feature(env, ARM_FEATURE_VAPA)) {
2070 define_arm_cp_regs(cpu, vapa_cp_reginfo);
2071 }
2072 if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) {
2073 define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo);
2074 }
2075 if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) {
2076 define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo);
2077 }
2078 if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) {
2079 define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo);
2080 }
2081 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
2082 define_arm_cp_regs(cpu, omap_cp_reginfo);
2083 }
2084 if (arm_feature(env, ARM_FEATURE_STRONGARM)) {
2085 define_arm_cp_regs(cpu, strongarm_cp_reginfo);
2086 }
2087 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
2088 define_arm_cp_regs(cpu, xscale_cp_reginfo);
2089 }
2090 if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
2091 define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
2092 }
2093 if (arm_feature(env, ARM_FEATURE_LPAE)) {
2094 define_arm_cp_regs(cpu, lpae_cp_reginfo);
2095 }
2096 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
2097 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
2098 * be read-only (ie write causes UNDEF exception).
2099 */
2100 {
2101 ARMCPRegInfo id_cp_reginfo[] = {
2102 /* Note that the MIDR isn't a simple constant register because
2103 * of the TI925 behaviour where writes to another register can
2104 * cause the MIDR value to change.
2105 *
2106 * Unimplemented registers in the c15 0 0 0 space default to
2107 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
2108 * and friends override accordingly.
2109 */
2110 { .name = "MIDR",
2111 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY,
2112 .access = PL1_R, .resetvalue = cpu->midr,
2113 .writefn = arm_cp_write_ignore, .raw_writefn = raw_write,
2114 .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
2115 .type = ARM_CP_OVERRIDE },
2116 { .name = "MIDR_EL1", .state = ARM_CP_STATE_AA64,
2117 .opc0 = 3, .opc1 = 0, .opc2 = 0, .crn = 0, .crm = 0,
2118 .access = PL1_R, .resetvalue = cpu->midr, .type = ARM_CP_CONST },
2119 { .name = "CTR",
2120 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
2121 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
2122 { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64,
2123 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0,
2124 .access = PL0_R, .accessfn = ctr_el0_access,
2125 .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
2126 { .name = "TCMTR",
2127 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2,
2128 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2129 { .name = "TLBTR",
2130 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
2131 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2132 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
2133 { .name = "DUMMY",
2134 .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY,
2135 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2136 { .name = "DUMMY",
2137 .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY,
2138 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2139 { .name = "DUMMY",
2140 .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY,
2141 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2142 { .name = "DUMMY",
2143 .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY,
2144 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2145 { .name = "DUMMY",
2146 .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
2147 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2148 REGINFO_SENTINEL
2149 };
2150 ARMCPRegInfo crn0_wi_reginfo = {
2151 .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
2152 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
2153 .type = ARM_CP_NOP | ARM_CP_OVERRIDE
2154 };
2155 if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
2156 arm_feature(env, ARM_FEATURE_STRONGARM)) {
2157 ARMCPRegInfo *r;
2158 /* Register the blanket "writes ignored" value first to cover the
2159 * whole space. Then update the specific ID registers to allow write
2160 * access, so that they ignore writes rather than causing them to
2161 * UNDEF.
2162 */
2163 define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
2164 for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
2165 r->access = PL1_RW;
2166 }
2167 }
2168 define_arm_cp_regs(cpu, id_cp_reginfo);
2169 }
2170
2171 if (arm_feature(env, ARM_FEATURE_MPIDR)) {
2172 define_arm_cp_regs(cpu, mpidr_cp_reginfo);
2173 }
2174
2175 if (arm_feature(env, ARM_FEATURE_AUXCR)) {
2176 ARMCPRegInfo auxcr = {
2177 .name = "AUXCR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1,
2178 .access = PL1_RW, .type = ARM_CP_CONST,
2179 .resetvalue = cpu->reset_auxcr
2180 };
2181 define_one_arm_cp_reg(cpu, &auxcr);
2182 }
2183
2184 if (arm_feature(env, ARM_FEATURE_CBAR)) {
2185 ARMCPRegInfo cbar = {
2186 .name = "CBAR", .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
2187 .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
2188 .fieldoffset = offsetof(CPUARMState, cp15.c15_config_base_address)
2189 };
2190 define_one_arm_cp_reg(cpu, &cbar);
2191 }
2192
2193 /* Generic registers whose values depend on the implementation */
2194 {
2195 ARMCPRegInfo sctlr = {
2196 .name = "SCTLR", .state = ARM_CP_STATE_BOTH,
2197 .opc0 = 3, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
2198 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_sys),
2199 .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
2200 .raw_writefn = raw_write,
2201 };
2202 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
2203 /* Normally we would always end the TB on an SCTLR write, but Linux
2204 * arch/arm/mach-pxa/sleep.S expects two instructions following
2205 * an MMU enable to execute from cache. Imitate this behaviour.
2206 */
2207 sctlr.type |= ARM_CP_SUPPRESS_TB_END;
2208 }
2209 define_one_arm_cp_reg(cpu, &sctlr);
2210 }
2211 }
2212
2213 ARMCPU *cpu_arm_init(const char *cpu_model)
2214 {
2215 return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model));
2216 }
2217
2218 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
2219 {
2220 CPUState *cs = CPU(cpu);
2221 CPUARMState *env = &cpu->env;
2222
2223 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
2224 gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
2225 aarch64_fpu_gdb_set_reg,
2226 34, "aarch64-fpu.xml", 0);
2227 } else if (arm_feature(env, ARM_FEATURE_NEON)) {
2228 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
2229 51, "arm-neon.xml", 0);
2230 } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
2231 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
2232 35, "arm-vfp3.xml", 0);
2233 } else if (arm_feature(env, ARM_FEATURE_VFP)) {
2234 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
2235 19, "arm-vfp.xml", 0);
2236 }
2237 }
2238
2239 /* Sort alphabetically by type name, except for "any". */
2240 static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
2241 {
2242 ObjectClass *class_a = (ObjectClass *)a;
2243 ObjectClass *class_b = (ObjectClass *)b;
2244 const char *name_a, *name_b;
2245
2246 name_a = object_class_get_name(class_a);
2247 name_b = object_class_get_name(class_b);
2248 if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) {
2249 return 1;
2250 } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) {
2251 return -1;
2252 } else {
2253 return strcmp(name_a, name_b);
2254 }
2255 }
2256
2257 static void arm_cpu_list_entry(gpointer data, gpointer user_data)
2258 {
2259 ObjectClass *oc = data;
2260 CPUListState *s = user_data;
2261 const char *typename;
2262 char *name;
2263
2264 typename = object_class_get_name(oc);
2265 name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU));
2266 (*s->cpu_fprintf)(s->file, " %s\n",
2267 name);
2268 g_free(name);
2269 }
2270
2271 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
2272 {
2273 CPUListState s = {
2274 .file = f,
2275 .cpu_fprintf = cpu_fprintf,
2276 };
2277 GSList *list;
2278
2279 list = object_class_get_list(TYPE_ARM_CPU, false);
2280 list = g_slist_sort(list, arm_cpu_list_compare);
2281 (*cpu_fprintf)(f, "Available CPUs:\n");
2282 g_slist_foreach(list, arm_cpu_list_entry, &s);
2283 g_slist_free(list);
2284 #ifdef CONFIG_KVM
2285 /* The 'host' CPU type is dynamically registered only if KVM is
2286 * enabled, so we have to special-case it here:
2287 */
2288 (*cpu_fprintf)(f, " host (only available in KVM mode)\n");
2289 #endif
2290 }
2291
2292 static void arm_cpu_add_definition(gpointer data, gpointer user_data)
2293 {
2294 ObjectClass *oc = data;
2295 CpuDefinitionInfoList **cpu_list = user_data;
2296 CpuDefinitionInfoList *entry;
2297 CpuDefinitionInfo *info;
2298 const char *typename;
2299
2300 typename = object_class_get_name(oc);
2301 info = g_malloc0(sizeof(*info));
2302 info->name = g_strndup(typename,
2303 strlen(typename) - strlen("-" TYPE_ARM_CPU));
2304
2305 entry = g_malloc0(sizeof(*entry));
2306 entry->value = info;
2307 entry->next = *cpu_list;
2308 *cpu_list = entry;
2309 }
2310
2311 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
2312 {
2313 CpuDefinitionInfoList *cpu_list = NULL;
2314 GSList *list;
2315
2316 list = object_class_get_list(TYPE_ARM_CPU, false);
2317 g_slist_foreach(list, arm_cpu_add_definition, &cpu_list);
2318 g_slist_free(list);
2319
2320 return cpu_list;
2321 }
2322
2323 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
2324 void *opaque, int state,
2325 int crm, int opc1, int opc2)
2326 {
2327 /* Private utility function for define_one_arm_cp_reg_with_opaque():
2328 * add a single reginfo struct to the hash table.
2329 */
2330 uint32_t *key = g_new(uint32_t, 1);
2331 ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
2332 int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
2333 if (r->state == ARM_CP_STATE_BOTH && state == ARM_CP_STATE_AA32) {
2334 /* The AArch32 view of a shared register sees the lower 32 bits
2335 * of a 64 bit backing field. It is not migratable as the AArch64
2336 * view handles that. AArch64 also handles reset.
2337 * We assume it is a cp15 register.
2338 */
2339 r2->cp = 15;
2340 r2->type |= ARM_CP_NO_MIGRATE;
2341 r2->resetfn = arm_cp_reset_ignore;
2342 #ifdef HOST_WORDS_BIGENDIAN
2343 if (r2->fieldoffset) {
2344 r2->fieldoffset += sizeof(uint32_t);
2345 }
2346 #endif
2347 }
2348 if (state == ARM_CP_STATE_AA64) {
2349 /* To allow abbreviation of ARMCPRegInfo
2350 * definitions, we treat cp == 0 as equivalent to
2351 * the value for "standard guest-visible sysreg".
2352 */
2353 if (r->cp == 0) {
2354 r2->cp = CP_REG_ARM64_SYSREG_CP;
2355 }
2356 *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
2357 r2->opc0, opc1, opc2);
2358 } else {
2359 *key = ENCODE_CP_REG(r2->cp, is64, r2->crn, crm, opc1, opc2);
2360 }
2361 if (opaque) {
2362 r2->opaque = opaque;
2363 }
2364 /* reginfo passed to helpers is correct for the actual access,
2365 * and is never ARM_CP_STATE_BOTH:
2366 */
2367 r2->state = state;
2368 /* Make sure reginfo passed to helpers for wildcarded regs
2369 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
2370 */
2371 r2->crm = crm;
2372 r2->opc1 = opc1;
2373 r2->opc2 = opc2;
2374 /* By convention, for wildcarded registers only the first
2375 * entry is used for migration; the others are marked as
2376 * NO_MIGRATE so we don't try to transfer the register
2377 * multiple times. Special registers (ie NOP/WFI) are
2378 * never migratable.
2379 */
2380 if ((r->type & ARM_CP_SPECIAL) ||
2381 ((r->crm == CP_ANY) && crm != 0) ||
2382 ((r->opc1 == CP_ANY) && opc1 != 0) ||
2383 ((r->opc2 == CP_ANY) && opc2 != 0)) {
2384 r2->type |= ARM_CP_NO_MIGRATE;
2385 }
2386
2387 /* Overriding of an existing definition must be explicitly
2388 * requested.
2389 */
2390 if (!(r->type & ARM_CP_OVERRIDE)) {
2391 ARMCPRegInfo *oldreg;
2392 oldreg = g_hash_table_lookup(cpu->cp_regs, key);
2393 if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
2394 fprintf(stderr, "Register redefined: cp=%d %d bit "
2395 "crn=%d crm=%d opc1=%d opc2=%d, "
2396 "was %s, now %s\n", r2->cp, 32 + 32 * is64,
2397 r2->crn, r2->crm, r2->opc1, r2->opc2,
2398 oldreg->name, r2->name);
2399 g_assert_not_reached();
2400 }
2401 }
2402 g_hash_table_insert(cpu->cp_regs, key, r2);
2403 }
2404
2405
2406 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
2407 const ARMCPRegInfo *r, void *opaque)
2408 {
2409 /* Define implementations of coprocessor registers.
2410 * We store these in a hashtable because typically
2411 * there are less than 150 registers in a space which
2412 * is 16*16*16*8*8 = 262144 in size.
2413 * Wildcarding is supported for the crm, opc1 and opc2 fields.
2414 * If a register is defined twice then the second definition is
2415 * used, so this can be used to define some generic registers and
2416 * then override them with implementation specific variations.
2417 * At least one of the original and the second definition should
2418 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
2419 * against accidental use.
2420 *
2421 * The state field defines whether the register is to be
2422 * visible in the AArch32 or AArch64 execution state. If the
2423 * state is set to ARM_CP_STATE_BOTH then we synthesise a
2424 * reginfo structure for the AArch32 view, which sees the lower
2425 * 32 bits of the 64 bit register.
2426 *
2427 * Only registers visible in AArch64 may set r->opc0; opc0 cannot
2428 * be wildcarded. AArch64 registers are always considered to be 64
2429 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
2430 * the register, if any.
2431 */
2432 int crm, opc1, opc2, state;
2433 int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
2434 int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
2435 int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
2436 int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
2437 int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
2438 int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
2439 /* 64 bit registers have only CRm and Opc1 fields */
2440 assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
2441 /* op0 only exists in the AArch64 encodings */
2442 assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0));
2443 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
2444 assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT));
2445 /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
2446 * encodes a minimum access level for the register. We roll this
2447 * runtime check into our general permission check code, so check
2448 * here that the reginfo's specified permissions are strict enough
2449 * to encompass the generic architectural permission check.
2450 */
2451 if (r->state != ARM_CP_STATE_AA32) {
2452 int mask = 0;
2453 switch (r->opc1) {
2454 case 0: case 1: case 2:
2455 /* min_EL EL1 */
2456 mask = PL1_RW;
2457 break;
2458 case 3:
2459 /* min_EL EL0 */
2460 mask = PL0_RW;
2461 break;
2462 case 4:
2463 /* min_EL EL2 */
2464 mask = PL2_RW;
2465 break;
2466 case 5:
2467 /* unallocated encoding, so not possible */
2468 assert(false);
2469 break;
2470 case 6:
2471 /* min_EL EL3 */
2472 mask = PL3_RW;
2473 break;
2474 case 7:
2475 /* min_EL EL1, secure mode only (we don't check the latter) */
2476 mask = PL1_RW;
2477 break;
2478 default:
2479 /* broken reginfo with out-of-range opc1 */
2480 assert(false);
2481 break;
2482 }
2483 /* assert our permissions are not too lax (stricter is fine) */
2484 assert((r->access & ~mask) == 0);
2485 }
2486
2487 /* Check that the register definition has enough info to handle
2488 * reads and writes if they are permitted.
2489 */
2490 if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
2491 if (r->access & PL3_R) {
2492 assert(r->fieldoffset || r->readfn);
2493 }
2494 if (r->access & PL3_W) {
2495 assert(r->fieldoffset || r->writefn);
2496 }
2497 }
2498 /* Bad type field probably means missing sentinel at end of reg list */
2499 assert(cptype_valid(r->type));
2500 for (crm = crmmin; crm <= crmmax; crm++) {
2501 for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
2502 for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
2503 for (state = ARM_CP_STATE_AA32;
2504 state <= ARM_CP_STATE_AA64; state++) {
2505 if (r->state != state && r->state != ARM_CP_STATE_BOTH) {
2506 continue;
2507 }
2508 add_cpreg_to_hashtable(cpu, r, opaque, state,
2509 crm, opc1, opc2);
2510 }
2511 }
2512 }
2513 }
2514 }
2515
2516 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
2517 const ARMCPRegInfo *regs, void *opaque)
2518 {
2519 /* Define a whole list of registers */
2520 const ARMCPRegInfo *r;
2521 for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
2522 define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
2523 }
2524 }
2525
2526 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp)
2527 {
2528 return g_hash_table_lookup(cpregs, &encoded_cp);
2529 }
2530
2531 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
2532 uint64_t value)
2533 {
2534 /* Helper coprocessor write function for write-ignore registers */
2535 }
2536
2537 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri)
2538 {
2539 /* Helper coprocessor write function for read-as-zero registers */
2540 return 0;
2541 }
2542
2543 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque)
2544 {
2545 /* Helper coprocessor reset function for do-nothing-on-reset registers */
2546 }
2547
2548 static int bad_mode_switch(CPUARMState *env, int mode)
2549 {
2550 /* Return true if it is not valid for us to switch to
2551 * this CPU mode (ie all the UNPREDICTABLE cases in
2552 * the ARM ARM CPSRWriteByInstr pseudocode).
2553 */
2554 switch (mode) {
2555 case ARM_CPU_MODE_USR:
2556 case ARM_CPU_MODE_SYS:
2557 case ARM_CPU_MODE_SVC:
2558 case ARM_CPU_MODE_ABT:
2559 case ARM_CPU_MODE_UND:
2560 case ARM_CPU_MODE_IRQ:
2561 case ARM_CPU_MODE_FIQ:
2562 return 0;
2563 default:
2564 return 1;
2565 }
2566 }
2567
2568 uint32_t cpsr_read(CPUARMState *env)
2569 {
2570 int ZF;
2571 ZF = (env->ZF == 0);
2572 return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
2573 (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
2574 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
2575 | ((env->condexec_bits & 0xfc) << 8)
2576 | (env->GE << 16) | (env->daif & CPSR_AIF);
2577 }
2578
2579 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
2580 {
2581 if (mask & CPSR_NZCV) {
2582 env->ZF = (~val) & CPSR_Z;
2583 env->NF = val;
2584 env->CF = (val >> 29) & 1;
2585 env->VF = (val << 3) & 0x80000000;
2586 }
2587 if (mask & CPSR_Q)
2588 env->QF = ((val & CPSR_Q) != 0);
2589 if (mask & CPSR_T)
2590 env->thumb = ((val & CPSR_T) != 0);
2591 if (mask & CPSR_IT_0_1) {
2592 env->condexec_bits &= ~3;
2593 env->condexec_bits |= (val >> 25) & 3;
2594 }
2595 if (mask & CPSR_IT_2_7) {
2596 env->condexec_bits &= 3;
2597 env->condexec_bits |= (val >> 8) & 0xfc;
2598 }
2599 if (mask & CPSR_GE) {
2600 env->GE = (val >> 16) & 0xf;
2601 }
2602
2603 env->daif &= ~(CPSR_AIF & mask);
2604 env->daif |= val & CPSR_AIF & mask;
2605
2606 if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
2607 if (bad_mode_switch(env, val & CPSR_M)) {
2608 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
2609 * We choose to ignore the attempt and leave the CPSR M field
2610 * untouched.
2611 */
2612 mask &= ~CPSR_M;
2613 } else {
2614 switch_mode(env, val & CPSR_M);
2615 }
2616 }
2617 mask &= ~CACHED_CPSR_BITS;
2618 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
2619 }
2620
2621 /* Sign/zero extend */
2622 uint32_t HELPER(sxtb16)(uint32_t x)
2623 {
2624 uint32_t res;
2625 res = (uint16_t)(int8_t)x;
2626 res |= (uint32_t)(int8_t)(x >> 16) << 16;
2627 return res;
2628 }
2629
2630 uint32_t HELPER(uxtb16)(uint32_t x)
2631 {
2632 uint32_t res;
2633 res = (uint16_t)(uint8_t)x;
2634 res |= (uint32_t)(uint8_t)(x >> 16) << 16;
2635 return res;
2636 }
2637
2638 uint32_t HELPER(clz)(uint32_t x)
2639 {
2640 return clz32(x);
2641 }
2642
2643 int32_t HELPER(sdiv)(int32_t num, int32_t den)
2644 {
2645 if (den == 0)
2646 return 0;
2647 if (num == INT_MIN && den == -1)
2648 return INT_MIN;
2649 return num / den;
2650 }
2651
2652 uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
2653 {
2654 if (den == 0)
2655 return 0;
2656 return num / den;
2657 }
2658
2659 uint32_t HELPER(rbit)(uint32_t x)
2660 {
2661 x = ((x & 0xff000000) >> 24)
2662 | ((x & 0x00ff0000) >> 8)
2663 | ((x & 0x0000ff00) << 8)
2664 | ((x & 0x000000ff) << 24);
2665 x = ((x & 0xf0f0f0f0) >> 4)
2666 | ((x & 0x0f0f0f0f) << 4);
2667 x = ((x & 0x88888888) >> 3)
2668 | ((x & 0x44444444) >> 1)
2669 | ((x & 0x22222222) << 1)
2670 | ((x & 0x11111111) << 3);
2671 return x;
2672 }
2673
2674 #if defined(CONFIG_USER_ONLY)
2675
2676 void arm_cpu_do_interrupt(CPUState *cs)
2677 {
2678 cs->exception_index = -1;
2679 }
2680
2681 int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
2682 int mmu_idx)
2683 {
2684 ARMCPU *cpu = ARM_CPU(cs);
2685 CPUARMState *env = &cpu->env;
2686
2687 if (rw == 2) {
2688 cs->exception_index = EXCP_PREFETCH_ABORT;
2689 env->cp15.c6_insn = address;
2690 } else {
2691 cs->exception_index = EXCP_DATA_ABORT;
2692 env->cp15.c6_data = address;
2693 }
2694 return 1;
2695 }
2696
2697 /* These should probably raise undefined insn exceptions. */
2698 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
2699 {
2700 ARMCPU *cpu = arm_env_get_cpu(env);
2701
2702 cpu_abort(CPU(cpu), "v7m_msr %d\n", reg);
2703 }
2704
2705 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
2706 {
2707 ARMCPU *cpu = arm_env_get_cpu(env);
2708
2709 cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg);
2710 return 0;
2711 }
2712
2713 void switch_mode(CPUARMState *env, int mode)
2714 {
2715 ARMCPU *cpu = arm_env_get_cpu(env);
2716
2717 if (mode != ARM_CPU_MODE_USR) {
2718 cpu_abort(CPU(cpu), "Tried to switch out of user mode\n");
2719 }
2720 }
2721
2722 void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
2723 {
2724 ARMCPU *cpu = arm_env_get_cpu(env);
2725
2726 cpu_abort(CPU(cpu), "banked r13 write\n");
2727 }
2728
2729 uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
2730 {
2731 ARMCPU *cpu = arm_env_get_cpu(env);
2732
2733 cpu_abort(CPU(cpu), "banked r13 read\n");
2734 return 0;
2735 }
2736
2737 #else
2738
2739 /* Map CPU modes onto saved register banks. */
2740 int bank_number(int mode)
2741 {
2742 switch (mode) {
2743 case ARM_CPU_MODE_USR:
2744 case ARM_CPU_MODE_SYS:
2745 return 0;
2746 case ARM_CPU_MODE_SVC:
2747 return 1;
2748 case ARM_CPU_MODE_ABT:
2749 return 2;
2750 case ARM_CPU_MODE_UND:
2751 return 3;
2752 case ARM_CPU_MODE_IRQ:
2753 return 4;
2754 case ARM_CPU_MODE_FIQ:
2755 return 5;
2756 }
2757 hw_error("bank number requested for bad CPSR mode value 0x%x\n", mode);
2758 }
2759
2760 void switch_mode(CPUARMState *env, int mode)
2761 {
2762 int old_mode;
2763 int i;
2764
2765 old_mode = env->uncached_cpsr & CPSR_M;
2766 if (mode == old_mode)
2767 return;
2768
2769 if (old_mode == ARM_CPU_MODE_FIQ) {
2770 memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
2771 memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
2772 } else if (mode == ARM_CPU_MODE_FIQ) {
2773 memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
2774 memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
2775 }
2776
2777 i = bank_number(old_mode);
2778 env->banked_r13[i] = env->regs[13];
2779 env->banked_r14[i] = env->regs[14];
2780 env->banked_spsr[i] = env->spsr;
2781
2782 i = bank_number(mode);
2783 env->regs[13] = env->banked_r13[i];
2784 env->regs[14] = env->banked_r14[i];
2785 env->spsr = env->banked_spsr[i];
2786 }
2787
2788 static void v7m_push(CPUARMState *env, uint32_t val)
2789 {
2790 CPUState *cs = CPU(arm_env_get_cpu(env));
2791
2792 env->regs[13] -= 4;
2793 stl_phys(cs->as, env->regs[13], val);
2794 }
2795
2796 static uint32_t v7m_pop(CPUARMState *env)
2797 {
2798 CPUState *cs = CPU(arm_env_get_cpu(env));
2799 uint32_t val;
2800
2801 val = ldl_phys(cs->as, env->regs[13]);
2802 env->regs[13] += 4;
2803 return val;
2804 }
2805
2806 /* Switch to V7M main or process stack pointer. */
2807 static void switch_v7m_sp(CPUARMState *env, int process)
2808 {
2809 uint32_t tmp;
2810 if (env->v7m.current_sp != process) {
2811 tmp = env->v7m.other_sp;
2812 env->v7m.other_sp = env->regs[13];
2813 env->regs[13] = tmp;
2814 env->v7m.current_sp = process;
2815 }
2816 }
2817
2818 static void do_v7m_exception_exit(CPUARMState *env)
2819 {
2820 uint32_t type;
2821 uint32_t xpsr;
2822
2823 type = env->regs[15];
2824 if (env->v7m.exception != 0)
2825 armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
2826
2827 /* Switch to the target stack. */
2828 switch_v7m_sp(env, (type & 4) != 0);
2829 /* Pop registers. */
2830 env->regs[0] = v7m_pop(env);
2831 env->regs[1] = v7m_pop(env);
2832 env->regs[2] = v7m_pop(env);
2833 env->regs[3] = v7m_pop(env);
2834 env->regs[12] = v7m_pop(env);
2835 env->regs[14] = v7m_pop(env);
2836 env->regs[15] = v7m_pop(env);
2837 xpsr = v7m_pop(env);
2838 xpsr_write(env, xpsr, 0xfffffdff);
2839 /* Undo stack alignment. */
2840 if (xpsr & 0x200)
2841 env->regs[13] |= 4;
2842 /* ??? The exception return type specifies Thread/Handler mode. However
2843 this is also implied by the xPSR value. Not sure what to do
2844 if there is a mismatch. */
2845 /* ??? Likewise for mismatches between the CONTROL register and the stack
2846 pointer. */
2847 }
2848
2849 /* Exception names for debug logging; note that not all of these
2850 * precisely correspond to architectural exceptions.
2851 */
2852 static const char * const excnames[] = {
2853 [EXCP_UDEF] = "Undefined Instruction",
2854 [EXCP_SWI] = "SVC",
2855 [EXCP_PREFETCH_ABORT] = "Prefetch Abort",
2856 [EXCP_DATA_ABORT] = "Data Abort",
2857 [EXCP_IRQ] = "IRQ",
2858 [EXCP_FIQ] = "FIQ",
2859 [EXCP_BKPT] = "Breakpoint",
2860 [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit",
2861 [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage",
2862 [EXCP_STREX] = "QEMU intercept of STREX",
2863 };
2864
2865 static inline void arm_log_exception(int idx)
2866 {
2867 if (qemu_loglevel_mask(CPU_LOG_INT)) {
2868 const char *exc = NULL;
2869
2870 if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
2871 exc = excnames[idx];
2872 }
2873 if (!exc) {
2874 exc = "unknown";
2875 }
2876 qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc);
2877 }
2878 }
2879
2880 void arm_v7m_cpu_do_interrupt(CPUState *cs)
2881 {
2882 ARMCPU *cpu = ARM_CPU(cs);
2883 CPUARMState *env = &cpu->env;
2884 uint32_t xpsr = xpsr_read(env);
2885 uint32_t lr;
2886 uint32_t addr;
2887
2888 arm_log_exception(cs->exception_index);
2889
2890 lr = 0xfffffff1;
2891 if (env->v7m.current_sp)
2892 lr |= 4;
2893 if (env->v7m.exception == 0)
2894 lr |= 8;
2895
2896 /* For exceptions we just mark as pending on the NVIC, and let that