qemu-img: Omit error_report() after img_open()
[qemu.git] / target-arm / helper.c
1 #include "cpu.h"
2 #include "internals.h"
3 #include "exec/gdbstub.h"
4 #include "exec/helper-proto.h"
5 #include "qemu/host-utils.h"
6 #include "sysemu/arch_init.h"
7 #include "sysemu/sysemu.h"
8 #include "qemu/bitops.h"
9 #include "qemu/crc32c.h"
10 #include "exec/cpu_ldst.h"
11 #include "arm_ldst.h"
12 #include <zlib.h> /* For crc32 */
13
14 #ifndef CONFIG_USER_ONLY
15 static inline int get_phys_addr(CPUARMState *env, target_ulong address,
16 int access_type, int is_user,
17 hwaddr *phys_ptr, int *prot,
18 target_ulong *page_size);
19
20 /* Definitions for the PMCCNTR and PMCR registers */
21 #define PMCRD 0x8
22 #define PMCRC 0x4
23 #define PMCRE 0x1
24 #endif
25
26 static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
27 {
28 int nregs;
29
30 /* VFP data registers are always little-endian. */
31 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
32 if (reg < nregs) {
33 stfq_le_p(buf, env->vfp.regs[reg]);
34 return 8;
35 }
36 if (arm_feature(env, ARM_FEATURE_NEON)) {
37 /* Aliases for Q regs. */
38 nregs += 16;
39 if (reg < nregs) {
40 stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
41 stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
42 return 16;
43 }
44 }
45 switch (reg - nregs) {
46 case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
47 case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
48 case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
49 }
50 return 0;
51 }
52
53 static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
54 {
55 int nregs;
56
57 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
58 if (reg < nregs) {
59 env->vfp.regs[reg] = ldfq_le_p(buf);
60 return 8;
61 }
62 if (arm_feature(env, ARM_FEATURE_NEON)) {
63 nregs += 16;
64 if (reg < nregs) {
65 env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
66 env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
67 return 16;
68 }
69 }
70 switch (reg - nregs) {
71 case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
72 case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
73 case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
74 }
75 return 0;
76 }
77
78 static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
79 {
80 switch (reg) {
81 case 0 ... 31:
82 /* 128 bit FP register */
83 stfq_le_p(buf, env->vfp.regs[reg * 2]);
84 stfq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]);
85 return 16;
86 case 32:
87 /* FPSR */
88 stl_p(buf, vfp_get_fpsr(env));
89 return 4;
90 case 33:
91 /* FPCR */
92 stl_p(buf, vfp_get_fpcr(env));
93 return 4;
94 default:
95 return 0;
96 }
97 }
98
99 static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
100 {
101 switch (reg) {
102 case 0 ... 31:
103 /* 128 bit FP register */
104 env->vfp.regs[reg * 2] = ldfq_le_p(buf);
105 env->vfp.regs[reg * 2 + 1] = ldfq_le_p(buf + 8);
106 return 16;
107 case 32:
108 /* FPSR */
109 vfp_set_fpsr(env, ldl_p(buf));
110 return 4;
111 case 33:
112 /* FPCR */
113 vfp_set_fpcr(env, ldl_p(buf));
114 return 4;
115 default:
116 return 0;
117 }
118 }
119
120 static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri)
121 {
122 if (cpreg_field_is_64bit(ri)) {
123 return CPREG_FIELD64(env, ri);
124 } else {
125 return CPREG_FIELD32(env, ri);
126 }
127 }
128
129 static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
130 uint64_t value)
131 {
132 if (cpreg_field_is_64bit(ri)) {
133 CPREG_FIELD64(env, ri) = value;
134 } else {
135 CPREG_FIELD32(env, ri) = value;
136 }
137 }
138
139 static uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri)
140 {
141 /* Raw read of a coprocessor register (as needed for migration, etc). */
142 if (ri->type & ARM_CP_CONST) {
143 return ri->resetvalue;
144 } else if (ri->raw_readfn) {
145 return ri->raw_readfn(env, ri);
146 } else if (ri->readfn) {
147 return ri->readfn(env, ri);
148 } else {
149 return raw_read(env, ri);
150 }
151 }
152
153 static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
154 uint64_t v)
155 {
156 /* Raw write of a coprocessor register (as needed for migration, etc).
157 * Note that constant registers are treated as write-ignored; the
158 * caller should check for success by whether a readback gives the
159 * value written.
160 */
161 if (ri->type & ARM_CP_CONST) {
162 return;
163 } else if (ri->raw_writefn) {
164 ri->raw_writefn(env, ri, v);
165 } else if (ri->writefn) {
166 ri->writefn(env, ri, v);
167 } else {
168 raw_write(env, ri, v);
169 }
170 }
171
172 bool write_cpustate_to_list(ARMCPU *cpu)
173 {
174 /* Write the coprocessor state from cpu->env to the (index,value) list. */
175 int i;
176 bool ok = true;
177
178 for (i = 0; i < cpu->cpreg_array_len; i++) {
179 uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
180 const ARMCPRegInfo *ri;
181
182 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
183 if (!ri) {
184 ok = false;
185 continue;
186 }
187 if (ri->type & ARM_CP_NO_MIGRATE) {
188 continue;
189 }
190 cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri);
191 }
192 return ok;
193 }
194
195 bool write_list_to_cpustate(ARMCPU *cpu)
196 {
197 int i;
198 bool ok = true;
199
200 for (i = 0; i < cpu->cpreg_array_len; i++) {
201 uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
202 uint64_t v = cpu->cpreg_values[i];
203 const ARMCPRegInfo *ri;
204
205 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
206 if (!ri) {
207 ok = false;
208 continue;
209 }
210 if (ri->type & ARM_CP_NO_MIGRATE) {
211 continue;
212 }
213 /* Write value and confirm it reads back as written
214 * (to catch read-only registers and partially read-only
215 * registers where the incoming migration value doesn't match)
216 */
217 write_raw_cp_reg(&cpu->env, ri, v);
218 if (read_raw_cp_reg(&cpu->env, ri) != v) {
219 ok = false;
220 }
221 }
222 return ok;
223 }
224
225 static void add_cpreg_to_list(gpointer key, gpointer opaque)
226 {
227 ARMCPU *cpu = opaque;
228 uint64_t regidx;
229 const ARMCPRegInfo *ri;
230
231 regidx = *(uint32_t *)key;
232 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
233
234 if (!(ri->type & ARM_CP_NO_MIGRATE)) {
235 cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
236 /* The value array need not be initialized at this point */
237 cpu->cpreg_array_len++;
238 }
239 }
240
241 static void count_cpreg(gpointer key, gpointer opaque)
242 {
243 ARMCPU *cpu = opaque;
244 uint64_t regidx;
245 const ARMCPRegInfo *ri;
246
247 regidx = *(uint32_t *)key;
248 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
249
250 if (!(ri->type & ARM_CP_NO_MIGRATE)) {
251 cpu->cpreg_array_len++;
252 }
253 }
254
255 static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
256 {
257 uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a);
258 uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b);
259
260 if (aidx > bidx) {
261 return 1;
262 }
263 if (aidx < bidx) {
264 return -1;
265 }
266 return 0;
267 }
268
269 static void cpreg_make_keylist(gpointer key, gpointer value, gpointer udata)
270 {
271 GList **plist = udata;
272
273 *plist = g_list_prepend(*plist, key);
274 }
275
276 void init_cpreg_list(ARMCPU *cpu)
277 {
278 /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
279 * Note that we require cpreg_tuples[] to be sorted by key ID.
280 */
281 GList *keys = NULL;
282 int arraylen;
283
284 g_hash_table_foreach(cpu->cp_regs, cpreg_make_keylist, &keys);
285
286 keys = g_list_sort(keys, cpreg_key_compare);
287
288 cpu->cpreg_array_len = 0;
289
290 g_list_foreach(keys, count_cpreg, cpu);
291
292 arraylen = cpu->cpreg_array_len;
293 cpu->cpreg_indexes = g_new(uint64_t, arraylen);
294 cpu->cpreg_values = g_new(uint64_t, arraylen);
295 cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen);
296 cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen);
297 cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
298 cpu->cpreg_array_len = 0;
299
300 g_list_foreach(keys, add_cpreg_to_list, cpu);
301
302 assert(cpu->cpreg_array_len == arraylen);
303
304 g_list_free(keys);
305 }
306
307 static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
308 {
309 ARMCPU *cpu = arm_env_get_cpu(env);
310
311 raw_write(env, ri, value);
312 tlb_flush(CPU(cpu), 1); /* Flush TLB as domain not tracked in TLB */
313 }
314
315 static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
316 {
317 ARMCPU *cpu = arm_env_get_cpu(env);
318
319 if (raw_read(env, ri) != value) {
320 /* Unlike real hardware the qemu TLB uses virtual addresses,
321 * not modified virtual addresses, so this causes a TLB flush.
322 */
323 tlb_flush(CPU(cpu), 1);
324 raw_write(env, ri, value);
325 }
326 }
327
328 static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
329 uint64_t value)
330 {
331 ARMCPU *cpu = arm_env_get_cpu(env);
332
333 if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_MPU)
334 && !extended_addresses_enabled(env)) {
335 /* For VMSA (when not using the LPAE long descriptor page table
336 * format) this register includes the ASID, so do a TLB flush.
337 * For PMSA it is purely a process ID and no action is needed.
338 */
339 tlb_flush(CPU(cpu), 1);
340 }
341 raw_write(env, ri, value);
342 }
343
344 static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
345 uint64_t value)
346 {
347 /* Invalidate all (TLBIALL) */
348 ARMCPU *cpu = arm_env_get_cpu(env);
349
350 tlb_flush(CPU(cpu), 1);
351 }
352
353 static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
354 uint64_t value)
355 {
356 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
357 ARMCPU *cpu = arm_env_get_cpu(env);
358
359 tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
360 }
361
362 static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
363 uint64_t value)
364 {
365 /* Invalidate by ASID (TLBIASID) */
366 ARMCPU *cpu = arm_env_get_cpu(env);
367
368 tlb_flush(CPU(cpu), value == 0);
369 }
370
371 static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
372 uint64_t value)
373 {
374 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
375 ARMCPU *cpu = arm_env_get_cpu(env);
376
377 tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
378 }
379
380 /* IS variants of TLB operations must affect all cores */
381 static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
382 uint64_t value)
383 {
384 CPUState *other_cs;
385
386 CPU_FOREACH(other_cs) {
387 tlb_flush(other_cs, 1);
388 }
389 }
390
391 static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
392 uint64_t value)
393 {
394 CPUState *other_cs;
395
396 CPU_FOREACH(other_cs) {
397 tlb_flush(other_cs, value == 0);
398 }
399 }
400
401 static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
402 uint64_t value)
403 {
404 CPUState *other_cs;
405
406 CPU_FOREACH(other_cs) {
407 tlb_flush_page(other_cs, value & TARGET_PAGE_MASK);
408 }
409 }
410
411 static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
412 uint64_t value)
413 {
414 CPUState *other_cs;
415
416 CPU_FOREACH(other_cs) {
417 tlb_flush_page(other_cs, value & TARGET_PAGE_MASK);
418 }
419 }
420
421 static const ARMCPRegInfo cp_reginfo[] = {
422 { .name = "FCSEIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 0,
423 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
424 .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
425 { .name = "CONTEXTIDR", .state = ARM_CP_STATE_BOTH,
426 .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
427 .access = PL1_RW,
428 .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el1),
429 .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
430 REGINFO_SENTINEL
431 };
432
433 static const ARMCPRegInfo not_v8_cp_reginfo[] = {
434 /* NB: Some of these registers exist in v8 but with more precise
435 * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
436 */
437 /* MMU Domain access control / MPU write buffer control */
438 { .name = "DACR", .cp = 15,
439 .crn = 3, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
440 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3),
441 .resetvalue = 0, .writefn = dacr_write, .raw_writefn = raw_write, },
442 /* ??? This covers not just the impdef TLB lockdown registers but also
443 * some v7VMSA registers relating to TEX remap, so it is overly broad.
444 */
445 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = CP_ANY,
446 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
447 /* Cache maintenance ops; some of this space may be overridden later. */
448 { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
449 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
450 .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
451 REGINFO_SENTINEL
452 };
453
454 static const ARMCPRegInfo not_v6_cp_reginfo[] = {
455 /* Not all pre-v6 cores implemented this WFI, so this is slightly
456 * over-broad.
457 */
458 { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
459 .access = PL1_W, .type = ARM_CP_WFI },
460 REGINFO_SENTINEL
461 };
462
463 static const ARMCPRegInfo not_v7_cp_reginfo[] = {
464 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
465 * is UNPREDICTABLE; we choose to NOP as most implementations do).
466 */
467 { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
468 .access = PL1_W, .type = ARM_CP_WFI },
469 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
470 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
471 * OMAPCP will override this space.
472 */
473 { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0,
474 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data),
475 .resetvalue = 0 },
476 { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1,
477 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn),
478 .resetvalue = 0 },
479 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
480 { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
481 .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
482 .resetvalue = 0 },
483 /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
484 * implementing it as RAZ means the "debug architecture version" bits
485 * will read as a reserved value, which should cause Linux to not try
486 * to use the debug hardware.
487 */
488 { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
489 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
490 /* MMU TLB control. Note that the wildcarding means we cover not just
491 * the unified TLB ops but also the dside/iside/inner-shareable variants.
492 */
493 { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
494 .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write,
495 .type = ARM_CP_NO_MIGRATE },
496 { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY,
497 .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write,
498 .type = ARM_CP_NO_MIGRATE },
499 { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY,
500 .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write,
501 .type = ARM_CP_NO_MIGRATE },
502 { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY,
503 .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write,
504 .type = ARM_CP_NO_MIGRATE },
505 REGINFO_SENTINEL
506 };
507
508 static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
509 uint64_t value)
510 {
511 uint32_t mask = 0;
512
513 /* In ARMv8 most bits of CPACR_EL1 are RES0. */
514 if (!arm_feature(env, ARM_FEATURE_V8)) {
515 /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
516 * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
517 * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
518 */
519 if (arm_feature(env, ARM_FEATURE_VFP)) {
520 /* VFP coprocessor: cp10 & cp11 [23:20] */
521 mask |= (1 << 31) | (1 << 30) | (0xf << 20);
522
523 if (!arm_feature(env, ARM_FEATURE_NEON)) {
524 /* ASEDIS [31] bit is RAO/WI */
525 value |= (1 << 31);
526 }
527
528 /* VFPv3 and upwards with NEON implement 32 double precision
529 * registers (D0-D31).
530 */
531 if (!arm_feature(env, ARM_FEATURE_NEON) ||
532 !arm_feature(env, ARM_FEATURE_VFP3)) {
533 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
534 value |= (1 << 30);
535 }
536 }
537 value &= mask;
538 }
539 env->cp15.c1_coproc = value;
540 }
541
542 static const ARMCPRegInfo v6_cp_reginfo[] = {
543 /* prefetch by MVA in v6, NOP in v7 */
544 { .name = "MVA_prefetch",
545 .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
546 .access = PL1_W, .type = ARM_CP_NOP },
547 { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
548 .access = PL0_W, .type = ARM_CP_NOP },
549 { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
550 .access = PL0_W, .type = ARM_CP_NOP },
551 { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
552 .access = PL0_W, .type = ARM_CP_NOP },
553 { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
554 .access = PL1_RW,
555 .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[1]),
556 .resetvalue = 0, },
557 /* Watchpoint Fault Address Register : should actually only be present
558 * for 1136, 1176, 11MPCore.
559 */
560 { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
561 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
562 { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
563 .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2,
564 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_coproc),
565 .resetvalue = 0, .writefn = cpacr_write },
566 REGINFO_SENTINEL
567 };
568
569 static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri)
570 {
571 /* Performance monitor registers user accessibility is controlled
572 * by PMUSERENR.
573 */
574 if (arm_current_el(env) == 0 && !env->cp15.c9_pmuserenr) {
575 return CP_ACCESS_TRAP;
576 }
577 return CP_ACCESS_OK;
578 }
579
580 #ifndef CONFIG_USER_ONLY
581
582 static inline bool arm_ccnt_enabled(CPUARMState *env)
583 {
584 /* This does not support checking PMCCFILTR_EL0 register */
585
586 if (!(env->cp15.c9_pmcr & PMCRE)) {
587 return false;
588 }
589
590 return true;
591 }
592
593 void pmccntr_sync(CPUARMState *env)
594 {
595 uint64_t temp_ticks;
596
597 temp_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL),
598 get_ticks_per_sec(), 1000000);
599
600 if (env->cp15.c9_pmcr & PMCRD) {
601 /* Increment once every 64 processor clock cycles */
602 temp_ticks /= 64;
603 }
604
605 if (arm_ccnt_enabled(env)) {
606 env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
607 }
608 }
609
610 static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
611 uint64_t value)
612 {
613 pmccntr_sync(env);
614
615 if (value & PMCRC) {
616 /* The counter has been reset */
617 env->cp15.c15_ccnt = 0;
618 }
619
620 /* only the DP, X, D and E bits are writable */
621 env->cp15.c9_pmcr &= ~0x39;
622 env->cp15.c9_pmcr |= (value & 0x39);
623
624 pmccntr_sync(env);
625 }
626
627 static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
628 {
629 uint64_t total_ticks;
630
631 if (!arm_ccnt_enabled(env)) {
632 /* Counter is disabled, do not change value */
633 return env->cp15.c15_ccnt;
634 }
635
636 total_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL),
637 get_ticks_per_sec(), 1000000);
638
639 if (env->cp15.c9_pmcr & PMCRD) {
640 /* Increment once every 64 processor clock cycles */
641 total_ticks /= 64;
642 }
643 return total_ticks - env->cp15.c15_ccnt;
644 }
645
646 static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
647 uint64_t value)
648 {
649 uint64_t total_ticks;
650
651 if (!arm_ccnt_enabled(env)) {
652 /* Counter is disabled, set the absolute value */
653 env->cp15.c15_ccnt = value;
654 return;
655 }
656
657 total_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL),
658 get_ticks_per_sec(), 1000000);
659
660 if (env->cp15.c9_pmcr & PMCRD) {
661 /* Increment once every 64 processor clock cycles */
662 total_ticks /= 64;
663 }
664 env->cp15.c15_ccnt = total_ticks - value;
665 }
666
667 static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri,
668 uint64_t value)
669 {
670 uint64_t cur_val = pmccntr_read(env, NULL);
671
672 pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value));
673 }
674
675 #else /* CONFIG_USER_ONLY */
676
677 void pmccntr_sync(CPUARMState *env)
678 {
679 }
680
681 #endif
682
683 static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri,
684 uint64_t value)
685 {
686 pmccntr_sync(env);
687 env->cp15.pmccfiltr_el0 = value & 0x7E000000;
688 pmccntr_sync(env);
689 }
690
691 static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
692 uint64_t value)
693 {
694 value &= (1 << 31);
695 env->cp15.c9_pmcnten |= value;
696 }
697
698 static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
699 uint64_t value)
700 {
701 value &= (1 << 31);
702 env->cp15.c9_pmcnten &= ~value;
703 }
704
705 static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
706 uint64_t value)
707 {
708 env->cp15.c9_pmovsr &= ~value;
709 }
710
711 static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
712 uint64_t value)
713 {
714 env->cp15.c9_pmxevtyper = value & 0xff;
715 }
716
717 static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
718 uint64_t value)
719 {
720 env->cp15.c9_pmuserenr = value & 1;
721 }
722
723 static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
724 uint64_t value)
725 {
726 /* We have no event counters so only the C bit can be changed */
727 value &= (1 << 31);
728 env->cp15.c9_pminten |= value;
729 }
730
731 static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
732 uint64_t value)
733 {
734 value &= (1 << 31);
735 env->cp15.c9_pminten &= ~value;
736 }
737
738 static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
739 uint64_t value)
740 {
741 /* Note that even though the AArch64 view of this register has bits
742 * [10:0] all RES0 we can only mask the bottom 5, to comply with the
743 * architectural requirements for bits which are RES0 only in some
744 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
745 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
746 */
747 raw_write(env, ri, value & ~0x1FULL);
748 }
749
750 static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
751 {
752 /* We only mask off bits that are RES0 both for AArch64 and AArch32.
753 * For bits that vary between AArch32/64, code needs to check the
754 * current execution mode before directly using the feature bit.
755 */
756 uint32_t valid_mask = SCR_AARCH64_MASK | SCR_AARCH32_MASK;
757
758 if (!arm_feature(env, ARM_FEATURE_EL2)) {
759 valid_mask &= ~SCR_HCE;
760
761 /* On ARMv7, SMD (or SCD as it is called in v7) is only
762 * supported if EL2 exists. The bit is UNK/SBZP when
763 * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
764 * when EL2 is unavailable.
765 */
766 if (arm_feature(env, ARM_FEATURE_V7)) {
767 valid_mask &= ~SCR_SMD;
768 }
769 }
770
771 /* Clear all-context RES0 bits. */
772 value &= valid_mask;
773 raw_write(env, ri, value);
774 }
775
776 static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
777 {
778 ARMCPU *cpu = arm_env_get_cpu(env);
779 return cpu->ccsidr[env->cp15.c0_cssel];
780 }
781
782 static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
783 uint64_t value)
784 {
785 raw_write(env, ri, value & 0xf);
786 }
787
788 static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
789 {
790 CPUState *cs = ENV_GET_CPU(env);
791 uint64_t ret = 0;
792
793 if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
794 ret |= CPSR_I;
795 }
796 if (cs->interrupt_request & CPU_INTERRUPT_FIQ) {
797 ret |= CPSR_F;
798 }
799 /* External aborts are not possible in QEMU so A bit is always clear */
800 return ret;
801 }
802
803 static const ARMCPRegInfo v7_cp_reginfo[] = {
804 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
805 { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
806 .access = PL1_W, .type = ARM_CP_NOP },
807 /* Performance monitors are implementation defined in v7,
808 * but with an ARM recommended set of registers, which we
809 * follow (although we don't actually implement any counters)
810 *
811 * Performance registers fall into three categories:
812 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
813 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
814 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
815 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
816 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
817 */
818 { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
819 .access = PL0_RW, .type = ARM_CP_NO_MIGRATE,
820 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
821 .writefn = pmcntenset_write,
822 .accessfn = pmreg_access,
823 .raw_writefn = raw_write },
824 { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64,
825 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1,
826 .access = PL0_RW, .accessfn = pmreg_access,
827 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0,
828 .writefn = pmcntenset_write, .raw_writefn = raw_write },
829 { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
830 .access = PL0_RW,
831 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
832 .accessfn = pmreg_access,
833 .writefn = pmcntenclr_write,
834 .type = ARM_CP_NO_MIGRATE },
835 { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64,
836 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2,
837 .access = PL0_RW, .accessfn = pmreg_access,
838 .type = ARM_CP_NO_MIGRATE,
839 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
840 .writefn = pmcntenclr_write },
841 { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
842 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
843 .accessfn = pmreg_access,
844 .writefn = pmovsr_write,
845 .raw_writefn = raw_write },
846 /* Unimplemented so WI. */
847 { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
848 .access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP },
849 /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
850 * We choose to RAZ/WI.
851 */
852 { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
853 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
854 .accessfn = pmreg_access },
855 #ifndef CONFIG_USER_ONLY
856 { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
857 .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO,
858 .readfn = pmccntr_read, .writefn = pmccntr_write32,
859 .accessfn = pmreg_access },
860 { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64,
861 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0,
862 .access = PL0_RW, .accessfn = pmreg_access,
863 .type = ARM_CP_IO,
864 .readfn = pmccntr_read, .writefn = pmccntr_write, },
865 #endif
866 { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64,
867 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7,
868 .writefn = pmccfiltr_write,
869 .access = PL0_RW, .accessfn = pmreg_access,
870 .type = ARM_CP_IO,
871 .fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0),
872 .resetvalue = 0, },
873 { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
874 .access = PL0_RW,
875 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
876 .accessfn = pmreg_access, .writefn = pmxevtyper_write,
877 .raw_writefn = raw_write },
878 /* Unimplemented, RAZ/WI. */
879 { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
880 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
881 .accessfn = pmreg_access },
882 { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
883 .access = PL0_R | PL1_RW,
884 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
885 .resetvalue = 0,
886 .writefn = pmuserenr_write, .raw_writefn = raw_write },
887 { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
888 .access = PL1_RW,
889 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
890 .resetvalue = 0,
891 .writefn = pmintenset_write, .raw_writefn = raw_write },
892 { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
893 .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
894 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
895 .resetvalue = 0, .writefn = pmintenclr_write, },
896 { .name = "VBAR", .state = ARM_CP_STATE_BOTH,
897 .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
898 .access = PL1_RW, .writefn = vbar_write,
899 .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[1]),
900 .resetvalue = 0 },
901 { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
902 .access = PL1_RW, .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3),
903 .resetvalue = 0, .writefn = scr_write },
904 { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
905 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
906 .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE },
907 { .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
908 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
909 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c0_cssel),
910 .writefn = csselr_write, .resetvalue = 0 },
911 /* Auxiliary ID register: this actually has an IMPDEF value but for now
912 * just RAZ for all cores:
913 */
914 { .name = "AIDR", .state = ARM_CP_STATE_BOTH,
915 .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7,
916 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
917 /* Auxiliary fault status registers: these also are IMPDEF, and we
918 * choose to RAZ/WI for all cores.
919 */
920 { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH,
921 .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0,
922 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
923 { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH,
924 .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1,
925 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
926 /* MAIR can just read-as-written because we don't implement caches
927 * and so don't need to care about memory attributes.
928 */
929 { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64,
930 .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0,
931 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el1),
932 .resetvalue = 0 },
933 /* For non-long-descriptor page tables these are PRRR and NMRR;
934 * regardless they still act as reads-as-written for QEMU.
935 * The override is necessary because of the overly-broad TLB_LOCKDOWN
936 * definition.
937 */
938 { .name = "MAIR0", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE,
939 .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW,
940 .fieldoffset = offsetoflow32(CPUARMState, cp15.mair_el1),
941 .resetfn = arm_cp_reset_ignore },
942 { .name = "MAIR1", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE,
943 .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW,
944 .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el1),
945 .resetfn = arm_cp_reset_ignore },
946 { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH,
947 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0,
948 .type = ARM_CP_NO_MIGRATE, .access = PL1_R, .readfn = isr_read },
949 /* 32 bit ITLB invalidates */
950 { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0,
951 .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiall_write },
952 { .name = "ITLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1,
953 .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write },
954 { .name = "ITLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 2,
955 .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiasid_write },
956 /* 32 bit DTLB invalidates */
957 { .name = "DTLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 0,
958 .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiall_write },
959 { .name = "DTLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1,
960 .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write },
961 { .name = "DTLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 2,
962 .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiasid_write },
963 /* 32 bit TLB invalidates */
964 { .name = "TLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
965 .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiall_write },
966 { .name = "TLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
967 .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write },
968 { .name = "TLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
969 .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiasid_write },
970 { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
971 .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimvaa_write },
972 REGINFO_SENTINEL
973 };
974
975 static const ARMCPRegInfo v7mp_cp_reginfo[] = {
976 /* 32 bit TLB invalidates, Inner Shareable */
977 { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
978 .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiall_is_write },
979 { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
980 .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_is_write },
981 { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
982 .type = ARM_CP_NO_MIGRATE, .access = PL1_W,
983 .writefn = tlbiasid_is_write },
984 { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
985 .type = ARM_CP_NO_MIGRATE, .access = PL1_W,
986 .writefn = tlbimvaa_is_write },
987 REGINFO_SENTINEL
988 };
989
990 static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri,
991 uint64_t value)
992 {
993 value &= 1;
994 env->teecr = value;
995 }
996
997 static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri)
998 {
999 if (arm_current_el(env) == 0 && (env->teecr & 1)) {
1000 return CP_ACCESS_TRAP;
1001 }
1002 return CP_ACCESS_OK;
1003 }
1004
1005 static const ARMCPRegInfo t2ee_cp_reginfo[] = {
1006 { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
1007 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
1008 .resetvalue = 0,
1009 .writefn = teecr_write },
1010 { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
1011 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
1012 .accessfn = teehbr_access, .resetvalue = 0 },
1013 REGINFO_SENTINEL
1014 };
1015
1016 static const ARMCPRegInfo v6k_cp_reginfo[] = {
1017 { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64,
1018 .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0,
1019 .access = PL0_RW,
1020 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el0), .resetvalue = 0 },
1021 { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
1022 .access = PL0_RW,
1023 .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidr_el0),
1024 .resetfn = arm_cp_reset_ignore },
1025 { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64,
1026 .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
1027 .access = PL0_R|PL1_W,
1028 .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el0), .resetvalue = 0 },
1029 { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
1030 .access = PL0_R|PL1_W,
1031 .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidrro_el0),
1032 .resetfn = arm_cp_reset_ignore },
1033 { .name = "TPIDR_EL1", .state = ARM_CP_STATE_BOTH,
1034 .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0,
1035 .access = PL1_RW,
1036 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el1), .resetvalue = 0 },
1037 REGINFO_SENTINEL
1038 };
1039
1040 #ifndef CONFIG_USER_ONLY
1041
1042 static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri)
1043 {
1044 /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero */
1045 if (arm_current_el(env) == 0 && !extract32(env->cp15.c14_cntkctl, 0, 2)) {
1046 return CP_ACCESS_TRAP;
1047 }
1048 return CP_ACCESS_OK;
1049 }
1050
1051 static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx)
1052 {
1053 /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
1054 if (arm_current_el(env) == 0 &&
1055 !extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
1056 return CP_ACCESS_TRAP;
1057 }
1058 return CP_ACCESS_OK;
1059 }
1060
1061 static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx)
1062 {
1063 /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
1064 * EL0[PV]TEN is zero.
1065 */
1066 if (arm_current_el(env) == 0 &&
1067 !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
1068 return CP_ACCESS_TRAP;
1069 }
1070 return CP_ACCESS_OK;
1071 }
1072
1073 static CPAccessResult gt_pct_access(CPUARMState *env,
1074 const ARMCPRegInfo *ri)
1075 {
1076 return gt_counter_access(env, GTIMER_PHYS);
1077 }
1078
1079 static CPAccessResult gt_vct_access(CPUARMState *env,
1080 const ARMCPRegInfo *ri)
1081 {
1082 return gt_counter_access(env, GTIMER_VIRT);
1083 }
1084
1085 static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri)
1086 {
1087 return gt_timer_access(env, GTIMER_PHYS);
1088 }
1089
1090 static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri)
1091 {
1092 return gt_timer_access(env, GTIMER_VIRT);
1093 }
1094
1095 static uint64_t gt_get_countervalue(CPUARMState *env)
1096 {
1097 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE;
1098 }
1099
1100 static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
1101 {
1102 ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
1103
1104 if (gt->ctl & 1) {
1105 /* Timer enabled: calculate and set current ISTATUS, irq, and
1106 * reset timer to when ISTATUS next has to change
1107 */
1108 uint64_t count = gt_get_countervalue(&cpu->env);
1109 /* Note that this must be unsigned 64 bit arithmetic: */
1110 int istatus = count >= gt->cval;
1111 uint64_t nexttick;
1112
1113 gt->ctl = deposit32(gt->ctl, 2, 1, istatus);
1114 qemu_set_irq(cpu->gt_timer_outputs[timeridx],
1115 (istatus && !(gt->ctl & 2)));
1116 if (istatus) {
1117 /* Next transition is when count rolls back over to zero */
1118 nexttick = UINT64_MAX;
1119 } else {
1120 /* Next transition is when we hit cval */
1121 nexttick = gt->cval;
1122 }
1123 /* Note that the desired next expiry time might be beyond the
1124 * signed-64-bit range of a QEMUTimer -- in this case we just
1125 * set the timer for as far in the future as possible. When the
1126 * timer expires we will reset the timer for any remaining period.
1127 */
1128 if (nexttick > INT64_MAX / GTIMER_SCALE) {
1129 nexttick = INT64_MAX / GTIMER_SCALE;
1130 }
1131 timer_mod(cpu->gt_timer[timeridx], nexttick);
1132 } else {
1133 /* Timer disabled: ISTATUS and timer output always clear */
1134 gt->ctl &= ~4;
1135 qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0);
1136 timer_del(cpu->gt_timer[timeridx]);
1137 }
1138 }
1139
1140 static void gt_cnt_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1141 {
1142 ARMCPU *cpu = arm_env_get_cpu(env);
1143 int timeridx = ri->opc1 & 1;
1144
1145 timer_del(cpu->gt_timer[timeridx]);
1146 }
1147
1148 static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
1149 {
1150 return gt_get_countervalue(env);
1151 }
1152
1153 static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1154 uint64_t value)
1155 {
1156 int timeridx = ri->opc1 & 1;
1157
1158 env->cp15.c14_timer[timeridx].cval = value;
1159 gt_recalc_timer(arm_env_get_cpu(env), timeridx);
1160 }
1161
1162 static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1163 {
1164 int timeridx = ri->crm & 1;
1165
1166 return (uint32_t)(env->cp15.c14_timer[timeridx].cval -
1167 gt_get_countervalue(env));
1168 }
1169
1170 static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1171 uint64_t value)
1172 {
1173 int timeridx = ri->crm & 1;
1174
1175 env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) +
1176 + sextract64(value, 0, 32);
1177 gt_recalc_timer(arm_env_get_cpu(env), timeridx);
1178 }
1179
1180 static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1181 uint64_t value)
1182 {
1183 ARMCPU *cpu = arm_env_get_cpu(env);
1184 int timeridx = ri->crm & 1;
1185 uint32_t oldval = env->cp15.c14_timer[timeridx].ctl;
1186
1187 env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value);
1188 if ((oldval ^ value) & 1) {
1189 /* Enable toggled */
1190 gt_recalc_timer(cpu, timeridx);
1191 } else if ((oldval ^ value) & 2) {
1192 /* IMASK toggled: don't need to recalculate,
1193 * just set the interrupt line based on ISTATUS
1194 */
1195 qemu_set_irq(cpu->gt_timer_outputs[timeridx],
1196 (oldval & 4) && !(value & 2));
1197 }
1198 }
1199
1200 void arm_gt_ptimer_cb(void *opaque)
1201 {
1202 ARMCPU *cpu = opaque;
1203
1204 gt_recalc_timer(cpu, GTIMER_PHYS);
1205 }
1206
1207 void arm_gt_vtimer_cb(void *opaque)
1208 {
1209 ARMCPU *cpu = opaque;
1210
1211 gt_recalc_timer(cpu, GTIMER_VIRT);
1212 }
1213
1214 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1215 /* Note that CNTFRQ is purely reads-as-written for the benefit
1216 * of software; writing it doesn't actually change the timer frequency.
1217 * Our reset value matches the fixed frequency we implement the timer at.
1218 */
1219 { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0,
1220 .type = ARM_CP_NO_MIGRATE,
1221 .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
1222 .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq),
1223 .resetfn = arm_cp_reset_ignore,
1224 },
1225 { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64,
1226 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0,
1227 .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
1228 .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq),
1229 .resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE,
1230 },
1231 /* overall control: mostly access permissions */
1232 { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH,
1233 .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0,
1234 .access = PL1_RW,
1235 .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl),
1236 .resetvalue = 0,
1237 },
1238 /* per-timer control */
1239 { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
1240 .type = ARM_CP_IO | ARM_CP_NO_MIGRATE, .access = PL1_RW | PL0_R,
1241 .accessfn = gt_ptimer_access,
1242 .fieldoffset = offsetoflow32(CPUARMState,
1243 cp15.c14_timer[GTIMER_PHYS].ctl),
1244 .resetfn = arm_cp_reset_ignore,
1245 .writefn = gt_ctl_write, .raw_writefn = raw_write,
1246 },
1247 { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64,
1248 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1,
1249 .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1250 .accessfn = gt_ptimer_access,
1251 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
1252 .resetvalue = 0,
1253 .writefn = gt_ctl_write, .raw_writefn = raw_write,
1254 },
1255 { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1,
1256 .type = ARM_CP_IO | ARM_CP_NO_MIGRATE, .access = PL1_RW | PL0_R,
1257 .accessfn = gt_vtimer_access,
1258 .fieldoffset = offsetoflow32(CPUARMState,
1259 cp15.c14_timer[GTIMER_VIRT].ctl),
1260 .resetfn = arm_cp_reset_ignore,
1261 .writefn = gt_ctl_write, .raw_writefn = raw_write,
1262 },
1263 { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64,
1264 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1,
1265 .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1266 .accessfn = gt_vtimer_access,
1267 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
1268 .resetvalue = 0,
1269 .writefn = gt_ctl_write, .raw_writefn = raw_write,
1270 },
1271 /* TimerValue views: a 32 bit downcounting view of the underlying state */
1272 { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
1273 .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
1274 .accessfn = gt_ptimer_access,
1275 .readfn = gt_tval_read, .writefn = gt_tval_write,
1276 },
1277 { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64,
1278 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0,
1279 .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
1280 .readfn = gt_tval_read, .writefn = gt_tval_write,
1281 },
1282 { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0,
1283 .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
1284 .accessfn = gt_vtimer_access,
1285 .readfn = gt_tval_read, .writefn = gt_tval_write,
1286 },
1287 { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64,
1288 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0,
1289 .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
1290 .readfn = gt_tval_read, .writefn = gt_tval_write,
1291 },
1292 /* The counter itself */
1293 { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0,
1294 .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO,
1295 .accessfn = gt_pct_access,
1296 .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
1297 },
1298 { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64,
1299 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1,
1300 .access = PL0_R, .type = ARM_CP_NO_MIGRATE | ARM_CP_IO,
1301 .accessfn = gt_pct_access,
1302 .readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
1303 },
1304 { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1,
1305 .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO,
1306 .accessfn = gt_vct_access,
1307 .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
1308 },
1309 { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64,
1310 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2,
1311 .access = PL0_R, .type = ARM_CP_NO_MIGRATE | ARM_CP_IO,
1312 .accessfn = gt_vct_access,
1313 .readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
1314 },
1315 /* Comparison value, indicating when the timer goes off */
1316 { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2,
1317 .access = PL1_RW | PL0_R,
1318 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_MIGRATE,
1319 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1320 .accessfn = gt_ptimer_access, .resetfn = arm_cp_reset_ignore,
1321 .writefn = gt_cval_write, .raw_writefn = raw_write,
1322 },
1323 { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64,
1324 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2,
1325 .access = PL1_RW | PL0_R,
1326 .type = ARM_CP_IO,
1327 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1328 .resetvalue = 0, .accessfn = gt_vtimer_access,
1329 .writefn = gt_cval_write, .raw_writefn = raw_write,
1330 },
1331 { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3,
1332 .access = PL1_RW | PL0_R,
1333 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_MIGRATE,
1334 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1335 .accessfn = gt_vtimer_access, .resetfn = arm_cp_reset_ignore,
1336 .writefn = gt_cval_write, .raw_writefn = raw_write,
1337 },
1338 { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64,
1339 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2,
1340 .access = PL1_RW | PL0_R,
1341 .type = ARM_CP_IO,
1342 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1343 .resetvalue = 0, .accessfn = gt_vtimer_access,
1344 .writefn = gt_cval_write, .raw_writefn = raw_write,
1345 },
1346 REGINFO_SENTINEL
1347 };
1348
1349 #else
1350 /* In user-mode none of the generic timer registers are accessible,
1351 * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs,
1352 * so instead just don't register any of them.
1353 */
1354 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1355 REGINFO_SENTINEL
1356 };
1357
1358 #endif
1359
1360 static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1361 {
1362 if (arm_feature(env, ARM_FEATURE_LPAE)) {
1363 raw_write(env, ri, value);
1364 } else if (arm_feature(env, ARM_FEATURE_V7)) {
1365 raw_write(env, ri, value & 0xfffff6ff);
1366 } else {
1367 raw_write(env, ri, value & 0xfffff1ff);
1368 }
1369 }
1370
1371 #ifndef CONFIG_USER_ONLY
1372 /* get_phys_addr() isn't present for user-mode-only targets */
1373
1374 static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri)
1375 {
1376 if (ri->opc2 & 4) {
1377 /* Other states are only available with TrustZone; in
1378 * a non-TZ implementation these registers don't exist
1379 * at all, which is an Uncategorized trap. This underdecoding
1380 * is safe because the reginfo is NO_MIGRATE.
1381 */
1382 return CP_ACCESS_TRAP_UNCATEGORIZED;
1383 }
1384 return CP_ACCESS_OK;
1385 }
1386
1387 static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1388 {
1389 hwaddr phys_addr;
1390 target_ulong page_size;
1391 int prot;
1392 int ret, is_user = ri->opc2 & 2;
1393 int access_type = ri->opc2 & 1;
1394
1395 ret = get_phys_addr(env, value, access_type, is_user,
1396 &phys_addr, &prot, &page_size);
1397 if (extended_addresses_enabled(env)) {
1398 /* ret is a DFSR/IFSR value for the long descriptor
1399 * translation table format, but with WnR always clear.
1400 * Convert it to a 64-bit PAR.
1401 */
1402 uint64_t par64 = (1 << 11); /* LPAE bit always set */
1403 if (ret == 0) {
1404 par64 |= phys_addr & ~0xfffULL;
1405 /* We don't set the ATTR or SH fields in the PAR. */
1406 } else {
1407 par64 |= 1; /* F */
1408 par64 |= (ret & 0x3f) << 1; /* FS */
1409 /* Note that S2WLK and FSTAGE are always zero, because we don't
1410 * implement virtualization and therefore there can't be a stage 2
1411 * fault.
1412 */
1413 }
1414 env->cp15.par_el1 = par64;
1415 } else {
1416 /* ret is a DFSR/IFSR value for the short descriptor
1417 * translation table format (with WnR always clear).
1418 * Convert it to a 32-bit PAR.
1419 */
1420 if (ret == 0) {
1421 /* We do not set any attribute bits in the PAR */
1422 if (page_size == (1 << 24)
1423 && arm_feature(env, ARM_FEATURE_V7)) {
1424 env->cp15.par_el1 = (phys_addr & 0xff000000) | 1 << 1;
1425 } else {
1426 env->cp15.par_el1 = phys_addr & 0xfffff000;
1427 }
1428 } else {
1429 env->cp15.par_el1 = ((ret & (1 << 10)) >> 5) |
1430 ((ret & (1 << 12)) >> 6) |
1431 ((ret & 0xf) << 1) | 1;
1432 }
1433 }
1434 }
1435 #endif
1436
1437 static const ARMCPRegInfo vapa_cp_reginfo[] = {
1438 { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
1439 .access = PL1_RW, .resetvalue = 0,
1440 .fieldoffset = offsetoflow32(CPUARMState, cp15.par_el1),
1441 .writefn = par_write },
1442 #ifndef CONFIG_USER_ONLY
1443 { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
1444 .access = PL1_W, .accessfn = ats_access,
1445 .writefn = ats_write, .type = ARM_CP_NO_MIGRATE },
1446 #endif
1447 REGINFO_SENTINEL
1448 };
1449
1450 /* Return basic MPU access permission bits. */
1451 static uint32_t simple_mpu_ap_bits(uint32_t val)
1452 {
1453 uint32_t ret;
1454 uint32_t mask;
1455 int i;
1456 ret = 0;
1457 mask = 3;
1458 for (i = 0; i < 16; i += 2) {
1459 ret |= (val >> i) & mask;
1460 mask <<= 2;
1461 }
1462 return ret;
1463 }
1464
1465 /* Pad basic MPU access permission bits to extended format. */
1466 static uint32_t extended_mpu_ap_bits(uint32_t val)
1467 {
1468 uint32_t ret;
1469 uint32_t mask;
1470 int i;
1471 ret = 0;
1472 mask = 3;
1473 for (i = 0; i < 16; i += 2) {
1474 ret |= (val & mask) << i;
1475 mask <<= 2;
1476 }
1477 return ret;
1478 }
1479
1480 static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
1481 uint64_t value)
1482 {
1483 env->cp15.pmsav5_data_ap = extended_mpu_ap_bits(value);
1484 }
1485
1486 static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
1487 {
1488 return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap);
1489 }
1490
1491 static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
1492 uint64_t value)
1493 {
1494 env->cp15.pmsav5_insn_ap = extended_mpu_ap_bits(value);
1495 }
1496
1497 static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
1498 {
1499 return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap);
1500 }
1501
1502 static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
1503 { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
1504 .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
1505 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
1506 .resetvalue = 0,
1507 .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
1508 { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
1509 .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
1510 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
1511 .resetvalue = 0,
1512 .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
1513 { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
1514 .access = PL1_RW,
1515 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
1516 .resetvalue = 0, },
1517 { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
1518 .access = PL1_RW,
1519 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
1520 .resetvalue = 0, },
1521 { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
1522 .access = PL1_RW,
1523 .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
1524 { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
1525 .access = PL1_RW,
1526 .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
1527 /* Protection region base and size registers */
1528 { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0,
1529 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1530 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) },
1531 { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0,
1532 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1533 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) },
1534 { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0,
1535 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1536 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) },
1537 { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0,
1538 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1539 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) },
1540 { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0,
1541 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1542 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) },
1543 { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0,
1544 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1545 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) },
1546 { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0,
1547 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1548 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) },
1549 { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0,
1550 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1551 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) },
1552 REGINFO_SENTINEL
1553 };
1554
1555 static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
1556 uint64_t value)
1557 {
1558 int maskshift = extract32(value, 0, 3);
1559
1560 if (!arm_feature(env, ARM_FEATURE_V8)) {
1561 if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) {
1562 /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
1563 * using Long-desciptor translation table format */
1564 value &= ~((7 << 19) | (3 << 14) | (0xf << 3));
1565 } else if (arm_feature(env, ARM_FEATURE_EL3)) {
1566 /* In an implementation that includes the Security Extensions
1567 * TTBCR has additional fields PD0 [4] and PD1 [5] for
1568 * Short-descriptor translation table format.
1569 */
1570 value &= TTBCR_PD1 | TTBCR_PD0 | TTBCR_N;
1571 } else {
1572 value &= TTBCR_N;
1573 }
1574 }
1575
1576 /* Note that we always calculate c2_mask and c2_base_mask, but
1577 * they are only used for short-descriptor tables (ie if EAE is 0);
1578 * for long-descriptor tables the TTBCR fields are used differently
1579 * and the c2_mask and c2_base_mask values are meaningless.
1580 */
1581 raw_write(env, ri, value);
1582 env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> maskshift);
1583 env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> maskshift);
1584 }
1585
1586 static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1587 uint64_t value)
1588 {
1589 ARMCPU *cpu = arm_env_get_cpu(env);
1590
1591 if (arm_feature(env, ARM_FEATURE_LPAE)) {
1592 /* With LPAE the TTBCR could result in a change of ASID
1593 * via the TTBCR.A1 bit, so do a TLB flush.
1594 */
1595 tlb_flush(CPU(cpu), 1);
1596 }
1597 vmsa_ttbcr_raw_write(env, ri, value);
1598 }
1599
1600 static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1601 {
1602 env->cp15.c2_base_mask = 0xffffc000u;
1603 raw_write(env, ri, 0);
1604 env->cp15.c2_mask = 0;
1605 }
1606
1607 static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
1608 uint64_t value)
1609 {
1610 ARMCPU *cpu = arm_env_get_cpu(env);
1611
1612 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
1613 tlb_flush(CPU(cpu), 1);
1614 raw_write(env, ri, value);
1615 }
1616
1617 static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1618 uint64_t value)
1619 {
1620 /* 64 bit accesses to the TTBRs can change the ASID and so we
1621 * must flush the TLB.
1622 */
1623 if (cpreg_field_is_64bit(ri)) {
1624 ARMCPU *cpu = arm_env_get_cpu(env);
1625
1626 tlb_flush(CPU(cpu), 1);
1627 }
1628 raw_write(env, ri, value);
1629 }
1630
1631 static const ARMCPRegInfo vmsa_cp_reginfo[] = {
1632 { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
1633 .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
1634 .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]),
1635 .resetfn = arm_cp_reset_ignore, },
1636 { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
1637 .access = PL1_RW,
1638 .fieldoffset = offsetof(CPUARMState, cp15.ifsr_el2), .resetvalue = 0, },
1639 { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64,
1640 .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0,
1641 .access = PL1_RW,
1642 .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, },
1643 { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
1644 .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
1645 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el1),
1646 .writefn = vmsa_ttbr_write, .resetvalue = 0 },
1647 { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH,
1648 .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
1649 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el1),
1650 .writefn = vmsa_ttbr_write, .resetvalue = 0 },
1651 { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64,
1652 .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
1653 .access = PL1_RW, .writefn = vmsa_tcr_el1_write,
1654 .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
1655 .fieldoffset = offsetof(CPUARMState, cp15.c2_control) },
1656 { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
1657 .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, .writefn = vmsa_ttbcr_write,
1658 .resetfn = arm_cp_reset_ignore, .raw_writefn = vmsa_ttbcr_raw_write,
1659 .fieldoffset = offsetoflow32(CPUARMState, cp15.c2_control) },
1660 /* 64-bit FAR; this entry also gives us the AArch32 DFAR */
1661 { .name = "FAR_EL1", .state = ARM_CP_STATE_BOTH,
1662 .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
1663 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]),
1664 .resetvalue = 0, },
1665 REGINFO_SENTINEL
1666 };
1667
1668 static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
1669 uint64_t value)
1670 {
1671 env->cp15.c15_ticonfig = value & 0xe7;
1672 /* The OS_TYPE bit in this register changes the reported CPUID! */
1673 env->cp15.c0_cpuid = (value & (1 << 5)) ?
1674 ARM_CPUID_TI915T : ARM_CPUID_TI925T;
1675 }
1676
1677 static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,
1678 uint64_t value)
1679 {
1680 env->cp15.c15_threadid = value & 0xffff;
1681 }
1682
1683 static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
1684 uint64_t value)
1685 {
1686 /* Wait-for-interrupt (deprecated) */
1687 cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT);
1688 }
1689
1690 static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
1691 uint64_t value)
1692 {
1693 /* On OMAP there are registers indicating the max/min index of dcache lines
1694 * containing a dirty line; cache flush operations have to reset these.
1695 */
1696 env->cp15.c15_i_max = 0x000;
1697 env->cp15.c15_i_min = 0xff0;
1698 }
1699
1700 static const ARMCPRegInfo omap_cp_reginfo[] = {
1701 { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
1702 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
1703 .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]),
1704 .resetvalue = 0, },
1705 { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
1706 .access = PL1_RW, .type = ARM_CP_NOP },
1707 { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
1708 .access = PL1_RW,
1709 .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
1710 .writefn = omap_ticonfig_write },
1711 { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,
1712 .access = PL1_RW,
1713 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
1714 { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
1715 .access = PL1_RW, .resetvalue = 0xff0,
1716 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },
1717 { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,
1718 .access = PL1_RW,
1719 .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
1720 .writefn = omap_threadid_write },
1721 { .name = "TI925T_STATUS", .cp = 15, .crn = 15,
1722 .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
1723 .type = ARM_CP_NO_MIGRATE,
1724 .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
1725 /* TODO: Peripheral port remap register:
1726 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
1727 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
1728 * when MMU is off.
1729 */
1730 { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
1731 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
1732 .type = ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE,
1733 .writefn = omap_cachemaint_write },
1734 { .name = "C9", .cp = 15, .crn = 9,
1735 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
1736 .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
1737 REGINFO_SENTINEL
1738 };
1739
1740 static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
1741 uint64_t value)
1742 {
1743 env->cp15.c15_cpar = value & 0x3fff;
1744 }
1745
1746 static const ARMCPRegInfo xscale_cp_reginfo[] = {
1747 { .name = "XSCALE_CPAR",
1748 .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
1749 .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
1750 .writefn = xscale_cpar_write, },
1751 { .name = "XSCALE_AUXCR",
1752 .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
1753 .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
1754 .resetvalue = 0, },
1755 /* XScale specific cache-lockdown: since we have no cache we NOP these
1756 * and hope the guest does not really rely on cache behaviour.
1757 */
1758 { .name = "XSCALE_LOCK_ICACHE_LINE",
1759 .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
1760 .access = PL1_W, .type = ARM_CP_NOP },
1761 { .name = "XSCALE_UNLOCK_ICACHE",
1762 .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
1763 .access = PL1_W, .type = ARM_CP_NOP },
1764 { .name = "XSCALE_DCACHE_LOCK",
1765 .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 0,
1766 .access = PL1_RW, .type = ARM_CP_NOP },
1767 { .name = "XSCALE_UNLOCK_DCACHE",
1768 .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1,
1769 .access = PL1_W, .type = ARM_CP_NOP },
1770 REGINFO_SENTINEL
1771 };
1772
1773 static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
1774 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
1775 * implementation of this implementation-defined space.
1776 * Ideally this should eventually disappear in favour of actually
1777 * implementing the correct behaviour for all cores.
1778 */
1779 { .name = "C15_IMPDEF", .cp = 15, .crn = 15,
1780 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
1781 .access = PL1_RW,
1782 .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE | ARM_CP_OVERRIDE,
1783 .resetvalue = 0 },
1784 REGINFO_SENTINEL
1785 };
1786
1787 static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
1788 /* Cache status: RAZ because we have no cache so it's always clean */
1789 { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
1790 .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1791 .resetvalue = 0 },
1792 REGINFO_SENTINEL
1793 };
1794
1795 static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
1796 /* We never have a a block transfer operation in progress */
1797 { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
1798 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1799 .resetvalue = 0 },
1800 /* The cache ops themselves: these all NOP for QEMU */
1801 { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
1802 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1803 { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
1804 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1805 { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
1806 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1807 { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
1808 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1809 { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
1810 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1811 { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
1812 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1813 REGINFO_SENTINEL
1814 };
1815
1816 static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
1817 /* The cache test-and-clean instructions always return (1 << 30)
1818 * to indicate that there are no dirty cache lines.
1819 */
1820 { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
1821 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1822 .resetvalue = (1 << 30) },
1823 { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
1824 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1825 .resetvalue = (1 << 30) },
1826 REGINFO_SENTINEL
1827 };
1828
1829 static const ARMCPRegInfo strongarm_cp_reginfo[] = {
1830 /* Ignore ReadBuffer accesses */
1831 { .name = "C9_READBUFFER", .cp = 15, .crn = 9,
1832 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
1833 .access = PL1_RW, .resetvalue = 0,
1834 .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE },
1835 REGINFO_SENTINEL
1836 };
1837
1838 static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1839 {
1840 CPUState *cs = CPU(arm_env_get_cpu(env));
1841 uint32_t mpidr = cs->cpu_index;
1842 /* We don't support setting cluster ID ([8..11]) (known as Aff1
1843 * in later ARM ARM versions), or any of the higher affinity level fields,
1844 * so these bits always RAZ.
1845 */
1846 if (arm_feature(env, ARM_FEATURE_V7MP)) {
1847 mpidr |= (1U << 31);
1848 /* Cores which are uniprocessor (non-coherent)
1849 * but still implement the MP extensions set
1850 * bit 30. (For instance, A9UP.) However we do
1851 * not currently model any of those cores.
1852 */
1853 }
1854 return mpidr;
1855 }
1856
1857 static const ARMCPRegInfo mpidr_cp_reginfo[] = {
1858 { .name = "MPIDR", .state = ARM_CP_STATE_BOTH,
1859 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
1860 .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_MIGRATE },
1861 REGINFO_SENTINEL
1862 };
1863
1864 static const ARMCPRegInfo lpae_cp_reginfo[] = {
1865 /* NOP AMAIR0/1: the override is because these clash with the rather
1866 * broadly specified TLB_LOCKDOWN entry in the generic cp_reginfo.
1867 */
1868 { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH,
1869 .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
1870 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
1871 .resetvalue = 0 },
1872 /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
1873 { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
1874 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
1875 .resetvalue = 0 },
1876 { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0,
1877 .access = PL1_RW, .type = ARM_CP_64BIT,
1878 .fieldoffset = offsetof(CPUARMState, cp15.par_el1), .resetvalue = 0 },
1879 { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0,
1880 .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE,
1881 .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el1),
1882 .writefn = vmsa_ttbr_write, .resetfn = arm_cp_reset_ignore },
1883 { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
1884 .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE,
1885 .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el1),
1886 .writefn = vmsa_ttbr_write, .resetfn = arm_cp_reset_ignore },
1887 REGINFO_SENTINEL
1888 };
1889
1890 static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1891 {
1892 return vfp_get_fpcr(env);
1893 }
1894
1895 static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1896 uint64_t value)
1897 {
1898 vfp_set_fpcr(env, value);
1899 }
1900
1901 static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1902 {
1903 return vfp_get_fpsr(env);
1904 }
1905
1906 static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1907 uint64_t value)
1908 {
1909 vfp_set_fpsr(env, value);
1910 }
1911
1912 static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri)
1913 {
1914 if (arm_current_el(env) == 0 && !(env->cp15.c1_sys & SCTLR_UMA)) {
1915 return CP_ACCESS_TRAP;
1916 }
1917 return CP_ACCESS_OK;
1918 }
1919
1920 static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri,
1921 uint64_t value)
1922 {
1923 env->daif = value & PSTATE_DAIF;
1924 }
1925
1926 static CPAccessResult aa64_cacheop_access(CPUARMState *env,
1927 const ARMCPRegInfo *ri)
1928 {
1929 /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless
1930 * SCTLR_EL1.UCI is set.
1931 */
1932 if (arm_current_el(env) == 0 && !(env->cp15.c1_sys & SCTLR_UCI)) {
1933 return CP_ACCESS_TRAP;
1934 }
1935 return CP_ACCESS_OK;
1936 }
1937
1938 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
1939 * Page D4-1736 (DDI0487A.b)
1940 */
1941
1942 static void tlbi_aa64_va_write(CPUARMState *env, const ARMCPRegInfo *ri,
1943 uint64_t value)
1944 {
1945 /* Invalidate by VA (AArch64 version) */
1946 ARMCPU *cpu = arm_env_get_cpu(env);
1947 uint64_t pageaddr = sextract64(value << 12, 0, 56);
1948
1949 tlb_flush_page(CPU(cpu), pageaddr);
1950 }
1951
1952 static void tlbi_aa64_vaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
1953 uint64_t value)
1954 {
1955 /* Invalidate by VA, all ASIDs (AArch64 version) */
1956 ARMCPU *cpu = arm_env_get_cpu(env);
1957 uint64_t pageaddr = sextract64(value << 12, 0, 56);
1958
1959 tlb_flush_page(CPU(cpu), pageaddr);
1960 }
1961
1962 static void tlbi_aa64_asid_write(CPUARMState *env, const ARMCPRegInfo *ri,
1963 uint64_t value)
1964 {
1965 /* Invalidate by ASID (AArch64 version) */
1966 ARMCPU *cpu = arm_env_get_cpu(env);
1967 int asid = extract64(value, 48, 16);
1968 tlb_flush(CPU(cpu), asid == 0);
1969 }
1970
1971 static void tlbi_aa64_va_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
1972 uint64_t value)
1973 {
1974 CPUState *other_cs;
1975 uint64_t pageaddr = sextract64(value << 12, 0, 56);
1976
1977 CPU_FOREACH(other_cs) {
1978 tlb_flush_page(other_cs, pageaddr);
1979 }
1980 }
1981
1982 static void tlbi_aa64_vaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
1983 uint64_t value)
1984 {
1985 CPUState *other_cs;
1986 uint64_t pageaddr = sextract64(value << 12, 0, 56);
1987
1988 CPU_FOREACH(other_cs) {
1989 tlb_flush_page(other_cs, pageaddr);
1990 }
1991 }
1992
1993 static void tlbi_aa64_asid_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
1994 uint64_t value)
1995 {
1996 CPUState *other_cs;
1997 int asid = extract64(value, 48, 16);
1998
1999 CPU_FOREACH(other_cs) {
2000 tlb_flush(other_cs, asid == 0);
2001 }
2002 }
2003
2004 static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri)
2005 {
2006 /* We don't implement EL2, so the only control on DC ZVA is the
2007 * bit in the SCTLR which can prohibit access for EL0.
2008 */
2009 if (arm_current_el(env) == 0 && !(env->cp15.c1_sys & SCTLR_DZE)) {
2010 return CP_ACCESS_TRAP;
2011 }
2012 return CP_ACCESS_OK;
2013 }
2014
2015 static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri)
2016 {
2017 ARMCPU *cpu = arm_env_get_cpu(env);
2018 int dzp_bit = 1 << 4;
2019
2020 /* DZP indicates whether DC ZVA access is allowed */
2021 if (aa64_zva_access(env, NULL) == CP_ACCESS_OK) {
2022 dzp_bit = 0;
2023 }
2024 return cpu->dcz_blocksize | dzp_bit;
2025 }
2026
2027 static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri)
2028 {
2029 if (!(env->pstate & PSTATE_SP)) {
2030 /* Access to SP_EL0 is undefined if it's being used as
2031 * the stack pointer.
2032 */
2033 return CP_ACCESS_TRAP_UNCATEGORIZED;
2034 }
2035 return CP_ACCESS_OK;
2036 }
2037
2038 static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri)
2039 {
2040 return env->pstate & PSTATE_SP;
2041 }
2042
2043 static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
2044 {
2045 update_spsel(env, val);
2046 }
2047
2048 static const ARMCPRegInfo v8_cp_reginfo[] = {
2049 /* Minimal set of EL0-visible registers. This will need to be expanded
2050 * significantly for system emulation of AArch64 CPUs.
2051 */
2052 { .name = "NZCV", .state = ARM_CP_STATE_AA64,
2053 .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2,
2054 .access = PL0_RW, .type = ARM_CP_NZCV },
2055 { .name = "DAIF", .state = ARM_CP_STATE_AA64,
2056 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2,
2057 .type = ARM_CP_NO_MIGRATE,
2058 .access = PL0_RW, .accessfn = aa64_daif_access,
2059 .fieldoffset = offsetof(CPUARMState, daif),
2060 .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore },
2061 { .name = "FPCR", .state = ARM_CP_STATE_AA64,
2062 .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4,
2063 .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write },
2064 { .name = "FPSR", .state = ARM_CP_STATE_AA64,
2065 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4,
2066 .access = PL0_RW, .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write },
2067 { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64,
2068 .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0,
2069 .access = PL0_R, .type = ARM_CP_NO_MIGRATE,
2070 .readfn = aa64_dczid_read },
2071 { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64,
2072 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1,
2073 .access = PL0_W, .type = ARM_CP_DC_ZVA,
2074 #ifndef CONFIG_USER_ONLY
2075 /* Avoid overhead of an access check that always passes in user-mode */
2076 .accessfn = aa64_zva_access,
2077 #endif
2078 },
2079 { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64,
2080 .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2,
2081 .access = PL1_R, .type = ARM_CP_CURRENTEL },
2082 /* Cache ops: all NOPs since we don't emulate caches */
2083 { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64,
2084 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
2085 .access = PL1_W, .type = ARM_CP_NOP },
2086 { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64,
2087 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
2088 .access = PL1_W, .type = ARM_CP_NOP },
2089 { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64,
2090 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1,
2091 .access = PL0_W, .type = ARM_CP_NOP,
2092 .accessfn = aa64_cacheop_access },
2093 { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64,
2094 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
2095 .access = PL1_W, .type = ARM_CP_NOP },
2096 { .name = "DC_ISW", .state = ARM_CP_STATE_AA64,
2097 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
2098 .access = PL1_W, .type = ARM_CP_NOP },
2099 { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64,
2100 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1,
2101 .access = PL0_W, .type = ARM_CP_NOP,
2102 .accessfn = aa64_cacheop_access },
2103 { .name = "DC_CSW", .state = ARM_CP_STATE_AA64,
2104 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
2105 .access = PL1_W, .type = ARM_CP_NOP },
2106 { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64,
2107 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1,
2108 .access = PL0_W, .type = ARM_CP_NOP,
2109 .accessfn = aa64_cacheop_access },
2110 { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64,
2111 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1,
2112 .access = PL0_W, .type = ARM_CP_NOP,
2113 .accessfn = aa64_cacheop_access },
2114 { .name = "DC_CISW", .state = ARM_CP_STATE_AA64,
2115 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
2116 .access = PL1_W, .type = ARM_CP_NOP },
2117 /* TLBI operations */
2118 { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
2119 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
2120 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2121 .writefn = tlbiall_is_write },
2122 { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
2123 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
2124 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2125 .writefn = tlbi_aa64_va_is_write },
2126 { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
2127 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
2128 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2129 .writefn = tlbi_aa64_asid_is_write },
2130 { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
2131 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
2132 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2133 .writefn = tlbi_aa64_vaa_is_write },
2134 { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
2135 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
2136 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2137 .writefn = tlbi_aa64_va_is_write },
2138 { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
2139 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
2140 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2141 .writefn = tlbi_aa64_vaa_is_write },
2142 { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
2143 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
2144 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2145 .writefn = tlbiall_write },
2146 { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64,
2147 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
2148 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2149 .writefn = tlbi_aa64_va_write },
2150 { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64,
2151 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
2152 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2153 .writefn = tlbi_aa64_asid_write },
2154 { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64,
2155 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
2156 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2157 .writefn = tlbi_aa64_vaa_write },
2158 { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64,
2159 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
2160 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2161 .writefn = tlbi_aa64_va_write },
2162 { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64,
2163 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
2164 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2165 .writefn = tlbi_aa64_vaa_write },
2166 #ifndef CONFIG_USER_ONLY
2167 /* 64 bit address translation operations */
2168 { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
2169 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0,
2170 .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write },
2171 { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64,
2172 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1,
2173 .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write },
2174 { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64,
2175 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2,
2176 .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write },
2177 { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64,
2178 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3,
2179 .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write },
2180 #endif
2181 /* TLB invalidate last level of translation table walk */
2182 { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
2183 .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_is_write },
2184 { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
2185 .type = ARM_CP_NO_MIGRATE, .access = PL1_W,
2186 .writefn = tlbimvaa_is_write },
2187 { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
2188 .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write },
2189 { .name = "TLBIMVAAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
2190 .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimvaa_write },
2191 /* 32 bit cache operations */
2192 { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
2193 .type = ARM_CP_NOP, .access = PL1_W },
2194 { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6,
2195 .type = ARM_CP_NOP, .access = PL1_W },
2196 { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
2197 .type = ARM_CP_NOP, .access = PL1_W },
2198 { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1,
2199 .type = ARM_CP_NOP, .access = PL1_W },
2200 { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6,
2201 .type = ARM_CP_NOP, .access = PL1_W },
2202 { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7,
2203 .type = ARM_CP_NOP, .access = PL1_W },
2204 { .name = "DCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
2205 .type = ARM_CP_NOP, .access = PL1_W },
2206 { .name = "DCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
2207 .type = ARM_CP_NOP, .access = PL1_W },
2208 { .name = "DCCMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 1,
2209 .type = ARM_CP_NOP, .access = PL1_W },
2210 { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
2211 .type = ARM_CP_NOP, .access = PL1_W },
2212 { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1,
2213 .type = ARM_CP_NOP, .access = PL1_W },
2214 { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1,
2215 .type = ARM_CP_NOP, .access = PL1_W },
2216 { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
2217 .type = ARM_CP_NOP, .access = PL1_W },
2218 /* MMU Domain access control / MPU write buffer control */
2219 { .name = "DACR", .cp = 15,
2220 .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0,
2221 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3),
2222 .resetvalue = 0, .writefn = dacr_write, .raw_writefn = raw_write, },
2223 { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64,
2224 .type = ARM_CP_NO_MIGRATE,
2225 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1,
2226 .access = PL1_RW,
2227 .fieldoffset = offsetof(CPUARMState, elr_el[1]) },
2228 { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64,
2229 .type = ARM_CP_NO_MIGRATE,
2230 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0,
2231 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[0]) },
2232 /* We rely on the access checks not allowing the guest to write to the
2233 * state field when SPSel indicates that it's being used as the stack
2234 * pointer.
2235 */
2236 { .name = "SP_EL0", .state = ARM_CP_STATE_AA64,
2237 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0,
2238 .access = PL1_RW, .accessfn = sp_el0_access,
2239 .type = ARM_CP_NO_MIGRATE,
2240 .fieldoffset = offsetof(CPUARMState, sp_el[0]) },
2241 { .name = "SPSel", .state = ARM_CP_STATE_AA64,
2242 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0,
2243 .type = ARM_CP_NO_MIGRATE,
2244 .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write },
2245 REGINFO_SENTINEL
2246 };
2247
2248 /* Used to describe the behaviour of EL2 regs when EL2 does not exist. */
2249 static const ARMCPRegInfo v8_el3_no_el2_cp_reginfo[] = {
2250 { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
2251 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
2252 .access = PL2_RW,
2253 .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
2254 { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64,
2255 .type = ARM_CP_NO_MIGRATE,
2256 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
2257 .access = PL2_RW,
2258 .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
2259 REGINFO_SENTINEL
2260 };
2261
2262 static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
2263 {
2264 ARMCPU *cpu = arm_env_get_cpu(env);
2265 uint64_t valid_mask = HCR_MASK;
2266
2267 if (arm_feature(env, ARM_FEATURE_EL3)) {
2268 valid_mask &= ~HCR_HCD;
2269 } else {
2270 valid_mask &= ~HCR_TSC;
2271 }
2272
2273 /* Clear RES0 bits. */
2274 value &= valid_mask;
2275
2276 /* These bits change the MMU setup:
2277 * HCR_VM enables stage 2 translation
2278 * HCR_PTW forbids certain page-table setups
2279 * HCR_DC Disables stage1 and enables stage2 translation
2280 */
2281 if ((raw_read(env, ri) ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) {
2282 tlb_flush(CPU(cpu), 1);
2283 }
2284 raw_write(env, ri, value);
2285 }
2286
2287 static const ARMCPRegInfo v8_el2_cp_reginfo[] = {
2288 { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64,
2289 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
2290 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2),
2291 .writefn = hcr_write },
2292 { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64,
2293 .type = ARM_CP_NO_MIGRATE,
2294 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1,
2295 .access = PL2_RW,
2296 .fieldoffset = offsetof(CPUARMState, elr_el[2]) },
2297 { .name = "ESR_EL2", .state = ARM_CP_STATE_AA64,
2298 .type = ARM_CP_NO_MIGRATE,
2299 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0,
2300 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) },
2301 { .name = "FAR_EL2", .state = ARM_CP_STATE_AA64,
2302 .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0,
2303 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) },
2304 { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64,
2305 .type = ARM_CP_NO_MIGRATE,
2306 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0,
2307 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[6]) },
2308 { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
2309 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
2310 .access = PL2_RW, .writefn = vbar_write,
2311 .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]),
2312 .resetvalue = 0 },
2313 REGINFO_SENTINEL
2314 };
2315
2316 static const ARMCPRegInfo v8_el3_cp_reginfo[] = {
2317 { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64,
2318 .type = ARM_CP_NO_MIGRATE,
2319 .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1,
2320 .access = PL3_RW,
2321 .fieldoffset = offsetof(CPUARMState, elr_el[3]) },
2322 { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64,
2323 .type = ARM_CP_NO_MIGRATE,
2324 .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0,
2325 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) },
2326 { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64,
2327 .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0,
2328 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) },
2329 { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64,
2330 .type = ARM_CP_NO_MIGRATE,
2331 .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0,
2332 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[7]) },
2333 { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64,
2334 .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0,
2335 .access = PL3_RW, .writefn = vbar_write,
2336 .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]),
2337 .resetvalue = 0 },
2338 { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64,
2339 .type = ARM_CP_NO_MIGRATE,
2340 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0,
2341 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3),
2342 .writefn = scr_write },
2343 REGINFO_SENTINEL
2344 };
2345
2346 static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2347 uint64_t value)
2348 {
2349 ARMCPU *cpu = arm_env_get_cpu(env);
2350
2351 if (raw_read(env, ri) == value) {
2352 /* Skip the TLB flush if nothing actually changed; Linux likes
2353 * to do a lot of pointless SCTLR writes.
2354 */
2355 return;
2356 }
2357
2358 raw_write(env, ri, value);
2359 /* ??? Lots of these bits are not implemented. */
2360 /* This may enable/disable the MMU, so do a TLB flush. */
2361 tlb_flush(CPU(cpu), 1);
2362 }
2363
2364 static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri)
2365 {
2366 /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64,
2367 * but the AArch32 CTR has its own reginfo struct)
2368 */
2369 if (arm_current_el(env) == 0 && !(env->cp15.c1_sys & SCTLR_UCT)) {
2370 return CP_ACCESS_TRAP;
2371 }
2372 return CP_ACCESS_OK;
2373 }
2374
2375 static const ARMCPRegInfo debug_cp_reginfo[] = {
2376 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
2377 * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1;
2378 * unlike DBGDRAR it is never accessible from EL0.
2379 * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64
2380 * accessor.
2381 */
2382 { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
2383 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2384 { .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64,
2385 .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
2386 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2387 { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
2388 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2389 /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */
2390 { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH,
2391 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
2392 .access = PL1_RW,
2393 .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1),
2394 .resetvalue = 0 },
2395 /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1.
2396 * We don't implement the configurable EL0 access.
2397 */
2398 { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_BOTH,
2399 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
2400 .type = ARM_CP_NO_MIGRATE,
2401 .access = PL1_R,
2402 .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1),
2403 .resetfn = arm_cp_reset_ignore },
2404 /* We define a dummy WI OSLAR_EL1, because Linux writes to it. */
2405 { .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH,
2406 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
2407 .access = PL1_W, .type = ARM_CP_NOP },
2408 /* Dummy OSDLR_EL1: 32-bit Linux will read this */
2409 { .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH,
2410 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4,
2411 .access = PL1_RW, .type = ARM_CP_NOP },
2412 /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't
2413 * implement vector catch debug events yet.
2414 */
2415 { .name = "DBGVCR",
2416 .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
2417 .access = PL1_RW, .type = ARM_CP_NOP },
2418 REGINFO_SENTINEL
2419 };
2420
2421 static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
2422 /* 64 bit access versions of the (dummy) debug registers */
2423 { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
2424 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
2425 { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
2426 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
2427 REGINFO_SENTINEL
2428 };
2429
2430 void hw_watchpoint_update(ARMCPU *cpu, int n)
2431 {
2432 CPUARMState *env = &cpu->env;
2433 vaddr len = 0;
2434 vaddr wvr = env->cp15.dbgwvr[n];
2435 uint64_t wcr = env->cp15.dbgwcr[n];
2436 int mask;
2437 int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
2438
2439 if (env->cpu_watchpoint[n]) {
2440 cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]);
2441 env->cpu_watchpoint[n] = NULL;
2442 }
2443
2444 if (!extract64(wcr, 0, 1)) {
2445 /* E bit clear : watchpoint disabled */
2446 return;
2447 }
2448
2449 switch (extract64(wcr, 3, 2)) {
2450 case 0:
2451 /* LSC 00 is reserved and must behave as if the wp is disabled */
2452 return;
2453 case 1:
2454 flags |= BP_MEM_READ;
2455 break;
2456 case 2:
2457 flags |= BP_MEM_WRITE;
2458 break;
2459 case 3:
2460 flags |= BP_MEM_ACCESS;
2461 break;
2462 }
2463
2464 /* Attempts to use both MASK and BAS fields simultaneously are
2465 * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
2466 * thus generating a watchpoint for every byte in the masked region.
2467 */
2468 mask = extract64(wcr, 24, 4);
2469 if (mask == 1 || mask == 2) {
2470 /* Reserved values of MASK; we must act as if the mask value was
2471 * some non-reserved value, or as if the watchpoint were disabled.
2472 * We choose the latter.
2473 */
2474 return;
2475 } else if (mask) {
2476 /* Watchpoint covers an aligned area up to 2GB in size */
2477 len = 1ULL << mask;
2478 /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE
2479 * whether the watchpoint fires when the unmasked bits match; we opt
2480 * to generate the exceptions.
2481 */
2482 wvr &= ~(len - 1);
2483 } else {
2484 /* Watchpoint covers bytes defined by the byte address select bits */
2485 int bas = extract64(wcr, 5, 8);
2486 int basstart;
2487
2488 if (bas == 0) {
2489 /* This must act as if the watchpoint is disabled */
2490 return;
2491 }
2492
2493 if (extract64(wvr, 2, 1)) {
2494 /* Deprecated case of an only 4-aligned address. BAS[7:4] are
2495 * ignored, and BAS[3:0] define which bytes to watch.
2496 */
2497 bas &= 0xf;
2498 }
2499 /* The BAS bits are supposed to be programmed to indicate a contiguous
2500 * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether
2501 * we fire for each byte in the word/doubleword addressed by the WVR.
2502 * We choose to ignore any non-zero bits after the first range of 1s.
2503 */
2504 basstart = ctz32(bas);
2505 len = cto32(bas >> basstart);
2506 wvr += basstart;
2507 }
2508
2509 cpu_watchpoint_insert(CPU(cpu), wvr, len, flags,
2510 &env->cpu_watchpoint[n]);
2511 }
2512
2513 void hw_watchpoint_update_all(ARMCPU *cpu)
2514 {
2515 int i;
2516 CPUARMState *env = &cpu->env;
2517
2518 /* Completely clear out existing QEMU watchpoints and our array, to
2519 * avoid possible stale entries following migration load.
2520 */
2521 cpu_watchpoint_remove_all(CPU(cpu), BP_CPU);
2522 memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint));
2523
2524 for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) {
2525 hw_watchpoint_update(cpu, i);
2526 }
2527 }
2528
2529 static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2530 uint64_t value)
2531 {
2532 ARMCPU *cpu = arm_env_get_cpu(env);
2533 int i = ri->crm;
2534
2535 /* Bits [63:49] are hardwired to the value of bit [48]; that is, the
2536 * register reads and behaves as if values written are sign extended.
2537 * Bits [1:0] are RES0.
2538 */
2539 value = sextract64(value, 0, 49) & ~3ULL;
2540
2541 raw_write(env, ri, value);
2542 hw_watchpoint_update(cpu, i);
2543 }
2544
2545 static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2546 uint64_t value)
2547 {
2548 ARMCPU *cpu = arm_env_get_cpu(env);
2549 int i = ri->crm;
2550
2551 raw_write(env, ri, value);
2552 hw_watchpoint_update(cpu, i);
2553 }
2554
2555 void hw_breakpoint_update(ARMCPU *cpu, int n)
2556 {
2557 CPUARMState *env = &cpu->env;
2558 uint64_t bvr = env->cp15.dbgbvr[n];
2559 uint64_t bcr = env->cp15.dbgbcr[n];
2560 vaddr addr;
2561 int bt;
2562 int flags = BP_CPU;
2563
2564 if (env->cpu_breakpoint[n]) {
2565 cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]);
2566 env->cpu_breakpoint[n] = NULL;
2567 }
2568
2569 if (!extract64(bcr, 0, 1)) {
2570 /* E bit clear : watchpoint disabled */
2571 return;
2572 }
2573
2574 bt = extract64(bcr, 20, 4);
2575
2576 switch (bt) {
2577 case 4: /* unlinked address mismatch (reserved if AArch64) */
2578 case 5: /* linked address mismatch (reserved if AArch64) */
2579 qemu_log_mask(LOG_UNIMP,
2580 "arm: address mismatch breakpoint types not implemented");
2581 return;
2582 case 0: /* unlinked address match */
2583 case 1: /* linked address match */
2584 {
2585 /* Bits [63:49] are hardwired to the value of bit [48]; that is,
2586 * we behave as if the register was sign extended. Bits [1:0] are
2587 * RES0. The BAS field is used to allow setting breakpoints on 16
2588 * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether
2589 * a bp will fire if the addresses covered by the bp and the addresses
2590 * covered by the insn overlap but the insn doesn't start at the
2591 * start of the bp address range. We choose to require the insn and
2592 * the bp to have the same address. The constraints on writing to
2593 * BAS enforced in dbgbcr_write mean we have only four cases:
2594 * 0b0000 => no breakpoint
2595 * 0b0011 => breakpoint on addr
2596 * 0b1100 => breakpoint on addr + 2
2597 * 0b1111 => breakpoint on addr
2598 * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
2599 */
2600 int bas = extract64(bcr, 5, 4);
2601 addr = sextract64(bvr, 0, 49) & ~3ULL;
2602 if (bas == 0) {
2603 return;
2604 }
2605 if (bas == 0xc) {
2606 addr += 2;
2607 }
2608 break;
2609 }
2610 case 2: /* unlinked context ID match */
2611 case 8: /* unlinked VMID match (reserved if no EL2) */
2612 case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
2613 qemu_log_mask(LOG_UNIMP,
2614 "arm: unlinked context breakpoint types not implemented");
2615 return;
2616 case 9: /* linked VMID match (reserved if no EL2) */
2617 case 11: /* linked context ID and VMID match (reserved if no EL2) */
2618 case 3: /* linked context ID match */
2619 default:
2620 /* We must generate no events for Linked context matches (unless
2621 * they are linked to by some other bp/wp, which is handled in
2622 * updates for the linking bp/wp). We choose to also generate no events
2623 * for reserved values.
2624 */
2625 return;
2626 }
2627
2628 cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]);
2629 }
2630
2631 void hw_breakpoint_update_all(ARMCPU *cpu)
2632 {
2633 int i;
2634 CPUARMState *env = &cpu->env;
2635
2636 /* Completely clear out existing QEMU breakpoints and our array, to
2637 * avoid possible stale entries following migration load.
2638 */
2639 cpu_breakpoint_remove_all(CPU(cpu), BP_CPU);
2640 memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint));
2641
2642 for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) {
2643 hw_breakpoint_update(cpu, i);
2644 }
2645 }
2646
2647 static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2648 uint64_t value)
2649 {
2650 ARMCPU *cpu = arm_env_get_cpu(env);
2651 int i = ri->crm;
2652
2653 raw_write(env, ri, value);
2654 hw_breakpoint_update(cpu, i);
2655 }
2656
2657 static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2658 uint64_t value)
2659 {
2660 ARMCPU *cpu = arm_env_get_cpu(env);
2661 int i = ri->crm;
2662
2663 /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only
2664 * copy of BAS[0].
2665 */
2666 value = deposit64(value, 6, 1, extract64(value, 5, 1));
2667 value = deposit64(value, 8, 1, extract64(value, 7, 1));
2668
2669 raw_write(env, ri, value);
2670 hw_breakpoint_update(cpu, i);
2671 }
2672
2673 static void define_debug_regs(ARMCPU *cpu)
2674 {
2675 /* Define v7 and v8 architectural debug registers.
2676 * These are just dummy implementations for now.
2677 */
2678 int i;
2679 int wrps, brps, ctx_cmps;
2680 ARMCPRegInfo dbgdidr = {
2681 .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
2682 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = cpu->dbgdidr,
2683 };
2684
2685 /* Note that all these register fields hold "number of Xs minus 1". */
2686 brps = extract32(cpu->dbgdidr, 24, 4);
2687 wrps = extract32(cpu->dbgdidr, 28, 4);
2688 ctx_cmps = extract32(cpu->dbgdidr, 20, 4);
2689
2690 assert(ctx_cmps <= brps);
2691
2692 /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties
2693 * of the debug registers such as number of breakpoints;
2694 * check that if they both exist then they agree.
2695 */
2696 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
2697 assert(extract32(cpu->id_aa64dfr0, 12, 4) == brps);
2698 assert(extract32(cpu->id_aa64dfr0, 20, 4) == wrps);
2699 assert(extract32(cpu->id_aa64dfr0, 28, 4) == ctx_cmps);
2700 }
2701
2702 define_one_arm_cp_reg(cpu, &dbgdidr);
2703 define_arm_cp_regs(cpu, debug_cp_reginfo);
2704
2705 if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) {
2706 define_arm_cp_regs(cpu, debug_lpae_cp_reginfo);
2707 }
2708
2709 for (i = 0; i < brps + 1; i++) {
2710 ARMCPRegInfo dbgregs[] = {
2711 { .name = "DBGBVR", .state = ARM_CP_STATE_BOTH,
2712 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4,
2713 .access = PL1_RW,
2714 .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]),
2715 .writefn = dbgbvr_write, .raw_writefn = raw_write
2716 },
2717 { .name = "DBGBCR", .state = ARM_CP_STATE_BOTH,
2718 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5,
2719 .access = PL1_RW,
2720 .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]),
2721 .writefn = dbgbcr_write, .raw_writefn = raw_write
2722 },
2723 REGINFO_SENTINEL
2724 };
2725 define_arm_cp_regs(cpu, dbgregs);
2726 }
2727
2728 for (i = 0; i < wrps + 1; i++) {
2729 ARMCPRegInfo dbgregs[] = {
2730 { .name = "DBGWVR", .state = ARM_CP_STATE_BOTH,
2731 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6,
2732 .access = PL1_RW,
2733 .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]),
2734 .writefn = dbgwvr_write, .raw_writefn = raw_write
2735 },
2736 { .name = "DBGWCR", .state = ARM_CP_STATE_BOTH,
2737 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7,
2738 .access = PL1_RW,
2739 .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]),
2740 .writefn = dbgwcr_write, .raw_writefn = raw_write
2741 },
2742 REGINFO_SENTINEL
2743 };
2744 define_arm_cp_regs(cpu, dbgregs);
2745 }
2746 }
2747
2748 void register_cp_regs_for_features(ARMCPU *cpu)
2749 {
2750 /* Register all the coprocessor registers based on feature bits */
2751 CPUARMState *env = &cpu->env;
2752 if (arm_feature(env, ARM_FEATURE_M)) {
2753 /* M profile has no coprocessor registers */
2754 return;
2755 }
2756
2757 define_arm_cp_regs(cpu, cp_reginfo);
2758 if (!arm_feature(env, ARM_FEATURE_V8)) {
2759 /* Must go early as it is full of wildcards that may be
2760 * overridden by later definitions.
2761 */
2762 define_arm_cp_regs(cpu, not_v8_cp_reginfo);
2763 }
2764
2765 if (arm_feature(env, ARM_FEATURE_V6)) {
2766 /* The ID registers all have impdef reset values */
2767 ARMCPRegInfo v6_idregs[] = {
2768 { .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH,
2769 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
2770 .access = PL1_R, .type = ARM_CP_CONST,
2771 .resetvalue = cpu->id_pfr0 },
2772 { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH,
2773 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1,
2774 .access = PL1_R, .type = ARM_CP_CONST,
2775 .resetvalue = cpu->id_pfr1 },
2776 { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH,
2777 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
2778 .access = PL1_R, .type = ARM_CP_CONST,
2779 .resetvalue = cpu->id_dfr0 },
2780 { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH,
2781 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3,
2782 .access = PL1_R, .type = ARM_CP_CONST,
2783 .resetvalue = cpu->id_afr0 },
2784 { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH,
2785 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4,
2786 .access = PL1_R, .type = ARM_CP_CONST,
2787 .resetvalue = cpu->id_mmfr0 },
2788 { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH,
2789 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5,
2790 .access = PL1_R, .type = ARM_CP_CONST,
2791 .resetvalue = cpu->id_mmfr1 },
2792 { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH,
2793 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6,
2794 .access = PL1_R, .type = ARM_CP_CONST,
2795 .resetvalue = cpu->id_mmfr2 },
2796 { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH,
2797 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7,
2798 .access = PL1_R, .type = ARM_CP_CONST,
2799 .resetvalue = cpu->id_mmfr3 },
2800 { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH,
2801 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
2802 .access = PL1_R, .type = ARM_CP_CONST,
2803 .resetvalue = cpu->id_isar0 },
2804 { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH,
2805 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1,
2806 .access = PL1_R, .type = ARM_CP_CONST,
2807 .resetvalue = cpu->id_isar1 },
2808 { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH,
2809 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
2810 .access = PL1_R, .type = ARM_CP_CONST,
2811 .resetvalue = cpu->id_isar2 },
2812 { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH,
2813 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3,
2814 .access = PL1_R, .type = ARM_CP_CONST,
2815 .resetvalue = cpu->id_isar3 },
2816 { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH,
2817 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4,
2818 .access = PL1_R, .type = ARM_CP_CONST,
2819 .resetvalue = cpu->id_isar4 },
2820 { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH,
2821 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5,
2822 .access = PL1_R, .type = ARM_CP_CONST,
2823 .resetvalue = cpu->id_isar5 },
2824 /* 6..7 are as yet unallocated and must RAZ */
2825 { .name = "ID_ISAR6", .cp = 15, .crn = 0, .crm = 2,
2826 .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
2827 .resetvalue = 0 },
2828 { .name = "ID_ISAR7", .cp = 15, .crn = 0, .crm = 2,
2829 .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
2830 .resetvalue = 0 },
2831 REGINFO_SENTINEL
2832 };
2833 define_arm_cp_regs(cpu, v6_idregs);
2834 define_arm_cp_regs(cpu, v6_cp_reginfo);
2835 } else {
2836 define_arm_cp_regs(cpu, not_v6_cp_reginfo);
2837 }
2838