cpu: Factor out cpu_generic_init()
[qemu.git] / target-arm / helper.c
1 #include "cpu.h"
2 #include "exec/gdbstub.h"
3 #include "helper.h"
4 #include "qemu/host-utils.h"
5 #include "sysemu/arch_init.h"
6 #include "sysemu/sysemu.h"
7 #include "qemu/bitops.h"
8 #include "qemu/crc32c.h"
9 #include <zlib.h> /* For crc32 */
10
11 #ifndef CONFIG_USER_ONLY
12 static inline int get_phys_addr(CPUARMState *env, uint32_t address,
13 int access_type, int is_user,
14 hwaddr *phys_ptr, int *prot,
15 target_ulong *page_size);
16
17 /* Definitions for the PMCCNTR and PMCR registers */
18 #define PMCRD 0x8
19 #define PMCRC 0x4
20 #define PMCRE 0x1
21 #endif
22
23 static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
24 {
25 int nregs;
26
27 /* VFP data registers are always little-endian. */
28 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
29 if (reg < nregs) {
30 stfq_le_p(buf, env->vfp.regs[reg]);
31 return 8;
32 }
33 if (arm_feature(env, ARM_FEATURE_NEON)) {
34 /* Aliases for Q regs. */
35 nregs += 16;
36 if (reg < nregs) {
37 stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
38 stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
39 return 16;
40 }
41 }
42 switch (reg - nregs) {
43 case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
44 case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
45 case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
46 }
47 return 0;
48 }
49
50 static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
51 {
52 int nregs;
53
54 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
55 if (reg < nregs) {
56 env->vfp.regs[reg] = ldfq_le_p(buf);
57 return 8;
58 }
59 if (arm_feature(env, ARM_FEATURE_NEON)) {
60 nregs += 16;
61 if (reg < nregs) {
62 env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
63 env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
64 return 16;
65 }
66 }
67 switch (reg - nregs) {
68 case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
69 case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
70 case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
71 }
72 return 0;
73 }
74
75 static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
76 {
77 switch (reg) {
78 case 0 ... 31:
79 /* 128 bit FP register */
80 stfq_le_p(buf, env->vfp.regs[reg * 2]);
81 stfq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]);
82 return 16;
83 case 32:
84 /* FPSR */
85 stl_p(buf, vfp_get_fpsr(env));
86 return 4;
87 case 33:
88 /* FPCR */
89 stl_p(buf, vfp_get_fpcr(env));
90 return 4;
91 default:
92 return 0;
93 }
94 }
95
96 static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
97 {
98 switch (reg) {
99 case 0 ... 31:
100 /* 128 bit FP register */
101 env->vfp.regs[reg * 2] = ldfq_le_p(buf);
102 env->vfp.regs[reg * 2 + 1] = ldfq_le_p(buf + 8);
103 return 16;
104 case 32:
105 /* FPSR */
106 vfp_set_fpsr(env, ldl_p(buf));
107 return 4;
108 case 33:
109 /* FPCR */
110 vfp_set_fpcr(env, ldl_p(buf));
111 return 4;
112 default:
113 return 0;
114 }
115 }
116
117 static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri)
118 {
119 if (cpreg_field_is_64bit(ri)) {
120 return CPREG_FIELD64(env, ri);
121 } else {
122 return CPREG_FIELD32(env, ri);
123 }
124 }
125
126 static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
127 uint64_t value)
128 {
129 if (cpreg_field_is_64bit(ri)) {
130 CPREG_FIELD64(env, ri) = value;
131 } else {
132 CPREG_FIELD32(env, ri) = value;
133 }
134 }
135
136 static uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri)
137 {
138 /* Raw read of a coprocessor register (as needed for migration, etc). */
139 if (ri->type & ARM_CP_CONST) {
140 return ri->resetvalue;
141 } else if (ri->raw_readfn) {
142 return ri->raw_readfn(env, ri);
143 } else if (ri->readfn) {
144 return ri->readfn(env, ri);
145 } else {
146 return raw_read(env, ri);
147 }
148 }
149
150 static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
151 uint64_t v)
152 {
153 /* Raw write of a coprocessor register (as needed for migration, etc).
154 * Note that constant registers are treated as write-ignored; the
155 * caller should check for success by whether a readback gives the
156 * value written.
157 */
158 if (ri->type & ARM_CP_CONST) {
159 return;
160 } else if (ri->raw_writefn) {
161 ri->raw_writefn(env, ri, v);
162 } else if (ri->writefn) {
163 ri->writefn(env, ri, v);
164 } else {
165 raw_write(env, ri, v);
166 }
167 }
168
169 bool write_cpustate_to_list(ARMCPU *cpu)
170 {
171 /* Write the coprocessor state from cpu->env to the (index,value) list. */
172 int i;
173 bool ok = true;
174
175 for (i = 0; i < cpu->cpreg_array_len; i++) {
176 uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
177 const ARMCPRegInfo *ri;
178
179 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
180 if (!ri) {
181 ok = false;
182 continue;
183 }
184 if (ri->type & ARM_CP_NO_MIGRATE) {
185 continue;
186 }
187 cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri);
188 }
189 return ok;
190 }
191
192 bool write_list_to_cpustate(ARMCPU *cpu)
193 {
194 int i;
195 bool ok = true;
196
197 for (i = 0; i < cpu->cpreg_array_len; i++) {
198 uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
199 uint64_t v = cpu->cpreg_values[i];
200 const ARMCPRegInfo *ri;
201
202 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
203 if (!ri) {
204 ok = false;
205 continue;
206 }
207 if (ri->type & ARM_CP_NO_MIGRATE) {
208 continue;
209 }
210 /* Write value and confirm it reads back as written
211 * (to catch read-only registers and partially read-only
212 * registers where the incoming migration value doesn't match)
213 */
214 write_raw_cp_reg(&cpu->env, ri, v);
215 if (read_raw_cp_reg(&cpu->env, ri) != v) {
216 ok = false;
217 }
218 }
219 return ok;
220 }
221
222 static void add_cpreg_to_list(gpointer key, gpointer opaque)
223 {
224 ARMCPU *cpu = opaque;
225 uint64_t regidx;
226 const ARMCPRegInfo *ri;
227
228 regidx = *(uint32_t *)key;
229 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
230
231 if (!(ri->type & ARM_CP_NO_MIGRATE)) {
232 cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
233 /* The value array need not be initialized at this point */
234 cpu->cpreg_array_len++;
235 }
236 }
237
238 static void count_cpreg(gpointer key, gpointer opaque)
239 {
240 ARMCPU *cpu = opaque;
241 uint64_t regidx;
242 const ARMCPRegInfo *ri;
243
244 regidx = *(uint32_t *)key;
245 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
246
247 if (!(ri->type & ARM_CP_NO_MIGRATE)) {
248 cpu->cpreg_array_len++;
249 }
250 }
251
252 static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
253 {
254 uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a);
255 uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b);
256
257 if (aidx > bidx) {
258 return 1;
259 }
260 if (aidx < bidx) {
261 return -1;
262 }
263 return 0;
264 }
265
266 static void cpreg_make_keylist(gpointer key, gpointer value, gpointer udata)
267 {
268 GList **plist = udata;
269
270 *plist = g_list_prepend(*plist, key);
271 }
272
273 void init_cpreg_list(ARMCPU *cpu)
274 {
275 /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
276 * Note that we require cpreg_tuples[] to be sorted by key ID.
277 */
278 GList *keys = NULL;
279 int arraylen;
280
281 g_hash_table_foreach(cpu->cp_regs, cpreg_make_keylist, &keys);
282
283 keys = g_list_sort(keys, cpreg_key_compare);
284
285 cpu->cpreg_array_len = 0;
286
287 g_list_foreach(keys, count_cpreg, cpu);
288
289 arraylen = cpu->cpreg_array_len;
290 cpu->cpreg_indexes = g_new(uint64_t, arraylen);
291 cpu->cpreg_values = g_new(uint64_t, arraylen);
292 cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen);
293 cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen);
294 cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
295 cpu->cpreg_array_len = 0;
296
297 g_list_foreach(keys, add_cpreg_to_list, cpu);
298
299 assert(cpu->cpreg_array_len == arraylen);
300
301 g_list_free(keys);
302 }
303
304 static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
305 {
306 env->cp15.c3 = value;
307 tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */
308 }
309
310 static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
311 {
312 if (env->cp15.c13_fcse != value) {
313 /* Unlike real hardware the qemu TLB uses virtual addresses,
314 * not modified virtual addresses, so this causes a TLB flush.
315 */
316 tlb_flush(env, 1);
317 env->cp15.c13_fcse = value;
318 }
319 }
320
321 static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
322 uint64_t value)
323 {
324 if (env->cp15.c13_context != value && !arm_feature(env, ARM_FEATURE_MPU)) {
325 /* For VMSA (when not using the LPAE long descriptor page table
326 * format) this register includes the ASID, so do a TLB flush.
327 * For PMSA it is purely a process ID and no action is needed.
328 */
329 tlb_flush(env, 1);
330 }
331 env->cp15.c13_context = value;
332 }
333
334 static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
335 uint64_t value)
336 {
337 /* Invalidate all (TLBIALL) */
338 tlb_flush(env, 1);
339 }
340
341 static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
342 uint64_t value)
343 {
344 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
345 tlb_flush_page(env, value & TARGET_PAGE_MASK);
346 }
347
348 static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
349 uint64_t value)
350 {
351 /* Invalidate by ASID (TLBIASID) */
352 tlb_flush(env, value == 0);
353 }
354
355 static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
356 uint64_t value)
357 {
358 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
359 tlb_flush_page(env, value & TARGET_PAGE_MASK);
360 }
361
362 static const ARMCPRegInfo cp_reginfo[] = {
363 /* DBGDIDR: just RAZ. In particular this means the "debug architecture
364 * version" bits will read as a reserved value, which should cause
365 * Linux to not try to use the debug hardware.
366 */
367 { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
368 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
369 /* MMU Domain access control / MPU write buffer control */
370 { .name = "DACR", .cp = 15,
371 .crn = 3, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
372 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3),
373 .resetvalue = 0, .writefn = dacr_write, .raw_writefn = raw_write, },
374 { .name = "FCSEIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 0,
375 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
376 .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
377 { .name = "CONTEXTIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 1,
378 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_context),
379 .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
380 /* ??? This covers not just the impdef TLB lockdown registers but also
381 * some v7VMSA registers relating to TEX remap, so it is overly broad.
382 */
383 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = CP_ANY,
384 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
385 /* MMU TLB control. Note that the wildcarding means we cover not just
386 * the unified TLB ops but also the dside/iside/inner-shareable variants.
387 */
388 { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
389 .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write,
390 .type = ARM_CP_NO_MIGRATE },
391 { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY,
392 .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write,
393 .type = ARM_CP_NO_MIGRATE },
394 { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY,
395 .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write,
396 .type = ARM_CP_NO_MIGRATE },
397 { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY,
398 .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write,
399 .type = ARM_CP_NO_MIGRATE },
400 /* Cache maintenance ops; some of this space may be overridden later. */
401 { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
402 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
403 .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
404 REGINFO_SENTINEL
405 };
406
407 static const ARMCPRegInfo not_v6_cp_reginfo[] = {
408 /* Not all pre-v6 cores implemented this WFI, so this is slightly
409 * over-broad.
410 */
411 { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
412 .access = PL1_W, .type = ARM_CP_WFI },
413 REGINFO_SENTINEL
414 };
415
416 static const ARMCPRegInfo not_v7_cp_reginfo[] = {
417 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
418 * is UNPREDICTABLE; we choose to NOP as most implementations do).
419 */
420 { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
421 .access = PL1_W, .type = ARM_CP_WFI },
422 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
423 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
424 * OMAPCP will override this space.
425 */
426 { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0,
427 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data),
428 .resetvalue = 0 },
429 { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1,
430 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn),
431 .resetvalue = 0 },
432 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
433 { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
434 .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
435 .resetvalue = 0 },
436 REGINFO_SENTINEL
437 };
438
439 static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
440 uint64_t value)
441 {
442 if (env->cp15.c1_coproc != value) {
443 env->cp15.c1_coproc = value;
444 /* ??? Is this safe when called from within a TB? */
445 tb_flush(env);
446 }
447 }
448
449 static const ARMCPRegInfo v6_cp_reginfo[] = {
450 /* prefetch by MVA in v6, NOP in v7 */
451 { .name = "MVA_prefetch",
452 .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
453 .access = PL1_W, .type = ARM_CP_NOP },
454 { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
455 .access = PL0_W, .type = ARM_CP_NOP },
456 { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
457 .access = PL0_W, .type = ARM_CP_NOP },
458 { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
459 .access = PL0_W, .type = ARM_CP_NOP },
460 { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
461 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_insn),
462 .resetvalue = 0, },
463 /* Watchpoint Fault Address Register : should actually only be present
464 * for 1136, 1176, 11MPCore.
465 */
466 { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
467 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
468 { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
469 .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2,
470 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_coproc),
471 .resetvalue = 0, .writefn = cpacr_write },
472 REGINFO_SENTINEL
473 };
474
475 static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri)
476 {
477 /* Perfomance monitor registers user accessibility is controlled
478 * by PMUSERENR.
479 */
480 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
481 return CP_ACCESS_TRAP;
482 }
483 return CP_ACCESS_OK;
484 }
485
486 #ifndef CONFIG_USER_ONLY
487 static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
488 uint64_t value)
489 {
490 /* Don't computer the number of ticks in user mode */
491 uint32_t temp_ticks;
492
493 temp_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) *
494 get_ticks_per_sec() / 1000000;
495
496 if (env->cp15.c9_pmcr & PMCRE) {
497 /* If the counter is enabled */
498 if (env->cp15.c9_pmcr & PMCRD) {
499 /* Increment once every 64 processor clock cycles */
500 env->cp15.c15_ccnt = (temp_ticks/64) - env->cp15.c15_ccnt;
501 } else {
502 env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
503 }
504 }
505
506 if (value & PMCRC) {
507 /* The counter has been reset */
508 env->cp15.c15_ccnt = 0;
509 }
510
511 /* only the DP, X, D and E bits are writable */
512 env->cp15.c9_pmcr &= ~0x39;
513 env->cp15.c9_pmcr |= (value & 0x39);
514
515 if (env->cp15.c9_pmcr & PMCRE) {
516 if (env->cp15.c9_pmcr & PMCRD) {
517 /* Increment once every 64 processor clock cycles */
518 temp_ticks /= 64;
519 }
520 env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
521 }
522 }
523
524 static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
525 {
526 uint32_t total_ticks;
527
528 if (!(env->cp15.c9_pmcr & PMCRE)) {
529 /* Counter is disabled, do not change value */
530 return env->cp15.c15_ccnt;
531 }
532
533 total_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) *
534 get_ticks_per_sec() / 1000000;
535
536 if (env->cp15.c9_pmcr & PMCRD) {
537 /* Increment once every 64 processor clock cycles */
538 total_ticks /= 64;
539 }
540 return total_ticks - env->cp15.c15_ccnt;
541 }
542
543 static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
544 uint64_t value)
545 {
546 uint32_t total_ticks;
547
548 if (!(env->cp15.c9_pmcr & PMCRE)) {
549 /* Counter is disabled, set the absolute value */
550 env->cp15.c15_ccnt = value;
551 return;
552 }
553
554 total_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) *
555 get_ticks_per_sec() / 1000000;
556
557 if (env->cp15.c9_pmcr & PMCRD) {
558 /* Increment once every 64 processor clock cycles */
559 total_ticks /= 64;
560 }
561 env->cp15.c15_ccnt = total_ticks - value;
562 }
563 #endif
564
565 static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
566 uint64_t value)
567 {
568 value &= (1 << 31);
569 env->cp15.c9_pmcnten |= value;
570 }
571
572 static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
573 uint64_t value)
574 {
575 value &= (1 << 31);
576 env->cp15.c9_pmcnten &= ~value;
577 }
578
579 static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
580 uint64_t value)
581 {
582 env->cp15.c9_pmovsr &= ~value;
583 }
584
585 static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
586 uint64_t value)
587 {
588 env->cp15.c9_pmxevtyper = value & 0xff;
589 }
590
591 static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
592 uint64_t value)
593 {
594 env->cp15.c9_pmuserenr = value & 1;
595 }
596
597 static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
598 uint64_t value)
599 {
600 /* We have no event counters so only the C bit can be changed */
601 value &= (1 << 31);
602 env->cp15.c9_pminten |= value;
603 }
604
605 static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
606 uint64_t value)
607 {
608 value &= (1 << 31);
609 env->cp15.c9_pminten &= ~value;
610 }
611
612 static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
613 uint64_t value)
614 {
615 /* Note that even though the AArch64 view of this register has bits
616 * [10:0] all RES0 we can only mask the bottom 5, to comply with the
617 * architectural requirements for bits which are RES0 only in some
618 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
619 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
620 */
621 env->cp15.c12_vbar = value & ~0x1Ful;
622 }
623
624 static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
625 {
626 ARMCPU *cpu = arm_env_get_cpu(env);
627 return cpu->ccsidr[env->cp15.c0_cssel];
628 }
629
630 static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
631 uint64_t value)
632 {
633 env->cp15.c0_cssel = value & 0xf;
634 }
635
636 static const ARMCPRegInfo v7_cp_reginfo[] = {
637 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
638 * debug components
639 */
640 { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
641 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
642 { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
643 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
644 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
645 { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
646 .access = PL1_W, .type = ARM_CP_NOP },
647 /* Performance monitors are implementation defined in v7,
648 * but with an ARM recommended set of registers, which we
649 * follow (although we don't actually implement any counters)
650 *
651 * Performance registers fall into three categories:
652 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
653 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
654 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
655 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
656 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
657 */
658 { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
659 .access = PL0_RW, .resetvalue = 0,
660 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
661 .writefn = pmcntenset_write,
662 .accessfn = pmreg_access,
663 .raw_writefn = raw_write },
664 { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
665 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
666 .accessfn = pmreg_access,
667 .writefn = pmcntenclr_write,
668 .type = ARM_CP_NO_MIGRATE },
669 { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
670 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
671 .accessfn = pmreg_access,
672 .writefn = pmovsr_write,
673 .raw_writefn = raw_write },
674 /* Unimplemented so WI. */
675 { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
676 .access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP },
677 /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
678 * We choose to RAZ/WI.
679 */
680 { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
681 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
682 .accessfn = pmreg_access },
683 #ifndef CONFIG_USER_ONLY
684 { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
685 .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO,
686 .readfn = pmccntr_read, .writefn = pmccntr_write,
687 .accessfn = pmreg_access },
688 #endif
689 { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
690 .access = PL0_RW,
691 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
692 .accessfn = pmreg_access, .writefn = pmxevtyper_write,
693 .raw_writefn = raw_write },
694 /* Unimplemented, RAZ/WI. */
695 { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
696 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
697 .accessfn = pmreg_access },
698 { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
699 .access = PL0_R | PL1_RW,
700 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
701 .resetvalue = 0,
702 .writefn = pmuserenr_write, .raw_writefn = raw_write },
703 { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
704 .access = PL1_RW,
705 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
706 .resetvalue = 0,
707 .writefn = pmintenset_write, .raw_writefn = raw_write },
708 { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
709 .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
710 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
711 .resetvalue = 0, .writefn = pmintenclr_write, },
712 { .name = "VBAR", .state = ARM_CP_STATE_BOTH,
713 .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
714 .access = PL1_RW, .writefn = vbar_write,
715 .fieldoffset = offsetof(CPUARMState, cp15.c12_vbar),
716 .resetvalue = 0 },
717 { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
718 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr),
719 .resetvalue = 0, },
720 { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
721 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
722 .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE },
723 { .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
724 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
725 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c0_cssel),
726 .writefn = csselr_write, .resetvalue = 0 },
727 /* Auxiliary ID register: this actually has an IMPDEF value but for now
728 * just RAZ for all cores:
729 */
730 { .name = "AIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 7,
731 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
732 /* MAIR can just read-as-written because we don't implement caches
733 * and so don't need to care about memory attributes.
734 */
735 { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64,
736 .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0,
737 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el1),
738 .resetvalue = 0 },
739 /* For non-long-descriptor page tables these are PRRR and NMRR;
740 * regardless they still act as reads-as-written for QEMU.
741 * The override is necessary because of the overly-broad TLB_LOCKDOWN
742 * definition.
743 */
744 { .name = "MAIR0", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE,
745 .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW,
746 .fieldoffset = offsetoflow32(CPUARMState, cp15.mair_el1),
747 .resetfn = arm_cp_reset_ignore },
748 { .name = "MAIR1", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE,
749 .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW,
750 .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el1),
751 .resetfn = arm_cp_reset_ignore },
752 REGINFO_SENTINEL
753 };
754
755 static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri,
756 uint64_t value)
757 {
758 value &= 1;
759 env->teecr = value;
760 }
761
762 static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri)
763 {
764 if (arm_current_pl(env) == 0 && (env->teecr & 1)) {
765 return CP_ACCESS_TRAP;
766 }
767 return CP_ACCESS_OK;
768 }
769
770 static const ARMCPRegInfo t2ee_cp_reginfo[] = {
771 { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
772 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
773 .resetvalue = 0,
774 .writefn = teecr_write },
775 { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
776 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
777 .accessfn = teehbr_access, .resetvalue = 0 },
778 REGINFO_SENTINEL
779 };
780
781 static const ARMCPRegInfo v6k_cp_reginfo[] = {
782 { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64,
783 .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0,
784 .access = PL0_RW,
785 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el0), .resetvalue = 0 },
786 { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
787 .access = PL0_RW,
788 .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidr_el0),
789 .resetfn = arm_cp_reset_ignore },
790 { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64,
791 .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
792 .access = PL0_R|PL1_W,
793 .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el0), .resetvalue = 0 },
794 { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
795 .access = PL0_R|PL1_W,
796 .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidrro_el0),
797 .resetfn = arm_cp_reset_ignore },
798 { .name = "TPIDR_EL1", .state = ARM_CP_STATE_BOTH,
799 .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0,
800 .access = PL1_RW,
801 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el1), .resetvalue = 0 },
802 REGINFO_SENTINEL
803 };
804
805 #ifndef CONFIG_USER_ONLY
806
807 static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri)
808 {
809 /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero */
810 if (arm_current_pl(env) == 0 && !extract32(env->cp15.c14_cntkctl, 0, 2)) {
811 return CP_ACCESS_TRAP;
812 }
813 return CP_ACCESS_OK;
814 }
815
816 static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx)
817 {
818 /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
819 if (arm_current_pl(env) == 0 &&
820 !extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
821 return CP_ACCESS_TRAP;
822 }
823 return CP_ACCESS_OK;
824 }
825
826 static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx)
827 {
828 /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
829 * EL0[PV]TEN is zero.
830 */
831 if (arm_current_pl(env) == 0 &&
832 !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
833 return CP_ACCESS_TRAP;
834 }
835 return CP_ACCESS_OK;
836 }
837
838 static CPAccessResult gt_pct_access(CPUARMState *env,
839 const ARMCPRegInfo *ri)
840 {
841 return gt_counter_access(env, GTIMER_PHYS);
842 }
843
844 static CPAccessResult gt_vct_access(CPUARMState *env,
845 const ARMCPRegInfo *ri)
846 {
847 return gt_counter_access(env, GTIMER_VIRT);
848 }
849
850 static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri)
851 {
852 return gt_timer_access(env, GTIMER_PHYS);
853 }
854
855 static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri)
856 {
857 return gt_timer_access(env, GTIMER_VIRT);
858 }
859
860 static uint64_t gt_get_countervalue(CPUARMState *env)
861 {
862 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE;
863 }
864
865 static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
866 {
867 ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
868
869 if (gt->ctl & 1) {
870 /* Timer enabled: calculate and set current ISTATUS, irq, and
871 * reset timer to when ISTATUS next has to change
872 */
873 uint64_t count = gt_get_countervalue(&cpu->env);
874 /* Note that this must be unsigned 64 bit arithmetic: */
875 int istatus = count >= gt->cval;
876 uint64_t nexttick;
877
878 gt->ctl = deposit32(gt->ctl, 2, 1, istatus);
879 qemu_set_irq(cpu->gt_timer_outputs[timeridx],
880 (istatus && !(gt->ctl & 2)));
881 if (istatus) {
882 /* Next transition is when count rolls back over to zero */
883 nexttick = UINT64_MAX;
884 } else {
885 /* Next transition is when we hit cval */
886 nexttick = gt->cval;
887 }
888 /* Note that the desired next expiry time might be beyond the
889 * signed-64-bit range of a QEMUTimer -- in this case we just
890 * set the timer for as far in the future as possible. When the
891 * timer expires we will reset the timer for any remaining period.
892 */
893 if (nexttick > INT64_MAX / GTIMER_SCALE) {
894 nexttick = INT64_MAX / GTIMER_SCALE;
895 }
896 timer_mod(cpu->gt_timer[timeridx], nexttick);
897 } else {
898 /* Timer disabled: ISTATUS and timer output always clear */
899 gt->ctl &= ~4;
900 qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0);
901 timer_del(cpu->gt_timer[timeridx]);
902 }
903 }
904
905 static void gt_cnt_reset(CPUARMState *env, const ARMCPRegInfo *ri)
906 {
907 ARMCPU *cpu = arm_env_get_cpu(env);
908 int timeridx = ri->opc1 & 1;
909
910 timer_del(cpu->gt_timer[timeridx]);
911 }
912
913 static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
914 {
915 return gt_get_countervalue(env);
916 }
917
918 static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
919 uint64_t value)
920 {
921 int timeridx = ri->opc1 & 1;
922
923 env->cp15.c14_timer[timeridx].cval = value;
924 gt_recalc_timer(arm_env_get_cpu(env), timeridx);
925 }
926
927 static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
928 {
929 int timeridx = ri->crm & 1;
930
931 return (uint32_t)(env->cp15.c14_timer[timeridx].cval -
932 gt_get_countervalue(env));
933 }
934
935 static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
936 uint64_t value)
937 {
938 int timeridx = ri->crm & 1;
939
940 env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) +
941 + sextract64(value, 0, 32);
942 gt_recalc_timer(arm_env_get_cpu(env), timeridx);
943 }
944
945 static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
946 uint64_t value)
947 {
948 ARMCPU *cpu = arm_env_get_cpu(env);
949 int timeridx = ri->crm & 1;
950 uint32_t oldval = env->cp15.c14_timer[timeridx].ctl;
951
952 env->cp15.c14_timer[timeridx].ctl = value & 3;
953 if ((oldval ^ value) & 1) {
954 /* Enable toggled */
955 gt_recalc_timer(cpu, timeridx);
956 } else if ((oldval & value) & 2) {
957 /* IMASK toggled: don't need to recalculate,
958 * just set the interrupt line based on ISTATUS
959 */
960 qemu_set_irq(cpu->gt_timer_outputs[timeridx],
961 (oldval & 4) && (value & 2));
962 }
963 }
964
965 void arm_gt_ptimer_cb(void *opaque)
966 {
967 ARMCPU *cpu = opaque;
968
969 gt_recalc_timer(cpu, GTIMER_PHYS);
970 }
971
972 void arm_gt_vtimer_cb(void *opaque)
973 {
974 ARMCPU *cpu = opaque;
975
976 gt_recalc_timer(cpu, GTIMER_VIRT);
977 }
978
979 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
980 /* Note that CNTFRQ is purely reads-as-written for the benefit
981 * of software; writing it doesn't actually change the timer frequency.
982 * Our reset value matches the fixed frequency we implement the timer at.
983 */
984 { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0,
985 .type = ARM_CP_NO_MIGRATE,
986 .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
987 .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq),
988 .resetfn = arm_cp_reset_ignore,
989 },
990 { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64,
991 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0,
992 .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
993 .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq),
994 .resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE,
995 },
996 /* overall control: mostly access permissions */
997 { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH,
998 .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0,
999 .access = PL1_RW,
1000 .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl),
1001 .resetvalue = 0,
1002 },
1003 /* per-timer control */
1004 { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
1005 .type = ARM_CP_IO | ARM_CP_NO_MIGRATE, .access = PL1_RW | PL0_R,
1006 .accessfn = gt_ptimer_access,
1007 .fieldoffset = offsetoflow32(CPUARMState,
1008 cp15.c14_timer[GTIMER_PHYS].ctl),
1009 .resetfn = arm_cp_reset_ignore,
1010 .writefn = gt_ctl_write, .raw_writefn = raw_write,
1011 },
1012 { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64,
1013 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1,
1014 .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1015 .accessfn = gt_ptimer_access,
1016 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
1017 .resetvalue = 0,
1018 .writefn = gt_ctl_write, .raw_writefn = raw_write,
1019 },
1020 { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1,
1021 .type = ARM_CP_IO | ARM_CP_NO_MIGRATE, .access = PL1_RW | PL0_R,
1022 .accessfn = gt_vtimer_access,
1023 .fieldoffset = offsetoflow32(CPUARMState,
1024 cp15.c14_timer[GTIMER_VIRT].ctl),
1025 .resetfn = arm_cp_reset_ignore,
1026 .writefn = gt_ctl_write, .raw_writefn = raw_write,
1027 },
1028 { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64,
1029 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1,
1030 .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1031 .accessfn = gt_vtimer_access,
1032 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
1033 .resetvalue = 0,
1034 .writefn = gt_ctl_write, .raw_writefn = raw_write,
1035 },
1036 /* TimerValue views: a 32 bit downcounting view of the underlying state */
1037 { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
1038 .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
1039 .accessfn = gt_ptimer_access,
1040 .readfn = gt_tval_read, .writefn = gt_tval_write,
1041 },
1042 { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64,
1043 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0,
1044 .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
1045 .readfn = gt_tval_read, .writefn = gt_tval_write,
1046 },
1047 { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0,
1048 .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
1049 .accessfn = gt_vtimer_access,
1050 .readfn = gt_tval_read, .writefn = gt_tval_write,
1051 },
1052 { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64,
1053 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0,
1054 .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
1055 .readfn = gt_tval_read, .writefn = gt_tval_write,
1056 },
1057 /* The counter itself */
1058 { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0,
1059 .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO,
1060 .accessfn = gt_pct_access,
1061 .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
1062 },
1063 { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64,
1064 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1,
1065 .access = PL0_R, .type = ARM_CP_NO_MIGRATE | ARM_CP_IO,
1066 .accessfn = gt_pct_access,
1067 .readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
1068 },
1069 { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1,
1070 .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO,
1071 .accessfn = gt_vct_access,
1072 .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
1073 },
1074 { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64,
1075 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2,
1076 .access = PL0_R, .type = ARM_CP_NO_MIGRATE | ARM_CP_IO,
1077 .accessfn = gt_vct_access,
1078 .readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
1079 },
1080 /* Comparison value, indicating when the timer goes off */
1081 { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2,
1082 .access = PL1_RW | PL0_R,
1083 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_MIGRATE,
1084 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1085 .accessfn = gt_ptimer_access, .resetfn = arm_cp_reset_ignore,
1086 .writefn = gt_cval_write, .raw_writefn = raw_write,
1087 },
1088 { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64,
1089 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2,
1090 .access = PL1_RW | PL0_R,
1091 .type = ARM_CP_IO,
1092 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1093 .resetvalue = 0, .accessfn = gt_vtimer_access,
1094 .writefn = gt_cval_write, .raw_writefn = raw_write,
1095 },
1096 { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3,
1097 .access = PL1_RW | PL0_R,
1098 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_MIGRATE,
1099 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1100 .accessfn = gt_vtimer_access, .resetfn = arm_cp_reset_ignore,
1101 .writefn = gt_cval_write, .raw_writefn = raw_write,
1102 },
1103 { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64,
1104 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2,
1105 .access = PL1_RW | PL0_R,
1106 .type = ARM_CP_IO,
1107 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1108 .resetvalue = 0, .accessfn = gt_vtimer_access,
1109 .writefn = gt_cval_write, .raw_writefn = raw_write,
1110 },
1111 REGINFO_SENTINEL
1112 };
1113
1114 #else
1115 /* In user-mode none of the generic timer registers are accessible,
1116 * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs,
1117 * so instead just don't register any of them.
1118 */
1119 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1120 REGINFO_SENTINEL
1121 };
1122
1123 #endif
1124
1125 static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1126 {
1127 if (arm_feature(env, ARM_FEATURE_LPAE)) {
1128 env->cp15.c7_par = value;
1129 } else if (arm_feature(env, ARM_FEATURE_V7)) {
1130 env->cp15.c7_par = value & 0xfffff6ff;
1131 } else {
1132 env->cp15.c7_par = value & 0xfffff1ff;
1133 }
1134 }
1135
1136 #ifndef CONFIG_USER_ONLY
1137 /* get_phys_addr() isn't present for user-mode-only targets */
1138
1139 /* Return true if extended addresses are enabled, ie this is an
1140 * LPAE implementation and we are using the long-descriptor translation
1141 * table format because the TTBCR EAE bit is set.
1142 */
1143 static inline bool extended_addresses_enabled(CPUARMState *env)
1144 {
1145 return arm_feature(env, ARM_FEATURE_LPAE)
1146 && (env->cp15.c2_control & (1U << 31));
1147 }
1148
1149 static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri)
1150 {
1151 if (ri->opc2 & 4) {
1152 /* Other states are only available with TrustZone; in
1153 * a non-TZ implementation these registers don't exist
1154 * at all, which is an Uncategorized trap. This underdecoding
1155 * is safe because the reginfo is NO_MIGRATE.
1156 */
1157 return CP_ACCESS_TRAP_UNCATEGORIZED;
1158 }
1159 return CP_ACCESS_OK;
1160 }
1161
1162 static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1163 {
1164 hwaddr phys_addr;
1165 target_ulong page_size;
1166 int prot;
1167 int ret, is_user = ri->opc2 & 2;
1168 int access_type = ri->opc2 & 1;
1169
1170 ret = get_phys_addr(env, value, access_type, is_user,
1171 &phys_addr, &prot, &page_size);
1172 if (extended_addresses_enabled(env)) {
1173 /* ret is a DFSR/IFSR value for the long descriptor
1174 * translation table format, but with WnR always clear.
1175 * Convert it to a 64-bit PAR.
1176 */
1177 uint64_t par64 = (1 << 11); /* LPAE bit always set */
1178 if (ret == 0) {
1179 par64 |= phys_addr & ~0xfffULL;
1180 /* We don't set the ATTR or SH fields in the PAR. */
1181 } else {
1182 par64 |= 1; /* F */
1183 par64 |= (ret & 0x3f) << 1; /* FS */
1184 /* Note that S2WLK and FSTAGE are always zero, because we don't
1185 * implement virtualization and therefore there can't be a stage 2
1186 * fault.
1187 */
1188 }
1189 env->cp15.c7_par = par64;
1190 env->cp15.c7_par_hi = par64 >> 32;
1191 } else {
1192 /* ret is a DFSR/IFSR value for the short descriptor
1193 * translation table format (with WnR always clear).
1194 * Convert it to a 32-bit PAR.
1195 */
1196 if (ret == 0) {
1197 /* We do not set any attribute bits in the PAR */
1198 if (page_size == (1 << 24)
1199 && arm_feature(env, ARM_FEATURE_V7)) {
1200 env->cp15.c7_par = (phys_addr & 0xff000000) | 1 << 1;
1201 } else {
1202 env->cp15.c7_par = phys_addr & 0xfffff000;
1203 }
1204 } else {
1205 env->cp15.c7_par = ((ret & (1 << 10)) >> 5) |
1206 ((ret & (1 << 12)) >> 6) |
1207 ((ret & 0xf) << 1) | 1;
1208 }
1209 env->cp15.c7_par_hi = 0;
1210 }
1211 }
1212 #endif
1213
1214 static const ARMCPRegInfo vapa_cp_reginfo[] = {
1215 { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
1216 .access = PL1_RW, .resetvalue = 0,
1217 .fieldoffset = offsetof(CPUARMState, cp15.c7_par),
1218 .writefn = par_write },
1219 #ifndef CONFIG_USER_ONLY
1220 { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
1221 .access = PL1_W, .accessfn = ats_access,
1222 .writefn = ats_write, .type = ARM_CP_NO_MIGRATE },
1223 #endif
1224 REGINFO_SENTINEL
1225 };
1226
1227 /* Return basic MPU access permission bits. */
1228 static uint32_t simple_mpu_ap_bits(uint32_t val)
1229 {
1230 uint32_t ret;
1231 uint32_t mask;
1232 int i;
1233 ret = 0;
1234 mask = 3;
1235 for (i = 0; i < 16; i += 2) {
1236 ret |= (val >> i) & mask;
1237 mask <<= 2;
1238 }
1239 return ret;
1240 }
1241
1242 /* Pad basic MPU access permission bits to extended format. */
1243 static uint32_t extended_mpu_ap_bits(uint32_t val)
1244 {
1245 uint32_t ret;
1246 uint32_t mask;
1247 int i;
1248 ret = 0;
1249 mask = 3;
1250 for (i = 0; i < 16; i += 2) {
1251 ret |= (val & mask) << i;
1252 mask <<= 2;
1253 }
1254 return ret;
1255 }
1256
1257 static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
1258 uint64_t value)
1259 {
1260 env->cp15.c5_data = extended_mpu_ap_bits(value);
1261 }
1262
1263 static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
1264 {
1265 return simple_mpu_ap_bits(env->cp15.c5_data);
1266 }
1267
1268 static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
1269 uint64_t value)
1270 {
1271 env->cp15.c5_insn = extended_mpu_ap_bits(value);
1272 }
1273
1274 static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
1275 {
1276 return simple_mpu_ap_bits(env->cp15.c5_insn);
1277 }
1278
1279 static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
1280 { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
1281 .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
1282 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0,
1283 .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
1284 { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
1285 .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
1286 .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0,
1287 .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
1288 { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
1289 .access = PL1_RW,
1290 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
1291 { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
1292 .access = PL1_RW,
1293 .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, },
1294 { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
1295 .access = PL1_RW,
1296 .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
1297 { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
1298 .access = PL1_RW,
1299 .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
1300 /* Protection region base and size registers */
1301 { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0,
1302 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1303 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) },
1304 { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0,
1305 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1306 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) },
1307 { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0,
1308 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1309 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) },
1310 { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0,
1311 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1312 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) },
1313 { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0,
1314 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1315 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) },
1316 { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0,
1317 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1318 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) },
1319 { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0,
1320 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1321 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) },
1322 { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0,
1323 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1324 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) },
1325 REGINFO_SENTINEL
1326 };
1327
1328 static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
1329 uint64_t value)
1330 {
1331 int maskshift = extract32(value, 0, 3);
1332
1333 if (arm_feature(env, ARM_FEATURE_LPAE) && (value & (1 << 31))) {
1334 value &= ~((7 << 19) | (3 << 14) | (0xf << 3));
1335 } else {
1336 value &= 7;
1337 }
1338 /* Note that we always calculate c2_mask and c2_base_mask, but
1339 * they are only used for short-descriptor tables (ie if EAE is 0);
1340 * for long-descriptor tables the TTBCR fields are used differently
1341 * and the c2_mask and c2_base_mask values are meaningless.
1342 */
1343 env->cp15.c2_control = value;
1344 env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> maskshift);
1345 env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> maskshift);
1346 }
1347
1348 static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1349 uint64_t value)
1350 {
1351 if (arm_feature(env, ARM_FEATURE_LPAE)) {
1352 /* With LPAE the TTBCR could result in a change of ASID
1353 * via the TTBCR.A1 bit, so do a TLB flush.
1354 */
1355 tlb_flush(env, 1);
1356 }
1357 vmsa_ttbcr_raw_write(env, ri, value);
1358 }
1359
1360 static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1361 {
1362 env->cp15.c2_base_mask = 0xffffc000u;
1363 env->cp15.c2_control = 0;
1364 env->cp15.c2_mask = 0;
1365 }
1366
1367 static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
1368 uint64_t value)
1369 {
1370 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
1371 tlb_flush(env, 1);
1372 env->cp15.c2_control = value;
1373 }
1374
1375 static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1376 uint64_t value)
1377 {
1378 /* 64 bit accesses to the TTBRs can change the ASID and so we
1379 * must flush the TLB.
1380 */
1381 if (cpreg_field_is_64bit(ri)) {
1382 tlb_flush(env, 1);
1383 }
1384 raw_write(env, ri, value);
1385 }
1386
1387 static const ARMCPRegInfo vmsa_cp_reginfo[] = {
1388 { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
1389 .access = PL1_RW,
1390 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
1391 { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
1392 .access = PL1_RW,
1393 .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, },
1394 { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
1395 .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
1396 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el1),
1397 .writefn = vmsa_ttbr_write, .resetvalue = 0 },
1398 { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH,
1399 .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
1400 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el1),
1401 .writefn = vmsa_ttbr_write, .resetvalue = 0 },
1402 { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64,
1403 .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
1404 .access = PL1_RW, .writefn = vmsa_tcr_el1_write,
1405 .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
1406 .fieldoffset = offsetof(CPUARMState, cp15.c2_control) },
1407 { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
1408 .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, .writefn = vmsa_ttbcr_write,
1409 .resetfn = arm_cp_reset_ignore, .raw_writefn = vmsa_ttbcr_raw_write,
1410 .fieldoffset = offsetoflow32(CPUARMState, cp15.c2_control) },
1411 { .name = "DFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
1412 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_data),
1413 .resetvalue = 0, },
1414 REGINFO_SENTINEL
1415 };
1416
1417 static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
1418 uint64_t value)
1419 {
1420 env->cp15.c15_ticonfig = value & 0xe7;
1421 /* The OS_TYPE bit in this register changes the reported CPUID! */
1422 env->cp15.c0_cpuid = (value & (1 << 5)) ?
1423 ARM_CPUID_TI915T : ARM_CPUID_TI925T;
1424 }
1425
1426 static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,
1427 uint64_t value)
1428 {
1429 env->cp15.c15_threadid = value & 0xffff;
1430 }
1431
1432 static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
1433 uint64_t value)
1434 {
1435 /* Wait-for-interrupt (deprecated) */
1436 cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT);
1437 }
1438
1439 static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
1440 uint64_t value)
1441 {
1442 /* On OMAP there are registers indicating the max/min index of dcache lines
1443 * containing a dirty line; cache flush operations have to reset these.
1444 */
1445 env->cp15.c15_i_max = 0x000;
1446 env->cp15.c15_i_min = 0xff0;
1447 }
1448
1449 static const ARMCPRegInfo omap_cp_reginfo[] = {
1450 { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
1451 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
1452 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
1453 { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
1454 .access = PL1_RW, .type = ARM_CP_NOP },
1455 { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
1456 .access = PL1_RW,
1457 .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
1458 .writefn = omap_ticonfig_write },
1459 { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,
1460 .access = PL1_RW,
1461 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
1462 { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
1463 .access = PL1_RW, .resetvalue = 0xff0,
1464 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },
1465 { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,
1466 .access = PL1_RW,
1467 .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
1468 .writefn = omap_threadid_write },
1469 { .name = "TI925T_STATUS", .cp = 15, .crn = 15,
1470 .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
1471 .type = ARM_CP_NO_MIGRATE,
1472 .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
1473 /* TODO: Peripheral port remap register:
1474 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
1475 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
1476 * when MMU is off.
1477 */
1478 { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
1479 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
1480 .type = ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE,
1481 .writefn = omap_cachemaint_write },
1482 { .name = "C9", .cp = 15, .crn = 9,
1483 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
1484 .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
1485 REGINFO_SENTINEL
1486 };
1487
1488 static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
1489 uint64_t value)
1490 {
1491 value &= 0x3fff;
1492 if (env->cp15.c15_cpar != value) {
1493 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
1494 tb_flush(env);
1495 env->cp15.c15_cpar = value;
1496 }
1497 }
1498
1499 static const ARMCPRegInfo xscale_cp_reginfo[] = {
1500 { .name = "XSCALE_CPAR",
1501 .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
1502 .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
1503 .writefn = xscale_cpar_write, },
1504 { .name = "XSCALE_AUXCR",
1505 .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
1506 .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
1507 .resetvalue = 0, },
1508 REGINFO_SENTINEL
1509 };
1510
1511 static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
1512 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
1513 * implementation of this implementation-defined space.
1514 * Ideally this should eventually disappear in favour of actually
1515 * implementing the correct behaviour for all cores.
1516 */
1517 { .name = "C15_IMPDEF", .cp = 15, .crn = 15,
1518 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
1519 .access = PL1_RW,
1520 .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE | ARM_CP_OVERRIDE,
1521 .resetvalue = 0 },
1522 REGINFO_SENTINEL
1523 };
1524
1525 static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
1526 /* Cache status: RAZ because we have no cache so it's always clean */
1527 { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
1528 .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1529 .resetvalue = 0 },
1530 REGINFO_SENTINEL
1531 };
1532
1533 static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
1534 /* We never have a a block transfer operation in progress */
1535 { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
1536 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1537 .resetvalue = 0 },
1538 /* The cache ops themselves: these all NOP for QEMU */
1539 { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
1540 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1541 { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
1542 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1543 { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
1544 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1545 { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
1546 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1547 { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
1548 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1549 { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
1550 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1551 REGINFO_SENTINEL
1552 };
1553
1554 static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
1555 /* The cache test-and-clean instructions always return (1 << 30)
1556 * to indicate that there are no dirty cache lines.
1557 */
1558 { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
1559 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1560 .resetvalue = (1 << 30) },
1561 { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
1562 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1563 .resetvalue = (1 << 30) },
1564 REGINFO_SENTINEL
1565 };
1566
1567 static const ARMCPRegInfo strongarm_cp_reginfo[] = {
1568 /* Ignore ReadBuffer accesses */
1569 { .name = "C9_READBUFFER", .cp = 15, .crn = 9,
1570 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
1571 .access = PL1_RW, .resetvalue = 0,
1572 .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE },
1573 REGINFO_SENTINEL
1574 };
1575
1576 static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1577 {
1578 CPUState *cs = CPU(arm_env_get_cpu(env));
1579 uint32_t mpidr = cs->cpu_index;
1580 /* We don't support setting cluster ID ([8..11]) (known as Aff1
1581 * in later ARM ARM versions), or any of the higher affinity level fields,
1582 * so these bits always RAZ.
1583 */
1584 if (arm_feature(env, ARM_FEATURE_V7MP)) {
1585 mpidr |= (1U << 31);
1586 /* Cores which are uniprocessor (non-coherent)
1587 * but still implement the MP extensions set
1588 * bit 30. (For instance, A9UP.) However we do
1589 * not currently model any of those cores.
1590 */
1591 }
1592 return mpidr;
1593 }
1594
1595 static const ARMCPRegInfo mpidr_cp_reginfo[] = {
1596 { .name = "MPIDR", .state = ARM_CP_STATE_BOTH,
1597 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
1598 .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_MIGRATE },
1599 REGINFO_SENTINEL
1600 };
1601
1602 static uint64_t par64_read(CPUARMState *env, const ARMCPRegInfo *ri)
1603 {
1604 return ((uint64_t)env->cp15.c7_par_hi << 32) | env->cp15.c7_par;
1605 }
1606
1607 static void par64_write(CPUARMState *env, const ARMCPRegInfo *ri,
1608 uint64_t value)
1609 {
1610 env->cp15.c7_par_hi = value >> 32;
1611 env->cp15.c7_par = value;
1612 }
1613
1614 static void par64_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1615 {
1616 env->cp15.c7_par_hi = 0;
1617 env->cp15.c7_par = 0;
1618 }
1619
1620 static const ARMCPRegInfo lpae_cp_reginfo[] = {
1621 /* NOP AMAIR0/1: the override is because these clash with the rather
1622 * broadly specified TLB_LOCKDOWN entry in the generic cp_reginfo.
1623 */
1624 { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH,
1625 .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
1626 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
1627 .resetvalue = 0 },
1628 /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
1629 { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
1630 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
1631 .resetvalue = 0 },
1632 /* 64 bit access versions of the (dummy) debug registers */
1633 { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
1634 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
1635 { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
1636 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
1637 { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0,
1638 .access = PL1_RW, .type = ARM_CP_64BIT,
1639 .readfn = par64_read, .writefn = par64_write, .resetfn = par64_reset },
1640 { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0,
1641 .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE,
1642 .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el1),
1643 .writefn = vmsa_ttbr_write, .resetfn = arm_cp_reset_ignore },
1644 { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
1645 .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE,
1646 .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el1),
1647 .writefn = vmsa_ttbr_write, .resetfn = arm_cp_reset_ignore },
1648 REGINFO_SENTINEL
1649 };
1650
1651 static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1652 {
1653 return vfp_get_fpcr(env);
1654 }
1655
1656 static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1657 uint64_t value)
1658 {
1659 vfp_set_fpcr(env, value);
1660 }
1661
1662 static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1663 {
1664 return vfp_get_fpsr(env);
1665 }
1666
1667 static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1668 uint64_t value)
1669 {
1670 vfp_set_fpsr(env, value);
1671 }
1672
1673 static CPAccessResult aa64_cacheop_access(CPUARMState *env,
1674 const ARMCPRegInfo *ri)
1675 {
1676 /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless
1677 * SCTLR_EL1.UCI is set.
1678 */
1679 if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UCI)) {
1680 return CP_ACCESS_TRAP;
1681 }
1682 return CP_ACCESS_OK;
1683 }
1684
1685 static void tlbi_aa64_va_write(CPUARMState *env, const ARMCPRegInfo *ri,
1686 uint64_t value)
1687 {
1688 /* Invalidate by VA (AArch64 version) */
1689 uint64_t pageaddr = value << 12;
1690 tlb_flush_page(env, pageaddr);
1691 }
1692
1693 static void tlbi_aa64_vaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
1694 uint64_t value)
1695 {
1696 /* Invalidate by VA, all ASIDs (AArch64 version) */
1697 uint64_t pageaddr = value << 12;
1698 tlb_flush_page(env, pageaddr);
1699 }
1700
1701 static void tlbi_aa64_asid_write(CPUARMState *env, const ARMCPRegInfo *ri,
1702 uint64_t value)
1703 {
1704 /* Invalidate by ASID (AArch64 version) */
1705 int asid = extract64(value, 48, 16);
1706 tlb_flush(env, asid == 0);
1707 }
1708
1709 static const ARMCPRegInfo v8_cp_reginfo[] = {
1710 /* Minimal set of EL0-visible registers. This will need to be expanded
1711 * significantly for system emulation of AArch64 CPUs.
1712 */
1713 { .name = "NZCV", .state = ARM_CP_STATE_AA64,
1714 .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2,
1715 .access = PL0_RW, .type = ARM_CP_NZCV },
1716 { .name = "FPCR", .state = ARM_CP_STATE_AA64,
1717 .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4,
1718 .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write },
1719 { .name = "FPSR", .state = ARM_CP_STATE_AA64,
1720 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4,
1721 .access = PL0_RW, .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write },
1722 /* Prohibit use of DC ZVA. OPTME: implement DC ZVA and allow its use.
1723 * For system mode the DZP bit here will need to be computed, not constant.
1724 */
1725 { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64,
1726 .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0,
1727 .access = PL0_R, .type = ARM_CP_CONST,
1728 .resetvalue = 0x10 },
1729 { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64,
1730 .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2,
1731 .access = PL1_R, .type = ARM_CP_CURRENTEL },
1732 /* Cache ops: all NOPs since we don't emulate caches */
1733 { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64,
1734 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
1735 .access = PL1_W, .type = ARM_CP_NOP },
1736 { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64,
1737 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
1738 .access = PL1_W, .type = ARM_CP_NOP },
1739 { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64,
1740 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1,
1741 .access = PL0_W, .type = ARM_CP_NOP,
1742 .accessfn = aa64_cacheop_access },
1743 { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64,
1744 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
1745 .access = PL1_W, .type = ARM_CP_NOP },
1746 { .name = "DC_ISW", .state = ARM_CP_STATE_AA64,
1747 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
1748 .access = PL1_W, .type = ARM_CP_NOP },
1749 { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64,
1750 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1,
1751 .access = PL0_W, .type = ARM_CP_NOP,
1752 .accessfn = aa64_cacheop_access },
1753 { .name = "DC_CSW", .state = ARM_CP_STATE_AA64,
1754 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
1755 .access = PL1_W, .type = ARM_CP_NOP },
1756 { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64,
1757 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1,
1758 .access = PL0_W, .type = ARM_CP_NOP,
1759 .accessfn = aa64_cacheop_access },
1760 { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64,
1761 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1,
1762 .access = PL0_W, .type = ARM_CP_NOP,
1763 .accessfn = aa64_cacheop_access },
1764 { .name = "DC_CISW", .state = ARM_CP_STATE_AA64,
1765 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
1766 .access = PL1_W, .type = ARM_CP_NOP },
1767 /* TLBI operations */
1768 { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
1769 .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 0,
1770 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1771 .writefn = tlbiall_write },
1772 { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
1773 .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 1,
1774 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1775 .writefn = tlbi_aa64_va_write },
1776 { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
1777 .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 2,
1778 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1779 .writefn = tlbi_aa64_asid_write },
1780 { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
1781 .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 3,
1782 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1783 .writefn = tlbi_aa64_vaa_write },
1784 { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
1785 .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 5,
1786 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1787 .writefn = tlbi_aa64_va_write },
1788 { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
1789 .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 7,
1790 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1791 .writefn = tlbi_aa64_vaa_write },
1792 { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
1793 .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 0,
1794 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1795 .writefn = tlbiall_write },
1796 { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64,
1797 .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 1,
1798 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1799 .writefn = tlbi_aa64_va_write },
1800 { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64,
1801 .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 2,
1802 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1803 .writefn = tlbi_aa64_asid_write },
1804 { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64,
1805 .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 3,
1806 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1807 .writefn = tlbi_aa64_vaa_write },
1808 { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64,
1809 .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 5,
1810 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1811 .writefn = tlbi_aa64_va_write },
1812 { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64,
1813 .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 7,
1814 .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1815 .writefn = tlbi_aa64_vaa_write },
1816 /* Dummy implementation of monitor debug system control register:
1817 * we don't support debug.
1818 */
1819 { .name = "MDSCR_EL1", .state = ARM_CP_STATE_AA64,
1820 .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
1821 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1822 /* We define a dummy WI OSLAR_EL1, because Linux writes to it. */
1823 { .name = "OSLAR_EL1", .state = ARM_CP_STATE_AA64,
1824 .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
1825 .access = PL1_W, .type = ARM_CP_NOP },
1826 REGINFO_SENTINEL
1827 };
1828
1829 static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1830 uint64_t value)
1831 {
1832 env->cp15.c1_sys = value;
1833 /* ??? Lots of these bits are not implemented. */
1834 /* This may enable/disable the MMU, so do a TLB flush. */
1835 tlb_flush(env, 1);
1836 }
1837
1838 static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri)
1839 {
1840 /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64,
1841 * but the AArch32 CTR has its own reginfo struct)
1842 */
1843 if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UCT)) {
1844 return CP_ACCESS_TRAP;
1845 }
1846 return CP_ACCESS_OK;
1847 }
1848
1849 static void define_aarch64_debug_regs(ARMCPU *cpu)
1850 {
1851 /* Define breakpoint and watchpoint registers. These do nothing
1852 * but read as written, for now.
1853 */
1854 int i;
1855
1856 for (i = 0; i < 16; i++) {
1857 ARMCPRegInfo dbgregs[] = {
1858 { .name = "DBGBVR", .state = ARM_CP_STATE_AA64,
1859 .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4,
1860 .access = PL1_RW,
1861 .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]) },
1862 { .name = "DBGBCR", .state = ARM_CP_STATE_AA64,
1863 .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5,
1864 .access = PL1_RW,
1865 .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]) },
1866 { .name = "DBGWVR", .state = ARM_CP_STATE_AA64,
1867 .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6,
1868 .access = PL1_RW,
1869 .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]) },
1870 { .name = "DBGWCR", .state = ARM_CP_STATE_AA64,
1871 .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7,
1872 .access = PL1_RW,
1873 .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]) },
1874 REGINFO_SENTINEL
1875 };
1876 define_arm_cp_regs(cpu, dbgregs);
1877 }
1878 }
1879
1880 void register_cp_regs_for_features(ARMCPU *cpu)
1881 {
1882 /* Register all the coprocessor registers based on feature bits */
1883 CPUARMState *env = &cpu->env;
1884 if (arm_feature(env, ARM_FEATURE_M)) {
1885 /* M profile has no coprocessor registers */
1886 return;
1887 }
1888
1889 define_arm_cp_regs(cpu, cp_reginfo);
1890 if (arm_feature(env, ARM_FEATURE_V6)) {
1891 /* The ID registers all have impdef reset values */
1892 ARMCPRegInfo v6_idregs[] = {
1893 { .name = "ID_PFR0", .cp = 15, .crn = 0, .crm = 1,
1894 .opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST,
1895 .resetvalue = cpu->id_pfr0 },
1896 { .name = "ID_PFR1", .cp = 15, .crn = 0, .crm = 1,
1897 .opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST,
1898 .resetvalue = cpu->id_pfr1 },
1899 { .name = "ID_DFR0", .cp = 15, .crn = 0, .crm = 1,
1900 .opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST,
1901 .resetvalue = cpu->id_dfr0 },
1902 { .name = "ID_AFR0", .cp = 15, .crn = 0, .crm = 1,
1903 .opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST,
1904 .resetvalue = cpu->id_afr0 },
1905 { .name = "ID_MMFR0", .cp = 15, .crn = 0, .crm = 1,
1906 .opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST,
1907 .resetvalue = cpu->id_mmfr0 },
1908 { .name = "ID_MMFR1", .cp = 15, .crn = 0, .crm = 1,
1909 .opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST,
1910 .resetvalue = cpu->id_mmfr1 },
1911 { .name = "ID_MMFR2", .cp = 15, .crn = 0, .crm = 1,
1912 .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
1913 .resetvalue = cpu->id_mmfr2 },
1914 { .name = "ID_MMFR3", .cp = 15, .crn = 0, .crm = 1,
1915 .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
1916 .resetvalue = cpu->id_mmfr3 },
1917 { .name = "ID_ISAR0", .cp = 15, .crn = 0, .crm = 2,
1918 .opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST,
1919 .resetvalue = cpu->id_isar0 },
1920 { .name = "ID_ISAR1", .cp = 15, .crn = 0, .crm = 2,
1921 .opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST,
1922 .resetvalue = cpu->id_isar1 },
1923 { .name = "ID_ISAR2", .cp = 15, .crn = 0, .crm = 2,
1924 .opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST,
1925 .resetvalue = cpu->id_isar2 },
1926 { .name = "ID_ISAR3", .cp = 15, .crn = 0, .crm = 2,
1927 .opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST,
1928 .resetvalue = cpu->id_isar3 },
1929 { .name = "ID_ISAR4", .cp = 15, .crn = 0, .crm = 2,
1930 .opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST,
1931 .resetvalue = cpu->id_isar4 },
1932 { .name = "ID_ISAR5", .cp = 15, .crn = 0, .crm = 2,
1933 .opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST,
1934 .resetvalue = cpu->id_isar5 },
1935 /* 6..7 are as yet unallocated and must RAZ */
1936 { .name = "ID_ISAR6", .cp = 15, .crn = 0, .crm = 2,
1937 .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
1938 .resetvalue = 0 },
1939 { .name = "ID_ISAR7", .cp = 15, .crn = 0, .crm = 2,
1940 .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
1941 .resetvalue = 0 },
1942 REGINFO_SENTINEL
1943 };
1944 define_arm_cp_regs(cpu, v6_idregs);
1945 define_arm_cp_regs(cpu, v6_cp_reginfo);
1946 } else {
1947 define_arm_cp_regs(cpu, not_v6_cp_reginfo);
1948 }
1949 if (arm_feature(env, ARM_FEATURE_V6K)) {
1950 define_arm_cp_regs(cpu, v6k_cp_reginfo);
1951 }
1952 if (arm_feature(env, ARM_FEATURE_V7)) {
1953 /* v7 performance monitor control register: same implementor
1954 * field as main ID register, and we implement only the cycle
1955 * count register.
1956 */
1957 #ifndef CONFIG_USER_ONLY
1958 ARMCPRegInfo pmcr = {
1959 .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
1960 .access = PL0_RW, .resetvalue = cpu->midr & 0xff000000,
1961 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
1962 .accessfn = pmreg_access, .writefn = pmcr_write,
1963 .raw_writefn = raw_write,
1964 };
1965 define_one_arm_cp_reg(cpu, &pmcr);
1966 #endif
1967 ARMCPRegInfo clidr = {
1968 .name = "CLIDR", .state = ARM_CP_STATE_BOTH,
1969 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
1970 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr
1971 };
1972 define_one_arm_cp_reg(cpu, &clidr);
1973 define_arm_cp_regs(cpu, v7_cp_reginfo);
1974 } else {
1975 define_arm_cp_regs(cpu, not_v7_cp_reginfo);
1976 }
1977 if (arm_feature(env, ARM_FEATURE_V8)) {
1978 /* AArch64 ID registers, which all have impdef reset values */
1979 ARMCPRegInfo v8_idregs[] = {
1980 { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64,
1981 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0,
1982 .access = PL1_R, .type = ARM_CP_CONST,
1983 .resetvalue = cpu->id_aa64pfr0 },
1984 { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64,
1985 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1,
1986 .access = PL1_R, .type = ARM_CP_CONST,
1987 .resetvalue = cpu->id_aa64pfr1},
1988 { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
1989 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
1990 .access = PL1_R, .type = ARM_CP_CONST,
1991 .resetvalue = cpu->id_aa64dfr0 },
1992 { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
1993 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
1994 .access = PL1_R, .type = ARM_CP_CONST,
1995 .resetvalue = cpu->id_aa64dfr1 },
1996 { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64,
1997 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4,
1998 .access = PL1_R, .type = ARM_CP_CONST,
1999 .resetvalue = cpu->id_aa64afr0 },
2000 { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64,
2001 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5,
2002 .access = PL1_R, .type = ARM_CP_CONST,
2003 .resetvalue = cpu->id_aa64afr1 },
2004 { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64,
2005 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0,
2006 .access = PL1_R, .type = ARM_CP_CONST,
2007 .resetvalue = cpu->id_aa64isar0 },
2008 { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64,
2009 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1,
2010 .access = PL1_R, .type = ARM_CP_CONST,
2011 .resetvalue = cpu->id_aa64isar1 },
2012 { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64,
2013 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
2014 .access = PL1_R, .type = ARM_CP_CONST,
2015 .resetvalue = cpu->id_aa64mmfr0 },
2016 { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64,
2017 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1,
2018 .access = PL1_R, .type = ARM_CP_CONST,
2019 .resetvalue = cpu->id_aa64mmfr1 },
2020 REGINFO_SENTINEL
2021 };
2022 define_arm_cp_regs(cpu, v8_idregs);
2023 define_arm_cp_regs(cpu, v8_cp_reginfo);
2024 define_aarch64_debug_regs(cpu);
2025 }
2026 if (arm_feature(env, ARM_FEATURE_MPU)) {
2027 /* These are the MPU registers prior to PMSAv6. Any new
2028 * PMSA core later than the ARM946 will require that we
2029 * implement the PMSAv6 or PMSAv7 registers, which are
2030 * completely different.
2031 */
2032 assert(!arm_feature(env, ARM_FEATURE_V6));
2033 define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
2034 } else {
2035 define_arm_cp_regs(cpu, vmsa_cp_reginfo);
2036 }
2037 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
2038 define_arm_cp_regs(cpu, t2ee_cp_reginfo);
2039 }
2040 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
2041 define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
2042 }
2043 if (arm_feature(env, ARM_FEATURE_VAPA)) {
2044 define_arm_cp_regs(cpu, vapa_cp_reginfo);
2045 }
2046 if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) {
2047 define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo);
2048 }
2049 if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) {
2050 define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo);
2051 }
2052 if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) {
2053 define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo);
2054 }
2055 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
2056 define_arm_cp_regs(cpu, omap_cp_reginfo);
2057 }
2058 if (arm_feature(env, ARM_FEATURE_STRONGARM)) {
2059 define_arm_cp_regs(cpu, strongarm_cp_reginfo);
2060 }
2061 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
2062 define_arm_cp_regs(cpu, xscale_cp_reginfo);
2063 }
2064 if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
2065 define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
2066 }
2067 if (arm_feature(env, ARM_FEATURE_LPAE)) {
2068 define_arm_cp_regs(cpu, lpae_cp_reginfo);
2069 }
2070 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
2071 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
2072 * be read-only (ie write causes UNDEF exception).
2073 */
2074 {
2075 ARMCPRegInfo id_cp_reginfo[] = {
2076 /* Note that the MIDR isn't a simple constant register because
2077 * of the TI925 behaviour where writes to another register can
2078 * cause the MIDR value to change.
2079 *
2080 * Unimplemented registers in the c15 0 0 0 space default to
2081 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
2082 * and friends override accordingly.
2083 */
2084 { .name = "MIDR",
2085 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY,
2086 .access = PL1_R, .resetvalue = cpu->midr,
2087 .writefn = arm_cp_write_ignore, .raw_writefn = raw_write,
2088 .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
2089 .type = ARM_CP_OVERRIDE },
2090 { .name = "MIDR_EL1", .state = ARM_CP_STATE_AA64,
2091 .opc0 = 3, .opc1 = 0, .opc2 = 0, .crn = 0, .crm = 0,
2092 .access = PL1_R, .resetvalue = cpu->midr, .type = ARM_CP_CONST },
2093 { .name = "CTR",
2094 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
2095 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
2096 { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64,
2097 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0,
2098 .access = PL0_R, .accessfn = ctr_el0_access,
2099 .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
2100 { .name = "TCMTR",
2101 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2,
2102 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2103 { .name = "TLBTR",
2104 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
2105 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2106 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
2107 { .name = "DUMMY",
2108 .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY,
2109 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2110 { .name = "DUMMY",
2111 .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY,
2112 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2113 { .name = "DUMMY",
2114 .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY,
2115 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2116 { .name = "DUMMY",
2117 .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY,
2118 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2119 { .name = "DUMMY",
2120 .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
2121 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2122 REGINFO_SENTINEL
2123 };
2124 ARMCPRegInfo crn0_wi_reginfo = {
2125 .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
2126 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
2127 .type = ARM_CP_NOP | ARM_CP_OVERRIDE
2128 };
2129 if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
2130 arm_feature(env, ARM_FEATURE_STRONGARM)) {
2131 ARMCPRegInfo *r;
2132 /* Register the blanket "writes ignored" value first to cover the
2133 * whole space. Then update the specific ID registers to allow write
2134 * access, so that they ignore writes rather than causing them to
2135 * UNDEF.
2136 */
2137 define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
2138 for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
2139 r->access = PL1_RW;
2140 }
2141 }
2142 define_arm_cp_regs(cpu, id_cp_reginfo);
2143 }
2144
2145 if (arm_feature(env, ARM_FEATURE_MPIDR)) {
2146 define_arm_cp_regs(cpu, mpidr_cp_reginfo);
2147 }
2148
2149 if (arm_feature(env, ARM_FEATURE_AUXCR)) {
2150 ARMCPRegInfo auxcr = {
2151 .name = "AUXCR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1,
2152 .access = PL1_RW, .type = ARM_CP_CONST,
2153 .resetvalue = cpu->reset_auxcr
2154 };
2155 define_one_arm_cp_reg(cpu, &auxcr);
2156 }
2157
2158 if (arm_feature(env, ARM_FEATURE_CBAR)) {
2159 ARMCPRegInfo cbar = {
2160 .name = "CBAR", .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
2161 .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
2162 .fieldoffset = offsetof(CPUARMState, cp15.c15_config_base_address)
2163 };
2164 define_one_arm_cp_reg(cpu, &cbar);
2165 }
2166
2167 /* Generic registers whose values depend on the implementation */
2168 {
2169 ARMCPRegInfo sctlr = {
2170 .name = "SCTLR", .state = ARM_CP_STATE_BOTH,
2171 .opc0 = 3, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
2172 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_sys),
2173 .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
2174 .raw_writefn = raw_write,
2175 };
2176 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
2177 /* Normally we would always end the TB on an SCTLR write, but Linux
2178 * arch/arm/mach-pxa/sleep.S expects two instructions following
2179 * an MMU enable to execute from cache. Imitate this behaviour.
2180 */
2181 sctlr.type |= ARM_CP_SUPPRESS_TB_END;
2182 }
2183 define_one_arm_cp_reg(cpu, &sctlr);
2184 }
2185 }
2186
2187 ARMCPU *cpu_arm_init(const char *cpu_model)
2188 {
2189 return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model));
2190 }
2191
2192 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
2193 {
2194 CPUState *cs = CPU(cpu);
2195 CPUARMState *env = &cpu->env;
2196
2197 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
2198 gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
2199 aarch64_fpu_gdb_set_reg,
2200 34, "aarch64-fpu.xml", 0);
2201 } else if (arm_feature(env, ARM_FEATURE_NEON)) {
2202 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
2203 51, "arm-neon.xml", 0);
2204 } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
2205 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
2206 35, "arm-vfp3.xml", 0);
2207 } else if (arm_feature(env, ARM_FEATURE_VFP)) {
2208 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
2209 19, "arm-vfp.xml", 0);
2210 }
2211 }
2212
2213 /* Sort alphabetically by type name, except for "any". */
2214 static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
2215 {
2216 ObjectClass *class_a = (ObjectClass *)a;
2217 ObjectClass *class_b = (ObjectClass *)b;
2218 const char *name_a, *name_b;
2219
2220 name_a = object_class_get_name(class_a);
2221 name_b = object_class_get_name(class_b);
2222 if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) {
2223 return 1;
2224 } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) {
2225 return -1;
2226 } else {
2227 return strcmp(name_a, name_b);
2228 }
2229 }
2230
2231 static void arm_cpu_list_entry(gpointer data, gpointer user_data)
2232 {
2233 ObjectClass *oc = data;
2234 CPUListState *s = user_data;
2235 const char *typename;
2236 char *name;
2237
2238 typename = object_class_get_name(oc);
2239 name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU));
2240 (*s->cpu_fprintf)(s->file, " %s\n",
2241 name);
2242 g_free(name);
2243 }
2244
2245 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
2246 {
2247 CPUListState s = {
2248 .file = f,
2249 .cpu_fprintf = cpu_fprintf,
2250 };
2251 GSList *list;
2252
2253 list = object_class_get_list(TYPE_ARM_CPU, false);
2254 list = g_slist_sort(list, arm_cpu_list_compare);
2255 (*cpu_fprintf)(f, "Available CPUs:\n");
2256 g_slist_foreach(list, arm_cpu_list_entry, &s);
2257 g_slist_free(list);
2258 #ifdef CONFIG_KVM
2259 /* The 'host' CPU type is dynamically registered only if KVM is
2260 * enabled, so we have to special-case it here:
2261 */
2262 (*cpu_fprintf)(f, " host (only available in KVM mode)\n");
2263 #endif
2264 }
2265
2266 static void arm_cpu_add_definition(gpointer data, gpointer user_data)
2267 {
2268 ObjectClass *oc = data;
2269 CpuDefinitionInfoList **cpu_list = user_data;
2270 CpuDefinitionInfoList *entry;
2271 CpuDefinitionInfo *info;
2272 const char *typename;
2273
2274 typename = object_class_get_name(oc);
2275 info = g_malloc0(sizeof(*info));
2276 info->name = g_strndup(typename,
2277 strlen(typename) - strlen("-" TYPE_ARM_CPU));
2278
2279 entry = g_malloc0(sizeof(*entry));
2280 entry->value = info;
2281 entry->next = *cpu_list;
2282 *cpu_list = entry;
2283 }
2284
2285 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
2286 {
2287 CpuDefinitionInfoList *cpu_list = NULL;
2288 GSList *list;
2289
2290 list = object_class_get_list(TYPE_ARM_CPU, false);
2291 g_slist_foreach(list, arm_cpu_add_definition, &cpu_list);
2292 g_slist_free(list);
2293
2294 return cpu_list;
2295 }
2296
2297 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
2298 void *opaque, int state,
2299 int crm, int opc1, int opc2)
2300 {
2301 /* Private utility function for define_one_arm_cp_reg_with_opaque():
2302 * add a single reginfo struct to the hash table.
2303 */
2304 uint32_t *key = g_new(uint32_t, 1);
2305 ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
2306 int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
2307 if (r->state == ARM_CP_STATE_BOTH && state == ARM_CP_STATE_AA32) {
2308 /* The AArch32 view of a shared register sees the lower 32 bits
2309 * of a 64 bit backing field. It is not migratable as the AArch64
2310 * view handles that. AArch64 also handles reset.
2311 * We assume it is a cp15 register.
2312 */
2313 r2->cp = 15;
2314 r2->type |= ARM_CP_NO_MIGRATE;
2315 r2->resetfn = arm_cp_reset_ignore;
2316 #ifdef HOST_WORDS_BIGENDIAN
2317 if (r2->fieldoffset) {
2318 r2->fieldoffset += sizeof(uint32_t);
2319 }
2320 #endif
2321 }
2322 if (state == ARM_CP_STATE_AA64) {
2323 /* To allow abbreviation of ARMCPRegInfo
2324 * definitions, we treat cp == 0 as equivalent to
2325 * the value for "standard guest-visible sysreg".
2326 */
2327 if (r->cp == 0) {
2328 r2->cp = CP_REG_ARM64_SYSREG_CP;
2329 }
2330 *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
2331 r2->opc0, opc1, opc2);
2332 } else {
2333 *key = ENCODE_CP_REG(r2->cp, is64, r2->crn, crm, opc1, opc2);
2334 }
2335 if (opaque) {
2336 r2->opaque = opaque;
2337 }
2338 /* reginfo passed to helpers is correct for the actual access,
2339 * and is never ARM_CP_STATE_BOTH:
2340 */
2341 r2->state = state;
2342 /* Make sure reginfo passed to helpers for wildcarded regs
2343 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
2344 */
2345 r2->crm = crm;
2346 r2->opc1 = opc1;
2347 r2->opc2 = opc2;
2348 /* By convention, for wildcarded registers only the first
2349 * entry is used for migration; the others are marked as
2350 * NO_MIGRATE so we don't try to transfer the register
2351 * multiple times. Special registers (ie NOP/WFI) are
2352 * never migratable.
2353 */
2354 if ((r->type & ARM_CP_SPECIAL) ||
2355 ((r->crm == CP_ANY) && crm != 0) ||
2356 ((r->opc1 == CP_ANY) && opc1 != 0) ||
2357 ((r->opc2 == CP_ANY) && opc2 != 0)) {
2358 r2->type |= ARM_CP_NO_MIGRATE;
2359 }
2360
2361 /* Overriding of an existing definition must be explicitly
2362 * requested.
2363 */
2364 if (!(r->type & ARM_CP_OVERRIDE)) {
2365 ARMCPRegInfo *oldreg;
2366 oldreg = g_hash_table_lookup(cpu->cp_regs, key);
2367 if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
2368 fprintf(stderr, "Register redefined: cp=%d %d bit "
2369 "crn=%d crm=%d opc1=%d opc2=%d, "
2370 "was %s, now %s\n", r2->cp, 32 + 32 * is64,
2371 r2->crn, r2->crm, r2->opc1, r2->opc2,
2372 oldreg->name, r2->name);
2373 g_assert_not_reached();
2374 }
2375 }
2376 g_hash_table_insert(cpu->cp_regs, key, r2);
2377 }
2378
2379
2380 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
2381 const ARMCPRegInfo *r, void *opaque)
2382 {
2383 /* Define implementations of coprocessor registers.
2384 * We store these in a hashtable because typically
2385 * there are less than 150 registers in a space which
2386 * is 16*16*16*8*8 = 262144 in size.
2387 * Wildcarding is supported for the crm, opc1 and opc2 fields.
2388 * If a register is defined twice then the second definition is
2389 * used, so this can be used to define some generic registers and
2390 * then override them with implementation specific variations.
2391 * At least one of the original and the second definition should
2392 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
2393 * against accidental use.
2394 *
2395 * The state field defines whether the register is to be
2396 * visible in the AArch32 or AArch64 execution state. If the
2397 * state is set to ARM_CP_STATE_BOTH then we synthesise a
2398 * reginfo structure for the AArch32 view, which sees the lower
2399 * 32 bits of the 64 bit register.
2400 *
2401 * Only registers visible in AArch64 may set r->opc0; opc0 cannot
2402 * be wildcarded. AArch64 registers are always considered to be 64
2403 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
2404 * the register, if any.
2405 */
2406 int crm, opc1, opc2, state;
2407 int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
2408 int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
2409 int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
2410 int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
2411 int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
2412 int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
2413 /* 64 bit registers have only CRm and Opc1 fields */
2414 assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
2415 /* op0 only exists in the AArch64 encodings */
2416 assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0));
2417 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
2418 assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT));
2419 /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
2420 * encodes a minimum access level for the register. We roll this
2421 * runtime check into our general permission check code, so check
2422 * here that the reginfo's specified permissions are strict enough
2423 * to encompass the generic architectural permission check.
2424 */
2425 if (r->state != ARM_CP_STATE_AA32) {
2426 int mask = 0;
2427 switch (r->opc1) {
2428 case 0: case 1: case 2:
2429 /* min_EL EL1 */
2430 mask = PL1_RW;
2431 break;
2432 case 3:
2433 /* min_EL EL0 */
2434 mask = PL0_RW;
2435 break;
2436 case 4:
2437 /* min_EL EL2 */
2438 mask = PL2_RW;
2439 break;
2440 case 5:
2441 /* unallocated encoding, so not possible */
2442 assert(false);
2443 break;
2444 case 6:
2445 /* min_EL EL3 */
2446 mask = PL3_RW;
2447 break;
2448 case 7:
2449 /* min_EL EL1, secure mode only (we don't check the latter) */
2450 mask = PL1_RW;
2451 break;
2452 default:
2453 /* broken reginfo with out-of-range opc1 */
2454 assert(false);
2455 break;
2456 }
2457 /* assert our permissions are not too lax (stricter is fine) */
2458 assert((r->access & ~mask) == 0);
2459 }
2460
2461 /* Check that the register definition has enough info to handle
2462 * reads and writes if they are permitted.
2463 */
2464 if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
2465 if (r->access & PL3_R) {
2466 assert(r->fieldoffset || r->readfn);
2467 }
2468 if (r->access & PL3_W) {
2469 assert(r->fieldoffset || r->writefn);
2470 }
2471 }
2472 /* Bad type field probably means missing sentinel at end of reg list */
2473 assert(cptype_valid(r->type));
2474 for (crm = crmmin; crm <= crmmax; crm++) {
2475 for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
2476 for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
2477 for (state = ARM_CP_STATE_AA32;
2478 state <= ARM_CP_STATE_AA64; state++) {
2479 if (r->state != state && r->state != ARM_CP_STATE_BOTH) {
2480 continue;
2481 }
2482 add_cpreg_to_hashtable(cpu, r, opaque, state,
2483 crm, opc1, opc2);
2484 }
2485 }
2486 }
2487 }
2488 }
2489
2490 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
2491 const ARMCPRegInfo *regs, void *opaque)
2492 {
2493 /* Define a whole list of registers */
2494 const ARMCPRegInfo *r;
2495 for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
2496 define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
2497 }
2498 }
2499
2500 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp)
2501 {
2502 return g_hash_table_lookup(cpregs, &encoded_cp);
2503 }
2504
2505 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
2506 uint64_t value)
2507 {
2508 /* Helper coprocessor write function for write-ignore registers */
2509 }
2510
2511 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri)
2512 {
2513 /* Helper coprocessor write function for read-as-zero registers */
2514 return 0;
2515 }
2516
2517 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque)
2518 {
2519 /* Helper coprocessor reset function for do-nothing-on-reset registers */
2520 }
2521
2522 static int bad_mode_switch(CPUARMState *env, int mode)
2523 {
2524 /* Return true if it is not valid for us to switch to
2525 * this CPU mode (ie all the UNPREDICTABLE cases in
2526 * the ARM ARM CPSRWriteByInstr pseudocode).
2527 */
2528 switch (mode) {
2529 case ARM_CPU_MODE_USR:
2530 case ARM_CPU_MODE_SYS:
2531 case ARM_CPU_MODE_SVC:
2532 case ARM_CPU_MODE_ABT:
2533 case ARM_CPU_MODE_UND:
2534 case ARM_CPU_MODE_IRQ:
2535 case ARM_CPU_MODE_FIQ:
2536 return 0;
2537 default:
2538 return 1;
2539 }
2540 }
2541
2542 uint32_t cpsr_read(CPUARMState *env)
2543 {
2544 int ZF;
2545 ZF = (env->ZF == 0);
2546 return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
2547 (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
2548 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
2549 | ((env->condexec_bits & 0xfc) << 8)
2550 | (env->GE << 16) | (env->daif & CPSR_AIF);
2551 }
2552
2553 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
2554 {
2555 if (mask & CPSR_NZCV) {
2556 env->ZF = (~val) & CPSR_Z;
2557 env->NF = val;
2558 env->CF = (val >> 29) & 1;
2559 env->VF = (val << 3) & 0x80000000;
2560 }
2561 if (mask & CPSR_Q)
2562 env->QF = ((val & CPSR_Q) != 0);
2563 if (mask & CPSR_T)
2564 env->thumb = ((val & CPSR_T) != 0);
2565 if (mask & CPSR_IT_0_1) {
2566 env->condexec_bits &= ~3;
2567 env->condexec_bits |= (val >> 25) & 3;
2568 }
2569 if (mask & CPSR_IT_2_7) {
2570 env->condexec_bits &= 3;
2571 env->condexec_bits |= (val >> 8) & 0xfc;
2572 }
2573 if (mask & CPSR_GE) {
2574 env->GE = (val >> 16) & 0xf;
2575 }
2576
2577 env->daif &= ~(CPSR_AIF & mask);
2578 env->daif |= val & CPSR_AIF & mask;
2579
2580 if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
2581 if (bad_mode_switch(env, val & CPSR_M)) {
2582 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
2583 * We choose to ignore the attempt and leave the CPSR M field
2584 * untouched.
2585 */
2586 mask &= ~CPSR_M;
2587 } else {
2588 switch_mode(env, val & CPSR_M);
2589 }
2590 }
2591 mask &= ~CACHED_CPSR_BITS;
2592 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
2593 }
2594
2595 /* Sign/zero extend */
2596 uint32_t HELPER(sxtb16)(uint32_t x)
2597 {
2598 uint32_t res;
2599 res = (uint16_t)(int8_t)x;
2600 res |= (uint32_t)(int8_t)(x >> 16) << 16;
2601 return res;
2602 }
2603
2604 uint32_t HELPER(uxtb16)(uint32_t x)
2605 {
2606 uint32_t res;
2607 res = (uint16_t)(uint8_t)x;
2608 res |= (uint32_t)(uint8_t)(x >> 16) << 16;
2609 return res;
2610 }
2611
2612 uint32_t HELPER(clz)(uint32_t x)
2613 {
2614 return clz32(x);
2615 }
2616
2617 int32_t HELPER(sdiv)(int32_t num, int32_t den)
2618 {
2619 if (den == 0)
2620 return 0;
2621 if (num == INT_MIN && den == -1)
2622 return INT_MIN;
2623 return num / den;
2624 }
2625
2626 uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
2627 {
2628 if (den == 0)
2629 return 0;
2630 return num / den;
2631 }
2632
2633 uint32_t HELPER(rbit)(uint32_t x)
2634 {
2635 x = ((x & 0xff000000) >> 24)
2636 | ((x & 0x00ff0000) >> 8)
2637 | ((x & 0x0000ff00) << 8)
2638 | ((x & 0x000000ff) << 24);
2639 x = ((x & 0xf0f0f0f0) >> 4)
2640 | ((x & 0x0f0f0f0f) << 4);
2641 x = ((x & 0x88888888) >> 3)
2642 | ((x & 0x44444444) >> 1)
2643 | ((x & 0x22222222) << 1)
2644 | ((x & 0x11111111) << 3);
2645 return x;
2646 }
2647
2648 #if defined(CONFIG_USER_ONLY)
2649
2650 void arm_cpu_do_interrupt(CPUState *cs)
2651 {
2652 ARMCPU *cpu = ARM_CPU(cs);
2653 CPUARMState *env = &cpu->env;
2654
2655 env->exception_index = -1;
2656 }
2657
2658 int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
2659 int mmu_idx)
2660 {
2661 if (rw == 2) {
2662 env->exception_index = EXCP_PREFETCH_ABORT;
2663 env->cp15.c6_insn = address;
2664 } else {
2665 env->exception_index = EXCP_DATA_ABORT;
2666 env->cp15.c6_data = address;
2667 }
2668 return 1;
2669 }
2670
2671 /* These should probably raise undefined insn exceptions. */
2672 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
2673 {
2674 cpu_abort(env, "v7m_mrs %d\n", reg);
2675 }
2676
2677 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
2678 {
2679 cpu_abort(env, "v7m_mrs %d\n", reg);
2680 return 0;
2681 }
2682
2683 void switch_mode(CPUARMState *env, int mode)
2684 {
2685 if (mode != ARM_CPU_MODE_USR)
2686 cpu_abort(env, "Tried to switch out of user mode\n");
2687 }
2688
2689 void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
2690 {
2691 cpu_abort(env, "banked r13 write\n");
2692 }
2693
2694 uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
2695 {
2696 cpu_abort(env, "banked r13 read\n");
2697 return 0;
2698 }
2699
2700 #else
2701
2702 /* Map CPU modes onto saved register banks. */
2703 int bank_number(int mode)
2704 {
2705 switch (mode) {
2706 case ARM_CPU_MODE_USR:
2707 case ARM_CPU_MODE_SYS:
2708 return 0;
2709 case ARM_CPU_MODE_SVC:
2710 return 1;
2711 case ARM_CPU_MODE_ABT:
2712 return 2;
2713 case ARM_CPU_MODE_UND:
2714 return 3;
2715 case ARM_CPU_MODE_IRQ:
2716 return 4;
2717 case ARM_CPU_MODE_FIQ:
2718 return 5;
2719 }
2720 hw_error("bank number requested for bad CPSR mode value 0x%x\n", mode);
2721 }
2722
2723 void switch_mode(CPUARMState *env, int mode)
2724 {
2725 int old_mode;
2726 int i;
2727
2728 old_mode = env->uncached_cpsr & CPSR_M;
2729 if (mode == old_mode)
2730 return;
2731
2732 if (old_mode == ARM_CPU_MODE_FIQ) {
2733 memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
2734 memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
2735 } else if (mode == ARM_CPU_MODE_FIQ) {
2736 memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
2737 memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
2738 }
2739
2740 i = bank_number(old_mode);
2741 env->banked_r13[i] = env->regs[13];
2742 env->banked_r14[i] = env->regs[14];
2743 env->banked_spsr[i] = env->spsr;
2744
2745 i = bank_number(mode);
2746 env->regs[13] = env->banked_r13[i];
2747 env->regs[14] = env->banked_r14[i];
2748 env->spsr = env->banked_spsr[i];
2749 }
2750
2751 static void v7m_push(CPUARMState *env, uint32_t val)
2752 {
2753 CPUState *cs = CPU(arm_env_get_cpu(env));
2754
2755 env->regs[13] -= 4;
2756 stl_phys(cs->as, env->regs[13], val);
2757 }
2758
2759 static uint32_t v7m_pop(CPUARMState *env)
2760 {
2761 CPUState *cs = CPU(arm_env_get_cpu(env));
2762 uint32_t val;
2763
2764 val = ldl_phys(cs->as, env->regs[13]);
2765 env->regs[13] += 4;
2766 return val;
2767 }
2768
2769 /* Switch to V7M main or process stack pointer. */
2770 static void switch_v7m_sp(CPUARMState *env, int process)
2771 {
2772 uint32_t tmp;
2773 if (env->v7m.current_sp != process) {
2774 tmp = env->v7m.other_sp;
2775 env->v7m.other_sp = env->regs[13];
2776 env->regs[13] = tmp;
2777 env->v7m.current_sp = process;
2778 }
2779 }
2780
2781 static void do_v7m_exception_exit(CPUARMState *env)
2782 {
2783 uint32_t type;
2784 uint32_t xpsr;
2785
2786 type = env->regs[15];
2787 if (env->v7m.exception != 0)
2788 armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
2789
2790 /* Switch to the target stack. */
2791 switch_v7m_sp(env, (type & 4) != 0);
2792 /* Pop registers. */
2793 env->regs[0] = v7m_pop(env);
2794 env->regs[1] = v7m_pop(env);
2795 env->regs[2] = v7m_pop(env);
2796 env->regs[3] = v7m_pop(env);
2797 env->regs[12] = v7m_pop(env);
2798 env->regs[14] = v7m_pop(env);
2799 env->regs[15] = v7m_pop(env);
2800 xpsr = v7m_pop(env);
2801 xpsr_write(env, xpsr, 0xfffffdff);
2802 /* Undo stack alignment. */
2803 if (xpsr & 0x200)
2804 env->regs[13] |= 4;
2805 /* ??? The exception return type specifies Thread/Handler mode. However
2806 this is also implied by the xPSR value. Not sure what to do
2807 if there is a mismatch. */
2808 /* ??? Likewise for mismatches between the CONTROL register and the stack
2809 pointer. */
2810 }
2811
2812 /* Exception names for debug logging; note that not all of these
2813 * precisely correspond to architectural exceptions.
2814 */
2815 static const char * const excnames[] = {
2816 [EXCP_UDEF] = "Undefined Instruction",
2817 [EXCP_SWI] = "SVC",
2818 [EXCP_PREFETCH_ABORT] = "Prefetch Abort",
2819 [EXCP_DATA_ABORT] = "Data Abort",
2820 [EXCP_IRQ] = "IRQ",
2821 [EXCP_FIQ] = "FIQ",
2822 [EXCP_BKPT] = "Breakpoint",
2823 [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit",
2824 [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage",
2825 [EXCP_STREX] = "QEMU intercept of STREX",
2826 };
2827
2828 static inline void arm_log_exception(int idx)
2829 {
2830 if (qemu_loglevel_mask(CPU_LOG_INT)) {
2831 const char *exc = NULL;
2832
2833 if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
2834 exc = excnames[idx];
2835 }
2836 if (!exc) {
2837 exc = "unknown";
2838 }
2839 qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc);
2840 }
2841 }
2842
2843 void arm_v7m_cpu_do_interrupt(CPUState *cs)
2844 {
2845 ARMCPU *cpu = ARM_CPU(cs);
2846 CPUARMState *env = &cpu->env;
2847 uint32_t xpsr = xpsr_read(env);
2848 uint32_t lr;
2849 uint32_t addr;
2850
2851 arm_log_exception(env->exception_index);
2852
2853 lr = 0xfffffff1;
2854 if (env->v7m.current_sp)
2855 lr |= 4;
2856 if (env->v7m.exception == 0)
2857 lr |= 8;
2858
2859 /* For exceptions we just mark as pending on the NVIC, and let that
2860 handle it. */
2861 /* TODO: Need to escalate if the current priority is higher than the
2862 one we're raising. */
2863 switch (env->exception_index) {
2864 case EXCP_UDEF:
2865 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
2866 return;
2867 case EXCP_SWI:
2868 /* The PC already points to the next instruction. */
2869 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
2870 return;
2871 case EXCP_PREFETCH_ABORT:
2872 case EXCP_DATA_ABORT:
2873 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
2874 return;
2875 case EXCP_BKPT:
2876 if (semihosting_enabled) {
2877 int nr;
2878 nr = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
2879 if (nr == 0xab) {
2880 env->regs[15] += 2;
2881 env->regs[0] = do_arm_semihosting(env);
2882 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
2883 return;
2884 }
2885 }
2886 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
2887 return;
2888 case EXCP_IRQ:
2889 env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
2890 break;
2891 case EXCP_EXCEPTION_EXIT:
2892 do_v7m_exception_exit(env);
2893 return;
2894 default:
2895 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
2896 return; /* Never happe