qemu-img: Omit error_report() after img_open()
[qemu.git] / target-arm / internals.h
1 /*
2 * QEMU ARM CPU -- internal functions and types
3 *
4 * Copyright (c) 2014 Linaro Ltd
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
19 *
20 * This header defines functions, types, etc which need to be shared
21 * between different source files within target-arm/ but which are
22 * private to it and not required by the rest of QEMU.
23 */
24
25 #ifndef TARGET_ARM_INTERNALS_H
26 #define TARGET_ARM_INTERNALS_H
27
28 static inline bool excp_is_internal(int excp)
29 {
30 /* Return true if this exception number represents a QEMU-internal
31 * exception that will not be passed to the guest.
32 */
33 return excp == EXCP_INTERRUPT
34 || excp == EXCP_HLT
35 || excp == EXCP_DEBUG
36 || excp == EXCP_HALTED
37 || excp == EXCP_EXCEPTION_EXIT
38 || excp == EXCP_KERNEL_TRAP
39 || excp == EXCP_STREX;
40 }
41
42 /* Exception names for debug logging; note that not all of these
43 * precisely correspond to architectural exceptions.
44 */
45 static const char * const excnames[] = {
46 [EXCP_UDEF] = "Undefined Instruction",
47 [EXCP_SWI] = "SVC",
48 [EXCP_PREFETCH_ABORT] = "Prefetch Abort",
49 [EXCP_DATA_ABORT] = "Data Abort",
50 [EXCP_IRQ] = "IRQ",
51 [EXCP_FIQ] = "FIQ",
52 [EXCP_BKPT] = "Breakpoint",
53 [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit",
54 [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage",
55 [EXCP_STREX] = "QEMU intercept of STREX",
56 [EXCP_HVC] = "Hypervisor Call",
57 [EXCP_HYP_TRAP] = "Hypervisor Trap",
58 [EXCP_SMC] = "Secure Monitor Call",
59 [EXCP_VIRQ] = "Virtual IRQ",
60 [EXCP_VFIQ] = "Virtual FIQ",
61 };
62
63 static inline void arm_log_exception(int idx)
64 {
65 if (qemu_loglevel_mask(CPU_LOG_INT)) {
66 const char *exc = NULL;
67
68 if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
69 exc = excnames[idx];
70 }
71 if (!exc) {
72 exc = "unknown";
73 }
74 qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc);
75 }
76 }
77
78 /* Scale factor for generic timers, ie number of ns per tick.
79 * This gives a 62.5MHz timer.
80 */
81 #define GTIMER_SCALE 16
82
83 /*
84 * For AArch64, map a given EL to an index in the banked_spsr array.
85 */
86 static inline unsigned int aarch64_banked_spsr_index(unsigned int el)
87 {
88 static const unsigned int map[4] = {
89 [1] = 0, /* EL1. */
90 [2] = 6, /* EL2. */
91 [3] = 7, /* EL3. */
92 };
93 assert(el >= 1 && el <= 3);
94 return map[el];
95 }
96
97 int bank_number(int mode);
98 void switch_mode(CPUARMState *, int);
99 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);
100 void arm_translate_init(void);
101
102 enum arm_fprounding {
103 FPROUNDING_TIEEVEN,
104 FPROUNDING_POSINF,
105 FPROUNDING_NEGINF,
106 FPROUNDING_ZERO,
107 FPROUNDING_TIEAWAY,
108 FPROUNDING_ODD
109 };
110
111 int arm_rmode_to_sf(int rmode);
112
113 static inline void aarch64_save_sp(CPUARMState *env, int el)
114 {
115 if (env->pstate & PSTATE_SP) {
116 env->sp_el[el] = env->xregs[31];
117 } else {
118 env->sp_el[0] = env->xregs[31];
119 }
120 }
121
122 static inline void aarch64_restore_sp(CPUARMState *env, int el)
123 {
124 if (env->pstate & PSTATE_SP) {
125 env->xregs[31] = env->sp_el[el];
126 } else {
127 env->xregs[31] = env->sp_el[0];
128 }
129 }
130
131 static inline void update_spsel(CPUARMState *env, uint32_t imm)
132 {
133 unsigned int cur_el = arm_current_el(env);
134 /* Update PSTATE SPSel bit; this requires us to update the
135 * working stack pointer in xregs[31].
136 */
137 if (!((imm ^ env->pstate) & PSTATE_SP)) {
138 return;
139 }
140 aarch64_save_sp(env, cur_el);
141 env->pstate = deposit32(env->pstate, 0, 1, imm);
142
143 /* We rely on illegal updates to SPsel from EL0 to get trapped
144 * at translation time.
145 */
146 assert(cur_el >= 1 && cur_el <= 3);
147 aarch64_restore_sp(env, cur_el);
148 }
149
150 /* Return true if extended addresses are enabled.
151 * This is always the case if our translation regime is 64 bit,
152 * but depends on TTBCR.EAE for 32 bit.
153 */
154 static inline bool extended_addresses_enabled(CPUARMState *env)
155 {
156 return arm_el_is_aa64(env, 1)
157 || ((arm_feature(env, ARM_FEATURE_LPAE)
158 && (env->cp15.c2_control & TTBCR_EAE)));
159 }
160
161 /* Valid Syndrome Register EC field values */
162 enum arm_exception_class {
163 EC_UNCATEGORIZED = 0x00,
164 EC_WFX_TRAP = 0x01,
165 EC_CP15RTTRAP = 0x03,
166 EC_CP15RRTTRAP = 0x04,
167 EC_CP14RTTRAP = 0x05,
168 EC_CP14DTTRAP = 0x06,
169 EC_ADVSIMDFPACCESSTRAP = 0x07,
170 EC_FPIDTRAP = 0x08,
171 EC_CP14RRTTRAP = 0x0c,
172 EC_ILLEGALSTATE = 0x0e,
173 EC_AA32_SVC = 0x11,
174 EC_AA32_HVC = 0x12,
175 EC_AA32_SMC = 0x13,
176 EC_AA64_SVC = 0x15,
177 EC_AA64_HVC = 0x16,
178 EC_AA64_SMC = 0x17,
179 EC_SYSTEMREGISTERTRAP = 0x18,
180 EC_INSNABORT = 0x20,
181 EC_INSNABORT_SAME_EL = 0x21,
182 EC_PCALIGNMENT = 0x22,
183 EC_DATAABORT = 0x24,
184 EC_DATAABORT_SAME_EL = 0x25,
185 EC_SPALIGNMENT = 0x26,
186 EC_AA32_FPTRAP = 0x28,
187 EC_AA64_FPTRAP = 0x2c,
188 EC_SERROR = 0x2f,
189 EC_BREAKPOINT = 0x30,
190 EC_BREAKPOINT_SAME_EL = 0x31,
191 EC_SOFTWARESTEP = 0x32,
192 EC_SOFTWARESTEP_SAME_EL = 0x33,
193 EC_WATCHPOINT = 0x34,
194 EC_WATCHPOINT_SAME_EL = 0x35,
195 EC_AA32_BKPT = 0x38,
196 EC_VECTORCATCH = 0x3a,
197 EC_AA64_BKPT = 0x3c,
198 };
199
200 #define ARM_EL_EC_SHIFT 26
201 #define ARM_EL_IL_SHIFT 25
202 #define ARM_EL_IL (1 << ARM_EL_IL_SHIFT)
203
204 /* Utility functions for constructing various kinds of syndrome value.
205 * Note that in general we follow the AArch64 syndrome values; in a
206 * few cases the value in HSR for exceptions taken to AArch32 Hyp
207 * mode differs slightly, so if we ever implemented Hyp mode then the
208 * syndrome value would need some massaging on exception entry.
209 * (One example of this is that AArch64 defaults to IL bit set for
210 * exceptions which don't specifically indicate information about the
211 * trapping instruction, whereas AArch32 defaults to IL bit clear.)
212 */
213 static inline uint32_t syn_uncategorized(void)
214 {
215 return (EC_UNCATEGORIZED << ARM_EL_EC_SHIFT) | ARM_EL_IL;
216 }
217
218 static inline uint32_t syn_aa64_svc(uint32_t imm16)
219 {
220 return (EC_AA64_SVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
221 }
222
223 static inline uint32_t syn_aa64_hvc(uint32_t imm16)
224 {
225 return (EC_AA64_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
226 }
227
228 static inline uint32_t syn_aa64_smc(uint32_t imm16)
229 {
230 return (EC_AA64_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
231 }
232
233 static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_thumb)
234 {
235 return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | (imm16 & 0xffff)
236 | (is_thumb ? 0 : ARM_EL_IL);
237 }
238
239 static inline uint32_t syn_aa32_hvc(uint32_t imm16)
240 {
241 return (EC_AA32_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
242 }
243
244 static inline uint32_t syn_aa32_smc(void)
245 {
246 return (EC_AA32_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL;
247 }
248
249 static inline uint32_t syn_aa64_bkpt(uint32_t imm16)
250 {
251 return (EC_AA64_BKPT << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
252 }
253
254 static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_thumb)
255 {
256 return (EC_AA32_BKPT << ARM_EL_EC_SHIFT) | (imm16 & 0xffff)
257 | (is_thumb ? 0 : ARM_EL_IL);
258 }
259
260 static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2,
261 int crn, int crm, int rt,
262 int isread)
263 {
264 return (EC_SYSTEMREGISTERTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL
265 | (op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (rt << 5)
266 | (crm << 1) | isread;
267 }
268
269 static inline uint32_t syn_cp14_rt_trap(int cv, int cond, int opc1, int opc2,
270 int crn, int crm, int rt, int isread,
271 bool is_thumb)
272 {
273 return (EC_CP14RTTRAP << ARM_EL_EC_SHIFT)
274 | (is_thumb ? 0 : ARM_EL_IL)
275 | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14)
276 | (crn << 10) | (rt << 5) | (crm << 1) | isread;
277 }
278
279 static inline uint32_t syn_cp15_rt_trap(int cv, int cond, int opc1, int opc2,
280 int crn, int crm, int rt, int isread,
281 bool is_thumb)
282 {
283 return (EC_CP15RTTRAP << ARM_EL_EC_SHIFT)
284 | (is_thumb ? 0 : ARM_EL_IL)
285 | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14)
286 | (crn << 10) | (rt << 5) | (crm << 1) | isread;
287 }
288
289 static inline uint32_t syn_cp14_rrt_trap(int cv, int cond, int opc1, int crm,
290 int rt, int rt2, int isread,
291 bool is_thumb)
292 {
293 return (EC_CP14RRTTRAP << ARM_EL_EC_SHIFT)
294 | (is_thumb ? 0 : ARM_EL_IL)
295 | (cv << 24) | (cond << 20) | (opc1 << 16)
296 | (rt2 << 10) | (rt << 5) | (crm << 1) | isread;
297 }
298
299 static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm,
300 int rt, int rt2, int isread,
301 bool is_thumb)
302 {
303 return (EC_CP15RRTTRAP << ARM_EL_EC_SHIFT)
304 | (is_thumb ? 0 : ARM_EL_IL)
305 | (cv << 24) | (cond << 20) | (opc1 << 16)
306 | (rt2 << 10) | (rt << 5) | (crm << 1) | isread;
307 }
308
309 static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_thumb)
310 {
311 return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT)
312 | (is_thumb ? 0 : ARM_EL_IL)
313 | (cv << 24) | (cond << 20);
314 }
315
316 static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc)
317 {
318 return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
319 | (ea << 9) | (s1ptw << 7) | fsc;
320 }
321
322 static inline uint32_t syn_data_abort(int same_el, int ea, int cm, int s1ptw,
323 int wnr, int fsc)
324 {
325 return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
326 | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc;
327 }
328
329 static inline uint32_t syn_swstep(int same_el, int isv, int ex)
330 {
331 return (EC_SOFTWARESTEP << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
332 | (isv << 24) | (ex << 6) | 0x22;
333 }
334
335 static inline uint32_t syn_watchpoint(int same_el, int cm, int wnr)
336 {
337 return (EC_WATCHPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
338 | (cm << 8) | (wnr << 6) | 0x22;
339 }
340
341 static inline uint32_t syn_breakpoint(int same_el)
342 {
343 return (EC_BREAKPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
344 | ARM_EL_IL | 0x22;
345 }
346
347 /* Update a QEMU watchpoint based on the information the guest has set in the
348 * DBGWCR<n>_EL1 and DBGWVR<n>_EL1 registers.
349 */
350 void hw_watchpoint_update(ARMCPU *cpu, int n);
351 /* Update the QEMU watchpoints for every guest watchpoint. This does a
352 * complete delete-and-reinstate of the QEMU watchpoint list and so is
353 * suitable for use after migration or on reset.
354 */
355 void hw_watchpoint_update_all(ARMCPU *cpu);
356 /* Update a QEMU breakpoint based on the information the guest has set in the
357 * DBGBCR<n>_EL1 and DBGBVR<n>_EL1 registers.
358 */
359 void hw_breakpoint_update(ARMCPU *cpu, int n);
360 /* Update the QEMU breakpoints for every guest breakpoint. This does a
361 * complete delete-and-reinstate of the QEMU breakpoint list and so is
362 * suitable for use after migration or on reset.
363 */
364 void hw_breakpoint_update_all(ARMCPU *cpu);
365
366 /* Callback function for when a watchpoint or breakpoint triggers. */
367 void arm_debug_excp_handler(CPUState *cs);
368
369 #ifdef CONFIG_USER_ONLY
370 static inline bool arm_is_psci_call(ARMCPU *cpu, int excp_type)
371 {
372 return false;
373 }
374 #else
375 /* Return true if the r0/x0 value indicates that this SMC/HVC is a PSCI call. */
376 bool arm_is_psci_call(ARMCPU *cpu, int excp_type);
377 /* Actually handle a PSCI call */
378 void arm_handle_psci_call(ARMCPU *cpu);
379 #endif
380
381 #endif