vl: Table-based select_vgahw()
[qemu.git] / target-arm / internals.h
1 /*
2 * QEMU ARM CPU -- internal functions and types
3 *
4 * Copyright (c) 2014 Linaro Ltd
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
19 *
20 * This header defines functions, types, etc which need to be shared
21 * between different source files within target-arm/ but which are
22 * private to it and not required by the rest of QEMU.
23 */
24
25 #ifndef TARGET_ARM_INTERNALS_H
26 #define TARGET_ARM_INTERNALS_H
27
28 /* register banks for CPU modes */
29 #define BANK_USRSYS 0
30 #define BANK_SVC 1
31 #define BANK_ABT 2
32 #define BANK_UND 3
33 #define BANK_IRQ 4
34 #define BANK_FIQ 5
35 #define BANK_HYP 6
36 #define BANK_MON 7
37
38 static inline bool excp_is_internal(int excp)
39 {
40 /* Return true if this exception number represents a QEMU-internal
41 * exception that will not be passed to the guest.
42 */
43 return excp == EXCP_INTERRUPT
44 || excp == EXCP_HLT
45 || excp == EXCP_DEBUG
46 || excp == EXCP_HALTED
47 || excp == EXCP_EXCEPTION_EXIT
48 || excp == EXCP_KERNEL_TRAP
49 || excp == EXCP_SEMIHOST
50 || excp == EXCP_STREX;
51 }
52
53 /* Exception names for debug logging; note that not all of these
54 * precisely correspond to architectural exceptions.
55 */
56 static const char * const excnames[] = {
57 [EXCP_UDEF] = "Undefined Instruction",
58 [EXCP_SWI] = "SVC",
59 [EXCP_PREFETCH_ABORT] = "Prefetch Abort",
60 [EXCP_DATA_ABORT] = "Data Abort",
61 [EXCP_IRQ] = "IRQ",
62 [EXCP_FIQ] = "FIQ",
63 [EXCP_BKPT] = "Breakpoint",
64 [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit",
65 [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage",
66 [EXCP_STREX] = "QEMU intercept of STREX",
67 [EXCP_HVC] = "Hypervisor Call",
68 [EXCP_HYP_TRAP] = "Hypervisor Trap",
69 [EXCP_SMC] = "Secure Monitor Call",
70 [EXCP_VIRQ] = "Virtual IRQ",
71 [EXCP_VFIQ] = "Virtual FIQ",
72 [EXCP_SEMIHOST] = "Semihosting call",
73 };
74
75 /* Scale factor for generic timers, ie number of ns per tick.
76 * This gives a 62.5MHz timer.
77 */
78 #define GTIMER_SCALE 16
79
80 /*
81 * For AArch64, map a given EL to an index in the banked_spsr array.
82 * Note that this mapping and the AArch32 mapping defined in bank_number()
83 * must agree such that the AArch64<->AArch32 SPSRs have the architecturally
84 * mandated mapping between each other.
85 */
86 static inline unsigned int aarch64_banked_spsr_index(unsigned int el)
87 {
88 static const unsigned int map[4] = {
89 [1] = BANK_SVC, /* EL1. */
90 [2] = BANK_HYP, /* EL2. */
91 [3] = BANK_MON, /* EL3. */
92 };
93 assert(el >= 1 && el <= 3);
94 return map[el];
95 }
96
97 /* Map CPU modes onto saved register banks. */
98 static inline int bank_number(int mode)
99 {
100 switch (mode) {
101 case ARM_CPU_MODE_USR:
102 case ARM_CPU_MODE_SYS:
103 return BANK_USRSYS;
104 case ARM_CPU_MODE_SVC:
105 return BANK_SVC;
106 case ARM_CPU_MODE_ABT:
107 return BANK_ABT;
108 case ARM_CPU_MODE_UND:
109 return BANK_UND;
110 case ARM_CPU_MODE_IRQ:
111 return BANK_IRQ;
112 case ARM_CPU_MODE_FIQ:
113 return BANK_FIQ;
114 case ARM_CPU_MODE_HYP:
115 return BANK_HYP;
116 case ARM_CPU_MODE_MON:
117 return BANK_MON;
118 }
119 g_assert_not_reached();
120 }
121
122 void switch_mode(CPUARMState *, int);
123 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);
124 void arm_translate_init(void);
125
126 enum arm_fprounding {
127 FPROUNDING_TIEEVEN,
128 FPROUNDING_POSINF,
129 FPROUNDING_NEGINF,
130 FPROUNDING_ZERO,
131 FPROUNDING_TIEAWAY,
132 FPROUNDING_ODD
133 };
134
135 int arm_rmode_to_sf(int rmode);
136
137 static inline void aarch64_save_sp(CPUARMState *env, int el)
138 {
139 if (env->pstate & PSTATE_SP) {
140 env->sp_el[el] = env->xregs[31];
141 } else {
142 env->sp_el[0] = env->xregs[31];
143 }
144 }
145
146 static inline void aarch64_restore_sp(CPUARMState *env, int el)
147 {
148 if (env->pstate & PSTATE_SP) {
149 env->xregs[31] = env->sp_el[el];
150 } else {
151 env->xregs[31] = env->sp_el[0];
152 }
153 }
154
155 static inline void update_spsel(CPUARMState *env, uint32_t imm)
156 {
157 unsigned int cur_el = arm_current_el(env);
158 /* Update PSTATE SPSel bit; this requires us to update the
159 * working stack pointer in xregs[31].
160 */
161 if (!((imm ^ env->pstate) & PSTATE_SP)) {
162 return;
163 }
164 aarch64_save_sp(env, cur_el);
165 env->pstate = deposit32(env->pstate, 0, 1, imm);
166
167 /* We rely on illegal updates to SPsel from EL0 to get trapped
168 * at translation time.
169 */
170 assert(cur_el >= 1 && cur_el <= 3);
171 aarch64_restore_sp(env, cur_el);
172 }
173
174 /*
175 * arm_pamax
176 * @cpu: ARMCPU
177 *
178 * Returns the implementation defined bit-width of physical addresses.
179 * The ARMv8 reference manuals refer to this as PAMax().
180 */
181 static inline unsigned int arm_pamax(ARMCPU *cpu)
182 {
183 static const unsigned int pamax_map[] = {
184 [0] = 32,
185 [1] = 36,
186 [2] = 40,
187 [3] = 42,
188 [4] = 44,
189 [5] = 48,
190 };
191 unsigned int parange = extract32(cpu->id_aa64mmfr0, 0, 4);
192
193 /* id_aa64mmfr0 is a read-only register so values outside of the
194 * supported mappings can be considered an implementation error. */
195 assert(parange < ARRAY_SIZE(pamax_map));
196 return pamax_map[parange];
197 }
198
199 /* Return true if extended addresses are enabled.
200 * This is always the case if our translation regime is 64 bit,
201 * but depends on TTBCR.EAE for 32 bit.
202 */
203 static inline bool extended_addresses_enabled(CPUARMState *env)
204 {
205 TCR *tcr = &env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1];
206 return arm_el_is_aa64(env, 1) ||
207 (arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EAE));
208 }
209
210 /* Valid Syndrome Register EC field values */
211 enum arm_exception_class {
212 EC_UNCATEGORIZED = 0x00,
213 EC_WFX_TRAP = 0x01,
214 EC_CP15RTTRAP = 0x03,
215 EC_CP15RRTTRAP = 0x04,
216 EC_CP14RTTRAP = 0x05,
217 EC_CP14DTTRAP = 0x06,
218 EC_ADVSIMDFPACCESSTRAP = 0x07,
219 EC_FPIDTRAP = 0x08,
220 EC_CP14RRTTRAP = 0x0c,
221 EC_ILLEGALSTATE = 0x0e,
222 EC_AA32_SVC = 0x11,
223 EC_AA32_HVC = 0x12,
224 EC_AA32_SMC = 0x13,
225 EC_AA64_SVC = 0x15,
226 EC_AA64_HVC = 0x16,
227 EC_AA64_SMC = 0x17,
228 EC_SYSTEMREGISTERTRAP = 0x18,
229 EC_INSNABORT = 0x20,
230 EC_INSNABORT_SAME_EL = 0x21,
231 EC_PCALIGNMENT = 0x22,
232 EC_DATAABORT = 0x24,
233 EC_DATAABORT_SAME_EL = 0x25,
234 EC_SPALIGNMENT = 0x26,
235 EC_AA32_FPTRAP = 0x28,
236 EC_AA64_FPTRAP = 0x2c,
237 EC_SERROR = 0x2f,
238 EC_BREAKPOINT = 0x30,
239 EC_BREAKPOINT_SAME_EL = 0x31,
240 EC_SOFTWARESTEP = 0x32,
241 EC_SOFTWARESTEP_SAME_EL = 0x33,
242 EC_WATCHPOINT = 0x34,
243 EC_WATCHPOINT_SAME_EL = 0x35,
244 EC_AA32_BKPT = 0x38,
245 EC_VECTORCATCH = 0x3a,
246 EC_AA64_BKPT = 0x3c,
247 };
248
249 #define ARM_EL_EC_SHIFT 26
250 #define ARM_EL_IL_SHIFT 25
251 #define ARM_EL_ISV_SHIFT 24
252 #define ARM_EL_IL (1 << ARM_EL_IL_SHIFT)
253 #define ARM_EL_ISV (1 << ARM_EL_ISV_SHIFT)
254
255 /* Utility functions for constructing various kinds of syndrome value.
256 * Note that in general we follow the AArch64 syndrome values; in a
257 * few cases the value in HSR for exceptions taken to AArch32 Hyp
258 * mode differs slightly, so if we ever implemented Hyp mode then the
259 * syndrome value would need some massaging on exception entry.
260 * (One example of this is that AArch64 defaults to IL bit set for
261 * exceptions which don't specifically indicate information about the
262 * trapping instruction, whereas AArch32 defaults to IL bit clear.)
263 */
264 static inline uint32_t syn_uncategorized(void)
265 {
266 return (EC_UNCATEGORIZED << ARM_EL_EC_SHIFT) | ARM_EL_IL;
267 }
268
269 static inline uint32_t syn_aa64_svc(uint32_t imm16)
270 {
271 return (EC_AA64_SVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
272 }
273
274 static inline uint32_t syn_aa64_hvc(uint32_t imm16)
275 {
276 return (EC_AA64_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
277 }
278
279 static inline uint32_t syn_aa64_smc(uint32_t imm16)
280 {
281 return (EC_AA64_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
282 }
283
284 static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_16bit)
285 {
286 return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | (imm16 & 0xffff)
287 | (is_16bit ? 0 : ARM_EL_IL);
288 }
289
290 static inline uint32_t syn_aa32_hvc(uint32_t imm16)
291 {
292 return (EC_AA32_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
293 }
294
295 static inline uint32_t syn_aa32_smc(void)
296 {
297 return (EC_AA32_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL;
298 }
299
300 static inline uint32_t syn_aa64_bkpt(uint32_t imm16)
301 {
302 return (EC_AA64_BKPT << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
303 }
304
305 static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_16bit)
306 {
307 return (EC_AA32_BKPT << ARM_EL_EC_SHIFT) | (imm16 & 0xffff)
308 | (is_16bit ? 0 : ARM_EL_IL);
309 }
310
311 static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2,
312 int crn, int crm, int rt,
313 int isread)
314 {
315 return (EC_SYSTEMREGISTERTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL
316 | (op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (rt << 5)
317 | (crm << 1) | isread;
318 }
319
320 static inline uint32_t syn_cp14_rt_trap(int cv, int cond, int opc1, int opc2,
321 int crn, int crm, int rt, int isread,
322 bool is_16bit)
323 {
324 return (EC_CP14RTTRAP << ARM_EL_EC_SHIFT)
325 | (is_16bit ? 0 : ARM_EL_IL)
326 | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14)
327 | (crn << 10) | (rt << 5) | (crm << 1) | isread;
328 }
329
330 static inline uint32_t syn_cp15_rt_trap(int cv, int cond, int opc1, int opc2,
331 int crn, int crm, int rt, int isread,
332 bool is_16bit)
333 {
334 return (EC_CP15RTTRAP << ARM_EL_EC_SHIFT)
335 | (is_16bit ? 0 : ARM_EL_IL)
336 | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14)
337 | (crn << 10) | (rt << 5) | (crm << 1) | isread;
338 }
339
340 static inline uint32_t syn_cp14_rrt_trap(int cv, int cond, int opc1, int crm,
341 int rt, int rt2, int isread,
342 bool is_16bit)
343 {
344 return (EC_CP14RRTTRAP << ARM_EL_EC_SHIFT)
345 | (is_16bit ? 0 : ARM_EL_IL)
346 | (cv << 24) | (cond << 20) | (opc1 << 16)
347 | (rt2 << 10) | (rt << 5) | (crm << 1) | isread;
348 }
349
350 static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm,
351 int rt, int rt2, int isread,
352 bool is_16bit)
353 {
354 return (EC_CP15RRTTRAP << ARM_EL_EC_SHIFT)
355 | (is_16bit ? 0 : ARM_EL_IL)
356 | (cv << 24) | (cond << 20) | (opc1 << 16)
357 | (rt2 << 10) | (rt << 5) | (crm << 1) | isread;
358 }
359
360 static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit)
361 {
362 return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT)
363 | (is_16bit ? 0 : ARM_EL_IL)
364 | (cv << 24) | (cond << 20);
365 }
366
367 static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc)
368 {
369 return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
370 | (ea << 9) | (s1ptw << 7) | fsc;
371 }
372
373 static inline uint32_t syn_data_abort_no_iss(int same_el,
374 int ea, int cm, int s1ptw,
375 int wnr, int fsc)
376 {
377 return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
378 | ARM_EL_IL
379 | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc;
380 }
381
382 static inline uint32_t syn_data_abort_with_iss(int same_el,
383 int sas, int sse, int srt,
384 int sf, int ar,
385 int ea, int cm, int s1ptw,
386 int wnr, int fsc,
387 bool is_16bit)
388 {
389 return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
390 | (is_16bit ? 0 : ARM_EL_IL)
391 | ARM_EL_ISV | (sas << 22) | (sse << 21) | (srt << 16)
392 | (sf << 15) | (ar << 14)
393 | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc;
394 }
395
396 static inline uint32_t syn_swstep(int same_el, int isv, int ex)
397 {
398 return (EC_SOFTWARESTEP << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
399 | (isv << 24) | (ex << 6) | 0x22;
400 }
401
402 static inline uint32_t syn_watchpoint(int same_el, int cm, int wnr)
403 {
404 return (EC_WATCHPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
405 | (cm << 8) | (wnr << 6) | 0x22;
406 }
407
408 static inline uint32_t syn_breakpoint(int same_el)
409 {
410 return (EC_BREAKPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
411 | ARM_EL_IL | 0x22;
412 }
413
414 static inline uint32_t syn_wfx(int cv, int cond, int ti)
415 {
416 return (EC_WFX_TRAP << ARM_EL_EC_SHIFT) |
417 (cv << 24) | (cond << 20) | ti;
418 }
419
420 /* Update a QEMU watchpoint based on the information the guest has set in the
421 * DBGWCR<n>_EL1 and DBGWVR<n>_EL1 registers.
422 */
423 void hw_watchpoint_update(ARMCPU *cpu, int n);
424 /* Update the QEMU watchpoints for every guest watchpoint. This does a
425 * complete delete-and-reinstate of the QEMU watchpoint list and so is
426 * suitable for use after migration or on reset.
427 */
428 void hw_watchpoint_update_all(ARMCPU *cpu);
429 /* Update a QEMU breakpoint based on the information the guest has set in the
430 * DBGBCR<n>_EL1 and DBGBVR<n>_EL1 registers.
431 */
432 void hw_breakpoint_update(ARMCPU *cpu, int n);
433 /* Update the QEMU breakpoints for every guest breakpoint. This does a
434 * complete delete-and-reinstate of the QEMU breakpoint list and so is
435 * suitable for use after migration or on reset.
436 */
437 void hw_breakpoint_update_all(ARMCPU *cpu);
438
439 /* Callback function for checking if a watchpoint should trigger. */
440 bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
441
442 /* Callback function for when a watchpoint or breakpoint triggers. */
443 void arm_debug_excp_handler(CPUState *cs);
444
445 #ifdef CONFIG_USER_ONLY
446 static inline bool arm_is_psci_call(ARMCPU *cpu, int excp_type)
447 {
448 return false;
449 }
450 #else
451 /* Return true if the r0/x0 value indicates that this SMC/HVC is a PSCI call. */
452 bool arm_is_psci_call(ARMCPU *cpu, int excp_type);
453 /* Actually handle a PSCI call */
454 void arm_handle_psci_call(ARMCPU *cpu);
455 #endif
456
457 /**
458 * ARMMMUFaultInfo: Information describing an ARM MMU Fault
459 * @s2addr: Address that caused a fault at stage 2
460 * @stage2: True if we faulted at stage 2
461 * @s1ptw: True if we faulted at stage 2 while doing a stage 1 page-table walk
462 */
463 typedef struct ARMMMUFaultInfo ARMMMUFaultInfo;
464 struct ARMMMUFaultInfo {
465 target_ulong s2addr;
466 bool stage2;
467 bool s1ptw;
468 };
469
470 /* Do a page table walk and add page to TLB if possible */
471 bool arm_tlb_fill(CPUState *cpu, vaddr address, int rw, int mmu_idx,
472 uint32_t *fsr, ARMMMUFaultInfo *fi);
473
474 /* Return true if the stage 1 translation regime is using LPAE format page
475 * tables */
476 bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx);
477
478 /* Raise a data fault alignment exception for the specified virtual address */
479 void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, int is_write,
480 int is_user, uintptr_t retaddr);
481
482 #endif