hw/arm/virt: Add PMU node for virt machine
[qemu.git] / target-arm / kvm64.c
1 /*
2 * ARM implementation of KVM hooks, 64 bit specific code
3 *
4 * Copyright Mian-M. Hamayun 2013, Virtual Open Systems
5 * Copyright Alex Bennée 2014, Linaro
6 *
7 * This work is licensed under the terms of the GNU GPL, version 2 or later.
8 * See the COPYING file in the top-level directory.
9 *
10 */
11
12 #include "qemu/osdep.h"
13 #include <sys/ioctl.h>
14 #include <sys/mman.h>
15 #include <sys/ptrace.h>
16
17 #include <linux/elf.h>
18 #include <linux/kvm.h>
19
20 #include "qemu-common.h"
21 #include "cpu.h"
22 #include "qemu/timer.h"
23 #include "qemu/error-report.h"
24 #include "qemu/host-utils.h"
25 #include "exec/gdbstub.h"
26 #include "sysemu/sysemu.h"
27 #include "sysemu/kvm.h"
28 #include "kvm_arm.h"
29 #include "internals.h"
30 #include "hw/arm/arm.h"
31
32 static bool have_guest_debug;
33
34 /*
35 * Although the ARM implementation of hardware assisted debugging
36 * allows for different breakpoints per-core, the current GDB
37 * interface treats them as a global pool of registers (which seems to
38 * be the case for x86, ppc and s390). As a result we store one copy
39 * of registers which is used for all active cores.
40 *
41 * Write access is serialised by virtue of the GDB protocol which
42 * updates things. Read access (i.e. when the values are copied to the
43 * vCPU) is also gated by GDB's run control.
44 *
45 * This is not unreasonable as most of the time debugging kernels you
46 * never know which core will eventually execute your function.
47 */
48
49 typedef struct {
50 uint64_t bcr;
51 uint64_t bvr;
52 } HWBreakpoint;
53
54 /* The watchpoint registers can cover more area than the requested
55 * watchpoint so we need to store the additional information
56 * somewhere. We also need to supply a CPUWatchpoint to the GDB stub
57 * when the watchpoint is hit.
58 */
59 typedef struct {
60 uint64_t wcr;
61 uint64_t wvr;
62 CPUWatchpoint details;
63 } HWWatchpoint;
64
65 /* Maximum and current break/watch point counts */
66 int max_hw_bps, max_hw_wps;
67 GArray *hw_breakpoints, *hw_watchpoints;
68
69 #define cur_hw_wps (hw_watchpoints->len)
70 #define cur_hw_bps (hw_breakpoints->len)
71 #define get_hw_bp(i) (&g_array_index(hw_breakpoints, HWBreakpoint, i))
72 #define get_hw_wp(i) (&g_array_index(hw_watchpoints, HWWatchpoint, i))
73
74 /**
75 * kvm_arm_init_debug() - check for guest debug capabilities
76 * @cs: CPUState
77 *
78 * kvm_check_extension returns the number of debug registers we have
79 * or 0 if we have none.
80 *
81 */
82 static void kvm_arm_init_debug(CPUState *cs)
83 {
84 have_guest_debug = kvm_check_extension(cs->kvm_state,
85 KVM_CAP_SET_GUEST_DEBUG);
86
87 max_hw_wps = kvm_check_extension(cs->kvm_state, KVM_CAP_GUEST_DEBUG_HW_WPS);
88 hw_watchpoints = g_array_sized_new(true, true,
89 sizeof(HWWatchpoint), max_hw_wps);
90
91 max_hw_bps = kvm_check_extension(cs->kvm_state, KVM_CAP_GUEST_DEBUG_HW_BPS);
92 hw_breakpoints = g_array_sized_new(true, true,
93 sizeof(HWBreakpoint), max_hw_bps);
94 return;
95 }
96
97 /**
98 * insert_hw_breakpoint()
99 * @addr: address of breakpoint
100 *
101 * See ARM ARM D2.9.1 for details but here we are only going to create
102 * simple un-linked breakpoints (i.e. we don't chain breakpoints
103 * together to match address and context or vmid). The hardware is
104 * capable of fancier matching but that will require exposing that
105 * fanciness to GDB's interface
106 *
107 * D7.3.2 DBGBCR<n>_EL1, Debug Breakpoint Control Registers
108 *
109 * 31 24 23 20 19 16 15 14 13 12 9 8 5 4 3 2 1 0
110 * +------+------+-------+-----+----+------+-----+------+-----+---+
111 * | RES0 | BT | LBN | SSC | HMC| RES0 | BAS | RES0 | PMC | E |
112 * +------+------+-------+-----+----+------+-----+------+-----+---+
113 *
114 * BT: Breakpoint type (0 = unlinked address match)
115 * LBN: Linked BP number (0 = unused)
116 * SSC/HMC/PMC: Security, Higher and Priv access control (Table D-12)
117 * BAS: Byte Address Select (RES1 for AArch64)
118 * E: Enable bit
119 */
120 static int insert_hw_breakpoint(target_ulong addr)
121 {
122 HWBreakpoint brk = {
123 .bcr = 0x1, /* BCR E=1, enable */
124 .bvr = addr
125 };
126
127 if (cur_hw_bps >= max_hw_bps) {
128 return -ENOBUFS;
129 }
130
131 brk.bcr = deposit32(brk.bcr, 1, 2, 0x3); /* PMC = 11 */
132 brk.bcr = deposit32(brk.bcr, 5, 4, 0xf); /* BAS = RES1 */
133
134 g_array_append_val(hw_breakpoints, brk);
135
136 return 0;
137 }
138
139 /**
140 * delete_hw_breakpoint()
141 * @pc: address of breakpoint
142 *
143 * Delete a breakpoint and shuffle any above down
144 */
145
146 static int delete_hw_breakpoint(target_ulong pc)
147 {
148 int i;
149 for (i = 0; i < hw_breakpoints->len; i++) {
150 HWBreakpoint *brk = get_hw_bp(i);
151 if (brk->bvr == pc) {
152 g_array_remove_index(hw_breakpoints, i);
153 return 0;
154 }
155 }
156 return -ENOENT;
157 }
158
159 /**
160 * insert_hw_watchpoint()
161 * @addr: address of watch point
162 * @len: size of area
163 * @type: type of watch point
164 *
165 * See ARM ARM D2.10. As with the breakpoints we can do some advanced
166 * stuff if we want to. The watch points can be linked with the break
167 * points above to make them context aware. However for simplicity
168 * currently we only deal with simple read/write watch points.
169 *
170 * D7.3.11 DBGWCR<n>_EL1, Debug Watchpoint Control Registers
171 *
172 * 31 29 28 24 23 21 20 19 16 15 14 13 12 5 4 3 2 1 0
173 * +------+-------+------+----+-----+-----+-----+-----+-----+-----+---+
174 * | RES0 | MASK | RES0 | WT | LBN | SSC | HMC | BAS | LSC | PAC | E |
175 * +------+-------+------+----+-----+-----+-----+-----+-----+-----+---+
176 *
177 * MASK: num bits addr mask (0=none,01/10=res,11=3 bits (8 bytes))
178 * WT: 0 - unlinked, 1 - linked (not currently used)
179 * LBN: Linked BP number (not currently used)
180 * SSC/HMC/PAC: Security, Higher and Priv access control (Table D2-11)
181 * BAS: Byte Address Select
182 * LSC: Load/Store control (01: load, 10: store, 11: both)
183 * E: Enable
184 *
185 * The bottom 2 bits of the value register are masked. Therefore to
186 * break on any sizes smaller than an unaligned word you need to set
187 * MASK=0, BAS=bit per byte in question. For larger regions (^2) you
188 * need to ensure you mask the address as required and set BAS=0xff
189 */
190
191 static int insert_hw_watchpoint(target_ulong addr,
192 target_ulong len, int type)
193 {
194 HWWatchpoint wp = {
195 .wcr = 1, /* E=1, enable */
196 .wvr = addr & (~0x7ULL),
197 .details = { .vaddr = addr, .len = len }
198 };
199
200 if (cur_hw_wps >= max_hw_wps) {
201 return -ENOBUFS;
202 }
203
204 /*
205 * HMC=0 SSC=0 PAC=3 will hit EL0 or EL1, any security state,
206 * valid whether EL3 is implemented or not
207 */
208 wp.wcr = deposit32(wp.wcr, 1, 2, 3);
209
210 switch (type) {
211 case GDB_WATCHPOINT_READ:
212 wp.wcr = deposit32(wp.wcr, 3, 2, 1);
213 wp.details.flags = BP_MEM_READ;
214 break;
215 case GDB_WATCHPOINT_WRITE:
216 wp.wcr = deposit32(wp.wcr, 3, 2, 2);
217 wp.details.flags = BP_MEM_WRITE;
218 break;
219 case GDB_WATCHPOINT_ACCESS:
220 wp.wcr = deposit32(wp.wcr, 3, 2, 3);
221 wp.details.flags = BP_MEM_ACCESS;
222 break;
223 default:
224 g_assert_not_reached();
225 break;
226 }
227 if (len <= 8) {
228 /* we align the address and set the bits in BAS */
229 int off = addr & 0x7;
230 int bas = (1 << len) - 1;
231
232 wp.wcr = deposit32(wp.wcr, 5 + off, 8 - off, bas);
233 } else {
234 /* For ranges above 8 bytes we need to be a power of 2 */
235 if (is_power_of_2(len)) {
236 int bits = ctz64(len);
237
238 wp.wvr &= ~((1 << bits) - 1);
239 wp.wcr = deposit32(wp.wcr, 24, 4, bits);
240 wp.wcr = deposit32(wp.wcr, 5, 8, 0xff);
241 } else {
242 return -ENOBUFS;
243 }
244 }
245
246 g_array_append_val(hw_watchpoints, wp);
247 return 0;
248 }
249
250
251 static bool check_watchpoint_in_range(int i, target_ulong addr)
252 {
253 HWWatchpoint *wp = get_hw_wp(i);
254 uint64_t addr_top, addr_bottom = wp->wvr;
255 int bas = extract32(wp->wcr, 5, 8);
256 int mask = extract32(wp->wcr, 24, 4);
257
258 if (mask) {
259 addr_top = addr_bottom + (1 << mask);
260 } else {
261 /* BAS must be contiguous but can offset against the base
262 * address in DBGWVR */
263 addr_bottom = addr_bottom + ctz32(bas);
264 addr_top = addr_bottom + clo32(bas);
265 }
266
267 if (addr >= addr_bottom && addr <= addr_top) {
268 return true;
269 }
270
271 return false;
272 }
273
274 /**
275 * delete_hw_watchpoint()
276 * @addr: address of breakpoint
277 *
278 * Delete a breakpoint and shuffle any above down
279 */
280
281 static int delete_hw_watchpoint(target_ulong addr,
282 target_ulong len, int type)
283 {
284 int i;
285 for (i = 0; i < cur_hw_wps; i++) {
286 if (check_watchpoint_in_range(i, addr)) {
287 g_array_remove_index(hw_watchpoints, i);
288 return 0;
289 }
290 }
291 return -ENOENT;
292 }
293
294
295 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
296 target_ulong len, int type)
297 {
298 switch (type) {
299 case GDB_BREAKPOINT_HW:
300 return insert_hw_breakpoint(addr);
301 break;
302 case GDB_WATCHPOINT_READ:
303 case GDB_WATCHPOINT_WRITE:
304 case GDB_WATCHPOINT_ACCESS:
305 return insert_hw_watchpoint(addr, len, type);
306 default:
307 return -ENOSYS;
308 }
309 }
310
311 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
312 target_ulong len, int type)
313 {
314 switch (type) {
315 case GDB_BREAKPOINT_HW:
316 return delete_hw_breakpoint(addr);
317 break;
318 case GDB_WATCHPOINT_READ:
319 case GDB_WATCHPOINT_WRITE:
320 case GDB_WATCHPOINT_ACCESS:
321 return delete_hw_watchpoint(addr, len, type);
322 default:
323 return -ENOSYS;
324 }
325 }
326
327
328 void kvm_arch_remove_all_hw_breakpoints(void)
329 {
330 if (cur_hw_wps > 0) {
331 g_array_remove_range(hw_watchpoints, 0, cur_hw_wps);
332 }
333 if (cur_hw_bps > 0) {
334 g_array_remove_range(hw_breakpoints, 0, cur_hw_bps);
335 }
336 }
337
338 void kvm_arm_copy_hw_debug_data(struct kvm_guest_debug_arch *ptr)
339 {
340 int i;
341 memset(ptr, 0, sizeof(struct kvm_guest_debug_arch));
342
343 for (i = 0; i < max_hw_wps; i++) {
344 HWWatchpoint *wp = get_hw_wp(i);
345 ptr->dbg_wcr[i] = wp->wcr;
346 ptr->dbg_wvr[i] = wp->wvr;
347 }
348 for (i = 0; i < max_hw_bps; i++) {
349 HWBreakpoint *bp = get_hw_bp(i);
350 ptr->dbg_bcr[i] = bp->bcr;
351 ptr->dbg_bvr[i] = bp->bvr;
352 }
353 }
354
355 bool kvm_arm_hw_debug_active(CPUState *cs)
356 {
357 return ((cur_hw_wps > 0) || (cur_hw_bps > 0));
358 }
359
360 static bool find_hw_breakpoint(CPUState *cpu, target_ulong pc)
361 {
362 int i;
363
364 for (i = 0; i < cur_hw_bps; i++) {
365 HWBreakpoint *bp = get_hw_bp(i);
366 if (bp->bvr == pc) {
367 return true;
368 }
369 }
370 return false;
371 }
372
373 static CPUWatchpoint *find_hw_watchpoint(CPUState *cpu, target_ulong addr)
374 {
375 int i;
376
377 for (i = 0; i < cur_hw_wps; i++) {
378 if (check_watchpoint_in_range(i, addr)) {
379 return &get_hw_wp(i)->details;
380 }
381 }
382 return NULL;
383 }
384
385 static bool kvm_arm_pmu_support_ctrl(CPUState *cs, struct kvm_device_attr *attr)
386 {
387 return kvm_vcpu_ioctl(cs, KVM_HAS_DEVICE_ATTR, attr) == 0;
388 }
389
390 int kvm_arm_pmu_create(CPUState *cs, int irq)
391 {
392 int err;
393
394 struct kvm_device_attr attr = {
395 .group = KVM_ARM_VCPU_PMU_V3_CTRL,
396 .addr = (intptr_t)&irq,
397 .attr = KVM_ARM_VCPU_PMU_V3_IRQ,
398 .flags = 0,
399 };
400
401 if (!kvm_arm_pmu_support_ctrl(cs, &attr)) {
402 return 0;
403 }
404
405 err = kvm_vcpu_ioctl(cs, KVM_SET_DEVICE_ATTR, &attr);
406 if (err < 0) {
407 fprintf(stderr, "KVM_SET_DEVICE_ATTR failed: %s\n",
408 strerror(-err));
409 abort();
410 }
411
412 attr.group = KVM_ARM_VCPU_PMU_V3_CTRL;
413 attr.attr = KVM_ARM_VCPU_PMU_V3_INIT;
414 attr.addr = 0;
415 attr.flags = 0;
416
417 err = kvm_vcpu_ioctl(cs, KVM_SET_DEVICE_ATTR, &attr);
418 if (err < 0) {
419 fprintf(stderr, "KVM_SET_DEVICE_ATTR failed: %s\n",
420 strerror(-err));
421 abort();
422 }
423
424 return 1;
425 }
426
427 static inline void set_feature(uint64_t *features, int feature)
428 {
429 *features |= 1ULL << feature;
430 }
431
432 bool kvm_arm_get_host_cpu_features(ARMHostCPUClass *ahcc)
433 {
434 /* Identify the feature bits corresponding to the host CPU, and
435 * fill out the ARMHostCPUClass fields accordingly. To do this
436 * we have to create a scratch VM, create a single CPU inside it,
437 * and then query that CPU for the relevant ID registers.
438 * For AArch64 we currently don't care about ID registers at
439 * all; we just want to know the CPU type.
440 */
441 int fdarray[3];
442 uint64_t features = 0;
443 /* Old kernels may not know about the PREFERRED_TARGET ioctl: however
444 * we know these will only support creating one kind of guest CPU,
445 * which is its preferred CPU type. Fortunately these old kernels
446 * support only a very limited number of CPUs.
447 */
448 static const uint32_t cpus_to_try[] = {
449 KVM_ARM_TARGET_AEM_V8,
450 KVM_ARM_TARGET_FOUNDATION_V8,
451 KVM_ARM_TARGET_CORTEX_A57,
452 QEMU_KVM_ARM_TARGET_NONE
453 };
454 struct kvm_vcpu_init init;
455
456 if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) {
457 return false;
458 }
459
460 ahcc->target = init.target;
461 ahcc->dtb_compatible = "arm,arm-v8";
462
463 kvm_arm_destroy_scratch_host_vcpu(fdarray);
464
465 /* We can assume any KVM supporting CPU is at least a v8
466 * with VFPv4+Neon; this in turn implies most of the other
467 * feature bits.
468 */
469 set_feature(&features, ARM_FEATURE_V8);
470 set_feature(&features, ARM_FEATURE_VFP4);
471 set_feature(&features, ARM_FEATURE_NEON);
472 set_feature(&features, ARM_FEATURE_AARCH64);
473
474 ahcc->features = features;
475
476 return true;
477 }
478
479 #define ARM_CPU_ID_MPIDR 3, 0, 0, 0, 5
480
481 int kvm_arch_init_vcpu(CPUState *cs)
482 {
483 int ret;
484 uint64_t mpidr;
485 ARMCPU *cpu = ARM_CPU(cs);
486
487 if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE ||
488 !object_dynamic_cast(OBJECT(cpu), TYPE_AARCH64_CPU)) {
489 fprintf(stderr, "KVM is not supported for this guest CPU type\n");
490 return -EINVAL;
491 }
492
493 /* Determine init features for this CPU */
494 memset(cpu->kvm_init_features, 0, sizeof(cpu->kvm_init_features));
495 if (cpu->start_powered_off) {
496 cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_POWER_OFF;
497 }
498 if (kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PSCI_0_2)) {
499 cpu->psci_version = 2;
500 cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PSCI_0_2;
501 }
502 if (!arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
503 cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_EL1_32BIT;
504 }
505 if (kvm_irqchip_in_kernel() &&
506 kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PMU_V3)) {
507 cpu->has_pmu = true;
508 cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PMU_V3;
509 }
510
511 /* Do KVM_ARM_VCPU_INIT ioctl */
512 ret = kvm_arm_vcpu_init(cs);
513 if (ret) {
514 return ret;
515 }
516
517 /*
518 * When KVM is in use, PSCI is emulated in-kernel and not by qemu.
519 * Currently KVM has its own idea about MPIDR assignment, so we
520 * override our defaults with what we get from KVM.
521 */
522 ret = kvm_get_one_reg(cs, ARM64_SYS_REG(ARM_CPU_ID_MPIDR), &mpidr);
523 if (ret) {
524 return ret;
525 }
526 cpu->mp_affinity = mpidr & ARM64_AFFINITY_MASK;
527
528 kvm_arm_init_debug(cs);
529
530 return kvm_arm_init_cpreg_list(cpu);
531 }
532
533 bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx)
534 {
535 /* Return true if the regidx is a register we should synchronize
536 * via the cpreg_tuples array (ie is not a core reg we sync by
537 * hand in kvm_arch_get/put_registers())
538 */
539 switch (regidx & KVM_REG_ARM_COPROC_MASK) {
540 case KVM_REG_ARM_CORE:
541 return false;
542 default:
543 return true;
544 }
545 }
546
547 typedef struct CPRegStateLevel {
548 uint64_t regidx;
549 int level;
550 } CPRegStateLevel;
551
552 /* All system registers not listed in the following table are assumed to be
553 * of the level KVM_PUT_RUNTIME_STATE. If a register should be written less
554 * often, you must add it to this table with a state of either
555 * KVM_PUT_RESET_STATE or KVM_PUT_FULL_STATE.
556 */
557 static const CPRegStateLevel non_runtime_cpregs[] = {
558 { KVM_REG_ARM_TIMER_CNT, KVM_PUT_FULL_STATE },
559 };
560
561 int kvm_arm_cpreg_level(uint64_t regidx)
562 {
563 int i;
564
565 for (i = 0; i < ARRAY_SIZE(non_runtime_cpregs); i++) {
566 const CPRegStateLevel *l = &non_runtime_cpregs[i];
567 if (l->regidx == regidx) {
568 return l->level;
569 }
570 }
571
572 return KVM_PUT_RUNTIME_STATE;
573 }
574
575 #define AARCH64_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \
576 KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x))
577
578 #define AARCH64_SIMD_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U128 | \
579 KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x))
580
581 #define AARCH64_SIMD_CTRL_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U32 | \
582 KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x))
583
584 int kvm_arch_put_registers(CPUState *cs, int level)
585 {
586 struct kvm_one_reg reg;
587 uint32_t fpr;
588 uint64_t val;
589 int i;
590 int ret;
591 unsigned int el;
592
593 ARMCPU *cpu = ARM_CPU(cs);
594 CPUARMState *env = &cpu->env;
595
596 /* If we are in AArch32 mode then we need to copy the AArch32 regs to the
597 * AArch64 registers before pushing them out to 64-bit KVM.
598 */
599 if (!is_a64(env)) {
600 aarch64_sync_32_to_64(env);
601 }
602
603 for (i = 0; i < 31; i++) {
604 reg.id = AARCH64_CORE_REG(regs.regs[i]);
605 reg.addr = (uintptr_t) &env->xregs[i];
606 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
607 if (ret) {
608 return ret;
609 }
610 }
611
612 /* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the
613 * QEMU side we keep the current SP in xregs[31] as well.
614 */
615 aarch64_save_sp(env, 1);
616
617 reg.id = AARCH64_CORE_REG(regs.sp);
618 reg.addr = (uintptr_t) &env->sp_el[0];
619 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
620 if (ret) {
621 return ret;
622 }
623
624 reg.id = AARCH64_CORE_REG(sp_el1);
625 reg.addr = (uintptr_t) &env->sp_el[1];
626 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
627 if (ret) {
628 return ret;
629 }
630
631 /* Note that KVM thinks pstate is 64 bit but we use a uint32_t */
632 if (is_a64(env)) {
633 val = pstate_read(env);
634 } else {
635 val = cpsr_read(env);
636 }
637 reg.id = AARCH64_CORE_REG(regs.pstate);
638 reg.addr = (uintptr_t) &val;
639 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
640 if (ret) {
641 return ret;
642 }
643
644 reg.id = AARCH64_CORE_REG(regs.pc);
645 reg.addr = (uintptr_t) &env->pc;
646 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
647 if (ret) {
648 return ret;
649 }
650
651 reg.id = AARCH64_CORE_REG(elr_el1);
652 reg.addr = (uintptr_t) &env->elr_el[1];
653 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
654 if (ret) {
655 return ret;
656 }
657
658 /* Saved Program State Registers
659 *
660 * Before we restore from the banked_spsr[] array we need to
661 * ensure that any modifications to env->spsr are correctly
662 * reflected in the banks.
663 */
664 el = arm_current_el(env);
665 if (el > 0 && !is_a64(env)) {
666 i = bank_number(env->uncached_cpsr & CPSR_M);
667 env->banked_spsr[i] = env->spsr;
668 }
669
670 /* KVM 0-4 map to QEMU banks 1-5 */
671 for (i = 0; i < KVM_NR_SPSR; i++) {
672 reg.id = AARCH64_CORE_REG(spsr[i]);
673 reg.addr = (uintptr_t) &env->banked_spsr[i + 1];
674 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
675 if (ret) {
676 return ret;
677 }
678 }
679
680 /* Advanced SIMD and FP registers
681 * We map Qn = regs[2n+1]:regs[2n]
682 */
683 for (i = 0; i < 32; i++) {
684 int rd = i << 1;
685 uint64_t fp_val[2];
686 #ifdef HOST_WORDS_BIGENDIAN
687 fp_val[0] = env->vfp.regs[rd + 1];
688 fp_val[1] = env->vfp.regs[rd];
689 #else
690 fp_val[1] = env->vfp.regs[rd + 1];
691 fp_val[0] = env->vfp.regs[rd];
692 #endif
693 reg.id = AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]);
694 reg.addr = (uintptr_t)(&fp_val);
695 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
696 if (ret) {
697 return ret;
698 }
699 }
700
701 reg.addr = (uintptr_t)(&fpr);
702 fpr = vfp_get_fpsr(env);
703 reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpsr);
704 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
705 if (ret) {
706 return ret;
707 }
708
709 fpr = vfp_get_fpcr(env);
710 reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpcr);
711 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
712 if (ret) {
713 return ret;
714 }
715
716 if (!write_list_to_kvmstate(cpu, level)) {
717 return EINVAL;
718 }
719
720 kvm_arm_sync_mpstate_to_kvm(cpu);
721
722 return ret;
723 }
724
725 int kvm_arch_get_registers(CPUState *cs)
726 {
727 struct kvm_one_reg reg;
728 uint64_t val;
729 uint32_t fpr;
730 unsigned int el;
731 int i;
732 int ret;
733
734 ARMCPU *cpu = ARM_CPU(cs);
735 CPUARMState *env = &cpu->env;
736
737 for (i = 0; i < 31; i++) {
738 reg.id = AARCH64_CORE_REG(regs.regs[i]);
739 reg.addr = (uintptr_t) &env->xregs[i];
740 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
741 if (ret) {
742 return ret;
743 }
744 }
745
746 reg.id = AARCH64_CORE_REG(regs.sp);
747 reg.addr = (uintptr_t) &env->sp_el[0];
748 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
749 if (ret) {
750 return ret;
751 }
752
753 reg.id = AARCH64_CORE_REG(sp_el1);
754 reg.addr = (uintptr_t) &env->sp_el[1];
755 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
756 if (ret) {
757 return ret;
758 }
759
760 reg.id = AARCH64_CORE_REG(regs.pstate);
761 reg.addr = (uintptr_t) &val;
762 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
763 if (ret) {
764 return ret;
765 }
766
767 env->aarch64 = ((val & PSTATE_nRW) == 0);
768 if (is_a64(env)) {
769 pstate_write(env, val);
770 } else {
771 cpsr_write(env, val, 0xffffffff, CPSRWriteRaw);
772 }
773
774 /* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the
775 * QEMU side we keep the current SP in xregs[31] as well.
776 */
777 aarch64_restore_sp(env, 1);
778
779 reg.id = AARCH64_CORE_REG(regs.pc);
780 reg.addr = (uintptr_t) &env->pc;
781 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
782 if (ret) {
783 return ret;
784 }
785
786 /* If we are in AArch32 mode then we need to sync the AArch32 regs with the
787 * incoming AArch64 regs received from 64-bit KVM.
788 * We must perform this after all of the registers have been acquired from
789 * the kernel.
790 */
791 if (!is_a64(env)) {
792 aarch64_sync_64_to_32(env);
793 }
794
795 reg.id = AARCH64_CORE_REG(elr_el1);
796 reg.addr = (uintptr_t) &env->elr_el[1];
797 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
798 if (ret) {
799 return ret;
800 }
801
802 /* Fetch the SPSR registers
803 *
804 * KVM SPSRs 0-4 map to QEMU banks 1-5
805 */
806 for (i = 0; i < KVM_NR_SPSR; i++) {
807 reg.id = AARCH64_CORE_REG(spsr[i]);
808 reg.addr = (uintptr_t) &env->banked_spsr[i + 1];
809 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
810 if (ret) {
811 return ret;
812 }
813 }
814
815 el = arm_current_el(env);
816 if (el > 0 && !is_a64(env)) {
817 i = bank_number(env->uncached_cpsr & CPSR_M);
818 env->spsr = env->banked_spsr[i];
819 }
820
821 /* Advanced SIMD and FP registers
822 * We map Qn = regs[2n+1]:regs[2n]
823 */
824 for (i = 0; i < 32; i++) {
825 uint64_t fp_val[2];
826 reg.id = AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]);
827 reg.addr = (uintptr_t)(&fp_val);
828 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
829 if (ret) {
830 return ret;
831 } else {
832 int rd = i << 1;
833 #ifdef HOST_WORDS_BIGENDIAN
834 env->vfp.regs[rd + 1] = fp_val[0];
835 env->vfp.regs[rd] = fp_val[1];
836 #else
837 env->vfp.regs[rd + 1] = fp_val[1];
838 env->vfp.regs[rd] = fp_val[0];
839 #endif
840 }
841 }
842
843 reg.addr = (uintptr_t)(&fpr);
844 reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpsr);
845 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
846 if (ret) {
847 return ret;
848 }
849 vfp_set_fpsr(env, fpr);
850
851 reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpcr);
852 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
853 if (ret) {
854 return ret;
855 }
856 vfp_set_fpcr(env, fpr);
857
858 if (!write_kvmstate_to_list(cpu)) {
859 return EINVAL;
860 }
861 /* Note that it's OK to have registers which aren't in CPUState,
862 * so we can ignore a failure return here.
863 */
864 write_list_to_cpustate(cpu);
865
866 kvm_arm_sync_mpstate_to_qemu(cpu);
867
868 /* TODO: other registers */
869 return ret;
870 }
871
872 /* C6.6.29 BRK instruction */
873 static const uint32_t brk_insn = 0xd4200000;
874
875 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
876 {
877 if (have_guest_debug) {
878 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 0) ||
879 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&brk_insn, 4, 1)) {
880 return -EINVAL;
881 }
882 return 0;
883 } else {
884 error_report("guest debug not supported on this kernel");
885 return -EINVAL;
886 }
887 }
888
889 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
890 {
891 static uint32_t brk;
892
893 if (have_guest_debug) {
894 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&brk, 4, 0) ||
895 brk != brk_insn ||
896 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 1)) {
897 return -EINVAL;
898 }
899 return 0;
900 } else {
901 error_report("guest debug not supported on this kernel");
902 return -EINVAL;
903 }
904 }
905
906 /* See v8 ARM ARM D7.2.27 ESR_ELx, Exception Syndrome Register
907 *
908 * To minimise translating between kernel and user-space the kernel
909 * ABI just provides user-space with the full exception syndrome
910 * register value to be decoded in QEMU.
911 */
912
913 bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit)
914 {
915 int hsr_ec = debug_exit->hsr >> ARM_EL_EC_SHIFT;
916 ARMCPU *cpu = ARM_CPU(cs);
917 CPUClass *cc = CPU_GET_CLASS(cs);
918 CPUARMState *env = &cpu->env;
919
920 /* Ensure PC is synchronised */
921 kvm_cpu_synchronize_state(cs);
922
923 switch (hsr_ec) {
924 case EC_SOFTWARESTEP:
925 if (cs->singlestep_enabled) {
926 return true;
927 } else {
928 /*
929 * The kernel should have suppressed the guest's ability to
930 * single step at this point so something has gone wrong.
931 */
932 error_report("%s: guest single-step while debugging unsupported"
933 " (%"PRIx64", %"PRIx32")\n",
934 __func__, env->pc, debug_exit->hsr);
935 return false;
936 }
937 break;
938 case EC_AA64_BKPT:
939 if (kvm_find_sw_breakpoint(cs, env->pc)) {
940 return true;
941 }
942 break;
943 case EC_BREAKPOINT:
944 if (find_hw_breakpoint(cs, env->pc)) {
945 return true;
946 }
947 break;
948 case EC_WATCHPOINT:
949 {
950 CPUWatchpoint *wp = find_hw_watchpoint(cs, debug_exit->far);
951 if (wp) {
952 cs->watchpoint_hit = wp;
953 return true;
954 }
955 break;
956 }
957 default:
958 error_report("%s: unhandled debug exit (%"PRIx32", %"PRIx64")\n",
959 __func__, debug_exit->hsr, env->pc);
960 }
961
962 /* If we are not handling the debug exception it must belong to
963 * the guest. Let's re-use the existing TCG interrupt code to set
964 * everything up properly.
965 */
966 cs->exception_index = EXCP_BKPT;
967 env->exception.syndrome = debug_exit->hsr;
968 env->exception.vaddress = debug_exit->far;
969 cc->do_interrupt(cs);
970
971 return false;
972 }