qemu-img: Omit error_report() after img_open()
[qemu.git] / target-arm / kvm64.c
1 /*
2 * ARM implementation of KVM hooks, 64 bit specific code
3 *
4 * Copyright Mian-M. Hamayun 2013, Virtual Open Systems
5 *
6 * This work is licensed under the terms of the GNU GPL, version 2 or later.
7 * See the COPYING file in the top-level directory.
8 *
9 */
10
11 #include <stdio.h>
12 #include <sys/types.h>
13 #include <sys/ioctl.h>
14 #include <sys/mman.h>
15
16 #include <linux/kvm.h>
17
18 #include "qemu-common.h"
19 #include "qemu/timer.h"
20 #include "sysemu/sysemu.h"
21 #include "sysemu/kvm.h"
22 #include "kvm_arm.h"
23 #include "cpu.h"
24 #include "internals.h"
25 #include "hw/arm/arm.h"
26
27 static inline void set_feature(uint64_t *features, int feature)
28 {
29 *features |= 1ULL << feature;
30 }
31
32 bool kvm_arm_get_host_cpu_features(ARMHostCPUClass *ahcc)
33 {
34 /* Identify the feature bits corresponding to the host CPU, and
35 * fill out the ARMHostCPUClass fields accordingly. To do this
36 * we have to create a scratch VM, create a single CPU inside it,
37 * and then query that CPU for the relevant ID registers.
38 * For AArch64 we currently don't care about ID registers at
39 * all; we just want to know the CPU type.
40 */
41 int fdarray[3];
42 uint64_t features = 0;
43 /* Old kernels may not know about the PREFERRED_TARGET ioctl: however
44 * we know these will only support creating one kind of guest CPU,
45 * which is its preferred CPU type. Fortunately these old kernels
46 * support only a very limited number of CPUs.
47 */
48 static const uint32_t cpus_to_try[] = {
49 KVM_ARM_TARGET_AEM_V8,
50 KVM_ARM_TARGET_FOUNDATION_V8,
51 KVM_ARM_TARGET_CORTEX_A57,
52 QEMU_KVM_ARM_TARGET_NONE
53 };
54 struct kvm_vcpu_init init;
55
56 if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) {
57 return false;
58 }
59
60 ahcc->target = init.target;
61 ahcc->dtb_compatible = "arm,arm-v8";
62
63 kvm_arm_destroy_scratch_host_vcpu(fdarray);
64
65 /* We can assume any KVM supporting CPU is at least a v8
66 * with VFPv4+Neon; this in turn implies most of the other
67 * feature bits.
68 */
69 set_feature(&features, ARM_FEATURE_V8);
70 set_feature(&features, ARM_FEATURE_VFP4);
71 set_feature(&features, ARM_FEATURE_NEON);
72 set_feature(&features, ARM_FEATURE_AARCH64);
73
74 ahcc->features = features;
75
76 return true;
77 }
78
79 int kvm_arch_init_vcpu(CPUState *cs)
80 {
81 int ret;
82 ARMCPU *cpu = ARM_CPU(cs);
83
84 if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE ||
85 !arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
86 fprintf(stderr, "KVM is not supported for this guest CPU type\n");
87 return -EINVAL;
88 }
89
90 /* Determine init features for this CPU */
91 memset(cpu->kvm_init_features, 0, sizeof(cpu->kvm_init_features));
92 if (cpu->start_powered_off) {
93 cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_POWER_OFF;
94 }
95 if (kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PSCI_0_2)) {
96 cpu->psci_version = 2;
97 cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PSCI_0_2;
98 }
99
100 /* Do KVM_ARM_VCPU_INIT ioctl */
101 ret = kvm_arm_vcpu_init(cs);
102 if (ret) {
103 return ret;
104 }
105
106 /* TODO : support for save/restore/reset of system regs via tuple list */
107
108 return 0;
109 }
110
111 #define AARCH64_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \
112 KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x))
113
114 int kvm_arch_put_registers(CPUState *cs, int level)
115 {
116 struct kvm_one_reg reg;
117 uint64_t val;
118 int i;
119 int ret;
120
121 ARMCPU *cpu = ARM_CPU(cs);
122 CPUARMState *env = &cpu->env;
123
124 for (i = 0; i < 31; i++) {
125 reg.id = AARCH64_CORE_REG(regs.regs[i]);
126 reg.addr = (uintptr_t) &env->xregs[i];
127 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
128 if (ret) {
129 return ret;
130 }
131 }
132
133 /* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the
134 * QEMU side we keep the current SP in xregs[31] as well.
135 */
136 aarch64_save_sp(env, 1);
137
138 reg.id = AARCH64_CORE_REG(regs.sp);
139 reg.addr = (uintptr_t) &env->sp_el[0];
140 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
141 if (ret) {
142 return ret;
143 }
144
145 reg.id = AARCH64_CORE_REG(sp_el1);
146 reg.addr = (uintptr_t) &env->sp_el[1];
147 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
148 if (ret) {
149 return ret;
150 }
151
152 /* Note that KVM thinks pstate is 64 bit but we use a uint32_t */
153 val = pstate_read(env);
154 reg.id = AARCH64_CORE_REG(regs.pstate);
155 reg.addr = (uintptr_t) &val;
156 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
157 if (ret) {
158 return ret;
159 }
160
161 reg.id = AARCH64_CORE_REG(regs.pc);
162 reg.addr = (uintptr_t) &env->pc;
163 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
164 if (ret) {
165 return ret;
166 }
167
168 reg.id = AARCH64_CORE_REG(elr_el1);
169 reg.addr = (uintptr_t) &env->elr_el[1];
170 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
171 if (ret) {
172 return ret;
173 }
174
175 for (i = 0; i < KVM_NR_SPSR; i++) {
176 reg.id = AARCH64_CORE_REG(spsr[i]);
177 reg.addr = (uintptr_t) &env->banked_spsr[i - 1];
178 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
179 if (ret) {
180 return ret;
181 }
182 }
183
184 /* TODO:
185 * FP state
186 * system registers
187 */
188 return ret;
189 }
190
191 int kvm_arch_get_registers(CPUState *cs)
192 {
193 struct kvm_one_reg reg;
194 uint64_t val;
195 int i;
196 int ret;
197
198 ARMCPU *cpu = ARM_CPU(cs);
199 CPUARMState *env = &cpu->env;
200
201 for (i = 0; i < 31; i++) {
202 reg.id = AARCH64_CORE_REG(regs.regs[i]);
203 reg.addr = (uintptr_t) &env->xregs[i];
204 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
205 if (ret) {
206 return ret;
207 }
208 }
209
210 reg.id = AARCH64_CORE_REG(regs.sp);
211 reg.addr = (uintptr_t) &env->sp_el[0];
212 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
213 if (ret) {
214 return ret;
215 }
216
217 reg.id = AARCH64_CORE_REG(sp_el1);
218 reg.addr = (uintptr_t) &env->sp_el[1];
219 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
220 if (ret) {
221 return ret;
222 }
223
224 reg.id = AARCH64_CORE_REG(regs.pstate);
225 reg.addr = (uintptr_t) &val;
226 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
227 if (ret) {
228 return ret;
229 }
230 pstate_write(env, val);
231
232 /* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the
233 * QEMU side we keep the current SP in xregs[31] as well.
234 */
235 aarch64_restore_sp(env, 1);
236
237 reg.id = AARCH64_CORE_REG(regs.pc);
238 reg.addr = (uintptr_t) &env->pc;
239 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
240 if (ret) {
241 return ret;
242 }
243
244 reg.id = AARCH64_CORE_REG(elr_el1);
245 reg.addr = (uintptr_t) &env->elr_el[1];
246 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
247 if (ret) {
248 return ret;
249 }
250
251 for (i = 0; i < KVM_NR_SPSR; i++) {
252 reg.id = AARCH64_CORE_REG(spsr[i]);
253 reg.addr = (uintptr_t) &env->banked_spsr[i - 1];
254 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
255 if (ret) {
256 return ret;
257 }
258 }
259
260 /* TODO: other registers */
261 return ret;
262 }
263
264 void kvm_arm_reset_vcpu(ARMCPU *cpu)
265 {
266 /* Re-init VCPU so that all registers are set to
267 * their respective reset values.
268 */
269 kvm_arm_vcpu_init(CPU(cpu));
270 }