cpu: Move breakpoints field from CPU_COMMON to CPUState
[qemu.git] / target-arm / translate-a64.c
1 /*
2 * AArch64 translation
3 *
4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdarg.h>
20 #include <stdlib.h>
21 #include <stdio.h>
22 #include <string.h>
23 #include <inttypes.h>
24
25 #include "cpu.h"
26 #include "tcg-op.h"
27 #include "qemu/log.h"
28 #include "translate.h"
29 #include "qemu/host-utils.h"
30
31 #include "exec/gen-icount.h"
32
33 #include "helper.h"
34 #define GEN_HELPER 1
35 #include "helper.h"
36
37 static TCGv_i64 cpu_X[32];
38 static TCGv_i64 cpu_pc;
39 static TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF;
40
41 /* Load/store exclusive handling */
42 static TCGv_i64 cpu_exclusive_addr;
43 static TCGv_i64 cpu_exclusive_val;
44 static TCGv_i64 cpu_exclusive_high;
45 #ifdef CONFIG_USER_ONLY
46 static TCGv_i64 cpu_exclusive_test;
47 static TCGv_i32 cpu_exclusive_info;
48 #endif
49
50 static const char *regnames[] = {
51 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
52 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
53 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
54 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
55 };
56
57 enum a64_shift_type {
58 A64_SHIFT_TYPE_LSL = 0,
59 A64_SHIFT_TYPE_LSR = 1,
60 A64_SHIFT_TYPE_ASR = 2,
61 A64_SHIFT_TYPE_ROR = 3
62 };
63
64 /* Table based decoder typedefs - used when the relevant bits for decode
65 * are too awkwardly scattered across the instruction (eg SIMD).
66 */
67 typedef void AArch64DecodeFn(DisasContext *s, uint32_t insn);
68
69 typedef struct AArch64DecodeTable {
70 uint32_t pattern;
71 uint32_t mask;
72 AArch64DecodeFn *disas_fn;
73 } AArch64DecodeTable;
74
75 /* Function prototype for gen_ functions for calling Neon helpers */
76 typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32);
77 typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
78 typedef void NeonGenTwo64OpFn(TCGv_i64, TCGv_i64, TCGv_i64);
79 typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64);
80 typedef void NeonGenNarrowEnvFn(TCGv_i32, TCGv_ptr, TCGv_i64);
81 typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32);
82 typedef void NeonGenTwoSingleOPFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr);
83 typedef void NeonGenTwoDoubleOPFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr);
84
85 /* initialize TCG globals. */
86 void a64_translate_init(void)
87 {
88 int i;
89
90 cpu_pc = tcg_global_mem_new_i64(TCG_AREG0,
91 offsetof(CPUARMState, pc),
92 "pc");
93 for (i = 0; i < 32; i++) {
94 cpu_X[i] = tcg_global_mem_new_i64(TCG_AREG0,
95 offsetof(CPUARMState, xregs[i]),
96 regnames[i]);
97 }
98
99 cpu_NF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, NF), "NF");
100 cpu_ZF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, ZF), "ZF");
101 cpu_CF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, CF), "CF");
102 cpu_VF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, VF), "VF");
103
104 cpu_exclusive_addr = tcg_global_mem_new_i64(TCG_AREG0,
105 offsetof(CPUARMState, exclusive_addr), "exclusive_addr");
106 cpu_exclusive_val = tcg_global_mem_new_i64(TCG_AREG0,
107 offsetof(CPUARMState, exclusive_val), "exclusive_val");
108 cpu_exclusive_high = tcg_global_mem_new_i64(TCG_AREG0,
109 offsetof(CPUARMState, exclusive_high), "exclusive_high");
110 #ifdef CONFIG_USER_ONLY
111 cpu_exclusive_test = tcg_global_mem_new_i64(TCG_AREG0,
112 offsetof(CPUARMState, exclusive_test), "exclusive_test");
113 cpu_exclusive_info = tcg_global_mem_new_i32(TCG_AREG0,
114 offsetof(CPUARMState, exclusive_info), "exclusive_info");
115 #endif
116 }
117
118 void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
119 fprintf_function cpu_fprintf, int flags)
120 {
121 ARMCPU *cpu = ARM_CPU(cs);
122 CPUARMState *env = &cpu->env;
123 uint32_t psr = pstate_read(env);
124 int i;
125
126 cpu_fprintf(f, "PC=%016"PRIx64" SP=%016"PRIx64"\n",
127 env->pc, env->xregs[31]);
128 for (i = 0; i < 31; i++) {
129 cpu_fprintf(f, "X%02d=%016"PRIx64, i, env->xregs[i]);
130 if ((i % 4) == 3) {
131 cpu_fprintf(f, "\n");
132 } else {
133 cpu_fprintf(f, " ");
134 }
135 }
136 cpu_fprintf(f, "PSTATE=%08x (flags %c%c%c%c)\n",
137 psr,
138 psr & PSTATE_N ? 'N' : '-',
139 psr & PSTATE_Z ? 'Z' : '-',
140 psr & PSTATE_C ? 'C' : '-',
141 psr & PSTATE_V ? 'V' : '-');
142 cpu_fprintf(f, "\n");
143
144 if (flags & CPU_DUMP_FPU) {
145 int numvfpregs = 32;
146 for (i = 0; i < numvfpregs; i += 2) {
147 uint64_t vlo = float64_val(env->vfp.regs[i * 2]);
148 uint64_t vhi = float64_val(env->vfp.regs[(i * 2) + 1]);
149 cpu_fprintf(f, "q%02d=%016" PRIx64 ":%016" PRIx64 " ",
150 i, vhi, vlo);
151 vlo = float64_val(env->vfp.regs[(i + 1) * 2]);
152 vhi = float64_val(env->vfp.regs[((i + 1) * 2) + 1]);
153 cpu_fprintf(f, "q%02d=%016" PRIx64 ":%016" PRIx64 "\n",
154 i + 1, vhi, vlo);
155 }
156 cpu_fprintf(f, "FPCR: %08x FPSR: %08x\n",
157 vfp_get_fpcr(env), vfp_get_fpsr(env));
158 }
159 }
160
161 static int get_mem_index(DisasContext *s)
162 {
163 #ifdef CONFIG_USER_ONLY
164 return 1;
165 #else
166 return s->user;
167 #endif
168 }
169
170 void gen_a64_set_pc_im(uint64_t val)
171 {
172 tcg_gen_movi_i64(cpu_pc, val);
173 }
174
175 static void gen_exception(int excp)
176 {
177 TCGv_i32 tmp = tcg_temp_new_i32();
178 tcg_gen_movi_i32(tmp, excp);
179 gen_helper_exception(cpu_env, tmp);
180 tcg_temp_free_i32(tmp);
181 }
182
183 static void gen_exception_insn(DisasContext *s, int offset, int excp)
184 {
185 gen_a64_set_pc_im(s->pc - offset);
186 gen_exception(excp);
187 s->is_jmp = DISAS_EXC;
188 }
189
190 static inline bool use_goto_tb(DisasContext *s, int n, uint64_t dest)
191 {
192 /* No direct tb linking with singlestep or deterministic io */
193 if (s->singlestep_enabled || (s->tb->cflags & CF_LAST_IO)) {
194 return false;
195 }
196
197 /* Only link tbs from inside the same guest page */
198 if ((s->tb->pc & TARGET_PAGE_MASK) != (dest & TARGET_PAGE_MASK)) {
199 return false;
200 }
201
202 return true;
203 }
204
205 static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest)
206 {
207 TranslationBlock *tb;
208
209 tb = s->tb;
210 if (use_goto_tb(s, n, dest)) {
211 tcg_gen_goto_tb(n);
212 gen_a64_set_pc_im(dest);
213 tcg_gen_exit_tb((intptr_t)tb + n);
214 s->is_jmp = DISAS_TB_JUMP;
215 } else {
216 gen_a64_set_pc_im(dest);
217 if (s->singlestep_enabled) {
218 gen_exception(EXCP_DEBUG);
219 }
220 tcg_gen_exit_tb(0);
221 s->is_jmp = DISAS_JUMP;
222 }
223 }
224
225 static void unallocated_encoding(DisasContext *s)
226 {
227 gen_exception_insn(s, 4, EXCP_UDEF);
228 }
229
230 #define unsupported_encoding(s, insn) \
231 do { \
232 qemu_log_mask(LOG_UNIMP, \
233 "%s:%d: unsupported instruction encoding 0x%08x " \
234 "at pc=%016" PRIx64 "\n", \
235 __FILE__, __LINE__, insn, s->pc - 4); \
236 unallocated_encoding(s); \
237 } while (0);
238
239 static void init_tmp_a64_array(DisasContext *s)
240 {
241 #ifdef CONFIG_DEBUG_TCG
242 int i;
243 for (i = 0; i < ARRAY_SIZE(s->tmp_a64); i++) {
244 TCGV_UNUSED_I64(s->tmp_a64[i]);
245 }
246 #endif
247 s->tmp_a64_count = 0;
248 }
249
250 static void free_tmp_a64(DisasContext *s)
251 {
252 int i;
253 for (i = 0; i < s->tmp_a64_count; i++) {
254 tcg_temp_free_i64(s->tmp_a64[i]);
255 }
256 init_tmp_a64_array(s);
257 }
258
259 static TCGv_i64 new_tmp_a64(DisasContext *s)
260 {
261 assert(s->tmp_a64_count < TMP_A64_MAX);
262 return s->tmp_a64[s->tmp_a64_count++] = tcg_temp_new_i64();
263 }
264
265 static TCGv_i64 new_tmp_a64_zero(DisasContext *s)
266 {
267 TCGv_i64 t = new_tmp_a64(s);
268 tcg_gen_movi_i64(t, 0);
269 return t;
270 }
271
272 /*
273 * Register access functions
274 *
275 * These functions are used for directly accessing a register in where
276 * changes to the final register value are likely to be made. If you
277 * need to use a register for temporary calculation (e.g. index type
278 * operations) use the read_* form.
279 *
280 * B1.2.1 Register mappings
281 *
282 * In instruction register encoding 31 can refer to ZR (zero register) or
283 * the SP (stack pointer) depending on context. In QEMU's case we map SP
284 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
285 * This is the point of the _sp forms.
286 */
287 static TCGv_i64 cpu_reg(DisasContext *s, int reg)
288 {
289 if (reg == 31) {
290 return new_tmp_a64_zero(s);
291 } else {
292 return cpu_X[reg];
293 }
294 }
295
296 /* register access for when 31 == SP */
297 static TCGv_i64 cpu_reg_sp(DisasContext *s, int reg)
298 {
299 return cpu_X[reg];
300 }
301
302 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
303 * representing the register contents. This TCGv is an auto-freed
304 * temporary so it need not be explicitly freed, and may be modified.
305 */
306 static TCGv_i64 read_cpu_reg(DisasContext *s, int reg, int sf)
307 {
308 TCGv_i64 v = new_tmp_a64(s);
309 if (reg != 31) {
310 if (sf) {
311 tcg_gen_mov_i64(v, cpu_X[reg]);
312 } else {
313 tcg_gen_ext32u_i64(v, cpu_X[reg]);
314 }
315 } else {
316 tcg_gen_movi_i64(v, 0);
317 }
318 return v;
319 }
320
321 static TCGv_i64 read_cpu_reg_sp(DisasContext *s, int reg, int sf)
322 {
323 TCGv_i64 v = new_tmp_a64(s);
324 if (sf) {
325 tcg_gen_mov_i64(v, cpu_X[reg]);
326 } else {
327 tcg_gen_ext32u_i64(v, cpu_X[reg]);
328 }
329 return v;
330 }
331
332 /* Return the offset into CPUARMState of an element of specified
333 * size, 'element' places in from the least significant end of
334 * the FP/vector register Qn.
335 */
336 static inline int vec_reg_offset(int regno, int element, TCGMemOp size)
337 {
338 int offs = offsetof(CPUARMState, vfp.regs[regno * 2]);
339 #ifdef HOST_WORDS_BIGENDIAN
340 /* This is complicated slightly because vfp.regs[2n] is
341 * still the low half and vfp.regs[2n+1] the high half
342 * of the 128 bit vector, even on big endian systems.
343 * Calculate the offset assuming a fully bigendian 128 bits,
344 * then XOR to account for the order of the two 64 bit halves.
345 */
346 offs += (16 - ((element + 1) * (1 << size)));
347 offs ^= 8;
348 #else
349 offs += element * (1 << size);
350 #endif
351 return offs;
352 }
353
354 /* Return the offset into CPUARMState of a slice (from
355 * the least significant end) of FP register Qn (ie
356 * Dn, Sn, Hn or Bn).
357 * (Note that this is not the same mapping as for A32; see cpu.h)
358 */
359 static inline int fp_reg_offset(int regno, TCGMemOp size)
360 {
361 int offs = offsetof(CPUARMState, vfp.regs[regno * 2]);
362 #ifdef HOST_WORDS_BIGENDIAN
363 offs += (8 - (1 << size));
364 #endif
365 return offs;
366 }
367
368 /* Offset of the high half of the 128 bit vector Qn */
369 static inline int fp_reg_hi_offset(int regno)
370 {
371 return offsetof(CPUARMState, vfp.regs[regno * 2 + 1]);
372 }
373
374 /* Convenience accessors for reading and writing single and double
375 * FP registers. Writing clears the upper parts of the associated
376 * 128 bit vector register, as required by the architecture.
377 * Note that unlike the GP register accessors, the values returned
378 * by the read functions must be manually freed.
379 */
380 static TCGv_i64 read_fp_dreg(DisasContext *s, int reg)
381 {
382 TCGv_i64 v = tcg_temp_new_i64();
383
384 tcg_gen_ld_i64(v, cpu_env, fp_reg_offset(reg, MO_64));
385 return v;
386 }
387
388 static TCGv_i32 read_fp_sreg(DisasContext *s, int reg)
389 {
390 TCGv_i32 v = tcg_temp_new_i32();
391
392 tcg_gen_ld_i32(v, cpu_env, fp_reg_offset(reg, MO_32));
393 return v;
394 }
395
396 static void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v)
397 {
398 TCGv_i64 tcg_zero = tcg_const_i64(0);
399
400 tcg_gen_st_i64(v, cpu_env, fp_reg_offset(reg, MO_64));
401 tcg_gen_st_i64(tcg_zero, cpu_env, fp_reg_hi_offset(reg));
402 tcg_temp_free_i64(tcg_zero);
403 }
404
405 static void write_fp_sreg(DisasContext *s, int reg, TCGv_i32 v)
406 {
407 TCGv_i64 tmp = tcg_temp_new_i64();
408
409 tcg_gen_extu_i32_i64(tmp, v);
410 write_fp_dreg(s, reg, tmp);
411 tcg_temp_free_i64(tmp);
412 }
413
414 static TCGv_ptr get_fpstatus_ptr(void)
415 {
416 TCGv_ptr statusptr = tcg_temp_new_ptr();
417 int offset;
418
419 /* In A64 all instructions (both FP and Neon) use the FPCR;
420 * there is no equivalent of the A32 Neon "standard FPSCR value"
421 * and all operations use vfp.fp_status.
422 */
423 offset = offsetof(CPUARMState, vfp.fp_status);
424 tcg_gen_addi_ptr(statusptr, cpu_env, offset);
425 return statusptr;
426 }
427
428 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
429 * than the 32 bit equivalent.
430 */
431 static inline void gen_set_NZ64(TCGv_i64 result)
432 {
433 TCGv_i64 flag = tcg_temp_new_i64();
434
435 tcg_gen_setcondi_i64(TCG_COND_NE, flag, result, 0);
436 tcg_gen_trunc_i64_i32(cpu_ZF, flag);
437 tcg_gen_shri_i64(flag, result, 32);
438 tcg_gen_trunc_i64_i32(cpu_NF, flag);
439 tcg_temp_free_i64(flag);
440 }
441
442 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
443 static inline void gen_logic_CC(int sf, TCGv_i64 result)
444 {
445 if (sf) {
446 gen_set_NZ64(result);
447 } else {
448 tcg_gen_trunc_i64_i32(cpu_ZF, result);
449 tcg_gen_trunc_i64_i32(cpu_NF, result);
450 }
451 tcg_gen_movi_i32(cpu_CF, 0);
452 tcg_gen_movi_i32(cpu_VF, 0);
453 }
454
455 /* dest = T0 + T1; compute C, N, V and Z flags */
456 static void gen_add_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1)
457 {
458 if (sf) {
459 TCGv_i64 result, flag, tmp;
460 result = tcg_temp_new_i64();
461 flag = tcg_temp_new_i64();
462 tmp = tcg_temp_new_i64();
463
464 tcg_gen_movi_i64(tmp, 0);
465 tcg_gen_add2_i64(result, flag, t0, tmp, t1, tmp);
466
467 tcg_gen_trunc_i64_i32(cpu_CF, flag);
468
469 gen_set_NZ64(result);
470
471 tcg_gen_xor_i64(flag, result, t0);
472 tcg_gen_xor_i64(tmp, t0, t1);
473 tcg_gen_andc_i64(flag, flag, tmp);
474 tcg_temp_free_i64(tmp);
475 tcg_gen_shri_i64(flag, flag, 32);
476 tcg_gen_trunc_i64_i32(cpu_VF, flag);
477
478 tcg_gen_mov_i64(dest, result);
479 tcg_temp_free_i64(result);
480 tcg_temp_free_i64(flag);
481 } else {
482 /* 32 bit arithmetic */
483 TCGv_i32 t0_32 = tcg_temp_new_i32();
484 TCGv_i32 t1_32 = tcg_temp_new_i32();
485 TCGv_i32 tmp = tcg_temp_new_i32();
486
487 tcg_gen_movi_i32(tmp, 0);
488 tcg_gen_trunc_i64_i32(t0_32, t0);
489 tcg_gen_trunc_i64_i32(t1_32, t1);
490 tcg_gen_add2_i32(cpu_NF, cpu_CF, t0_32, tmp, t1_32, tmp);
491 tcg_gen_mov_i32(cpu_ZF, cpu_NF);
492 tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32);
493 tcg_gen_xor_i32(tmp, t0_32, t1_32);
494 tcg_gen_andc_i32(cpu_VF, cpu_VF, tmp);
495 tcg_gen_extu_i32_i64(dest, cpu_NF);
496
497 tcg_temp_free_i32(tmp);
498 tcg_temp_free_i32(t0_32);
499 tcg_temp_free_i32(t1_32);
500 }
501 }
502
503 /* dest = T0 - T1; compute C, N, V and Z flags */
504 static void gen_sub_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1)
505 {
506 if (sf) {
507 /* 64 bit arithmetic */
508 TCGv_i64 result, flag, tmp;
509
510 result = tcg_temp_new_i64();
511 flag = tcg_temp_new_i64();
512 tcg_gen_sub_i64(result, t0, t1);
513
514 gen_set_NZ64(result);
515
516 tcg_gen_setcond_i64(TCG_COND_GEU, flag, t0, t1);
517 tcg_gen_trunc_i64_i32(cpu_CF, flag);
518
519 tcg_gen_xor_i64(flag, result, t0);
520 tmp = tcg_temp_new_i64();
521 tcg_gen_xor_i64(tmp, t0, t1);
522 tcg_gen_and_i64(flag, flag, tmp);
523 tcg_temp_free_i64(tmp);
524 tcg_gen_shri_i64(flag, flag, 32);
525 tcg_gen_trunc_i64_i32(cpu_VF, flag);
526 tcg_gen_mov_i64(dest, result);
527 tcg_temp_free_i64(flag);
528 tcg_temp_free_i64(result);
529 } else {
530 /* 32 bit arithmetic */
531 TCGv_i32 t0_32 = tcg_temp_new_i32();
532 TCGv_i32 t1_32 = tcg_temp_new_i32();
533 TCGv_i32 tmp;
534
535 tcg_gen_trunc_i64_i32(t0_32, t0);
536 tcg_gen_trunc_i64_i32(t1_32, t1);
537 tcg_gen_sub_i32(cpu_NF, t0_32, t1_32);
538 tcg_gen_mov_i32(cpu_ZF, cpu_NF);
539 tcg_gen_setcond_i32(TCG_COND_GEU, cpu_CF, t0_32, t1_32);
540 tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32);
541 tmp = tcg_temp_new_i32();
542 tcg_gen_xor_i32(tmp, t0_32, t1_32);
543 tcg_temp_free_i32(t0_32);
544 tcg_temp_free_i32(t1_32);
545 tcg_gen_and_i32(cpu_VF, cpu_VF, tmp);
546 tcg_temp_free_i32(tmp);
547 tcg_gen_extu_i32_i64(dest, cpu_NF);
548 }
549 }
550
551 /* dest = T0 + T1 + CF; do not compute flags. */
552 static void gen_adc(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1)
553 {
554 TCGv_i64 flag = tcg_temp_new_i64();
555 tcg_gen_extu_i32_i64(flag, cpu_CF);
556 tcg_gen_add_i64(dest, t0, t1);
557 tcg_gen_add_i64(dest, dest, flag);
558 tcg_temp_free_i64(flag);
559
560 if (!sf) {
561 tcg_gen_ext32u_i64(dest, dest);
562 }
563 }
564
565 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
566 static void gen_adc_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1)
567 {
568 if (sf) {
569 TCGv_i64 result, cf_64, vf_64, tmp;
570 result = tcg_temp_new_i64();
571 cf_64 = tcg_temp_new_i64();
572 vf_64 = tcg_temp_new_i64();
573 tmp = tcg_const_i64(0);
574
575 tcg_gen_extu_i32_i64(cf_64, cpu_CF);
576 tcg_gen_add2_i64(result, cf_64, t0, tmp, cf_64, tmp);
577 tcg_gen_add2_i64(result, cf_64, result, cf_64, t1, tmp);
578 tcg_gen_trunc_i64_i32(cpu_CF, cf_64);
579 gen_set_NZ64(result);
580
581 tcg_gen_xor_i64(vf_64, result, t0);
582 tcg_gen_xor_i64(tmp, t0, t1);
583 tcg_gen_andc_i64(vf_64, vf_64, tmp);
584 tcg_gen_shri_i64(vf_64, vf_64, 32);
585 tcg_gen_trunc_i64_i32(cpu_VF, vf_64);
586
587 tcg_gen_mov_i64(dest, result);
588
589 tcg_temp_free_i64(tmp);
590 tcg_temp_free_i64(vf_64);
591 tcg_temp_free_i64(cf_64);
592 tcg_temp_free_i64(result);
593 } else {
594 TCGv_i32 t0_32, t1_32, tmp;
595 t0_32 = tcg_temp_new_i32();
596 t1_32 = tcg_temp_new_i32();
597 tmp = tcg_const_i32(0);
598
599 tcg_gen_trunc_i64_i32(t0_32, t0);
600 tcg_gen_trunc_i64_i32(t1_32, t1);
601 tcg_gen_add2_i32(cpu_NF, cpu_CF, t0_32, tmp, cpu_CF, tmp);
602 tcg_gen_add2_i32(cpu_NF, cpu_CF, cpu_NF, cpu_CF, t1_32, tmp);
603
604 tcg_gen_mov_i32(cpu_ZF, cpu_NF);
605 tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32);
606 tcg_gen_xor_i32(tmp, t0_32, t1_32);
607 tcg_gen_andc_i32(cpu_VF, cpu_VF, tmp);
608 tcg_gen_extu_i32_i64(dest, cpu_NF);
609
610 tcg_temp_free_i32(tmp);
611 tcg_temp_free_i32(t1_32);
612 tcg_temp_free_i32(t0_32);
613 }
614 }
615
616 /*
617 * Load/Store generators
618 */
619
620 /*
621 * Store from GPR register to memory.
622 */
623 static void do_gpr_st_memidx(DisasContext *s, TCGv_i64 source,
624 TCGv_i64 tcg_addr, int size, int memidx)
625 {
626 g_assert(size <= 3);
627 tcg_gen_qemu_st_i64(source, tcg_addr, memidx, MO_TE + size);
628 }
629
630 static void do_gpr_st(DisasContext *s, TCGv_i64 source,
631 TCGv_i64 tcg_addr, int size)
632 {
633 do_gpr_st_memidx(s, source, tcg_addr, size, get_mem_index(s));
634 }
635
636 /*
637 * Load from memory to GPR register
638 */
639 static void do_gpr_ld_memidx(DisasContext *s, TCGv_i64 dest, TCGv_i64 tcg_addr,
640 int size, bool is_signed, bool extend, int memidx)
641 {
642 TCGMemOp memop = MO_TE + size;
643
644 g_assert(size <= 3);
645
646 if (is_signed) {
647 memop += MO_SIGN;
648 }
649
650 tcg_gen_qemu_ld_i64(dest, tcg_addr, memidx, memop);
651
652 if (extend && is_signed) {
653 g_assert(size < 3);
654 tcg_gen_ext32u_i64(dest, dest);
655 }
656 }
657
658 static void do_gpr_ld(DisasContext *s, TCGv_i64 dest, TCGv_i64 tcg_addr,
659 int size, bool is_signed, bool extend)
660 {
661 do_gpr_ld_memidx(s, dest, tcg_addr, size, is_signed, extend,
662 get_mem_index(s));
663 }
664
665 /*
666 * Store from FP register to memory
667 */
668 static void do_fp_st(DisasContext *s, int srcidx, TCGv_i64 tcg_addr, int size)
669 {
670 /* This writes the bottom N bits of a 128 bit wide vector to memory */
671 TCGv_i64 tmp = tcg_temp_new_i64();
672 tcg_gen_ld_i64(tmp, cpu_env, fp_reg_offset(srcidx, MO_64));
673 if (size < 4) {
674 tcg_gen_qemu_st_i64(tmp, tcg_addr, get_mem_index(s), MO_TE + size);
675 } else {
676 TCGv_i64 tcg_hiaddr = tcg_temp_new_i64();
677 tcg_gen_qemu_st_i64(tmp, tcg_addr, get_mem_index(s), MO_TEQ);
678 tcg_gen_qemu_st64(tmp, tcg_addr, get_mem_index(s));
679 tcg_gen_ld_i64(tmp, cpu_env, fp_reg_hi_offset(srcidx));
680 tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8);
681 tcg_gen_qemu_st_i64(tmp, tcg_hiaddr, get_mem_index(s), MO_TEQ);
682 tcg_temp_free_i64(tcg_hiaddr);
683 }
684
685 tcg_temp_free_i64(tmp);
686 }
687
688 /*
689 * Load from memory to FP register
690 */
691 static void do_fp_ld(DisasContext *s, int destidx, TCGv_i64 tcg_addr, int size)
692 {
693 /* This always zero-extends and writes to a full 128 bit wide vector */
694 TCGv_i64 tmplo = tcg_temp_new_i64();
695 TCGv_i64 tmphi;
696
697 if (size < 4) {
698 TCGMemOp memop = MO_TE + size;
699 tmphi = tcg_const_i64(0);
700 tcg_gen_qemu_ld_i64(tmplo, tcg_addr, get_mem_index(s), memop);
701 } else {
702 TCGv_i64 tcg_hiaddr;
703 tmphi = tcg_temp_new_i64();
704 tcg_hiaddr = tcg_temp_new_i64();
705
706 tcg_gen_qemu_ld_i64(tmplo, tcg_addr, get_mem_index(s), MO_TEQ);
707 tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8);
708 tcg_gen_qemu_ld_i64(tmphi, tcg_hiaddr, get_mem_index(s), MO_TEQ);
709 tcg_temp_free_i64(tcg_hiaddr);
710 }
711
712 tcg_gen_st_i64(tmplo, cpu_env, fp_reg_offset(destidx, MO_64));
713 tcg_gen_st_i64(tmphi, cpu_env, fp_reg_hi_offset(destidx));
714
715 tcg_temp_free_i64(tmplo);
716 tcg_temp_free_i64(tmphi);
717 }
718
719 /*
720 * Vector load/store helpers.
721 *
722 * The principal difference between this and a FP load is that we don't
723 * zero extend as we are filling a partial chunk of the vector register.
724 * These functions don't support 128 bit loads/stores, which would be
725 * normal load/store operations.
726 *
727 * The _i32 versions are useful when operating on 32 bit quantities
728 * (eg for floating point single or using Neon helper functions).
729 */
730
731 /* Get value of an element within a vector register */
732 static void read_vec_element(DisasContext *s, TCGv_i64 tcg_dest, int srcidx,
733 int element, TCGMemOp memop)
734 {
735 int vect_off = vec_reg_offset(srcidx, element, memop & MO_SIZE);
736 switch (memop) {
737 case MO_8:
738 tcg_gen_ld8u_i64(tcg_dest, cpu_env, vect_off);
739 break;
740 case MO_16:
741 tcg_gen_ld16u_i64(tcg_dest, cpu_env, vect_off);
742 break;
743 case MO_32:
744 tcg_gen_ld32u_i64(tcg_dest, cpu_env, vect_off);
745 break;
746 case MO_8|MO_SIGN:
747 tcg_gen_ld8s_i64(tcg_dest, cpu_env, vect_off);
748 break;
749 case MO_16|MO_SIGN:
750 tcg_gen_ld16s_i64(tcg_dest, cpu_env, vect_off);
751 break;
752 case MO_32|MO_SIGN:
753 tcg_gen_ld32s_i64(tcg_dest, cpu_env, vect_off);
754 break;
755 case MO_64:
756 case MO_64|MO_SIGN:
757 tcg_gen_ld_i64(tcg_dest, cpu_env, vect_off);
758 break;
759 default:
760 g_assert_not_reached();
761 }
762 }
763
764 static void read_vec_element_i32(DisasContext *s, TCGv_i32 tcg_dest, int srcidx,
765 int element, TCGMemOp memop)
766 {
767 int vect_off = vec_reg_offset(srcidx, element, memop & MO_SIZE);
768 switch (memop) {
769 case MO_8:
770 tcg_gen_ld8u_i32(tcg_dest, cpu_env, vect_off);
771 break;
772 case MO_16:
773 tcg_gen_ld16u_i32(tcg_dest, cpu_env, vect_off);
774 break;
775 case MO_8|MO_SIGN:
776 tcg_gen_ld8s_i32(tcg_dest, cpu_env, vect_off);
777 break;
778 case MO_16|MO_SIGN:
779 tcg_gen_ld16s_i32(tcg_dest, cpu_env, vect_off);
780 break;
781 case MO_32:
782 case MO_32|MO_SIGN:
783 tcg_gen_ld_i32(tcg_dest, cpu_env, vect_off);
784 break;
785 default:
786 g_assert_not_reached();
787 }
788 }
789
790 /* Set value of an element within a vector register */
791 static void write_vec_element(DisasContext *s, TCGv_i64 tcg_src, int destidx,
792 int element, TCGMemOp memop)
793 {
794 int vect_off = vec_reg_offset(destidx, element, memop & MO_SIZE);
795 switch (memop) {
796 case MO_8:
797 tcg_gen_st8_i64(tcg_src, cpu_env, vect_off);
798 break;
799 case MO_16:
800 tcg_gen_st16_i64(tcg_src, cpu_env, vect_off);
801 break;
802 case MO_32:
803 tcg_gen_st32_i64(tcg_src, cpu_env, vect_off);
804 break;
805 case MO_64:
806 tcg_gen_st_i64(tcg_src, cpu_env, vect_off);
807 break;
808 default:
809 g_assert_not_reached();
810 }
811 }
812
813 static void write_vec_element_i32(DisasContext *s, TCGv_i32 tcg_src,
814 int destidx, int element, TCGMemOp memop)
815 {
816 int vect_off = vec_reg_offset(destidx, element, memop & MO_SIZE);
817 switch (memop) {
818 case MO_8:
819 tcg_gen_st8_i32(tcg_src, cpu_env, vect_off);
820 break;
821 case MO_16:
822 tcg_gen_st16_i32(tcg_src, cpu_env, vect_off);
823 break;
824 case MO_32:
825 tcg_gen_st_i32(tcg_src, cpu_env, vect_off);
826 break;
827 default:
828 g_assert_not_reached();
829 }
830 }
831
832 /* Clear the high 64 bits of a 128 bit vector (in general non-quad
833 * vector ops all need to do this).
834 */
835 static void clear_vec_high(DisasContext *s, int rd)
836 {
837 TCGv_i64 tcg_zero = tcg_const_i64(0);
838
839 write_vec_element(s, tcg_zero, rd, 1, MO_64);
840 tcg_temp_free_i64(tcg_zero);
841 }
842
843 /* Store from vector register to memory */
844 static void do_vec_st(DisasContext *s, int srcidx, int element,
845 TCGv_i64 tcg_addr, int size)
846 {
847 TCGMemOp memop = MO_TE + size;
848 TCGv_i64 tcg_tmp = tcg_temp_new_i64();
849
850 read_vec_element(s, tcg_tmp, srcidx, element, size);
851 tcg_gen_qemu_st_i64(tcg_tmp, tcg_addr, get_mem_index(s), memop);
852
853 tcg_temp_free_i64(tcg_tmp);
854 }
855
856 /* Load from memory to vector register */
857 static void do_vec_ld(DisasContext *s, int destidx, int element,
858 TCGv_i64 tcg_addr, int size)
859 {
860 TCGMemOp memop = MO_TE + size;
861 TCGv_i64 tcg_tmp = tcg_temp_new_i64();
862
863 tcg_gen_qemu_ld_i64(tcg_tmp, tcg_addr, get_mem_index(s), memop);
864 write_vec_element(s, tcg_tmp, destidx, element, size);
865
866 tcg_temp_free_i64(tcg_tmp);
867 }
868
869 /*
870 * This utility function is for doing register extension with an
871 * optional shift. You will likely want to pass a temporary for the
872 * destination register. See DecodeRegExtend() in the ARM ARM.
873 */
874 static void ext_and_shift_reg(TCGv_i64 tcg_out, TCGv_i64 tcg_in,
875 int option, unsigned int shift)
876 {
877 int extsize = extract32(option, 0, 2);
878 bool is_signed = extract32(option, 2, 1);
879
880 if (is_signed) {
881 switch (extsize) {
882 case 0:
883 tcg_gen_ext8s_i64(tcg_out, tcg_in);
884 break;
885 case 1:
886 tcg_gen_ext16s_i64(tcg_out, tcg_in);
887 break;
888 case 2:
889 tcg_gen_ext32s_i64(tcg_out, tcg_in);
890 break;
891 case 3:
892 tcg_gen_mov_i64(tcg_out, tcg_in);
893 break;
894 }
895 } else {
896 switch (extsize) {
897 case 0:
898 tcg_gen_ext8u_i64(tcg_out, tcg_in);
899 break;
900 case 1:
901 tcg_gen_ext16u_i64(tcg_out, tcg_in);
902 break;
903 case 2:
904 tcg_gen_ext32u_i64(tcg_out, tcg_in);
905 break;
906 case 3:
907 tcg_gen_mov_i64(tcg_out, tcg_in);
908 break;
909 }
910 }
911
912 if (shift) {
913 tcg_gen_shli_i64(tcg_out, tcg_out, shift);
914 }
915 }
916
917 static inline void gen_check_sp_alignment(DisasContext *s)
918 {
919 /* The AArch64 architecture mandates that (if enabled via PSTATE
920 * or SCTLR bits) there is a check that SP is 16-aligned on every
921 * SP-relative load or store (with an exception generated if it is not).
922 * In line with general QEMU practice regarding misaligned accesses,
923 * we omit these checks for the sake of guest program performance.
924 * This function is provided as a hook so we can more easily add these
925 * checks in future (possibly as a "favour catching guest program bugs
926 * over speed" user selectable option).
927 */
928 }
929
930 /*
931 * This provides a simple table based table lookup decoder. It is
932 * intended to be used when the relevant bits for decode are too
933 * awkwardly placed and switch/if based logic would be confusing and
934 * deeply nested. Since it's a linear search through the table, tables
935 * should be kept small.
936 *
937 * It returns the first handler where insn & mask == pattern, or
938 * NULL if there is no match.
939 * The table is terminated by an empty mask (i.e. 0)
940 */
941 static inline AArch64DecodeFn *lookup_disas_fn(const AArch64DecodeTable *table,
942 uint32_t insn)
943 {
944 const AArch64DecodeTable *tptr = table;
945
946 while (tptr->mask) {
947 if ((insn & tptr->mask) == tptr->pattern) {
948 return tptr->disas_fn;
949 }
950 tptr++;
951 }
952 return NULL;
953 }
954
955 /*
956 * the instruction disassembly implemented here matches
957 * the instruction encoding classifications in chapter 3 (C3)
958 * of the ARM Architecture Reference Manual (DDI0487A_a)
959 */
960
961 /* C3.2.7 Unconditional branch (immediate)
962 * 31 30 26 25 0
963 * +----+-----------+-------------------------------------+
964 * | op | 0 0 1 0 1 | imm26 |
965 * +----+-----------+-------------------------------------+
966 */
967 static void disas_uncond_b_imm(DisasContext *s, uint32_t insn)
968 {
969 uint64_t addr = s->pc + sextract32(insn, 0, 26) * 4 - 4;
970
971 if (insn & (1 << 31)) {
972 /* C5.6.26 BL Branch with link */
973 tcg_gen_movi_i64(cpu_reg(s, 30), s->pc);
974 }
975
976 /* C5.6.20 B Branch / C5.6.26 BL Branch with link */
977 gen_goto_tb(s, 0, addr);
978 }
979
980 /* C3.2.1 Compare & branch (immediate)
981 * 31 30 25 24 23 5 4 0
982 * +----+-------------+----+---------------------+--------+
983 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
984 * +----+-------------+----+---------------------+--------+
985 */
986 static void disas_comp_b_imm(DisasContext *s, uint32_t insn)
987 {
988 unsigned int sf, op, rt;
989 uint64_t addr;
990 int label_match;
991 TCGv_i64 tcg_cmp;
992
993 sf = extract32(insn, 31, 1);
994 op = extract32(insn, 24, 1); /* 0: CBZ; 1: CBNZ */
995 rt = extract32(insn, 0, 5);
996 addr = s->pc + sextract32(insn, 5, 19) * 4 - 4;
997
998 tcg_cmp = read_cpu_reg(s, rt, sf);
999 label_match = gen_new_label();
1000
1001 tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ,
1002 tcg_cmp, 0, label_match);
1003
1004 gen_goto_tb(s, 0, s->pc);
1005 gen_set_label(label_match);
1006 gen_goto_tb(s, 1, addr);
1007 }
1008
1009 /* C3.2.5 Test & branch (immediate)
1010 * 31 30 25 24 23 19 18 5 4 0
1011 * +----+-------------+----+-------+-------------+------+
1012 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
1013 * +----+-------------+----+-------+-------------+------+
1014 */
1015 static void disas_test_b_imm(DisasContext *s, uint32_t insn)
1016 {
1017 unsigned int bit_pos, op, rt;
1018 uint64_t addr;
1019 int label_match;
1020 TCGv_i64 tcg_cmp;
1021
1022 bit_pos = (extract32(insn, 31, 1) << 5) | extract32(insn, 19, 5);
1023 op = extract32(insn, 24, 1); /* 0: TBZ; 1: TBNZ */
1024 addr = s->pc + sextract32(insn, 5, 14) * 4 - 4;
1025 rt = extract32(insn, 0, 5);
1026
1027 tcg_cmp = tcg_temp_new_i64();
1028 tcg_gen_andi_i64(tcg_cmp, cpu_reg(s, rt), (1ULL << bit_pos));
1029 label_match = gen_new_label();
1030 tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ,
1031 tcg_cmp, 0, label_match);
1032 tcg_temp_free_i64(tcg_cmp);
1033 gen_goto_tb(s, 0, s->pc);
1034 gen_set_label(label_match);
1035 gen_goto_tb(s, 1, addr);
1036 }
1037
1038 /* C3.2.2 / C5.6.19 Conditional branch (immediate)
1039 * 31 25 24 23 5 4 3 0
1040 * +---------------+----+---------------------+----+------+
1041 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
1042 * +---------------+----+---------------------+----+------+
1043 */
1044 static void disas_cond_b_imm(DisasContext *s, uint32_t insn)
1045 {
1046 unsigned int cond;
1047 uint64_t addr;
1048
1049 if ((insn & (1 << 4)) || (insn & (1 << 24))) {
1050 unallocated_encoding(s);
1051 return;
1052 }
1053 addr = s->pc + sextract32(insn, 5, 19) * 4 - 4;
1054 cond = extract32(insn, 0, 4);
1055
1056 if (cond < 0x0e) {
1057 /* genuinely conditional branches */
1058 int label_match = gen_new_label();
1059 arm_gen_test_cc(cond, label_match);
1060 gen_goto_tb(s, 0, s->pc);
1061 gen_set_label(label_match);
1062 gen_goto_tb(s, 1, addr);
1063 } else {
1064 /* 0xe and 0xf are both "always" conditions */
1065 gen_goto_tb(s, 0, addr);
1066 }
1067 }
1068
1069 /* C5.6.68 HINT */
1070 static void handle_hint(DisasContext *s, uint32_t insn,
1071 unsigned int op1, unsigned int op2, unsigned int crm)
1072 {
1073 unsigned int selector = crm << 3 | op2;
1074
1075 if (op1 != 3) {
1076 unallocated_encoding(s);
1077 return;
1078 }
1079
1080 switch (selector) {
1081 case 0: /* NOP */
1082 return;
1083 case 3: /* WFI */
1084 s->is_jmp = DISAS_WFI;
1085 return;
1086 case 1: /* YIELD */
1087 case 2: /* WFE */
1088 case 4: /* SEV */
1089 case 5: /* SEVL */
1090 /* we treat all as NOP at least for now */
1091 return;
1092 default:
1093 /* default specified as NOP equivalent */
1094 return;
1095 }
1096 }
1097
1098 static void gen_clrex(DisasContext *s, uint32_t insn)
1099 {
1100 tcg_gen_movi_i64(cpu_exclusive_addr, -1);
1101 }
1102
1103 /* CLREX, DSB, DMB, ISB */
1104 static void handle_sync(DisasContext *s, uint32_t insn,
1105 unsigned int op1, unsigned int op2, unsigned int crm)
1106 {
1107 if (op1 != 3) {
1108 unallocated_encoding(s);
1109 return;
1110 }
1111
1112 switch (op2) {
1113 case 2: /* CLREX */
1114 gen_clrex(s, insn);
1115 return;
1116 case 4: /* DSB */
1117 case 5: /* DMB */
1118 case 6: /* ISB */
1119 /* We don't emulate caches so barriers are no-ops */
1120 return;
1121 default:
1122 unallocated_encoding(s);
1123 return;
1124 }
1125 }
1126
1127 /* C5.6.130 MSR (immediate) - move immediate to processor state field */
1128 static void handle_msr_i(DisasContext *s, uint32_t insn,
1129 unsigned int op1, unsigned int op2, unsigned int crm)
1130 {
1131 int op = op1 << 3 | op2;
1132 switch (op) {
1133 case 0x05: /* SPSel */
1134 if (s->current_pl == 0) {
1135 unallocated_encoding(s);
1136 return;
1137 }
1138 /* fall through */
1139 case 0x1e: /* DAIFSet */
1140 case 0x1f: /* DAIFClear */
1141 {
1142 TCGv_i32 tcg_imm = tcg_const_i32(crm);
1143 TCGv_i32 tcg_op = tcg_const_i32(op);
1144 gen_a64_set_pc_im(s->pc - 4);
1145 gen_helper_msr_i_pstate(cpu_env, tcg_op, tcg_imm);
1146 tcg_temp_free_i32(tcg_imm);
1147 tcg_temp_free_i32(tcg_op);
1148 s->is_jmp = DISAS_UPDATE;
1149 break;
1150 }
1151 default:
1152 unallocated_encoding(s);
1153 return;
1154 }
1155 }
1156
1157 static void gen_get_nzcv(TCGv_i64 tcg_rt)
1158 {
1159 TCGv_i32 tmp = tcg_temp_new_i32();
1160 TCGv_i32 nzcv = tcg_temp_new_i32();
1161
1162 /* build bit 31, N */
1163 tcg_gen_andi_i32(nzcv, cpu_NF, (1 << 31));
1164 /* build bit 30, Z */
1165 tcg_gen_setcondi_i32(TCG_COND_EQ, tmp, cpu_ZF, 0);
1166 tcg_gen_deposit_i32(nzcv, nzcv, tmp, 30, 1);
1167 /* build bit 29, C */
1168 tcg_gen_deposit_i32(nzcv, nzcv, cpu_CF, 29, 1);
1169 /* build bit 28, V */
1170 tcg_gen_shri_i32(tmp, cpu_VF, 31);
1171 tcg_gen_deposit_i32(nzcv, nzcv, tmp, 28, 1);
1172 /* generate result */
1173 tcg_gen_extu_i32_i64(tcg_rt, nzcv);
1174
1175 tcg_temp_free_i32(nzcv);
1176 tcg_temp_free_i32(tmp);
1177 }
1178
1179 static void gen_set_nzcv(TCGv_i64 tcg_rt)
1180
1181 {
1182 TCGv_i32 nzcv = tcg_temp_new_i32();
1183
1184 /* take NZCV from R[t] */
1185 tcg_gen_trunc_i64_i32(nzcv, tcg_rt);
1186
1187 /* bit 31, N */
1188 tcg_gen_andi_i32(cpu_NF, nzcv, (1 << 31));
1189 /* bit 30, Z */
1190 tcg_gen_andi_i32(cpu_ZF, nzcv, (1 << 30));
1191 tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_ZF, cpu_ZF, 0);
1192 /* bit 29, C */
1193 tcg_gen_andi_i32(cpu_CF, nzcv, (1 << 29));
1194 tcg_gen_shri_i32(cpu_CF, cpu_CF, 29);
1195 /* bit 28, V */
1196 tcg_gen_andi_i32(cpu_VF, nzcv, (1 << 28));
1197 tcg_gen_shli_i32(cpu_VF, cpu_VF, 3);
1198 tcg_temp_free_i32(nzcv);
1199 }
1200
1201 /* C5.6.129 MRS - move from system register
1202 * C5.6.131 MSR (register) - move to system register
1203 * C5.6.204 SYS
1204 * C5.6.205 SYSL
1205 * These are all essentially the same insn in 'read' and 'write'
1206 * versions, with varying op0 fields.
1207 */
1208 static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
1209 unsigned int op0, unsigned int op1, unsigned int op2,
1210 unsigned int crn, unsigned int crm, unsigned int rt)
1211 {
1212 const ARMCPRegInfo *ri;
1213 TCGv_i64 tcg_rt;
1214
1215 ri = get_arm_cp_reginfo(s->cp_regs,
1216 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP,
1217 crn, crm, op0, op1, op2));
1218
1219 if (!ri) {
1220 /* Unknown register; this might be a guest error or a QEMU
1221 * unimplemented feature.
1222 */
1223 qemu_log_mask(LOG_UNIMP, "%s access to unsupported AArch64 "
1224 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
1225 isread ? "read" : "write", op0, op1, crn, crm, op2);
1226 unallocated_encoding(s);
1227 return;
1228 }
1229
1230 /* Check access permissions */
1231 if (!cp_access_ok(s->current_pl, ri, isread)) {
1232 unallocated_encoding(s);
1233 return;
1234 }
1235
1236 if (ri->accessfn) {
1237 /* Emit code to perform further access permissions checks at
1238 * runtime; this may result in an exception.
1239 */
1240 TCGv_ptr tmpptr;
1241 gen_a64_set_pc_im(s->pc - 4);
1242 tmpptr = tcg_const_ptr(ri);
1243 gen_helper_access_check_cp_reg(cpu_env, tmpptr);
1244 tcg_temp_free_ptr(tmpptr);
1245 }
1246
1247 /* Handle special cases first */
1248 switch (ri->type & ~(ARM_CP_FLAG_MASK & ~ARM_CP_SPECIAL)) {
1249 case ARM_CP_NOP:
1250 return;
1251 case ARM_CP_NZCV:
1252 tcg_rt = cpu_reg(s, rt);
1253 if (isread) {
1254 gen_get_nzcv(tcg_rt);
1255 } else {
1256 gen_set_nzcv(tcg_rt);
1257 }
1258 return;
1259 case ARM_CP_CURRENTEL:
1260 /* Reads as current EL value from pstate, which is
1261 * guaranteed to be constant by the tb flags.
1262 */
1263 tcg_rt = cpu_reg(s, rt);
1264 tcg_gen_movi_i64(tcg_rt, s->current_pl << 2);
1265 return;
1266 default:
1267 break;
1268 }
1269
1270 if (use_icount && (ri->type & ARM_CP_IO)) {
1271 gen_io_start();
1272 }
1273
1274 tcg_rt = cpu_reg(s, rt);
1275
1276 if (isread) {
1277 if (ri->type & ARM_CP_CONST) {
1278 tcg_gen_movi_i64(tcg_rt, ri->resetvalue);
1279 } else if (ri->readfn) {
1280 TCGv_ptr tmpptr;
1281 tmpptr = tcg_const_ptr(ri);
1282 gen_helper_get_cp_reg64(tcg_rt, cpu_env, tmpptr);
1283 tcg_temp_free_ptr(tmpptr);
1284 } else {
1285 tcg_gen_ld_i64(tcg_rt, cpu_env, ri->fieldoffset);
1286 }
1287 } else {
1288 if (ri->type & ARM_CP_CONST) {
1289 /* If not forbidden by access permissions, treat as WI */
1290 return;
1291 } else if (ri->writefn) {
1292 TCGv_ptr tmpptr;
1293 tmpptr = tcg_const_ptr(ri);
1294 gen_helper_set_cp_reg64(cpu_env, tmpptr, tcg_rt);
1295 tcg_temp_free_ptr(tmpptr);
1296 } else {
1297 tcg_gen_st_i64(tcg_rt, cpu_env, ri->fieldoffset);
1298 }
1299 }
1300
1301 if (use_icount && (ri->type & ARM_CP_IO)) {
1302 /* I/O operations must end the TB here (whether read or write) */
1303 gen_io_end();
1304 s->is_jmp = DISAS_UPDATE;
1305 } else if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) {
1306 /* We default to ending the TB on a coprocessor register write,
1307 * but allow this to be suppressed by the register definition
1308 * (usually only necessary to work around guest bugs).
1309 */
1310 s->is_jmp = DISAS_UPDATE;
1311 }
1312 }
1313
1314 /* C3.2.4 System
1315 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
1316 * +---------------------+---+-----+-----+-------+-------+-----+------+
1317 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
1318 * +---------------------+---+-----+-----+-------+-------+-----+------+
1319 */
1320 static void disas_system(DisasContext *s, uint32_t insn)
1321 {
1322 unsigned int l, op0, op1, crn, crm, op2, rt;
1323 l = extract32(insn, 21, 1);
1324 op0 = extract32(insn, 19, 2);
1325 op1 = extract32(insn, 16, 3);
1326 crn = extract32(insn, 12, 4);
1327 crm = extract32(insn, 8, 4);
1328 op2 = extract32(insn, 5, 3);
1329 rt = extract32(insn, 0, 5);
1330
1331 if (op0 == 0) {
1332 if (l || rt != 31) {
1333 unallocated_encoding(s);
1334 return;
1335 }
1336 switch (crn) {
1337 case 2: /* C5.6.68 HINT */
1338 handle_hint(s, insn, op1, op2, crm);
1339 break;
1340 case 3: /* CLREX, DSB, DMB, ISB */
1341 handle_sync(s, insn, op1, op2, crm);
1342 break;
1343 case 4: /* C5.6.130 MSR (immediate) */
1344 handle_msr_i(s, insn, op1, op2, crm);
1345 break;
1346 default:
1347 unallocated_encoding(s);
1348 break;
1349 }
1350 return;
1351 }
1352 handle_sys(s, insn, l, op0, op1, op2, crn, crm, rt);
1353 }
1354
1355 /* C3.2.3 Exception generation
1356 *
1357 * 31 24 23 21 20 5 4 2 1 0
1358 * +-----------------+-----+------------------------+-----+----+
1359 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
1360 * +-----------------------+------------------------+----------+
1361 */
1362 static void disas_exc(DisasContext *s, uint32_t insn)
1363 {
1364 int opc = extract32(insn, 21, 3);
1365 int op2_ll = extract32(insn, 0, 5);
1366
1367 switch (opc) {
1368 case 0:
1369 /* SVC, HVC, SMC; since we don't support the Virtualization
1370 * or TrustZone extensions these all UNDEF except SVC.
1371 */
1372 if (op2_ll != 1) {
1373 unallocated_encoding(s);
1374 break;
1375 }
1376 gen_exception_insn(s, 0, EXCP_SWI);
1377 break;
1378 case 1:
1379 if (op2_ll != 0) {
1380 unallocated_encoding(s);
1381 break;
1382 }
1383 /* BRK */
1384 gen_exception_insn(s, 0, EXCP_BKPT);
1385 break;
1386 case 2:
1387 if (op2_ll != 0) {
1388 unallocated_encoding(s);
1389 break;
1390 }
1391 /* HLT */
1392 unsupported_encoding(s, insn);
1393 break;
1394 case 5:
1395 if (op2_ll < 1 || op2_ll > 3) {
1396 unallocated_encoding(s);
1397 break;
1398 }
1399 /* DCPS1, DCPS2, DCPS3 */
1400 unsupported_encoding(s, insn);
1401 break;
1402 default:
1403 unallocated_encoding(s);
1404 break;
1405 }
1406 }
1407
1408 /* C3.2.7 Unconditional branch (register)
1409 * 31 25 24 21 20 16 15 10 9 5 4 0
1410 * +---------------+-------+-------+-------+------+-------+
1411 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
1412 * +---------------+-------+-------+-------+------+-------+
1413 */
1414 static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
1415 {
1416 unsigned int opc, op2, op3, rn, op4;
1417
1418 opc = extract32(insn, 21, 4);
1419 op2 = extract32(insn, 16, 5);
1420 op3 = extract32(insn, 10, 6);
1421 rn = extract32(insn, 5, 5);
1422 op4 = extract32(insn, 0, 5);
1423
1424 if (op4 != 0x0 || op3 != 0x0 || op2 != 0x1f) {
1425 unallocated_encoding(s);
1426 return;
1427 }
1428
1429 switch (opc) {
1430 case 0: /* BR */
1431 case 2: /* RET */
1432 break;
1433 case 1: /* BLR */
1434 tcg_gen_movi_i64(cpu_reg(s, 30), s->pc);
1435 break;
1436 case 4: /* ERET */
1437 case 5: /* DRPS */
1438 if (rn != 0x1f) {
1439 unallocated_encoding(s);
1440 } else {
1441 unsupported_encoding(s, insn);
1442 }
1443 return;
1444 default:
1445 unallocated_encoding(s);
1446 return;
1447 }
1448
1449 tcg_gen_mov_i64(cpu_pc, cpu_reg(s, rn));
1450 s->is_jmp = DISAS_JUMP;
1451 }
1452
1453 /* C3.2 Branches, exception generating and system instructions */
1454 static void disas_b_exc_sys(DisasContext *s, uint32_t insn)
1455 {
1456 switch (extract32(insn, 25, 7)) {
1457 case 0x0a: case 0x0b:
1458 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
1459 disas_uncond_b_imm(s, insn);
1460 break;
1461 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
1462 disas_comp_b_imm(s, insn);
1463 break;
1464 case 0x1b: case 0x5b: /* Test & branch (immediate) */
1465 disas_test_b_imm(s, insn);
1466 break;
1467 case 0x2a: /* Conditional branch (immediate) */
1468 disas_cond_b_imm(s, insn);
1469 break;
1470 case 0x6a: /* Exception generation / System */
1471 if (insn & (1 << 24)) {
1472 disas_system(s, insn);
1473 } else {
1474 disas_exc(s, insn);
1475 }
1476 break;
1477 case 0x6b: /* Unconditional branch (register) */
1478 disas_uncond_b_reg(s, insn);
1479 break;
1480 default:
1481 unallocated_encoding(s);
1482 break;
1483 }
1484 }
1485
1486 /*
1487 * Load/Store exclusive instructions are implemented by remembering
1488 * the value/address loaded, and seeing if these are the same
1489 * when the store is performed. This is not actually the architecturally
1490 * mandated semantics, but it works for typical guest code sequences
1491 * and avoids having to monitor regular stores.
1492 *
1493 * In system emulation mode only one CPU will be running at once, so
1494 * this sequence is effectively atomic. In user emulation mode we
1495 * throw an exception and handle the atomic operation elsewhere.
1496 */
1497 static void gen_load_exclusive(DisasContext *s, int rt, int rt2,
1498 TCGv_i64 addr, int size, bool is_pair)
1499 {
1500 TCGv_i64 tmp = tcg_temp_new_i64();
1501 TCGMemOp memop = MO_TE + size;
1502
1503 g_assert(size <= 3);
1504 tcg_gen_qemu_ld_i64(tmp, addr, get_mem_index(s), memop);
1505
1506 if (is_pair) {
1507 TCGv_i64 addr2 = tcg_temp_new_i64();
1508 TCGv_i64 hitmp = tcg_temp_new_i64();
1509
1510 g_assert(size >= 2);
1511 tcg_gen_addi_i64(addr2, addr, 1 << size);
1512 tcg_gen_qemu_ld_i64(hitmp, addr2, get_mem_index(s), memop);
1513 tcg_temp_free_i64(addr2);
1514 tcg_gen_mov_i64(cpu_exclusive_high, hitmp);
1515 tcg_gen_mov_i64(cpu_reg(s, rt2), hitmp);
1516 tcg_temp_free_i64(hitmp);
1517 }
1518
1519 tcg_gen_mov_i64(cpu_exclusive_val, tmp);
1520 tcg_gen_mov_i64(cpu_reg(s, rt), tmp);
1521
1522 tcg_temp_free_i64(tmp);
1523 tcg_gen_mov_i64(cpu_exclusive_addr, addr);
1524 }
1525
1526 #ifdef CONFIG_USER_ONLY
1527 static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
1528 TCGv_i64 addr, int size, int is_pair)
1529 {
1530 tcg_gen_mov_i64(cpu_exclusive_test, addr);
1531 tcg_gen_movi_i32(cpu_exclusive_info,
1532 size | is_pair << 2 | (rd << 4) | (rt << 9) | (rt2 << 14));
1533 gen_exception_insn(s, 4, EXCP_STREX);
1534 }
1535 #else
1536 static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
1537 TCGv_i64 inaddr, int size, int is_pair)
1538 {
1539 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
1540 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
1541 * [addr] = {Rt};
1542 * if (is_pair) {
1543 * [addr + datasize] = {Rt2};
1544 * }
1545 * {Rd} = 0;
1546 * } else {
1547 * {Rd} = 1;
1548 * }
1549 * env->exclusive_addr = -1;
1550 */
1551 int fail_label = gen_new_label();
1552 int done_label = gen_new_label();
1553 TCGv_i64 addr = tcg_temp_local_new_i64();
1554 TCGv_i64 tmp;
1555
1556 /* Copy input into a local temp so it is not trashed when the
1557 * basic block ends at the branch insn.
1558 */
1559 tcg_gen_mov_i64(addr, inaddr);
1560 tcg_gen_brcond_i64(TCG_COND_NE, addr, cpu_exclusive_addr, fail_label);
1561
1562 tmp = tcg_temp_new_i64();
1563 tcg_gen_qemu_ld_i64(tmp, addr, get_mem_index(s), MO_TE + size);
1564 tcg_gen_brcond_i64(TCG_COND_NE, tmp, cpu_exclusive_val, fail_label);
1565 tcg_temp_free_i64(tmp);
1566
1567 if (is_pair) {
1568 TCGv_i64 addrhi = tcg_temp_new_i64();
1569 TCGv_i64 tmphi = tcg_temp_new_i64();
1570
1571 tcg_gen_addi_i64(addrhi, addr, 1 << size);
1572 tcg_gen_qemu_ld_i64(tmphi, addrhi, get_mem_index(s), MO_TE + size);
1573 tcg_gen_brcond_i64(TCG_COND_NE, tmphi, cpu_exclusive_high, fail_label);
1574
1575 tcg_temp_free_i64(tmphi);
1576 tcg_temp_free_i64(addrhi);
1577 }
1578
1579 /* We seem to still have the exclusive monitor, so do the store */
1580 tcg_gen_qemu_st_i64(cpu_reg(s, rt), addr, get_mem_index(s), MO_TE + size);
1581 if (is_pair) {
1582 TCGv_i64 addrhi = tcg_temp_new_i64();
1583
1584 tcg_gen_addi_i64(addrhi, addr, 1 << size);
1585 tcg_gen_qemu_st_i64(cpu_reg(s, rt2), addrhi,
1586 get_mem_index(s), MO_TE + size);
1587 tcg_temp_free_i64(addrhi);
1588 }
1589
1590 tcg_temp_free_i64(addr);
1591
1592 tcg_gen_movi_i64(cpu_reg(s, rd), 0);
1593 tcg_gen_br(done_label);
1594 gen_set_label(fail_label);
1595 tcg_gen_movi_i64(cpu_reg(s, rd), 1);
1596 gen_set_label(done_label);
1597 tcg_gen_movi_i64(cpu_exclusive_addr, -1);
1598
1599 }
1600 #endif
1601
1602 /* C3.3.6 Load/store exclusive
1603 *
1604 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
1605 * +-----+-------------+----+---+----+------+----+-------+------+------+
1606 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
1607 * +-----+-------------+----+---+----+------+----+-------+------+------+
1608 *
1609 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
1610 * L: 0 -> store, 1 -> load
1611 * o2: 0 -> exclusive, 1 -> not
1612 * o1: 0 -> single register, 1 -> register pair
1613 * o0: 1 -> load-acquire/store-release, 0 -> not
1614 *
1615 * o0 == 0 AND o2 == 1 is un-allocated
1616 * o1 == 1 is un-allocated except for 32 and 64 bit sizes
1617 */
1618 static void disas_ldst_excl(DisasContext *s, uint32_t insn)
1619 {
1620 int rt = extract32(insn, 0, 5);
1621 int rn = extract32(insn, 5, 5);
1622 int rt2 = extract32(insn, 10, 5);
1623 int is_lasr = extract32(insn, 15, 1);
1624 int rs = extract32(insn, 16, 5);
1625 int is_pair = extract32(insn, 21, 1);
1626 int is_store = !extract32(insn, 22, 1);
1627 int is_excl = !extract32(insn, 23, 1);
1628 int size = extract32(insn, 30, 2);
1629 TCGv_i64 tcg_addr;
1630
1631 if ((!is_excl && !is_lasr) ||
1632 (is_pair && size < 2)) {
1633 unallocated_encoding(s);
1634 return;
1635 }
1636
1637 if (rn == 31) {
1638 gen_check_sp_alignment(s);
1639 }
1640 tcg_addr = read_cpu_reg_sp(s, rn, 1);
1641
1642 /* Note that since TCG is single threaded load-acquire/store-release
1643 * semantics require no extra if (is_lasr) { ... } handling.
1644 */
1645
1646 if (is_excl) {
1647 if (!is_store) {
1648 gen_load_exclusive(s, rt, rt2, tcg_addr, size, is_pair);
1649 } else {
1650 gen_store_exclusive(s, rs, rt, rt2, tcg_addr, size, is_pair);
1651 }
1652 } else {
1653 TCGv_i64 tcg_rt = cpu_reg(s, rt);
1654 if (is_store) {
1655 do_gpr_st(s, tcg_rt, tcg_addr, size);
1656 } else {
1657 do_gpr_ld(s, tcg_rt, tcg_addr, size, false, false);
1658 }
1659 if (is_pair) {
1660 TCGv_i64 tcg_rt2 = cpu_reg(s, rt);
1661 tcg_gen_addi_i64(tcg_addr, tcg_addr, 1 << size);
1662 if (is_store) {
1663 do_gpr_st(s, tcg_rt2, tcg_addr, size);
1664 } else {
1665 do_gpr_ld(s, tcg_rt2, tcg_addr, size, false, false);
1666 }
1667 }
1668 }
1669 }
1670
1671 /*
1672 * C3.3.5 Load register (literal)
1673 *
1674 * 31 30 29 27 26 25 24 23 5 4 0
1675 * +-----+-------+---+-----+-------------------+-------+
1676 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
1677 * +-----+-------+---+-----+-------------------+-------+
1678 *
1679 * V: 1 -> vector (simd/fp)
1680 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
1681 * 10-> 32 bit signed, 11 -> prefetch
1682 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
1683 */
1684 static void disas_ld_lit(DisasContext *s, uint32_t insn)
1685 {
1686 int rt = extract32(insn, 0, 5);
1687 int64_t imm = sextract32(insn, 5, 19) << 2;
1688 bool is_vector = extract32(insn, 26, 1);
1689 int opc = extract32(insn, 30, 2);
1690 bool is_signed = false;
1691 int size = 2;
1692 TCGv_i64 tcg_rt, tcg_addr;
1693
1694 if (is_vector) {
1695 if (opc == 3) {
1696 unallocated_encoding(s);
1697 return;
1698 }
1699 size = 2 + opc;
1700 } else {
1701 if (opc == 3) {
1702 /* PRFM (literal) : prefetch */
1703 return;
1704 }
1705 size = 2 + extract32(opc, 0, 1);
1706 is_signed = extract32(opc, 1, 1);
1707 }
1708
1709 tcg_rt = cpu_reg(s, rt);
1710
1711 tcg_addr = tcg_const_i64((s->pc - 4) + imm);
1712 if (is_vector) {
1713 do_fp_ld(s, rt, tcg_addr, size);
1714 } else {
1715 do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, false);
1716 }
1717 tcg_temp_free_i64(tcg_addr);
1718 }
1719
1720 /*
1721 * C5.6.80 LDNP (Load Pair - non-temporal hint)
1722 * C5.6.81 LDP (Load Pair - non vector)
1723 * C5.6.82 LDPSW (Load Pair Signed Word - non vector)
1724 * C5.6.176 STNP (Store Pair - non-temporal hint)
1725 * C5.6.177 STP (Store Pair - non vector)
1726 * C6.3.165 LDNP (Load Pair of SIMD&FP - non-temporal hint)
1727 * C6.3.165 LDP (Load Pair of SIMD&FP)
1728 * C6.3.284 STNP (Store Pair of SIMD&FP - non-temporal hint)
1729 * C6.3.284 STP (Store Pair of SIMD&FP)
1730 *
1731 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
1732 * +-----+-------+---+---+-------+---+-----------------------------+
1733 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
1734 * +-----+-------+---+---+-------+---+-------+-------+------+------+
1735 *
1736 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
1737 * LDPSW 01
1738 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
1739 * V: 0 -> GPR, 1 -> Vector
1740 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
1741 * 10 -> signed offset, 11 -> pre-index
1742 * L: 0 -> Store 1 -> Load
1743 *
1744 * Rt, Rt2 = GPR or SIMD registers to be stored
1745 * Rn = general purpose register containing address
1746 * imm7 = signed offset (multiple of 4 or 8 depending on size)
1747 */
1748 static void disas_ldst_pair(DisasContext *s, uint32_t insn)
1749 {
1750 int rt = extract32(insn, 0, 5);
1751 int rn = extract32(insn, 5, 5);
1752 int rt2 = extract32(insn, 10, 5);
1753 int64_t offset = sextract32(insn, 15, 7);
1754 int index = extract32(insn, 23, 2);
1755 bool is_vector = extract32(insn, 26, 1);
1756 bool is_load = extract32(insn, 22, 1);
1757 int opc = extract32(insn, 30, 2);
1758
1759 bool is_signed = false;
1760 bool postindex = false;
1761 bool wback = false;
1762
1763 TCGv_i64 tcg_addr; /* calculated address */
1764 int size;
1765
1766 if (opc == 3) {
1767 unallocated_encoding(s);
1768 return;
1769 }
1770
1771 if (is_vector) {
1772 size = 2 + opc;
1773 } else {
1774 size = 2 + extract32(opc, 1, 1);
1775 is_signed = extract32(opc, 0, 1);
1776 if (!is_load && is_signed) {
1777 unallocated_encoding(s);
1778 return;
1779 }
1780 }
1781
1782 switch (index) {
1783 case 1: /* post-index */
1784 postindex = true;
1785 wback = true;
1786 break;
1787 case 0:
1788 /* signed offset with "non-temporal" hint. Since we don't emulate
1789 * caches we don't care about hints to the cache system about
1790 * data access patterns, and handle this identically to plain
1791 * signed offset.
1792 */
1793 if (is_signed) {
1794 /* There is no non-temporal-hint version of LDPSW */
1795 unallocated_encoding(s);
1796 return;
1797 }
1798 postindex = false;
1799 break;
1800 case 2: /* signed offset, rn not updated */
1801 postindex = false;
1802 break;
1803 case 3: /* pre-index */
1804 postindex = false;
1805 wback = true;
1806 break;
1807 }
1808
1809 offset <<= size;
1810
1811 if (rn == 31) {
1812 gen_check_sp_alignment(s);
1813 }
1814
1815 tcg_addr = read_cpu_reg_sp(s, rn, 1);
1816
1817 if (!postindex) {
1818 tcg_gen_addi_i64(tcg_addr, tcg_addr, offset);
1819 }
1820
1821 if (is_vector) {
1822 if (is_load) {
1823 do_fp_ld(s, rt, tcg_addr, size);
1824 } else {
1825 do_fp_st(s, rt, tcg_addr, size);
1826 }
1827 } else {
1828 TCGv_i64 tcg_rt = cpu_reg(s, rt);
1829 if (is_load) {
1830 do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, false);
1831 } else {
1832 do_gpr_st(s, tcg_rt, tcg_addr, size);
1833 }
1834 }
1835 tcg_gen_addi_i64(tcg_addr, tcg_addr, 1 << size);
1836 if (is_vector) {
1837 if (is_load) {
1838 do_fp_ld(s, rt2, tcg_addr, size);
1839 } else {
1840 do_fp_st(s, rt2, tcg_addr, size);
1841 }
1842 } else {
1843 TCGv_i64 tcg_rt2 = cpu_reg(s, rt2);
1844 if (is_load) {
1845 do_gpr_ld(s, tcg_rt2, tcg_addr, size, is_signed, false);
1846 } else {
1847 do_gpr_st(s, tcg_rt2, tcg_addr, size);
1848 }
1849 }
1850
1851 if (wback) {
1852 if (postindex) {
1853 tcg_gen_addi_i64(tcg_addr, tcg_addr, offset - (1 << size));
1854 } else {
1855 tcg_gen_subi_i64(tcg_addr, tcg_addr, 1 << size);
1856 }
1857 tcg_gen_mov_i64(cpu_reg_sp(s, rn), tcg_addr);
1858 }
1859 }
1860
1861 /*
1862 * C3.3.8 Load/store (immediate post-indexed)
1863 * C3.3.9 Load/store (immediate pre-indexed)
1864 * C3.3.12 Load/store (unscaled immediate)
1865 *
1866 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
1867 * +----+-------+---+-----+-----+---+--------+-----+------+------+
1868 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
1869 * +----+-------+---+-----+-----+---+--------+-----+------+------+
1870 *
1871 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
1872 10 -> unprivileged
1873 * V = 0 -> non-vector
1874 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
1875 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
1876 */
1877 static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn)
1878 {
1879 int rt = extract32(insn, 0, 5);
1880 int rn = extract32(insn, 5, 5);
1881 int imm9 = sextract32(insn, 12, 9);
1882 int opc = extract32(insn, 22, 2);
1883 int size = extract32(insn, 30, 2);
1884 int idx = extract32(insn, 10, 2);
1885 bool is_signed = false;
1886 bool is_store = false;
1887 bool is_extended = false;
1888 bool is_unpriv = (idx == 2);
1889 bool is_vector = extract32(insn, 26, 1);
1890 bool post_index;
1891 bool writeback;
1892
1893 TCGv_i64 tcg_addr;
1894
1895 if (is_vector) {
1896 size |= (opc & 2) << 1;
1897 if (size > 4 || is_unpriv) {
1898 unallocated_encoding(s);
1899 return;
1900 }
1901 is_store = ((opc & 1) == 0);
1902 } else {
1903 if (size == 3 && opc == 2) {
1904 /* PRFM - prefetch */
1905 if (is_unpriv) {
1906 unallocated_encoding(s);
1907 return;
1908 }
1909 return;
1910 }
1911 if (opc == 3 && size > 1) {
1912 unallocated_encoding(s);
1913 return;
1914 }
1915 is_store = (opc == 0);
1916 is_signed = opc & (1<<1);
1917 is_extended = (size < 3) && (opc & 1);
1918 }
1919
1920 switch (idx) {
1921 case 0:
1922 case 2:
1923 post_index = false;
1924 writeback = false;
1925 break;
1926 case 1:
1927 post_index = true;
1928 writeback = true;
1929 break;
1930 case 3:
1931 post_index = false;
1932 writeback = true;
1933 break;
1934 }
1935
1936 if (rn == 31) {
1937 gen_check_sp_alignment(s);
1938 }
1939 tcg_addr = read_cpu_reg_sp(s, rn, 1);
1940
1941 if (!post_index) {
1942 tcg_gen_addi_i64(tcg_addr, tcg_addr, imm9);
1943 }
1944
1945 if (is_vector) {
1946 if (is_store) {
1947 do_fp_st(s, rt, tcg_addr, size);
1948 } else {
1949 do_fp_ld(s, rt, tcg_addr, size);
1950 }
1951 } else {
1952 TCGv_i64 tcg_rt = cpu_reg(s, rt);
1953 int memidx = is_unpriv ? 1 : get_mem_index(s);
1954
1955 if (is_store) {
1956 do_gpr_st_memidx(s, tcg_rt, tcg_addr, size, memidx);
1957 } else {
1958 do_gpr_ld_memidx(s, tcg_rt, tcg_addr, size,
1959 is_signed, is_extended, memidx);
1960 }
1961 }
1962
1963 if (writeback) {
1964 TCGv_i64 tcg_rn = cpu_reg_sp(s, rn);
1965 if (post_index) {
1966 tcg_gen_addi_i64(tcg_addr, tcg_addr, imm9);
1967 }
1968 tcg_gen_mov_i64(tcg_rn, tcg_addr);
1969 }
1970 }
1971
1972 /*
1973 * C3.3.10 Load/store (register offset)
1974 *
1975 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
1976 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
1977 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
1978 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
1979 *
1980 * For non-vector:
1981 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
1982 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
1983 * For vector:
1984 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
1985 * opc<0>: 0 -> store, 1 -> load
1986 * V: 1 -> vector/simd
1987 * opt: extend encoding (see DecodeRegExtend)
1988 * S: if S=1 then scale (essentially index by sizeof(size))
1989 * Rt: register to transfer into/out of
1990 * Rn: address register or SP for base
1991 * Rm: offset register or ZR for offset
1992 */
1993 static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn)
1994 {
1995 int rt = extract32(insn, 0, 5);
1996 int rn = extract32(insn, 5, 5);
1997 int shift = extract32(insn, 12, 1);
1998 int rm = extract32(insn, 16, 5);
1999 int opc = extract32(insn, 22, 2);
2000 int opt = extract32(insn, 13, 3);
2001 int size = extract32(insn, 30, 2);
2002 bool is_signed = false;
2003 bool is_store = false;
2004 bool is_extended = false;
2005 bool is_vector = extract32(insn, 26, 1);
2006
2007 TCGv_i64 tcg_rm;
2008 TCGv_i64 tcg_addr;
2009
2010 if (extract32(opt, 1, 1) == 0) {
2011 unallocated_encoding(s);
2012 return;
2013 }
2014
2015 if (is_vector) {
2016 size |= (opc & 2) << 1;
2017 if (size > 4) {
2018 unallocated_encoding(s);
2019 return;
2020 }
2021 is_store = !extract32(opc, 0, 1);
2022 } else {
2023 if (size == 3 && opc == 2) {
2024 /* PRFM - prefetch */
2025 return;
2026 }
2027 if (opc == 3 && size > 1) {
2028 unallocated_encoding(s);
2029 return;
2030 }
2031 is_store = (opc == 0);
2032 is_signed = extract32(opc, 1, 1);
2033 is_extended = (size < 3) && extract32(opc, 0, 1);
2034 }
2035
2036 if (rn == 31) {
2037 gen_check_sp_alignment(s);
2038 }
2039 tcg_addr = read_cpu_reg_sp(s, rn, 1);
2040
2041 tcg_rm = read_cpu_reg(s, rm, 1);
2042 ext_and_shift_reg(tcg_rm, tcg_rm, opt, shift ? size : 0);
2043
2044 tcg_gen_add_i64(tcg_addr, tcg_addr, tcg_rm);
2045
2046 if (is_vector) {
2047 if (is_store) {
2048 do_fp_st(s, rt, tcg_addr, size);
2049 } else {
2050 do_fp_ld(s, rt, tcg_addr, size);
2051 }
2052 } else {
2053 TCGv_i64 tcg_rt = cpu_reg(s, rt);
2054 if (is_store) {
2055 do_gpr_st(s, tcg_rt, tcg_addr, size);
2056 } else {
2057 do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, is_extended);
2058 }
2059 }
2060 }
2061
2062 /*
2063 * C3.3.13 Load/store (unsigned immediate)
2064 *
2065 * 31 30 29 27 26 25 24 23 22 21 10 9 5
2066 * +----+-------+---+-----+-----+------------+-------+------+
2067 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
2068 * +----+-------+---+-----+-----+------------+-------+------+
2069 *
2070 * For non-vector:
2071 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2072 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2073 * For vector:
2074 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2075 * opc<0>: 0 -> store, 1 -> load
2076 * Rn: base address register (inc SP)
2077 * Rt: target register
2078 */
2079 static void disas_ldst_reg_unsigned_imm(DisasContext *s, uint32_t insn)
2080 {
2081 int rt = extract32(insn, 0, 5);
2082 int rn = extract32(insn, 5, 5);
2083 unsigned int imm12 = extract32(insn, 10, 12);
2084 bool is_vector = extract32(insn, 26, 1);
2085 int size = extract32(insn, 30, 2);
2086 int opc = extract32(insn, 22, 2);
2087 unsigned int offset;
2088
2089 TCGv_i64 tcg_addr;
2090
2091 bool is_store;
2092 bool is_signed = false;
2093 bool is_extended = false;
2094
2095 if (is_vector) {
2096 size |= (opc & 2) << 1;
2097 if (size > 4) {
2098 unallocated_encoding(s);
2099 return;
2100 }
2101 is_store = !extract32(opc, 0, 1);
2102 } else {
2103 if (size == 3 && opc == 2) {
2104 /* PRFM - prefetch */
2105 return;
2106 }
2107 if (opc == 3 && size > 1) {
2108 unallocated_encoding(s);
2109 return;
2110 }
2111 is_store = (opc == 0);
2112 is_signed = extract32(opc, 1, 1);
2113 is_extended = (size < 3) && extract32(opc, 0, 1);
2114 }
2115
2116 if (rn == 31) {
2117 gen_check_sp_alignment(s);
2118 }
2119 tcg_addr = read_cpu_reg_sp(s, rn, 1);
2120 offset = imm12 << size;
2121 tcg_gen_addi_i64(tcg_addr, tcg_addr, offset);
2122
2123 if (is_vector) {
2124 if (is_store) {
2125 do_fp_st(s, rt, tcg_addr, size);
2126 } else {
2127 do_fp_ld(s, rt, tcg_addr, size);
2128 }
2129 } else {
2130 TCGv_i64 tcg_rt = cpu_reg(s, rt);
2131 if (is_store) {
2132 do_gpr_st(s, tcg_rt, tcg_addr, size);
2133 } else {
2134 do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, is_extended);
2135 }
2136 }
2137 }
2138
2139 /* Load/store register (all forms) */
2140 static void disas_ldst_reg(DisasContext *s, uint32_t insn)
2141 {
2142 switch (extract32(insn, 24, 2)) {
2143 case 0:
2144 if (extract32(insn, 21, 1) == 1 && extract32(insn, 10, 2) == 2) {
2145 disas_ldst_reg_roffset(s, insn);
2146 } else {
2147 /* Load/store register (unscaled immediate)
2148 * Load/store immediate pre/post-indexed
2149 * Load/store register unprivileged
2150 */
2151 disas_ldst_reg_imm9(s, insn);
2152 }
2153 break;
2154 case 1:
2155 disas_ldst_reg_unsigned_imm(s, insn);
2156 break;
2157 default:
2158 unallocated_encoding(s);
2159 break;
2160 }
2161 }
2162
2163 /* C3.3.1 AdvSIMD load/store multiple structures
2164 *
2165 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
2166 * +---+---+---------------+---+-------------+--------+------+------+------+
2167 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
2168 * +---+---+---------------+---+-------------+--------+------+------+------+
2169 *
2170 * C3.3.2 AdvSIMD load/store multiple structures (post-indexed)
2171 *
2172 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
2173 * +---+---+---------------+---+---+---------+--------+------+------+------+
2174 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
2175 * +---+---+---------------+---+---+---------+--------+------+------+------+
2176 *
2177 * Rt: first (or only) SIMD&FP register to be transferred
2178 * Rn: base address or SP
2179 * Rm (post-index only): post-index register (when !31) or size dependent #imm
2180 */
2181 static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn)
2182 {
2183 int rt = extract32(insn, 0, 5);
2184 int rn = extract32(insn, 5, 5);
2185 int size = extract32(insn, 10, 2);
2186 int opcode = extract32(insn, 12, 4);
2187 bool is_store = !extract32(insn, 22, 1);
2188 bool is_postidx = extract32(insn, 23, 1);
2189 bool is_q = extract32(insn, 30, 1);
2190 TCGv_i64 tcg_addr, tcg_rn;
2191
2192 int ebytes = 1 << size;
2193 int elements = (is_q ? 128 : 64) / (8 << size);
2194 int rpt; /* num iterations */
2195 int selem; /* structure elements */
2196 int r;
2197
2198 if (extract32(insn, 31, 1) || extract32(insn, 21, 1)) {
2199 unallocated_encoding(s);
2200 return;
2201 }
2202
2203 /* From the shared decode logic */
2204 switch (opcode) {
2205 case 0x0:
2206 rpt = 1;
2207 selem = 4;
2208 break;
2209 case 0x2:
2210 rpt = 4;
2211 selem = 1;
2212 break;
2213 case 0x4:
2214 rpt = 1;
2215 selem = 3;
2216 break;
2217 case 0x6:
2218 rpt = 3;
2219 selem = 1;
2220 break;
2221 case 0x7:
2222 rpt = 1;
2223 selem = 1;
2224 break;
2225 case 0x8:
2226 rpt = 1;
2227 selem = 2;
2228 break;
2229 case 0xa:
2230 rpt = 2;
2231 selem = 1;
2232 break;
2233 default:
2234 unallocated_encoding(s);
2235 return;
2236 }
2237
2238 if (size == 3 && !is_q && selem != 1) {
2239 /* reserved */
2240 unallocated_encoding(s);
2241 return;
2242 }
2243
2244 if (rn == 31) {
2245 gen_check_sp_alignment(s);
2246 }
2247
2248 tcg_rn = cpu_reg_sp(s, rn);
2249 tcg_addr = tcg_temp_new_i64();
2250 tcg_gen_mov_i64(tcg_addr, tcg_rn);
2251
2252 for (r = 0; r < rpt; r++) {
2253 int e;
2254 for (e = 0; e < elements; e++) {
2255 int tt = (rt + r) % 32;
2256 int xs;
2257 for (xs = 0; xs < selem; xs++) {
2258 if (is_store) {
2259 do_vec_st(s, tt, e, tcg_addr, size);
2260 } else {
2261 do_vec_ld(s, tt, e, tcg_addr, size);
2262
2263 /* For non-quad operations, setting a slice of the low
2264 * 64 bits of the register clears the high 64 bits (in
2265 * the ARM ARM pseudocode this is implicit in the fact
2266 * that 'rval' is a 64 bit wide variable). We optimize
2267 * by noticing that we only need to do this the first
2268 * time we touch a register.
2269 */
2270 if (!is_q && e == 0 && (r == 0 || xs == selem - 1)) {
2271 clear_vec_high(s, tt);
2272 }
2273 }
2274 tcg_gen_addi_i64(tcg_addr, tcg_addr, ebytes);
2275 tt = (tt + 1) % 32;
2276 }
2277 }
2278 }
2279
2280 if (is_postidx) {
2281 int rm = extract32(insn, 16, 5);
2282 if (rm == 31) {
2283 tcg_gen_mov_i64(tcg_rn, tcg_addr);
2284 } else {
2285 tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm));
2286 }
2287 }
2288 tcg_temp_free_i64(tcg_addr);
2289 }
2290
2291 /* C3.3.3 AdvSIMD load/store single structure
2292 *
2293 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2294 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2295 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
2296 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2297 *
2298 * C3.3.4 AdvSIMD load/store single structure (post-indexed)
2299 *
2300 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2301 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2302 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
2303 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2304 *
2305 * Rt: first (or only) SIMD&FP register to be transferred
2306 * Rn: base address or SP
2307 * Rm (post-index only): post-index register (when !31) or size dependent #imm
2308 * index = encoded in Q:S:size dependent on size
2309 *
2310 * lane_size = encoded in R, opc
2311 * transfer width = encoded in opc, S, size
2312 */
2313 static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)
2314 {
2315 int rt = extract32(insn, 0, 5);
2316 int rn = extract32(insn, 5, 5);
2317 int size = extract32(insn, 10, 2);
2318 int S = extract32(insn, 12, 1);
2319 int opc = extract32(insn, 13, 3);
2320 int R = extract32(insn, 21, 1);
2321 int is_load = extract32(insn, 22, 1);
2322 int is_postidx = extract32(insn, 23, 1);
2323 int is_q = extract32(insn, 30, 1);
2324
2325 int scale = extract32(opc, 1, 2);
2326 int selem = (extract32(opc, 0, 1) << 1 | R) + 1;
2327 bool replicate = false;
2328 int index = is_q << 3 | S << 2 | size;
2329 int ebytes, xs;
2330 TCGv_i64 tcg_addr, tcg_rn;
2331
2332 switch (scale) {
2333 case 3:
2334 if (!is_load || S) {
2335 unallocated_encoding(s);
2336 return;
2337 }
2338 scale = size;
2339 replicate = true;
2340 break;
2341 case 0:
2342 break;
2343 case 1:
2344 if (extract32(size, 0, 1)) {
2345 unallocated_encoding(s);
2346 return;
2347 }
2348 index >>= 1;
2349 break;
2350 case 2:
2351 if (extract32(size, 1, 1)) {
2352 unallocated_encoding(s);
2353 return;
2354 }
2355 if (!extract32(size, 0, 1)) {
2356 index >>= 2;
2357 } else {
2358 if (S) {
2359 unallocated_encoding(s);
2360 return;
2361 }
2362 index >>= 3;
2363 scale = 3;
2364 }
2365 break;
2366 default:
2367 g_assert_not_reached();
2368 }
2369
2370 ebytes = 1 << scale;
2371
2372 if (rn == 31) {
2373 gen_check_sp_alignment(s);
2374 }
2375
2376 tcg_rn = cpu_reg_sp(s, rn);
2377 tcg_addr = tcg_temp_new_i64();
2378 tcg_gen_mov_i64(tcg_addr, tcg_rn);
2379
2380 for (xs = 0; xs < selem; xs++) {
2381 if (replicate) {
2382 /* Load and replicate to all elements */
2383 uint64_t mulconst;
2384 TCGv_i64 tcg_tmp = tcg_temp_new_i64();
2385
2386 tcg_gen_qemu_ld_i64(tcg_tmp, tcg_addr,
2387 get_mem_index(s), MO_TE + scale);
2388 switch (scale) {
2389 case 0:
2390 mulconst = 0x0101010101010101ULL;
2391 break;
2392 case 1:
2393 mulconst = 0x0001000100010001ULL;
2394 break;
2395 case 2:
2396 mulconst = 0x0000000100000001ULL;
2397 break;
2398 case 3:
2399 mulconst = 0;
2400 break;
2401 default:
2402 g_assert_not_reached();
2403 }
2404 if (mulconst) {
2405 tcg_gen_muli_i64(tcg_tmp, tcg_tmp, mulconst);
2406 }
2407 write_vec_element(s, tcg_tmp, rt, 0, MO_64);
2408 if (is_q) {
2409 write_vec_element(s, tcg_tmp, rt, 1, MO_64);
2410 } else {
2411 clear_vec_high(s, rt);
2412 }
2413 tcg_temp_free_i64(tcg_tmp);
2414 } else {
2415 /* Load/store one element per register */
2416 if (is_load) {
2417 do_vec_ld(s, rt, index, tcg_addr, MO_TE + scale);
2418 } else {
2419 do_vec_st(s, rt, index, tcg_addr, MO_TE + scale);
2420 }
2421 }
2422 tcg_gen_addi_i64(tcg_addr, tcg_addr, ebytes);
2423 rt = (rt + 1) % 32;
2424 }
2425
2426 if (is_postidx) {
2427 int rm = extract32(insn, 16, 5);
2428 if (rm == 31) {
2429 tcg_gen_mov_i64(tcg_rn, tcg_addr);
2430 } else {
2431 tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm));
2432 }
2433 }
2434 tcg_temp_free_i64(tcg_addr);
2435 }
2436
2437 /* C3.3 Loads and stores */
2438 static void disas_ldst(DisasContext *s, uint32_t insn)
2439 {
2440 switch (extract32(insn, 24, 6)) {
2441 case 0x08: /* Load/store exclusive */
2442 disas_ldst_excl(s, insn);
2443 break;
2444 case 0x18: case 0x1c: /* Load register (literal) */
2445 disas_ld_lit(s, insn);
2446 break;
2447 case 0x28: case 0x29:
2448 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
2449 disas_ldst_pair(s, insn);
2450 break;
2451 case 0x38: case 0x39:
2452 case 0x3c: case 0x3d: /* Load/store register (all forms) */
2453 disas_ldst_reg(s, insn);
2454 break;
2455 case 0x0c: /* AdvSIMD load/store multiple structures */
2456 disas_ldst_multiple_struct(s, insn);
2457 break;
2458 case 0x0d: /* AdvSIMD load/store single structure */
2459 disas_ldst_single_struct(s, insn);
2460 break;
2461 default:
2462 unallocated_encoding(s);
2463 break;
2464 }
2465 }
2466
2467 /* C3.4.6 PC-rel. addressing
2468 * 31 30 29 28 24 23 5 4 0
2469 * +----+-------+-----------+-------------------+------+
2470 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
2471 * +----+-------+-----------+-------------------+------+
2472 */
2473 static void disas_pc_rel_adr(DisasContext *s, uint32_t insn)
2474 {
2475 unsigned int page, rd;
2476 uint64_t base;
2477 int64_t offset;
2478
2479 page = extract32(insn, 31, 1);
2480 /* SignExtend(immhi:immlo) -> offset */
2481 offset = ((int64_t)sextract32(insn, 5, 19) << 2) | extract32(insn, 29, 2);
2482 rd = extract32(insn, 0, 5);
2483 base = s->pc - 4;
2484
2485 if (page) {
2486 /* ADRP (page based) */
2487 base &= ~0xfff;
2488 offset <<= 12;
2489 }
2490
2491 tcg_gen_movi_i64(cpu_reg(s, rd), base + offset);
2492 }
2493
2494 /*
2495 * C3.4.1 Add/subtract (immediate)
2496 *
2497 * 31 30 29 28 24 23 22 21 10 9 5 4 0
2498 * +--+--+--+-----------+-----+-------------+-----+-----+
2499 * |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd |
2500 * +--+--+--+-----------+-----+-------------+-----+-----+
2501 *
2502 * sf: 0 -> 32bit, 1 -> 64bit
2503 * op: 0 -> add , 1 -> sub
2504 * S: 1 -> set flags
2505 * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12
2506 */
2507 static void disas_add_sub_imm(DisasContext *s, uint32_t insn)
2508 {
2509 int rd = extract32(insn, 0, 5);
2510 int rn = extract32(insn, 5, 5);
2511 uint64_t imm = extract32(insn, 10, 12);
2512 int shift = extract32(insn, 22, 2);
2513 bool setflags = extract32(insn, 29, 1);
2514 bool sub_op = extract32(insn, 30, 1);
2515 bool is_64bit = extract32(insn, 31, 1);
2516
2517 TCGv_i64 tcg_rn = cpu_reg_sp(s, rn);
2518 TCGv_i64 tcg_rd = setflags ? cpu_reg(s, rd) : cpu_reg_sp(s, rd);
2519 TCGv_i64 tcg_result;
2520
2521 switch (shift) {
2522 case 0x0:
2523 break;
2524 case 0x1:
2525 imm <<= 12;
2526 break;
2527 default:
2528 unallocated_encoding(s);
2529 return;
2530 }
2531
2532 tcg_result = tcg_temp_new_i64();
2533 if (!setflags) {
2534 if (sub_op) {
2535 tcg_gen_subi_i64(tcg_result, tcg_rn, imm);
2536 } else {
2537 tcg_gen_addi_i64(tcg_result, tcg_rn, imm);
2538 }
2539 } else {
2540 TCGv_i64 tcg_imm = tcg_const_i64(imm);
2541 if (sub_op) {
2542 gen_sub_CC(is_64bit, tcg_result, tcg_rn, tcg_imm);
2543 } else {
2544 gen_add_CC(is_64bit, tcg_result, tcg_rn, tcg_imm);
2545 }
2546 tcg_temp_free_i64(tcg_imm);
2547 }
2548
2549 if (is_64bit) {
2550 tcg_gen_mov_i64(tcg_rd, tcg_result);
2551 } else {
2552 tcg_gen_ext32u_i64(tcg_rd, tcg_result);
2553 }
2554
2555 tcg_temp_free_i64(tcg_result);
2556 }
2557
2558 /* The input should be a value in the bottom e bits (with higher
2559 * bits zero); returns that value replicated into every element
2560 * of size e in a 64 bit integer.
2561 */
2562 static uint64_t bitfield_replicate(uint64_t mask, unsigned int e)
2563 {
2564 assert(e != 0);
2565 while (e < 64) {
2566 mask |= mask << e;
2567 e *= 2;
2568 }
2569 return mask;
2570 }
2571
2572 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
2573 static inline uint64_t bitmask64(unsigned int length)
2574 {
2575 assert(length > 0 && length <= 64);
2576 return ~0ULL >> (64 - length);
2577 }
2578
2579 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
2580 * only require the wmask. Returns false if the imms/immr/immn are a reserved
2581 * value (ie should cause a guest UNDEF exception), and true if they are
2582 * valid, in which case the decoded bit pattern is written to result.
2583 */
2584 static bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn,
2585 unsigned int imms, unsigned int immr)
2586 {
2587 uint64_t mask;
2588 unsigned e, levels, s, r;
2589 int len;
2590
2591 assert(immn < 2 && imms < 64 && immr < 64);
2592
2593 /* The bit patterns we create here are 64 bit patterns which
2594 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
2595 * 64 bits each. Each element contains the same value: a run
2596 * of between 1 and e-1 non-zero bits, rotated within the
2597 * element by between 0 and e-1 bits.
2598 *
2599 * The element size and run length are encoded into immn (1 bit)
2600 * and imms (6 bits) as follows:
2601 * 64 bit elements: immn = 1, imms = <length of run - 1>
2602 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
2603 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
2604 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
2605 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
2606 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
2607 * Notice that immn = 0, imms = 11111x is the only combination
2608 * not covered by one of the above options; this is reserved.
2609 * Further, <length of run - 1> all-ones is a reserved pattern.
2610 *
2611 * In all cases the rotation is by immr % e (and immr is 6 bits).
2612 */
2613
2614 /* First determine the element size */
2615 len = 31 - clz32((immn << 6) | (~imms & 0x3f));
2616 if (len < 1) {
2617 /* This is the immn == 0, imms == 0x11111x case */
2618 return false;
2619 }
2620 e = 1 << len;
2621
2622 levels = e - 1;
2623 s = imms & levels;
2624 r = immr & levels;
2625
2626 if (s == levels) {
2627 /* <length of run - 1> mustn't be all-ones. */
2628 return false;
2629 }
2630
2631 /* Create the value of one element: s+1 set bits rotated
2632 * by r within the element (which is e bits wide)...
2633 */
2634 mask = bitmask64(s + 1);
2635 mask = (mask >> r) | (mask << (e - r));
2636 /* ...then replicate the element over the whole 64 bit value */
2637 mask = bitfield_replicate(mask, e);
2638 *result = mask;
2639 return true;
2640 }
2641
2642 /* C3.4.4 Logical (immediate)
2643 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
2644 * +----+-----+-------------+---+------+------+------+------+
2645 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
2646 * +----+-----+-------------+---+------+------+------+------+
2647 */
2648 static void disas_logic_imm(DisasContext *s, uint32_t insn)
2649 {
2650 unsigned int sf, opc, is_n, immr, imms, rn, rd;
2651 TCGv_i64 tcg_rd, tcg_rn;
2652 uint64_t wmask;
2653 bool is_and = false;
2654
2655 sf = extract32(insn, 31, 1);
2656 opc = extract32(insn, 29, 2);
2657 is_n = extract32(insn, 22, 1);
2658 immr = extract32(insn, 16, 6);
2659 imms = extract32(insn, 10, 6);
2660 rn = extract32(insn, 5, 5);
2661 rd = extract32(insn, 0, 5);
2662
2663 if (!sf && is_n) {
2664 unallocated_encoding(s);
2665 return;
2666 }
2667
2668 if (opc == 0x3) { /* ANDS */
2669 tcg_rd = cpu_reg(s, rd);
2670 } else {
2671 tcg_rd = cpu_reg_sp(s, rd);
2672 }
2673 tcg_rn = cpu_reg(s, rn);
2674
2675 if (!logic_imm_decode_wmask(&wmask, is_n, imms, immr)) {
2676 /* some immediate field values are reserved */
2677 unallocated_encoding(s);
2678 return;
2679 }
2680
2681 if (!sf) {
2682 wmask &= 0xffffffff;
2683 }
2684
2685 switch (opc) {
2686 case 0x3: /* ANDS */
2687 case 0x0: /* AND */
2688 tcg_gen_andi_i64(tcg_rd, tcg_rn, wmask);
2689 is_and = true;
2690 break;
2691 case 0x1: /* ORR */
2692 tcg_gen_ori_i64(tcg_rd, tcg_rn, wmask);
2693 break;
2694 case 0x2: /* EOR */
2695 tcg_gen_xori_i64(tcg_rd, tcg_rn, wmask);
2696 break;
2697 default:
2698 assert(FALSE); /* must handle all above */
2699 break;
2700 }
2701
2702 if (!sf && !is_and) {
2703 /* zero extend final result; we know we can skip this for AND
2704 * since the immediate had the high 32 bits clear.
2705 */
2706 tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
2707 }
2708
2709 if (opc == 3) { /* ANDS */
2710 gen_logic_CC(sf, tcg_rd);
2711 }
2712 }
2713
2714 /*
2715 * C3.4.5 Move wide (immediate)
2716 *
2717 * 31 30 29 28 23 22 21 20 5 4 0
2718 * +--+-----+-------------+-----+----------------+------+
2719 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
2720 * +--+-----+-------------+-----+----------------+------+
2721 *
2722 * sf: 0 -> 32 bit, 1 -> 64 bit
2723 * opc: 00 -> N, 10 -> Z, 11 -> K
2724 * hw: shift/16 (0,16, and sf only 32, 48)
2725 */
2726 static void disas_movw_imm(DisasContext *s, uint32_t insn)
2727 {
2728 int rd = extract32(insn, 0, 5);
2729 uint64_t imm = extract32(insn, 5, 16);
2730 int sf = extract32(insn, 31, 1);
2731 int opc = extract32(insn, 29, 2);
2732 int pos = extract32(insn, 21, 2) << 4;
2733 TCGv_i64 tcg_rd = cpu_reg(s, rd);
2734 TCGv_i64 tcg_imm;
2735
2736 if (!sf && (pos >= 32)) {
2737 unallocated_encoding(s);
2738 return;
2739 }
2740
2741 switch (opc) {
2742 case 0: /* MOVN */
2743 case 2: /* MOVZ */
2744 imm <<= pos;
2745 if (opc == 0) {
2746 imm = ~imm;
2747 }
2748 if (!sf) {
2749 imm &= 0xffffffffu;
2750 }
2751 tcg_gen_movi_i64(tcg_rd, imm);
2752 break;
2753 case 3: /* MOVK */
2754 tcg_imm = tcg_const_i64(imm);
2755 tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_imm, pos, 16);
2756 tcg_temp_free_i64(tcg_imm);
2757 if (!sf) {
2758 tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
2759 }
2760 break;
2761 default:
2762 unallocated_encoding(s);
2763 break;
2764 }
2765 }
2766
2767 /* C3.4.2 Bitfield
2768 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
2769 * +----+-----+-------------+---+------+------+------+------+
2770 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
2771 * +----+-----+-------------+---+------+------+------+------+
2772 */
2773 static void disas_bitfield(DisasContext *s, uint32_t insn)
2774 {
2775 unsigned int sf, n, opc, ri, si, rn, rd, bitsize, pos, len;
2776 TCGv_i64 tcg_rd, tcg_tmp;
2777
2778 sf = extract32(insn, 31, 1);
2779 opc = extract32(insn, 29, 2);
2780 n = extract32(insn, 22, 1);
2781 ri = extract32(insn, 16, 6);
2782 si = extract32(insn, 10, 6);
2783 rn = extract32(insn, 5, 5);
2784 rd = extract32(insn, 0, 5);
2785 bitsize = sf ? 64 : 32;
2786
2787 if (sf != n || ri >= bitsize || si >= bitsize || opc > 2) {
2788 unallocated_encoding(s);
2789 return;
2790 }
2791
2792 tcg_rd = cpu_reg(s, rd);
2793 tcg_tmp = read_cpu_reg(s, rn, sf);
2794
2795 /* OPTME: probably worth recognizing common cases of ext{8,16,32}{u,s} */
2796
2797 if (opc != 1) { /* SBFM or UBFM */
2798 tcg_gen_movi_i64(tcg_rd, 0);
2799 }
2800
2801 /* do the bit move operation */
2802 if (si >= ri) {
2803 /* Wd<s-r:0> = Wn<s:r> */
2804 tcg_gen_shri_i64(tcg_tmp, tcg_tmp, ri);
2805 pos = 0;
2806 len = (si - ri) + 1;
2807 } else {
2808 /* Wd<32+s-r,32-r> = Wn<s:0> */
2809 pos = bitsize - ri;
2810 len = si + 1;
2811 }
2812
2813 tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, pos, len);
2814
2815 if (opc == 0) { /* SBFM - sign extend the destination field */
2816 tcg_gen_shli_i64(tcg_rd, tcg_rd, 64 - (pos + len));
2817 tcg_gen_sari_i64(tcg_rd, tcg_rd, 64 - (pos + len));
2818 }
2819
2820 if (!sf) { /* zero extend final result */
2821 tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
2822 }
2823 }
2824
2825 /* C3.4.3 Extract
2826 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
2827 * +----+------+-------------+---+----+------+--------+------+------+
2828 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
2829 * +----+------+-------------+---+----+------+--------+------+------+
2830 */
2831 static void disas_extract(DisasContext *s, uint32_t insn)
2832 {
2833 unsigned int sf, n, rm, imm, rn, rd, bitsize, op21, op0;
2834
2835 sf = extract32(insn, 31, 1);
2836 n = extract32(insn, 22, 1);
2837 rm = extract32(insn, 16, 5);
2838 imm = extract32(insn, 10, 6);
2839 rn = extract32(insn, 5, 5);
2840 rd = extract32(insn, 0, 5);
2841 op21 = extract32(insn, 29, 2);
2842 op0 = extract32(insn, 21, 1);
2843 bitsize = sf ? 64 : 32;
2844
2845 if (sf != n || op21 || op0 || imm >= bitsize) {
2846 unallocated_encoding(s);
2847 } else {
2848 TCGv_i64 tcg_rd, tcg_rm, tcg_rn;
2849
2850 tcg_rd = cpu_reg(s, rd);
2851
2852 if (imm) {
2853 /* OPTME: we can special case rm==rn as a rotate */
2854 tcg_rm = read_cpu_reg(s, rm, sf);
2855 tcg_rn = read_cpu_reg(s, rn, sf);
2856 tcg_gen_shri_i64(tcg_rm, tcg_rm, imm);
2857 tcg_gen_shli_i64(tcg_rn, tcg_rn, bitsize - imm);
2858 tcg_gen_or_i64(tcg_rd, tcg_rm, tcg_rn);
2859 if (!sf) {
2860 tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
2861 }
2862 } else {
2863 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
2864 * so an extract from bit 0 is a special case.
2865 */
2866 if (sf) {
2867 tcg_gen_mov_i64(tcg_rd, cpu_reg(s, rm));
2868 } else {
2869 tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rm));
2870 }
2871 }
2872
2873 }
2874 }
2875
2876 /* C3.4 Data processing - immediate */
2877 static void disas_data_proc_imm(DisasContext *s, uint32_t insn)
2878 {
2879 switch (extract32(insn, 23, 6)) {
2880 case 0x20: case 0x21: /* PC-rel. addressing */
2881 disas_pc_rel_adr(s, insn);
2882 break;
2883 case 0x22: case 0x23: /* Add/subtract (immediate) */
2884 disas_add_sub_imm(s, insn);
2885 break;
2886 case 0x24: /* Logical (immediate) */
2887 disas_logic_imm(s, insn);
2888 break;
2889 case 0x25: /* Move wide (immediate) */
2890 disas_movw_imm(s, insn);
2891 break;
2892 case 0x26: /* Bitfield */
2893 disas_bitfield(s, insn);
2894 break;
2895 case 0x27: /* Extract */
2896 disas_extract(s, insn);
2897 break;
2898 default:
2899 unallocated_encoding(s);
2900 break;
2901 }
2902 }
2903
2904 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
2905 * Note that it is the caller's responsibility to ensure that the
2906 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
2907 * mandated semantics for out of range shifts.
2908 */
2909 static void shift_reg(TCGv_i64 dst, TCGv_i64 src, int sf,
2910 enum a64_shift_type shift_type, TCGv_i64 shift_amount)
2911 {
2912 switch (shift_type) {
2913 case A64_SHIFT_TYPE_LSL:
2914 tcg_gen_shl_i64(dst, src, shift_amount);
2915 break;
2916 case A64_SHIFT_TYPE_LSR:
2917 tcg_gen_shr_i64(dst, src, shift_amount);
2918 break;
2919 case A64_SHIFT_TYPE_ASR:
2920 if (!sf) {
2921 tcg_gen_ext32s_i64(dst, src);
2922 }
2923 tcg_gen_sar_i64(dst, sf ? src : dst, shift_amount);
2924 break;
2925 case A64_SHIFT_TYPE_ROR:
2926 if (sf) {
2927 tcg_gen_rotr_i64(dst, src, shift_amount);
2928 } else {
2929 TCGv_i32 t0, t1;
2930 t0 = tcg_temp_new_i32();
2931 t1 = tcg_temp_new_i32();
2932 tcg_gen_trunc_i64_i32(t0, src);
2933 tcg_gen_trunc_i64_i32(t1, shift_amount);
2934 tcg_gen_rotr_i32(t0, t0, t1);
2935 tcg_gen_extu_i32_i64(dst, t0);
2936 tcg_temp_free_i32(t0);
2937 tcg_temp_free_i32(t1);
2938 }
2939 break;
2940 default:
2941 assert(FALSE); /* all shift types should be handled */
2942 break;
2943 }
2944
2945 if (!sf) { /* zero extend final result */
2946 tcg_gen_ext32u_i64(dst, dst);
2947 }
2948 }
2949
2950 /* Shift a TCGv src by immediate, put result in dst.
2951 * The shift amount must be in range (this should always be true as the
2952 * relevant instructions will UNDEF on bad shift immediates).
2953 */
2954 static void shift_reg_imm(TCGv_i64 dst, TCGv_i64 src, int sf,
2955 enum a64_shift_type shift_type, unsigned int shift_i)
2956 {
2957 assert(shift_i < (sf ? 64 : 32));
2958
2959 if (shift_i == 0) {
2960 tcg_gen_mov_i64(dst, src);
2961 } else {
2962 TCGv_i64 shift_const;
2963
2964 shift_const = tcg_const_i64(shift_i);
2965 shift_reg(dst, src, sf, shift_type, shift_const);
2966 tcg_temp_free_i64(shift_const);
2967 }
2968 }
2969
2970 /* C3.5.10 Logical (shifted register)
2971 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
2972 * +----+-----+-----------+-------+---+------+--------+------+------+
2973 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
2974 * +----+-----+-----------+-------+---+------+--------+------+------+
2975 */
2976 static void disas_logic_reg(DisasContext *s, uint32_t insn)
2977 {
2978 TCGv_i64 tcg_rd, tcg_rn, tcg_rm;
2979 unsigned int sf, opc, shift_type, invert, rm, shift_amount, rn, rd;
2980
2981 sf = extract32(insn, 31, 1);
2982 opc = extract32(insn, 29, 2);
2983 shift_type = extract32(insn, 22, 2);
2984 invert = extract32(insn, 21, 1);
2985 rm = extract32(insn, 16, 5);
2986 shift_amount = extract32(insn, 10, 6);
2987 rn = extract32(insn, 5, 5);
2988 rd = extract32(insn, 0, 5);
2989
2990 if (!sf && (shift_amount & (1 << 5))) {
2991 unallocated_encoding(s);
2992 return;
2993 }
2994
2995 tcg_rd = cpu_reg(s, rd);
2996
2997 if (opc == 1 && shift_amount == 0 && shift_type == 0 && rn == 31) {
2998 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
2999 * register-register MOV and MVN, so it is worth special casing.
3000 */
3001 tcg_rm = cpu_reg(s, rm);
3002 if (invert) {
3003 tcg_gen_not_i64(tcg_rd, tcg_rm);
3004 if (!sf) {
3005 tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
3006 }
3007 } else {
3008 if (sf) {
3009 tcg_gen_mov_i64(tcg_rd, tcg_rm);
3010 } else {
3011 tcg_gen_ext32u_i64(tcg_rd, tcg_rm);
3012 }
3013 }
3014 return;
3015 }
3016
3017 tcg_rm = read_cpu_reg(s, rm, sf);
3018
3019 if (shift_amount) {
3020 shift_reg_imm(tcg_rm, tcg_rm, sf, shift_type, shift_amount);
3021 }
3022
3023 tcg_rn = cpu_reg(s, rn);
3024
3025 switch (opc | (invert << 2)) {
3026 case 0: /* AND */
3027 case 3: /* ANDS */
3028 tcg_gen_and_i64(tcg_rd, tcg_rn, tcg_rm);
3029 break;
3030 case 1: /* ORR */
3031 tcg_gen_or_i64(tcg_rd, tcg_rn, tcg_rm);
3032 break;
3033 case 2: /* EOR */
3034 tcg_gen_xor_i64(tcg_rd, tcg_rn, tcg_rm);
3035 break;
3036 case 4: /* BIC */
3037 case 7: /* BICS */
3038 tcg_gen_andc_i64(tcg_rd, tcg_rn, tcg_rm);
3039 break;
3040 case 5: /* ORN */
3041 tcg_gen_orc_i64(tcg_rd, tcg_rn, tcg_rm);
3042 break;
3043 case 6: /* EON */
3044 tcg_gen_eqv_i64(tcg_rd, tcg_rn, tcg_rm);
3045 break;
3046 default:
3047 assert(FALSE);
3048 break;
3049 }
3050
3051 if (!sf) {
3052 tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
3053 }
3054
3055 if (opc == 3) {
3056 gen_logic_CC(sf, tcg_rd);
3057 }
3058 }
3059
3060 /*
3061 * C3.5.1 Add/subtract (extended register)
3062 *
3063 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
3064 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3065 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
3066 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3067 *
3068 * sf: 0 -> 32bit, 1 -> 64bit
3069 * op: 0 -> add , 1 -> sub
3070 * S: 1 -> set flags
3071 * opt: 00
3072 * option: extension type (see DecodeRegExtend)
3073 * imm3: optional shift to Rm
3074 *
3075 * Rd = Rn + LSL(extend(Rm), amount)
3076 */
3077 static void disas_add_sub_ext_reg(DisasContext *s, uint32_t insn)
3078 {
3079 int rd = extract32(insn, 0, 5);
3080 int rn = extract32(insn, 5, 5);
3081 int imm3 = extract32(insn, 10, 3);
3082 int option = extract32(insn, 13, 3);
3083 int rm = extract32(insn, 16, 5);
3084 bool setflags = extract32(insn, 29, 1);
3085 bool sub_op = extract32(insn, 30, 1);
3086 bool sf = extract32(insn, 31, 1);
3087
3088 TCGv_i64 tcg_rm, tcg_rn; /* temps */
3089 TCGv_i64 tcg_rd;
3090 TCGv_i64 tcg_result;
3091
3092 if (imm3 > 4) {
3093 unallocated_encoding(s);
3094 return;
3095 }
3096
3097 /* non-flag setting ops may use SP */
3098 if (!setflags) {
3099 tcg_rn = read_cpu_reg_sp(s, rn, sf);
3100 tcg_rd = cpu_reg_sp(s, rd);
3101 } else {
3102 tcg_rn = read_cpu_reg(s, rn, sf);
3103 tcg_rd = cpu_reg(s, rd);
3104 }
3105
3106 tcg_rm = read_cpu_reg(s, rm, sf);
3107 ext_and_shift_reg(tcg_rm, tcg_rm, option, imm3);
3108
3109 tcg_result = tcg_temp_new_i64();
3110
3111 if (!setflags) {
3112 if (sub_op) {
3113 tcg_gen_sub_i64(tcg_result, tcg_rn, tcg_rm);
3114 } else {
3115 tcg_gen_add_i64(tcg_result, tcg_rn, tcg_rm);
3116 }
3117 } else {
3118 if (sub_op) {
3119 gen_sub_CC(sf, tcg_result, tcg_rn, tcg_rm);
3120 } else {
3121 gen_add_CC(sf, tcg_result, tcg_rn, tcg_rm);
3122 }
3123 }
3124
3125 if (sf) {
3126 tcg_gen_mov_i64(tcg_rd, tcg_result);
3127 } else {
3128 tcg_gen_ext32u_i64(tcg_rd, tcg_result);
3129 }
3130
3131 tcg_temp_free_i64(tcg_result);
3132 }
3133
3134 /*
3135 * C3.5.2 Add/subtract (shifted register)
3136 *
3137 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
3138 * +--+--+--+-----------+-----+--+-------+---------+------+------+
3139 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
3140 * +--+--+--+-----------+-----+--+-------+---------+------+------+
3141 *
3142 * sf: 0 -> 32bit, 1 -> 64bit
3143 * op: 0 -> add , 1 -> sub
3144 * S: 1 -> set flags
3145 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
3146 * imm6: Shift amount to apply to Rm before the add/sub
3147 */
3148 static void disas_add_sub_reg(DisasContext *s, uint32_t insn)
3149 {
3150 int rd = extract32(insn, 0, 5);
3151 int rn = extract32(insn, 5, 5);
3152 int imm6 = extract32(insn, 10, 6);
3153 int rm = extract32(insn, 16, 5);
3154 int shift_type = extract32(insn, 22, 2);
3155 bool setflags = extract32(insn, 29, 1);
3156 bool sub_op = extract32(insn, 30, 1);
3157 bool sf = extract32(insn, 31, 1);
3158
3159 TCGv_i64 tcg_rd = cpu_reg(s, rd);
3160 TCGv_i64 tcg_rn, tcg_rm;
3161 TCGv_i64 tcg_result;
3162
3163 if ((shift_type == 3) || (!sf && (imm6 > 31))) {
3164 unallocated_encoding(s);
3165 return;
3166 }
3167
3168 tcg_rn = read_cpu_reg(s, rn, sf);
3169 tcg_rm = read_cpu_reg(s, rm, sf);
3170
3171 shift_reg_imm(tcg_rm, tcg_rm, sf, shift_type, imm6);
3172
3173 tcg_result = tcg_temp_new_i64();
3174
3175 if (!setflags) {
3176 if (sub_op) {
3177 tcg_gen_sub_i64(tcg_result, tcg_rn, tcg_rm);
3178 } else {
3179 tcg_gen_add_i64(tcg_result, tcg_rn, tcg_rm);
3180 }
3181 } else {
3182 if (sub_op) {
3183 gen_sub_CC(sf, tcg_result, tcg_rn, tcg_rm);
3184 } else {
3185 gen_add_CC(sf, tcg_result, tcg_rn, tcg_rm);
3186 }
3187 }
3188
3189 if (sf) {
3190 tcg_gen_mov_i64(tcg_rd, tcg_result);
3191 } else {
3192 tcg_gen_ext32u_i64(tcg_rd, tcg_result);
3193 }
3194
3195 tcg_temp_free_i64(tcg_result);
3196 }
3197
3198 /* C3.5.9 Data-processing (3 source)
3199
3200 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
3201 +--+------+-----------+------+------+----+------+------+------+
3202 |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
3203 +--+------+-----------+------+------+----+------+------+------+
3204
3205 */
3206 static void disas_data_proc_3src(DisasContext *s, uint32_t insn)
3207 {
3208 int rd = extract32(insn, 0, 5);
3209 int rn = extract32(insn, 5, 5);
3210 int ra = extract32(insn, 10, 5);
3211 int rm = extract32(insn, 16, 5);
3212 int op_id = (extract32(insn, 29, 3) << 4) |