target-arm: A64: Implement AdvSIMD reciprocal estimate insns URECPE, FRECPE
[qemu.git] / target-arm / translate-a64.c
1 /*
2 * AArch64 translation
3 *
4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdarg.h>
20 #include <stdlib.h>
21 #include <stdio.h>
22 #include <string.h>
23 #include <inttypes.h>
24
25 #include "cpu.h"
26 #include "tcg-op.h"
27 #include "qemu/log.h"
28 #include "translate.h"
29 #include "qemu/host-utils.h"
30
31 #include "exec/gen-icount.h"
32
33 #include "helper.h"
34 #define GEN_HELPER 1
35 #include "helper.h"
36
37 static TCGv_i64 cpu_X[32];
38 static TCGv_i64 cpu_pc;
39 static TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF;
40
41 /* Load/store exclusive handling */
42 static TCGv_i64 cpu_exclusive_addr;
43 static TCGv_i64 cpu_exclusive_val;
44 static TCGv_i64 cpu_exclusive_high;
45 #ifdef CONFIG_USER_ONLY
46 static TCGv_i64 cpu_exclusive_test;
47 static TCGv_i32 cpu_exclusive_info;
48 #endif
49
50 static const char *regnames[] = {
51 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
52 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
53 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
54 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
55 };
56
57 enum a64_shift_type {
58 A64_SHIFT_TYPE_LSL = 0,
59 A64_SHIFT_TYPE_LSR = 1,
60 A64_SHIFT_TYPE_ASR = 2,
61 A64_SHIFT_TYPE_ROR = 3
62 };
63
64 /* Table based decoder typedefs - used when the relevant bits for decode
65 * are too awkwardly scattered across the instruction (eg SIMD).
66 */
67 typedef void AArch64DecodeFn(DisasContext *s, uint32_t insn);
68
69 typedef struct AArch64DecodeTable {
70 uint32_t pattern;
71 uint32_t mask;
72 AArch64DecodeFn *disas_fn;
73 } AArch64DecodeTable;
74
75 /* Function prototype for gen_ functions for calling Neon helpers */
76 typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32);
77 typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
78 typedef void NeonGenTwo64OpFn(TCGv_i64, TCGv_i64, TCGv_i64);
79 typedef void NeonGenTwo64OpEnvFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64);
80 typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64);
81 typedef void NeonGenNarrowEnvFn(TCGv_i32, TCGv_ptr, TCGv_i64);
82 typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32);
83 typedef void NeonGenTwoSingleOPFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr);
84 typedef void NeonGenTwoDoubleOPFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr);
85 typedef void NeonGenOneOpFn(TCGv_i64, TCGv_i64);
86
87 /* initialize TCG globals. */
88 void a64_translate_init(void)
89 {
90 int i;
91
92 cpu_pc = tcg_global_mem_new_i64(TCG_AREG0,
93 offsetof(CPUARMState, pc),
94 "pc");
95 for (i = 0; i < 32; i++) {
96 cpu_X[i] = tcg_global_mem_new_i64(TCG_AREG0,
97 offsetof(CPUARMState, xregs[i]),
98 regnames[i]);
99 }
100
101 cpu_NF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, NF), "NF");
102 cpu_ZF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, ZF), "ZF");
103 cpu_CF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, CF), "CF");
104 cpu_VF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, VF), "VF");
105
106 cpu_exclusive_addr = tcg_global_mem_new_i64(TCG_AREG0,
107 offsetof(CPUARMState, exclusive_addr), "exclusive_addr");
108 cpu_exclusive_val = tcg_global_mem_new_i64(TCG_AREG0,
109 offsetof(CPUARMState, exclusive_val), "exclusive_val");
110 cpu_exclusive_high = tcg_global_mem_new_i64(TCG_AREG0,
111 offsetof(CPUARMState, exclusive_high), "exclusive_high");
112 #ifdef CONFIG_USER_ONLY
113 cpu_exclusive_test = tcg_global_mem_new_i64(TCG_AREG0,
114 offsetof(CPUARMState, exclusive_test), "exclusive_test");
115 cpu_exclusive_info = tcg_global_mem_new_i32(TCG_AREG0,
116 offsetof(CPUARMState, exclusive_info), "exclusive_info");
117 #endif
118 }
119
120 void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
121 fprintf_function cpu_fprintf, int flags)
122 {
123 ARMCPU *cpu = ARM_CPU(cs);
124 CPUARMState *env = &cpu->env;
125 uint32_t psr = pstate_read(env);
126 int i;
127
128 cpu_fprintf(f, "PC=%016"PRIx64" SP=%016"PRIx64"\n",
129 env->pc, env->xregs[31]);
130 for (i = 0; i < 31; i++) {
131 cpu_fprintf(f, "X%02d=%016"PRIx64, i, env->xregs[i]);
132 if ((i % 4) == 3) {
133 cpu_fprintf(f, "\n");
134 } else {
135 cpu_fprintf(f, " ");
136 }
137 }
138 cpu_fprintf(f, "PSTATE=%08x (flags %c%c%c%c)\n",
139 psr,
140 psr & PSTATE_N ? 'N' : '-',
141 psr & PSTATE_Z ? 'Z' : '-',
142 psr & PSTATE_C ? 'C' : '-',
143 psr & PSTATE_V ? 'V' : '-');
144 cpu_fprintf(f, "\n");
145
146 if (flags & CPU_DUMP_FPU) {
147 int numvfpregs = 32;
148 for (i = 0; i < numvfpregs; i += 2) {
149 uint64_t vlo = float64_val(env->vfp.regs[i * 2]);
150 uint64_t vhi = float64_val(env->vfp.regs[(i * 2) + 1]);
151 cpu_fprintf(f, "q%02d=%016" PRIx64 ":%016" PRIx64 " ",
152 i, vhi, vlo);
153 vlo = float64_val(env->vfp.regs[(i + 1) * 2]);
154 vhi = float64_val(env->vfp.regs[((i + 1) * 2) + 1]);
155 cpu_fprintf(f, "q%02d=%016" PRIx64 ":%016" PRIx64 "\n",
156 i + 1, vhi, vlo);
157 }
158 cpu_fprintf(f, "FPCR: %08x FPSR: %08x\n",
159 vfp_get_fpcr(env), vfp_get_fpsr(env));
160 }
161 }
162
163 static int get_mem_index(DisasContext *s)
164 {
165 #ifdef CONFIG_USER_ONLY
166 return 1;
167 #else
168 return s->user;
169 #endif
170 }
171
172 void gen_a64_set_pc_im(uint64_t val)
173 {
174 tcg_gen_movi_i64(cpu_pc, val);
175 }
176
177 static void gen_exception(int excp)
178 {
179 TCGv_i32 tmp = tcg_temp_new_i32();
180 tcg_gen_movi_i32(tmp, excp);
181 gen_helper_exception(cpu_env, tmp);
182 tcg_temp_free_i32(tmp);
183 }
184
185 static void gen_exception_insn(DisasContext *s, int offset, int excp)
186 {
187 gen_a64_set_pc_im(s->pc - offset);
188 gen_exception(excp);
189 s->is_jmp = DISAS_EXC;
190 }
191
192 static inline bool use_goto_tb(DisasContext *s, int n, uint64_t dest)
193 {
194 /* No direct tb linking with singlestep or deterministic io */
195 if (s->singlestep_enabled || (s->tb->cflags & CF_LAST_IO)) {
196 return false;
197 }
198
199 /* Only link tbs from inside the same guest page */
200 if ((s->tb->pc & TARGET_PAGE_MASK) != (dest & TARGET_PAGE_MASK)) {
201 return false;
202 }
203
204 return true;
205 }
206
207 static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest)
208 {
209 TranslationBlock *tb;
210
211 tb = s->tb;
212 if (use_goto_tb(s, n, dest)) {
213 tcg_gen_goto_tb(n);
214 gen_a64_set_pc_im(dest);
215 tcg_gen_exit_tb((intptr_t)tb + n);
216 s->is_jmp = DISAS_TB_JUMP;
217 } else {
218 gen_a64_set_pc_im(dest);
219 if (s->singlestep_enabled) {
220 gen_exception(EXCP_DEBUG);
221 }
222 tcg_gen_exit_tb(0);
223 s->is_jmp = DISAS_JUMP;
224 }
225 }
226
227 static void unallocated_encoding(DisasContext *s)
228 {
229 gen_exception_insn(s, 4, EXCP_UDEF);
230 }
231
232 #define unsupported_encoding(s, insn) \
233 do { \
234 qemu_log_mask(LOG_UNIMP, \
235 "%s:%d: unsupported instruction encoding 0x%08x " \
236 "at pc=%016" PRIx64 "\n", \
237 __FILE__, __LINE__, insn, s->pc - 4); \
238 unallocated_encoding(s); \
239 } while (0);
240
241 static void init_tmp_a64_array(DisasContext *s)
242 {
243 #ifdef CONFIG_DEBUG_TCG
244 int i;
245 for (i = 0; i < ARRAY_SIZE(s->tmp_a64); i++) {
246 TCGV_UNUSED_I64(s->tmp_a64[i]);
247 }
248 #endif
249 s->tmp_a64_count = 0;
250 }
251
252 static void free_tmp_a64(DisasContext *s)
253 {
254 int i;
255 for (i = 0; i < s->tmp_a64_count; i++) {
256 tcg_temp_free_i64(s->tmp_a64[i]);
257 }
258 init_tmp_a64_array(s);
259 }
260
261 static TCGv_i64 new_tmp_a64(DisasContext *s)
262 {
263 assert(s->tmp_a64_count < TMP_A64_MAX);
264 return s->tmp_a64[s->tmp_a64_count++] = tcg_temp_new_i64();
265 }
266
267 static TCGv_i64 new_tmp_a64_zero(DisasContext *s)
268 {
269 TCGv_i64 t = new_tmp_a64(s);
270 tcg_gen_movi_i64(t, 0);
271 return t;
272 }
273
274 /*
275 * Register access functions
276 *
277 * These functions are used for directly accessing a register in where
278 * changes to the final register value are likely to be made. If you
279 * need to use a register for temporary calculation (e.g. index type
280 * operations) use the read_* form.
281 *
282 * B1.2.1 Register mappings
283 *
284 * In instruction register encoding 31 can refer to ZR (zero register) or
285 * the SP (stack pointer) depending on context. In QEMU's case we map SP
286 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
287 * This is the point of the _sp forms.
288 */
289 static TCGv_i64 cpu_reg(DisasContext *s, int reg)
290 {
291 if (reg == 31) {
292 return new_tmp_a64_zero(s);
293 } else {
294 return cpu_X[reg];
295 }
296 }
297
298 /* register access for when 31 == SP */
299 static TCGv_i64 cpu_reg_sp(DisasContext *s, int reg)
300 {
301 return cpu_X[reg];
302 }
303
304 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
305 * representing the register contents. This TCGv is an auto-freed
306 * temporary so it need not be explicitly freed, and may be modified.
307 */
308 static TCGv_i64 read_cpu_reg(DisasContext *s, int reg, int sf)
309 {
310 TCGv_i64 v = new_tmp_a64(s);
311 if (reg != 31) {
312 if (sf) {
313 tcg_gen_mov_i64(v, cpu_X[reg]);
314 } else {
315 tcg_gen_ext32u_i64(v, cpu_X[reg]);
316 }
317 } else {
318 tcg_gen_movi_i64(v, 0);
319 }
320 return v;
321 }
322
323 static TCGv_i64 read_cpu_reg_sp(DisasContext *s, int reg, int sf)
324 {
325 TCGv_i64 v = new_tmp_a64(s);
326 if (sf) {
327 tcg_gen_mov_i64(v, cpu_X[reg]);
328 } else {
329 tcg_gen_ext32u_i64(v, cpu_X[reg]);
330 }
331 return v;
332 }
333
334 /* Return the offset into CPUARMState of an element of specified
335 * size, 'element' places in from the least significant end of
336 * the FP/vector register Qn.
337 */
338 static inline int vec_reg_offset(int regno, int element, TCGMemOp size)
339 {
340 int offs = offsetof(CPUARMState, vfp.regs[regno * 2]);
341 #ifdef HOST_WORDS_BIGENDIAN
342 /* This is complicated slightly because vfp.regs[2n] is
343 * still the low half and vfp.regs[2n+1] the high half
344 * of the 128 bit vector, even on big endian systems.
345 * Calculate the offset assuming a fully bigendian 128 bits,
346 * then XOR to account for the order of the two 64 bit halves.
347 */
348 offs += (16 - ((element + 1) * (1 << size)));
349 offs ^= 8;
350 #else
351 offs += element * (1 << size);
352 #endif
353 return offs;
354 }
355
356 /* Return the offset into CPUARMState of a slice (from
357 * the least significant end) of FP register Qn (ie
358 * Dn, Sn, Hn or Bn).
359 * (Note that this is not the same mapping as for A32; see cpu.h)
360 */
361 static inline int fp_reg_offset(int regno, TCGMemOp size)
362 {
363 int offs = offsetof(CPUARMState, vfp.regs[regno * 2]);
364 #ifdef HOST_WORDS_BIGENDIAN
365 offs += (8 - (1 << size));
366 #endif
367 return offs;
368 }
369
370 /* Offset of the high half of the 128 bit vector Qn */
371 static inline int fp_reg_hi_offset(int regno)
372 {
373 return offsetof(CPUARMState, vfp.regs[regno * 2 + 1]);
374 }
375
376 /* Convenience accessors for reading and writing single and double
377 * FP registers. Writing clears the upper parts of the associated
378 * 128 bit vector register, as required by the architecture.
379 * Note that unlike the GP register accessors, the values returned
380 * by the read functions must be manually freed.
381 */
382 static TCGv_i64 read_fp_dreg(DisasContext *s, int reg)
383 {
384 TCGv_i64 v = tcg_temp_new_i64();
385
386 tcg_gen_ld_i64(v, cpu_env, fp_reg_offset(reg, MO_64));
387 return v;
388 }
389
390 static TCGv_i32 read_fp_sreg(DisasContext *s, int reg)
391 {
392 TCGv_i32 v = tcg_temp_new_i32();
393
394 tcg_gen_ld_i32(v, cpu_env, fp_reg_offset(reg, MO_32));
395 return v;
396 }
397
398 static void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v)
399 {
400 TCGv_i64 tcg_zero = tcg_const_i64(0);
401
402 tcg_gen_st_i64(v, cpu_env, fp_reg_offset(reg, MO_64));
403 tcg_gen_st_i64(tcg_zero, cpu_env, fp_reg_hi_offset(reg));
404 tcg_temp_free_i64(tcg_zero);
405 }
406
407 static void write_fp_sreg(DisasContext *s, int reg, TCGv_i32 v)
408 {
409 TCGv_i64 tmp = tcg_temp_new_i64();
410
411 tcg_gen_extu_i32_i64(tmp, v);
412 write_fp_dreg(s, reg, tmp);
413 tcg_temp_free_i64(tmp);
414 }
415
416 static TCGv_ptr get_fpstatus_ptr(void)
417 {
418 TCGv_ptr statusptr = tcg_temp_new_ptr();
419 int offset;
420
421 /* In A64 all instructions (both FP and Neon) use the FPCR;
422 * there is no equivalent of the A32 Neon "standard FPSCR value"
423 * and all operations use vfp.fp_status.
424 */
425 offset = offsetof(CPUARMState, vfp.fp_status);
426 tcg_gen_addi_ptr(statusptr, cpu_env, offset);
427 return statusptr;
428 }
429
430 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
431 * than the 32 bit equivalent.
432 */
433 static inline void gen_set_NZ64(TCGv_i64 result)
434 {
435 TCGv_i64 flag = tcg_temp_new_i64();
436
437 tcg_gen_setcondi_i64(TCG_COND_NE, flag, result, 0);
438 tcg_gen_trunc_i64_i32(cpu_ZF, flag);
439 tcg_gen_shri_i64(flag, result, 32);
440 tcg_gen_trunc_i64_i32(cpu_NF, flag);
441 tcg_temp_free_i64(flag);
442 }
443
444 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
445 static inline void gen_logic_CC(int sf, TCGv_i64 result)
446 {
447 if (sf) {
448 gen_set_NZ64(result);
449 } else {
450 tcg_gen_trunc_i64_i32(cpu_ZF, result);
451 tcg_gen_trunc_i64_i32(cpu_NF, result);
452 }
453 tcg_gen_movi_i32(cpu_CF, 0);
454 tcg_gen_movi_i32(cpu_VF, 0);
455 }
456
457 /* dest = T0 + T1; compute C, N, V and Z flags */
458 static void gen_add_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1)
459 {
460 if (sf) {
461 TCGv_i64 result, flag, tmp;
462 result = tcg_temp_new_i64();
463 flag = tcg_temp_new_i64();
464 tmp = tcg_temp_new_i64();
465
466 tcg_gen_movi_i64(tmp, 0);
467 tcg_gen_add2_i64(result, flag, t0, tmp, t1, tmp);
468
469 tcg_gen_trunc_i64_i32(cpu_CF, flag);
470
471 gen_set_NZ64(result);
472
473 tcg_gen_xor_i64(flag, result, t0);
474 tcg_gen_xor_i64(tmp, t0, t1);
475 tcg_gen_andc_i64(flag, flag, tmp);
476 tcg_temp_free_i64(tmp);
477 tcg_gen_shri_i64(flag, flag, 32);
478 tcg_gen_trunc_i64_i32(cpu_VF, flag);
479
480 tcg_gen_mov_i64(dest, result);
481 tcg_temp_free_i64(result);
482 tcg_temp_free_i64(flag);
483 } else {
484 /* 32 bit arithmetic */
485 TCGv_i32 t0_32 = tcg_temp_new_i32();
486 TCGv_i32 t1_32 = tcg_temp_new_i32();
487 TCGv_i32 tmp = tcg_temp_new_i32();
488
489 tcg_gen_movi_i32(tmp, 0);
490 tcg_gen_trunc_i64_i32(t0_32, t0);
491 tcg_gen_trunc_i64_i32(t1_32, t1);
492 tcg_gen_add2_i32(cpu_NF, cpu_CF, t0_32, tmp, t1_32, tmp);
493 tcg_gen_mov_i32(cpu_ZF, cpu_NF);
494 tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32);
495 tcg_gen_xor_i32(tmp, t0_32, t1_32);
496 tcg_gen_andc_i32(cpu_VF, cpu_VF, tmp);
497 tcg_gen_extu_i32_i64(dest, cpu_NF);
498
499 tcg_temp_free_i32(tmp);
500 tcg_temp_free_i32(t0_32);
501 tcg_temp_free_i32(t1_32);
502 }
503 }
504
505 /* dest = T0 - T1; compute C, N, V and Z flags */
506 static void gen_sub_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1)
507 {
508 if (sf) {
509 /* 64 bit arithmetic */
510 TCGv_i64 result, flag, tmp;
511
512 result = tcg_temp_new_i64();
513 flag = tcg_temp_new_i64();
514 tcg_gen_sub_i64(result, t0, t1);
515
516 gen_set_NZ64(result);
517
518 tcg_gen_setcond_i64(TCG_COND_GEU, flag, t0, t1);
519 tcg_gen_trunc_i64_i32(cpu_CF, flag);
520
521 tcg_gen_xor_i64(flag, result, t0);
522 tmp = tcg_temp_new_i64();
523 tcg_gen_xor_i64(tmp, t0, t1);
524 tcg_gen_and_i64(flag, flag, tmp);
525 tcg_temp_free_i64(tmp);
526 tcg_gen_shri_i64(flag, flag, 32);
527 tcg_gen_trunc_i64_i32(cpu_VF, flag);
528 tcg_gen_mov_i64(dest, result);
529 tcg_temp_free_i64(flag);
530 tcg_temp_free_i64(result);
531 } else {
532 /* 32 bit arithmetic */
533 TCGv_i32 t0_32 = tcg_temp_new_i32();
534 TCGv_i32 t1_32 = tcg_temp_new_i32();
535 TCGv_i32 tmp;
536
537 tcg_gen_trunc_i64_i32(t0_32, t0);
538 tcg_gen_trunc_i64_i32(t1_32, t1);
539 tcg_gen_sub_i32(cpu_NF, t0_32, t1_32);
540 tcg_gen_mov_i32(cpu_ZF, cpu_NF);
541 tcg_gen_setcond_i32(TCG_COND_GEU, cpu_CF, t0_32, t1_32);
542 tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32);
543 tmp = tcg_temp_new_i32();
544 tcg_gen_xor_i32(tmp, t0_32, t1_32);
545 tcg_temp_free_i32(t0_32);
546 tcg_temp_free_i32(t1_32);
547 tcg_gen_and_i32(cpu_VF, cpu_VF, tmp);
548 tcg_temp_free_i32(tmp);
549 tcg_gen_extu_i32_i64(dest, cpu_NF);
550 }
551 }
552
553 /* dest = T0 + T1 + CF; do not compute flags. */
554 static void gen_adc(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1)
555 {
556 TCGv_i64 flag = tcg_temp_new_i64();
557 tcg_gen_extu_i32_i64(flag, cpu_CF);
558 tcg_gen_add_i64(dest, t0, t1);
559 tcg_gen_add_i64(dest, dest, flag);
560 tcg_temp_free_i64(flag);
561
562 if (!sf) {
563 tcg_gen_ext32u_i64(dest, dest);
564 }
565 }
566
567 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
568 static void gen_adc_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1)
569 {
570 if (sf) {
571 TCGv_i64 result, cf_64, vf_64, tmp;
572 result = tcg_temp_new_i64();
573 cf_64 = tcg_temp_new_i64();
574 vf_64 = tcg_temp_new_i64();
575 tmp = tcg_const_i64(0);
576
577 tcg_gen_extu_i32_i64(cf_64, cpu_CF);
578 tcg_gen_add2_i64(result, cf_64, t0, tmp, cf_64, tmp);
579 tcg_gen_add2_i64(result, cf_64, result, cf_64, t1, tmp);
580 tcg_gen_trunc_i64_i32(cpu_CF, cf_64);
581 gen_set_NZ64(result);
582
583 tcg_gen_xor_i64(vf_64, result, t0);
584 tcg_gen_xor_i64(tmp, t0, t1);
585 tcg_gen_andc_i64(vf_64, vf_64, tmp);
586 tcg_gen_shri_i64(vf_64, vf_64, 32);
587 tcg_gen_trunc_i64_i32(cpu_VF, vf_64);
588
589 tcg_gen_mov_i64(dest, result);
590
591 tcg_temp_free_i64(tmp);
592 tcg_temp_free_i64(vf_64);
593 tcg_temp_free_i64(cf_64);
594 tcg_temp_free_i64(result);
595 } else {
596 TCGv_i32 t0_32, t1_32, tmp;
597 t0_32 = tcg_temp_new_i32();
598 t1_32 = tcg_temp_new_i32();
599 tmp = tcg_const_i32(0);
600
601 tcg_gen_trunc_i64_i32(t0_32, t0);
602 tcg_gen_trunc_i64_i32(t1_32, t1);
603 tcg_gen_add2_i32(cpu_NF, cpu_CF, t0_32, tmp, cpu_CF, tmp);
604 tcg_gen_add2_i32(cpu_NF, cpu_CF, cpu_NF, cpu_CF, t1_32, tmp);
605
606 tcg_gen_mov_i32(cpu_ZF, cpu_NF);
607 tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32);
608 tcg_gen_xor_i32(tmp, t0_32, t1_32);
609 tcg_gen_andc_i32(cpu_VF, cpu_VF, tmp);
610 tcg_gen_extu_i32_i64(dest, cpu_NF);
611
612 tcg_temp_free_i32(tmp);
613 tcg_temp_free_i32(t1_32);
614 tcg_temp_free_i32(t0_32);
615 }
616 }
617
618 /*
619 * Load/Store generators
620 */
621
622 /*
623 * Store from GPR register to memory.
624 */
625 static void do_gpr_st_memidx(DisasContext *s, TCGv_i64 source,
626 TCGv_i64 tcg_addr, int size, int memidx)
627 {
628 g_assert(size <= 3);
629 tcg_gen_qemu_st_i64(source, tcg_addr, memidx, MO_TE + size);
630 }
631
632 static void do_gpr_st(DisasContext *s, TCGv_i64 source,
633 TCGv_i64 tcg_addr, int size)
634 {
635 do_gpr_st_memidx(s, source, tcg_addr, size, get_mem_index(s));
636 }
637
638 /*
639 * Load from memory to GPR register
640 */
641 static void do_gpr_ld_memidx(DisasContext *s, TCGv_i64 dest, TCGv_i64 tcg_addr,
642 int size, bool is_signed, bool extend, int memidx)
643 {
644 TCGMemOp memop = MO_TE + size;
645
646 g_assert(size <= 3);
647
648 if (is_signed) {
649 memop += MO_SIGN;
650 }
651
652 tcg_gen_qemu_ld_i64(dest, tcg_addr, memidx, memop);
653
654 if (extend && is_signed) {
655 g_assert(size < 3);
656 tcg_gen_ext32u_i64(dest, dest);
657 }
658 }
659
660 static void do_gpr_ld(DisasContext *s, TCGv_i64 dest, TCGv_i64 tcg_addr,
661 int size, bool is_signed, bool extend)
662 {
663 do_gpr_ld_memidx(s, dest, tcg_addr, size, is_signed, extend,
664 get_mem_index(s));
665 }
666
667 /*
668 * Store from FP register to memory
669 */
670 static void do_fp_st(DisasContext *s, int srcidx, TCGv_i64 tcg_addr, int size)
671 {
672 /* This writes the bottom N bits of a 128 bit wide vector to memory */
673 TCGv_i64 tmp = tcg_temp_new_i64();
674 tcg_gen_ld_i64(tmp, cpu_env, fp_reg_offset(srcidx, MO_64));
675 if (size < 4) {
676 tcg_gen_qemu_st_i64(tmp, tcg_addr, get_mem_index(s), MO_TE + size);
677 } else {
678 TCGv_i64 tcg_hiaddr = tcg_temp_new_i64();
679 tcg_gen_qemu_st_i64(tmp, tcg_addr, get_mem_index(s), MO_TEQ);
680 tcg_gen_qemu_st64(tmp, tcg_addr, get_mem_index(s));
681 tcg_gen_ld_i64(tmp, cpu_env, fp_reg_hi_offset(srcidx));
682 tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8);
683 tcg_gen_qemu_st_i64(tmp, tcg_hiaddr, get_mem_index(s), MO_TEQ);
684 tcg_temp_free_i64(tcg_hiaddr);
685 }
686
687 tcg_temp_free_i64(tmp);
688 }
689
690 /*
691 * Load from memory to FP register
692 */
693 static void do_fp_ld(DisasContext *s, int destidx, TCGv_i64 tcg_addr, int size)
694 {
695 /* This always zero-extends and writes to a full 128 bit wide vector */
696 TCGv_i64 tmplo = tcg_temp_new_i64();
697 TCGv_i64 tmphi;
698
699 if (size < 4) {
700 TCGMemOp memop = MO_TE + size;
701 tmphi = tcg_const_i64(0);
702 tcg_gen_qemu_ld_i64(tmplo, tcg_addr, get_mem_index(s), memop);
703 } else {
704 TCGv_i64 tcg_hiaddr;
705 tmphi = tcg_temp_new_i64();
706 tcg_hiaddr = tcg_temp_new_i64();
707
708 tcg_gen_qemu_ld_i64(tmplo, tcg_addr, get_mem_index(s), MO_TEQ);
709 tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8);
710 tcg_gen_qemu_ld_i64(tmphi, tcg_hiaddr, get_mem_index(s), MO_TEQ);
711 tcg_temp_free_i64(tcg_hiaddr);
712 }
713
714 tcg_gen_st_i64(tmplo, cpu_env, fp_reg_offset(destidx, MO_64));
715 tcg_gen_st_i64(tmphi, cpu_env, fp_reg_hi_offset(destidx));
716
717 tcg_temp_free_i64(tmplo);
718 tcg_temp_free_i64(tmphi);
719 }
720
721 /*
722 * Vector load/store helpers.
723 *
724 * The principal difference between this and a FP load is that we don't
725 * zero extend as we are filling a partial chunk of the vector register.
726 * These functions don't support 128 bit loads/stores, which would be
727 * normal load/store operations.
728 *
729 * The _i32 versions are useful when operating on 32 bit quantities
730 * (eg for floating point single or using Neon helper functions).
731 */
732
733 /* Get value of an element within a vector register */
734 static void read_vec_element(DisasContext *s, TCGv_i64 tcg_dest, int srcidx,
735 int element, TCGMemOp memop)
736 {
737 int vect_off = vec_reg_offset(srcidx, element, memop & MO_SIZE);
738 switch (memop) {
739 case MO_8:
740 tcg_gen_ld8u_i64(tcg_dest, cpu_env, vect_off);
741 break;
742 case MO_16:
743 tcg_gen_ld16u_i64(tcg_dest, cpu_env, vect_off);
744 break;
745 case MO_32:
746 tcg_gen_ld32u_i64(tcg_dest, cpu_env, vect_off);
747 break;
748 case MO_8|MO_SIGN:
749 tcg_gen_ld8s_i64(tcg_dest, cpu_env, vect_off);
750 break;
751 case MO_16|MO_SIGN:
752 tcg_gen_ld16s_i64(tcg_dest, cpu_env, vect_off);
753 break;
754 case MO_32|MO_SIGN:
755 tcg_gen_ld32s_i64(tcg_dest, cpu_env, vect_off);
756 break;
757 case MO_64:
758 case MO_64|MO_SIGN:
759 tcg_gen_ld_i64(tcg_dest, cpu_env, vect_off);
760 break;
761 default:
762 g_assert_not_reached();
763 }
764 }
765
766 static void read_vec_element_i32(DisasContext *s, TCGv_i32 tcg_dest, int srcidx,
767 int element, TCGMemOp memop)
768 {
769 int vect_off = vec_reg_offset(srcidx, element, memop & MO_SIZE);
770 switch (memop) {
771 case MO_8:
772 tcg_gen_ld8u_i32(tcg_dest, cpu_env, vect_off);
773 break;
774 case MO_16:
775 tcg_gen_ld16u_i32(tcg_dest, cpu_env, vect_off);
776 break;
777 case MO_8|MO_SIGN:
778 tcg_gen_ld8s_i32(tcg_dest, cpu_env, vect_off);
779 break;
780 case MO_16|MO_SIGN:
781 tcg_gen_ld16s_i32(tcg_dest, cpu_env, vect_off);
782 break;
783 case MO_32:
784 case MO_32|MO_SIGN:
785 tcg_gen_ld_i32(tcg_dest, cpu_env, vect_off);
786 break;
787 default:
788 g_assert_not_reached();
789 }
790 }
791
792 /* Set value of an element within a vector register */
793 static void write_vec_element(DisasContext *s, TCGv_i64 tcg_src, int destidx,
794 int element, TCGMemOp memop)
795 {
796 int vect_off = vec_reg_offset(destidx, element, memop & MO_SIZE);
797 switch (memop) {
798 case MO_8:
799 tcg_gen_st8_i64(tcg_src, cpu_env, vect_off);
800 break;
801 case MO_16:
802 tcg_gen_st16_i64(tcg_src, cpu_env, vect_off);
803 break;
804 case MO_32:
805 tcg_gen_st32_i64(tcg_src, cpu_env, vect_off);
806 break;
807 case MO_64:
808 tcg_gen_st_i64(tcg_src, cpu_env, vect_off);
809 break;
810 default:
811 g_assert_not_reached();
812 }
813 }
814
815 static void write_vec_element_i32(DisasContext *s, TCGv_i32 tcg_src,
816 int destidx, int element, TCGMemOp memop)
817 {
818 int vect_off = vec_reg_offset(destidx, element, memop & MO_SIZE);
819 switch (memop) {
820 case MO_8:
821 tcg_gen_st8_i32(tcg_src, cpu_env, vect_off);
822 break;
823 case MO_16:
824 tcg_gen_st16_i32(tcg_src, cpu_env, vect_off);
825 break;
826 case MO_32:
827 tcg_gen_st_i32(tcg_src, cpu_env, vect_off);
828 break;
829 default:
830 g_assert_not_reached();
831 }
832 }
833
834 /* Clear the high 64 bits of a 128 bit vector (in general non-quad
835 * vector ops all need to do this).
836 */
837 static void clear_vec_high(DisasContext *s, int rd)
838 {
839 TCGv_i64 tcg_zero = tcg_const_i64(0);
840
841 write_vec_element(s, tcg_zero, rd, 1, MO_64);
842 tcg_temp_free_i64(tcg_zero);
843 }
844
845 /* Store from vector register to memory */
846 static void do_vec_st(DisasContext *s, int srcidx, int element,
847 TCGv_i64 tcg_addr, int size)
848 {
849 TCGMemOp memop = MO_TE + size;
850 TCGv_i64 tcg_tmp = tcg_temp_new_i64();
851
852 read_vec_element(s, tcg_tmp, srcidx, element, size);
853 tcg_gen_qemu_st_i64(tcg_tmp, tcg_addr, get_mem_index(s), memop);
854
855 tcg_temp_free_i64(tcg_tmp);
856 }
857
858 /* Load from memory to vector register */
859 static void do_vec_ld(DisasContext *s, int destidx, int element,
860 TCGv_i64 tcg_addr, int size)
861 {
862 TCGMemOp memop = MO_TE + size;
863 TCGv_i64 tcg_tmp = tcg_temp_new_i64();
864
865 tcg_gen_qemu_ld_i64(tcg_tmp, tcg_addr, get_mem_index(s), memop);
866 write_vec_element(s, tcg_tmp, destidx, element, size);
867
868 tcg_temp_free_i64(tcg_tmp);
869 }
870
871 /*
872 * This utility function is for doing register extension with an
873 * optional shift. You will likely want to pass a temporary for the
874 * destination register. See DecodeRegExtend() in the ARM ARM.
875 */
876 static void ext_and_shift_reg(TCGv_i64 tcg_out, TCGv_i64 tcg_in,
877 int option, unsigned int shift)
878 {
879 int extsize = extract32(option, 0, 2);
880 bool is_signed = extract32(option, 2, 1);
881
882 if (is_signed) {
883 switch (extsize) {
884 case 0:
885 tcg_gen_ext8s_i64(tcg_out, tcg_in);
886 break;
887 case 1:
888 tcg_gen_ext16s_i64(tcg_out, tcg_in);
889 break;
890 case 2:
891 tcg_gen_ext32s_i64(tcg_out, tcg_in);
892 break;
893 case 3:
894 tcg_gen_mov_i64(tcg_out, tcg_in);
895 break;
896 }
897 } else {
898 switch (extsize) {
899 case 0:
900 tcg_gen_ext8u_i64(tcg_out, tcg_in);
901 break;
902 case 1:
903 tcg_gen_ext16u_i64(tcg_out, tcg_in);
904 break;
905 case 2:
906 tcg_gen_ext32u_i64(tcg_out, tcg_in);
907 break;
908 case 3:
909 tcg_gen_mov_i64(tcg_out, tcg_in);
910 break;
911 }
912 }
913
914 if (shift) {
915 tcg_gen_shli_i64(tcg_out, tcg_out, shift);
916 }
917 }
918
919 static inline void gen_check_sp_alignment(DisasContext *s)
920 {
921 /* The AArch64 architecture mandates that (if enabled via PSTATE
922 * or SCTLR bits) there is a check that SP is 16-aligned on every
923 * SP-relative load or store (with an exception generated if it is not).
924 * In line with general QEMU practice regarding misaligned accesses,
925 * we omit these checks for the sake of guest program performance.
926 * This function is provided as a hook so we can more easily add these
927 * checks in future (possibly as a "favour catching guest program bugs
928 * over speed" user selectable option).
929 */
930 }
931
932 /*
933 * This provides a simple table based table lookup decoder. It is
934 * intended to be used when the relevant bits for decode are too
935 * awkwardly placed and switch/if based logic would be confusing and
936 * deeply nested. Since it's a linear search through the table, tables
937 * should be kept small.
938 *
939 * It returns the first handler where insn & mask == pattern, or
940 * NULL if there is no match.
941 * The table is terminated by an empty mask (i.e. 0)
942 */
943 static inline AArch64DecodeFn *lookup_disas_fn(const AArch64DecodeTable *table,
944 uint32_t insn)
945 {
946 const AArch64DecodeTable *tptr = table;
947
948 while (tptr->mask) {
949 if ((insn & tptr->mask) == tptr->pattern) {
950 return tptr->disas_fn;
951 }
952 tptr++;
953 }
954 return NULL;
955 }
956
957 /*
958 * the instruction disassembly implemented here matches
959 * the instruction encoding classifications in chapter 3 (C3)
960 * of the ARM Architecture Reference Manual (DDI0487A_a)
961 */
962
963 /* C3.2.7 Unconditional branch (immediate)
964 * 31 30 26 25 0
965 * +----+-----------+-------------------------------------+
966 * | op | 0 0 1 0 1 | imm26 |
967 * +----+-----------+-------------------------------------+
968 */
969 static void disas_uncond_b_imm(DisasContext *s, uint32_t insn)
970 {
971 uint64_t addr = s->pc + sextract32(insn, 0, 26) * 4 - 4;
972
973 if (insn & (1 << 31)) {
974 /* C5.6.26 BL Branch with link */
975 tcg_gen_movi_i64(cpu_reg(s, 30), s->pc);
976 }
977
978 /* C5.6.20 B Branch / C5.6.26 BL Branch with link */
979 gen_goto_tb(s, 0, addr);
980 }
981
982 /* C3.2.1 Compare & branch (immediate)
983 * 31 30 25 24 23 5 4 0
984 * +----+-------------+----+---------------------+--------+
985 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
986 * +----+-------------+----+---------------------+--------+
987 */
988 static void disas_comp_b_imm(DisasContext *s, uint32_t insn)
989 {
990 unsigned int sf, op, rt;
991 uint64_t addr;
992 int label_match;
993 TCGv_i64 tcg_cmp;
994
995 sf = extract32(insn, 31, 1);
996 op = extract32(insn, 24, 1); /* 0: CBZ; 1: CBNZ */
997 rt = extract32(insn, 0, 5);
998 addr = s->pc + sextract32(insn, 5, 19) * 4 - 4;
999
1000 tcg_cmp = read_cpu_reg(s, rt, sf);
1001 label_match = gen_new_label();
1002
1003 tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ,
1004 tcg_cmp, 0, label_match);
1005
1006 gen_goto_tb(s, 0, s->pc);
1007 gen_set_label(label_match);
1008 gen_goto_tb(s, 1, addr);
1009 }
1010
1011 /* C3.2.5 Test & branch (immediate)
1012 * 31 30 25 24 23 19 18 5 4 0
1013 * +----+-------------+----+-------+-------------+------+
1014 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
1015 * +----+-------------+----+-------+-------------+------+
1016 */
1017 static void disas_test_b_imm(DisasContext *s, uint32_t insn)
1018 {
1019 unsigned int bit_pos, op, rt;
1020 uint64_t addr;
1021 int label_match;
1022 TCGv_i64 tcg_cmp;
1023
1024 bit_pos = (extract32(insn, 31, 1) << 5) | extract32(insn, 19, 5);
1025 op = extract32(insn, 24, 1); /* 0: TBZ; 1: TBNZ */
1026 addr = s->pc + sextract32(insn, 5, 14) * 4 - 4;
1027 rt = extract32(insn, 0, 5);
1028
1029 tcg_cmp = tcg_temp_new_i64();
1030 tcg_gen_andi_i64(tcg_cmp, cpu_reg(s, rt), (1ULL << bit_pos));
1031 label_match = gen_new_label();
1032 tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ,
1033 tcg_cmp, 0, label_match);
1034 tcg_temp_free_i64(tcg_cmp);
1035 gen_goto_tb(s, 0, s->pc);
1036 gen_set_label(label_match);
1037 gen_goto_tb(s, 1, addr);
1038 }
1039
1040 /* C3.2.2 / C5.6.19 Conditional branch (immediate)
1041 * 31 25 24 23 5 4 3 0
1042 * +---------------+----+---------------------+----+------+
1043 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
1044 * +---------------+----+---------------------+----+------+
1045 */
1046 static void disas_cond_b_imm(DisasContext *s, uint32_t insn)
1047 {
1048 unsigned int cond;
1049 uint64_t addr;
1050
1051 if ((insn & (1 << 4)) || (insn & (1 << 24))) {
1052 unallocated_encoding(s);
1053 return;
1054 }
1055 addr = s->pc + sextract32(insn, 5, 19) * 4 - 4;
1056 cond = extract32(insn, 0, 4);
1057
1058 if (cond < 0x0e) {
1059 /* genuinely conditional branches */
1060 int label_match = gen_new_label();
1061 arm_gen_test_cc(cond, label_match);
1062 gen_goto_tb(s, 0, s->pc);
1063 gen_set_label(label_match);
1064 gen_goto_tb(s, 1, addr);
1065 } else {
1066 /* 0xe and 0xf are both "always" conditions */
1067 gen_goto_tb(s, 0, addr);
1068 }
1069 }
1070
1071 /* C5.6.68 HINT */
1072 static void handle_hint(DisasContext *s, uint32_t insn,
1073 unsigned int op1, unsigned int op2, unsigned int crm)
1074 {
1075 unsigned int selector = crm << 3 | op2;
1076
1077 if (op1 != 3) {
1078 unallocated_encoding(s);
1079 return;
1080 }
1081
1082 switch (selector) {
1083 case 0: /* NOP */
1084 return;
1085 case 3: /* WFI */
1086 s->is_jmp = DISAS_WFI;
1087 return;
1088 case 1: /* YIELD */
1089 case 2: /* WFE */
1090 case 4: /* SEV */
1091 case 5: /* SEVL */
1092 /* we treat all as NOP at least for now */
1093 return;
1094 default:
1095 /* default specified as NOP equivalent */
1096 return;
1097 }
1098 }
1099
1100 static void gen_clrex(DisasContext *s, uint32_t insn)
1101 {
1102 tcg_gen_movi_i64(cpu_exclusive_addr, -1);
1103 }
1104
1105 /* CLREX, DSB, DMB, ISB */
1106 static void handle_sync(DisasContext *s, uint32_t insn,
1107 unsigned int op1, unsigned int op2, unsigned int crm)
1108 {
1109 if (op1 != 3) {
1110 unallocated_encoding(s);
1111 return;
1112 }
1113
1114 switch (op2) {
1115 case 2: /* CLREX */
1116 gen_clrex(s, insn);
1117 return;
1118 case 4: /* DSB */
1119 case 5: /* DMB */
1120 case 6: /* ISB */
1121 /* We don't emulate caches so barriers are no-ops */
1122 return;
1123 default:
1124 unallocated_encoding(s);
1125 return;
1126 }
1127 }
1128
1129 /* C5.6.130 MSR (immediate) - move immediate to processor state field */
1130 static void handle_msr_i(DisasContext *s, uint32_t insn,
1131 unsigned int op1, unsigned int op2, unsigned int crm)
1132 {
1133 int op = op1 << 3 | op2;
1134 switch (op) {
1135 case 0x05: /* SPSel */
1136 if (s->current_pl == 0) {
1137 unallocated_encoding(s);
1138 return;
1139 }
1140 /* fall through */
1141 case 0x1e: /* DAIFSet */
1142 case 0x1f: /* DAIFClear */
1143 {
1144 TCGv_i32 tcg_imm = tcg_const_i32(crm);
1145 TCGv_i32 tcg_op = tcg_const_i32(op);
1146 gen_a64_set_pc_im(s->pc - 4);
1147 gen_helper_msr_i_pstate(cpu_env, tcg_op, tcg_imm);
1148 tcg_temp_free_i32(tcg_imm);
1149 tcg_temp_free_i32(tcg_op);
1150 s->is_jmp = DISAS_UPDATE;
1151 break;
1152 }
1153 default:
1154 unallocated_encoding(s);
1155 return;
1156 }
1157 }
1158
1159 static void gen_get_nzcv(TCGv_i64 tcg_rt)
1160 {
1161 TCGv_i32 tmp = tcg_temp_new_i32();
1162 TCGv_i32 nzcv = tcg_temp_new_i32();
1163
1164 /* build bit 31, N */
1165 tcg_gen_andi_i32(nzcv, cpu_NF, (1 << 31));
1166 /* build bit 30, Z */
1167 tcg_gen_setcondi_i32(TCG_COND_EQ, tmp, cpu_ZF, 0);
1168 tcg_gen_deposit_i32(nzcv, nzcv, tmp, 30, 1);
1169 /* build bit 29, C */
1170 tcg_gen_deposit_i32(nzcv, nzcv, cpu_CF, 29, 1);
1171 /* build bit 28, V */
1172 tcg_gen_shri_i32(tmp, cpu_VF, 31);
1173 tcg_gen_deposit_i32(nzcv, nzcv, tmp, 28, 1);
1174 /* generate result */
1175 tcg_gen_extu_i32_i64(tcg_rt, nzcv);
1176
1177 tcg_temp_free_i32(nzcv);
1178 tcg_temp_free_i32(tmp);
1179 }
1180
1181 static void gen_set_nzcv(TCGv_i64 tcg_rt)
1182
1183 {
1184 TCGv_i32 nzcv = tcg_temp_new_i32();
1185
1186 /* take NZCV from R[t] */
1187 tcg_gen_trunc_i64_i32(nzcv, tcg_rt);
1188
1189 /* bit 31, N */
1190 tcg_gen_andi_i32(cpu_NF, nzcv, (1 << 31));
1191 /* bit 30, Z */
1192 tcg_gen_andi_i32(cpu_ZF, nzcv, (1 << 30));
1193 tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_ZF, cpu_ZF, 0);
1194 /* bit 29, C */
1195 tcg_gen_andi_i32(cpu_CF, nzcv, (1 << 29));
1196 tcg_gen_shri_i32(cpu_CF, cpu_CF, 29);
1197 /* bit 28, V */
1198 tcg_gen_andi_i32(cpu_VF, nzcv, (1 << 28));
1199 tcg_gen_shli_i32(cpu_VF, cpu_VF, 3);
1200 tcg_temp_free_i32(nzcv);
1201 }
1202
1203 /* C5.6.129 MRS - move from system register
1204 * C5.6.131 MSR (register) - move to system register
1205 * C5.6.204 SYS
1206 * C5.6.205 SYSL
1207 * These are all essentially the same insn in 'read' and 'write'
1208 * versions, with varying op0 fields.
1209 */
1210 static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
1211 unsigned int op0, unsigned int op1, unsigned int op2,
1212 unsigned int crn, unsigned int crm, unsigned int rt)
1213 {
1214 const ARMCPRegInfo *ri;
1215 TCGv_i64 tcg_rt;
1216
1217 ri = get_arm_cp_reginfo(s->cp_regs,
1218 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP,
1219 crn, crm, op0, op1, op2));
1220
1221 if (!ri) {
1222 /* Unknown register; this might be a guest error or a QEMU
1223 * unimplemented feature.
1224 */
1225 qemu_log_mask(LOG_UNIMP, "%s access to unsupported AArch64 "
1226 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
1227 isread ? "read" : "write", op0, op1, crn, crm, op2);
1228 unallocated_encoding(s);
1229 return;
1230 }
1231
1232 /* Check access permissions */
1233 if (!cp_access_ok(s->current_pl, ri, isread)) {
1234 unallocated_encoding(s);
1235 return;
1236 }
1237
1238 if (ri->accessfn) {
1239 /* Emit code to perform further access permissions checks at
1240 * runtime; this may result in an exception.
1241 */
1242 TCGv_ptr tmpptr;
1243 gen_a64_set_pc_im(s->pc - 4);
1244 tmpptr = tcg_const_ptr(ri);
1245 gen_helper_access_check_cp_reg(cpu_env, tmpptr);
1246 tcg_temp_free_ptr(tmpptr);
1247 }
1248
1249 /* Handle special cases first */
1250 switch (ri->type & ~(ARM_CP_FLAG_MASK & ~ARM_CP_SPECIAL)) {
1251 case ARM_CP_NOP:
1252 return;
1253 case ARM_CP_NZCV:
1254 tcg_rt = cpu_reg(s, rt);
1255 if (isread) {
1256 gen_get_nzcv(tcg_rt);
1257 } else {
1258 gen_set_nzcv(tcg_rt);
1259 }
1260 return;
1261 case ARM_CP_CURRENTEL:
1262 /* Reads as current EL value from pstate, which is
1263 * guaranteed to be constant by the tb flags.
1264 */
1265 tcg_rt = cpu_reg(s, rt);
1266 tcg_gen_movi_i64(tcg_rt, s->current_pl << 2);
1267 return;
1268 default:
1269 break;
1270 }
1271
1272 if (use_icount && (ri->type & ARM_CP_IO)) {
1273 gen_io_start();
1274 }
1275
1276 tcg_rt = cpu_reg(s, rt);
1277
1278 if (isread) {
1279 if (ri->type & ARM_CP_CONST) {
1280 tcg_gen_movi_i64(tcg_rt, ri->resetvalue);
1281 } else if (ri->readfn) {
1282 TCGv_ptr tmpptr;
1283 tmpptr = tcg_const_ptr(ri);
1284 gen_helper_get_cp_reg64(tcg_rt, cpu_env, tmpptr);
1285 tcg_temp_free_ptr(tmpptr);
1286 } else {
1287 tcg_gen_ld_i64(tcg_rt, cpu_env, ri->fieldoffset);
1288 }
1289 } else {
1290 if (ri->type & ARM_CP_CONST) {
1291 /* If not forbidden by access permissions, treat as WI */
1292 return;
1293 } else if (ri->writefn) {
1294 TCGv_ptr tmpptr;
1295 tmpptr = tcg_const_ptr(ri);
1296 gen_helper_set_cp_reg64(cpu_env, tmpptr, tcg_rt);
1297 tcg_temp_free_ptr(tmpptr);
1298 } else {
1299 tcg_gen_st_i64(tcg_rt, cpu_env, ri->fieldoffset);
1300 }
1301 }
1302
1303 if (use_icount && (ri->type & ARM_CP_IO)) {
1304 /* I/O operations must end the TB here (whether read or write) */
1305 gen_io_end();
1306 s->is_jmp = DISAS_UPDATE;
1307 } else if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) {
1308 /* We default to ending the TB on a coprocessor register write,
1309 * but allow this to be suppressed by the register definition
1310 * (usually only necessary to work around guest bugs).
1311 */
1312 s->is_jmp = DISAS_UPDATE;
1313 }
1314 }
1315
1316 /* C3.2.4 System
1317 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
1318 * +---------------------+---+-----+-----+-------+-------+-----+------+
1319 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
1320 * +---------------------+---+-----+-----+-------+-------+-----+------+
1321 */
1322 static void disas_system(DisasContext *s, uint32_t insn)
1323 {
1324 unsigned int l, op0, op1, crn, crm, op2, rt;
1325 l = extract32(insn, 21, 1);
1326 op0 = extract32(insn, 19, 2);
1327 op1 = extract32(insn, 16, 3);
1328 crn = extract32(insn, 12, 4);
1329 crm = extract32(insn, 8, 4);
1330 op2 = extract32(insn, 5, 3);
1331 rt = extract32(insn, 0, 5);
1332
1333 if (op0 == 0) {
1334 if (l || rt != 31) {
1335 unallocated_encoding(s);
1336 return;
1337 }
1338 switch (crn) {
1339 case 2: /* C5.6.68 HINT */
1340 handle_hint(s, insn, op1, op2, crm);
1341 break;
1342 case 3: /* CLREX, DSB, DMB, ISB */
1343 handle_sync(s, insn, op1, op2, crm);
1344 break;
1345 case 4: /* C5.6.130 MSR (immediate) */
1346 handle_msr_i(s, insn, op1, op2, crm);
1347 break;
1348 default:
1349 unallocated_encoding(s);
1350 break;
1351 }
1352 return;
1353 }
1354 handle_sys(s, insn, l, op0, op1, op2, crn, crm, rt);
1355 }
1356
1357 /* C3.2.3 Exception generation
1358 *
1359 * 31 24 23 21 20 5 4 2 1 0
1360 * +-----------------+-----+------------------------+-----+----+
1361 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
1362 * +-----------------------+------------------------+----------+
1363 */
1364 static void disas_exc(DisasContext *s, uint32_t insn)
1365 {
1366 int opc = extract32(insn, 21, 3);
1367 int op2_ll = extract32(insn, 0, 5);
1368
1369 switch (opc) {
1370 case 0:
1371 /* SVC, HVC, SMC; since we don't support the Virtualization
1372 * or TrustZone extensions these all UNDEF except SVC.
1373 */
1374 if (op2_ll != 1) {
1375 unallocated_encoding(s);
1376 break;
1377 }
1378 gen_exception_insn(s, 0, EXCP_SWI);
1379 break;
1380 case 1:
1381 if (op2_ll != 0) {
1382 unallocated_encoding(s);
1383 break;
1384 }
1385 /* BRK */
1386 gen_exception_insn(s, 0, EXCP_BKPT);
1387 break;
1388 case 2:
1389 if (op2_ll != 0) {
1390 unallocated_encoding(s);
1391 break;
1392 }
1393 /* HLT */
1394 unsupported_encoding(s, insn);
1395 break;
1396 case 5:
1397 if (op2_ll < 1 || op2_ll > 3) {
1398 unallocated_encoding(s);
1399 break;
1400 }
1401 /* DCPS1, DCPS2, DCPS3 */
1402 unsupported_encoding(s, insn);
1403 break;
1404 default:
1405 unallocated_encoding(s);
1406 break;
1407 }
1408 }
1409
1410 /* C3.2.7 Unconditional branch (register)
1411 * 31 25 24 21 20 16 15 10 9 5 4 0
1412 * +---------------+-------+-------+-------+------+-------+
1413 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
1414 * +---------------+-------+-------+-------+------+-------+
1415 */
1416 static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
1417 {
1418 unsigned int opc, op2, op3, rn, op4;
1419
1420 opc = extract32(insn, 21, 4);
1421 op2 = extract32(insn, 16, 5);
1422 op3 = extract32(insn, 10, 6);
1423 rn = extract32(insn, 5, 5);
1424 op4 = extract32(insn, 0, 5);
1425
1426 if (op4 != 0x0 || op3 != 0x0 || op2 != 0x1f) {
1427 unallocated_encoding(s);
1428 return;
1429 }
1430
1431 switch (opc) {
1432 case 0: /* BR */
1433 case 2: /* RET */
1434 break;
1435 case 1: /* BLR */
1436 tcg_gen_movi_i64(cpu_reg(s, 30), s->pc);
1437 break;
1438 case 4: /* ERET */
1439 case 5: /* DRPS */
1440 if (rn != 0x1f) {
1441 unallocated_encoding(s);
1442 } else {
1443 unsupported_encoding(s, insn);
1444 }
1445 return;
1446 default:
1447 unallocated_encoding(s);
1448 return;
1449 }
1450
1451 tcg_gen_mov_i64(cpu_pc, cpu_reg(s, rn));
1452 s->is_jmp = DISAS_JUMP;
1453 }
1454
1455 /* C3.2 Branches, exception generating and system instructions */
1456 static void disas_b_exc_sys(DisasContext *s, uint32_t insn)
1457 {
1458 switch (extract32(insn, 25, 7)) {
1459 case 0x0a: case 0x0b:
1460 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
1461 disas_uncond_b_imm(s, insn);
1462 break;
1463 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
1464 disas_comp_b_imm(s, insn);
1465 break;
1466 case 0x1b: case 0x5b: /* Test & branch (immediate) */
1467 disas_test_b_imm(s, insn);
1468 break;
1469 case 0x2a: /* Conditional branch (immediate) */
1470 disas_cond_b_imm(s, insn);
1471 break;
1472 case 0x6a: /* Exception generation / System */
1473 if (insn & (1 << 24)) {
1474 disas_system(s, insn);
1475 } else {
1476 disas_exc(s, insn);
1477 }
1478 break;
1479 case 0x6b: /* Unconditional branch (register) */
1480 disas_uncond_b_reg(s, insn);
1481 break;
1482 default:
1483 unallocated_encoding(s);
1484 break;
1485 }
1486 }
1487
1488 /*
1489 * Load/Store exclusive instructions are implemented by remembering
1490 * the value/address loaded, and seeing if these are the same
1491 * when the store is performed. This is not actually the architecturally
1492 * mandated semantics, but it works for typical guest code sequences
1493 * and avoids having to monitor regular stores.
1494 *
1495 * In system emulation mode only one CPU will be running at once, so
1496 * this sequence is effectively atomic. In user emulation mode we
1497 * throw an exception and handle the atomic operation elsewhere.
1498 */
1499 static void gen_load_exclusive(DisasContext *s, int rt, int rt2,
1500 TCGv_i64 addr, int size, bool is_pair)
1501 {
1502 TCGv_i64 tmp = tcg_temp_new_i64();
1503 TCGMemOp memop = MO_TE + size;
1504
1505 g_assert(size <= 3);
1506 tcg_gen_qemu_ld_i64(tmp, addr, get_mem_index(s), memop);
1507
1508 if (is_pair) {
1509 TCGv_i64 addr2 = tcg_temp_new_i64();
1510 TCGv_i64 hitmp = tcg_temp_new_i64();
1511
1512 g_assert(size >= 2);
1513 tcg_gen_addi_i64(addr2, addr, 1 << size);
1514 tcg_gen_qemu_ld_i64(hitmp, addr2, get_mem_index(s), memop);
1515 tcg_temp_free_i64(addr2);
1516 tcg_gen_mov_i64(cpu_exclusive_high, hitmp);
1517 tcg_gen_mov_i64(cpu_reg(s, rt2), hitmp);
1518 tcg_temp_free_i64(hitmp);
1519 }
1520
1521 tcg_gen_mov_i64(cpu_exclusive_val, tmp);
1522 tcg_gen_mov_i64(cpu_reg(s, rt), tmp);
1523
1524 tcg_temp_free_i64(tmp);
1525 tcg_gen_mov_i64(cpu_exclusive_addr, addr);
1526 }
1527
1528 #ifdef CONFIG_USER_ONLY
1529 static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
1530 TCGv_i64 addr, int size, int is_pair)
1531 {
1532 tcg_gen_mov_i64(cpu_exclusive_test, addr);
1533 tcg_gen_movi_i32(cpu_exclusive_info,
1534 size | is_pair << 2 | (rd << 4) | (rt << 9) | (rt2 << 14));
1535 gen_exception_insn(s, 4, EXCP_STREX);
1536 }
1537 #else
1538 static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
1539 TCGv_i64 inaddr, int size, int is_pair)
1540 {
1541 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
1542 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
1543 * [addr] = {Rt};
1544 * if (is_pair) {
1545 * [addr + datasize] = {Rt2};
1546 * }
1547 * {Rd} = 0;
1548 * } else {
1549 * {Rd} = 1;
1550 * }
1551 * env->exclusive_addr = -1;
1552 */
1553 int fail_label = gen_new_label();
1554 int done_label = gen_new_label();
1555 TCGv_i64 addr = tcg_temp_local_new_i64();
1556 TCGv_i64 tmp;
1557
1558 /* Copy input into a local temp so it is not trashed when the
1559 * basic block ends at the branch insn.
1560 */
1561 tcg_gen_mov_i64(addr, inaddr);
1562 tcg_gen_brcond_i64(TCG_COND_NE, addr, cpu_exclusive_addr, fail_label);
1563
1564 tmp = tcg_temp_new_i64();
1565 tcg_gen_qemu_ld_i64(tmp, addr, get_mem_index(s), MO_TE + size);
1566 tcg_gen_brcond_i64(TCG_COND_NE, tmp, cpu_exclusive_val, fail_label);
1567 tcg_temp_free_i64(tmp);
1568
1569 if (is_pair) {
1570 TCGv_i64 addrhi = tcg_temp_new_i64();
1571 TCGv_i64 tmphi = tcg_temp_new_i64();
1572
1573 tcg_gen_addi_i64(addrhi, addr, 1 << size);
1574 tcg_gen_qemu_ld_i64(tmphi, addrhi, get_mem_index(s), MO_TE + size);
1575 tcg_gen_brcond_i64(TCG_COND_NE, tmphi, cpu_exclusive_high, fail_label);
1576
1577 tcg_temp_free_i64(tmphi);
1578 tcg_temp_free_i64(addrhi);
1579 }
1580
1581 /* We seem to still have the exclusive monitor, so do the store */
1582 tcg_gen_qemu_st_i64(cpu_reg(s, rt), addr, get_mem_index(s), MO_TE + size);
1583 if (is_pair) {
1584 TCGv_i64 addrhi = tcg_temp_new_i64();
1585
1586 tcg_gen_addi_i64(addrhi, addr, 1 << size);
1587 tcg_gen_qemu_st_i64(cpu_reg(s, rt2), addrhi,
1588 get_mem_index(s), MO_TE + size);
1589 tcg_temp_free_i64(addrhi);
1590 }
1591
1592 tcg_temp_free_i64(addr);
1593
1594 tcg_gen_movi_i64(cpu_reg(s, rd), 0);
1595 tcg_gen_br(done_label);
1596 gen_set_label(fail_label);
1597 tcg_gen_movi_i64(cpu_reg(s, rd), 1);
1598 gen_set_label(done_label);
1599 tcg_gen_movi_i64(cpu_exclusive_addr, -1);
1600
1601 }
1602 #endif
1603
1604 /* C3.3.6 Load/store exclusive
1605 *
1606 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
1607 * +-----+-------------+----+---+----+------+----+-------+------+------+
1608 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
1609 * +-----+-------------+----+---+----+------+----+-------+------+------+
1610 *
1611 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
1612 * L: 0 -> store, 1 -> load
1613 * o2: 0 -> exclusive, 1 -> not
1614 * o1: 0 -> single register, 1 -> register pair
1615 * o0: 1 -> load-acquire/store-release, 0 -> not
1616 *
1617 * o0 == 0 AND o2 == 1 is un-allocated
1618 * o1 == 1 is un-allocated except for 32 and 64 bit sizes
1619 */
1620 static void disas_ldst_excl(DisasContext *s, uint32_t insn)
1621 {
1622 int rt = extract32(insn, 0, 5);
1623 int rn = extract32(insn, 5, 5);
1624 int rt2 = extract32(insn, 10, 5);
1625 int is_lasr = extract32(insn, 15, 1);
1626 int rs = extract32(insn, 16, 5);
1627 int is_pair = extract32(insn, 21, 1);
1628 int is_store = !extract32(insn, 22, 1);
1629 int is_excl = !extract32(insn, 23, 1);
1630 int size = extract32(insn, 30, 2);
1631 TCGv_i64 tcg_addr;
1632
1633 if ((!is_excl && !is_lasr) ||
1634 (is_pair && size < 2)) {
1635 unallocated_encoding(s);
1636 return;
1637 }
1638
1639 if (rn == 31) {
1640 gen_check_sp_alignment(s);
1641 }
1642 tcg_addr = read_cpu_reg_sp(s, rn, 1);
1643
1644 /* Note that since TCG is single threaded load-acquire/store-release
1645 * semantics require no extra if (is_lasr) { ... } handling.
1646 */
1647
1648 if (is_excl) {
1649 if (!is_store) {
1650 gen_load_exclusive(s, rt, rt2, tcg_addr, size, is_pair);
1651 } else {
1652 gen_store_exclusive(s, rs, rt, rt2, tcg_addr, size, is_pair);
1653 }
1654 } else {
1655 TCGv_i64 tcg_rt = cpu_reg(s, rt);
1656 if (is_store) {
1657 do_gpr_st(s, tcg_rt, tcg_addr, size);
1658 } else {
1659 do_gpr_ld(s, tcg_rt, tcg_addr, size, false, false);
1660 }
1661 if (is_pair) {
1662 TCGv_i64 tcg_rt2 = cpu_reg(s, rt);
1663 tcg_gen_addi_i64(tcg_addr, tcg_addr, 1 << size);
1664 if (is_store) {
1665 do_gpr_st(s, tcg_rt2, tcg_addr, size);
1666 } else {
1667 do_gpr_ld(s, tcg_rt2, tcg_addr, size, false, false);
1668 }
1669 }
1670 }
1671 }
1672
1673 /*
1674 * C3.3.5 Load register (literal)
1675 *
1676 * 31 30 29 27 26 25 24 23 5 4 0
1677 * +-----+-------+---+-----+-------------------+-------+
1678 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
1679 * +-----+-------+---+-----+-------------------+-------+
1680 *
1681 * V: 1 -> vector (simd/fp)
1682 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
1683 * 10-> 32 bit signed, 11 -> prefetch
1684 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
1685 */
1686 static void disas_ld_lit(DisasContext *s, uint32_t insn)
1687 {
1688 int rt = extract32(insn, 0, 5);
1689 int64_t imm = sextract32(insn, 5, 19) << 2;
1690 bool is_vector = extract32(insn, 26, 1);
1691 int opc = extract32(insn, 30, 2);
1692 bool is_signed = false;
1693 int size = 2;
1694 TCGv_i64 tcg_rt, tcg_addr;
1695
1696 if (is_vector) {
1697 if (opc == 3) {
1698 unallocated_encoding(s);
1699 return;
1700 }
1701 size = 2 + opc;
1702 } else {
1703 if (opc == 3) {
1704 /* PRFM (literal) : prefetch */
1705 return;
1706 }
1707 size = 2 + extract32(opc, 0, 1);
1708 is_signed = extract32(opc, 1, 1);
1709 }
1710
1711 tcg_rt = cpu_reg(s, rt);
1712
1713 tcg_addr = tcg_const_i64((s->pc - 4) + imm);
1714 if (is_vector) {
1715 do_fp_ld(s, rt, tcg_addr, size);
1716 } else {
1717 do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, false);
1718 }
1719 tcg_temp_free_i64(tcg_addr);
1720 }
1721
1722 /*
1723 * C5.6.80 LDNP (Load Pair - non-temporal hint)
1724 * C5.6.81 LDP (Load Pair - non vector)
1725 * C5.6.82 LDPSW (Load Pair Signed Word - non vector)
1726 * C5.6.176 STNP (Store Pair - non-temporal hint)
1727 * C5.6.177 STP (Store Pair - non vector)
1728 * C6.3.165 LDNP (Load Pair of SIMD&FP - non-temporal hint)
1729 * C6.3.165 LDP (Load Pair of SIMD&FP)
1730 * C6.3.284 STNP (Store Pair of SIMD&FP - non-temporal hint)
1731 * C6.3.284 STP (Store Pair of SIMD&FP)
1732 *
1733 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
1734 * +-----+-------+---+---+-------+---+-----------------------------+
1735 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
1736 * +-----+-------+---+---+-------+---+-------+-------+------+------+
1737 *
1738 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
1739 * LDPSW 01
1740 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
1741 * V: 0 -> GPR, 1 -> Vector
1742 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
1743 * 10 -> signed offset, 11 -> pre-index
1744 * L: 0 -> Store 1 -> Load
1745 *
1746 * Rt, Rt2 = GPR or SIMD registers to be stored
1747 * Rn = general purpose register containing address
1748 * imm7 = signed offset (multiple of 4 or 8 depending on size)
1749 */
1750 static void disas_ldst_pair(DisasContext *s, uint32_t insn)
1751 {
1752 int rt = extract32(insn, 0, 5);
1753 int rn = extract32(insn, 5, 5);
1754 int rt2 = extract32(insn, 10, 5);
1755 int64_t offset = sextract32(insn, 15, 7);
1756 int index = extract32(insn, 23, 2);
1757 bool is_vector = extract32(insn, 26, 1);
1758 bool is_load = extract32(insn, 22, 1);
1759 int opc = extract32(insn, 30, 2);
1760
1761 bool is_signed = false;
1762 bool postindex = false;
1763 bool wback = false;
1764
1765 TCGv_i64 tcg_addr; /* calculated address */
1766 int size;
1767
1768 if (opc == 3) {
1769 unallocated_encoding(s);
1770 return;
1771 }
1772
1773 if (is_vector) {
1774 size = 2 + opc;
1775 } else {
1776 size = 2 + extract32(opc, 1, 1);
1777 is_signed = extract32(opc, 0, 1);
1778 if (!is_load && is_signed) {
1779 unallocated_encoding(s);
1780 return;
1781 }
1782 }
1783
1784 switch (index) {
1785 case 1: /* post-index */
1786 postindex = true;
1787 wback = true;
1788 break;
1789 case 0:
1790 /* signed offset with "non-temporal" hint. Since we don't emulate
1791 * caches we don't care about hints to the cache system about
1792 * data access patterns, and handle this identically to plain
1793 * signed offset.
1794 */
1795 if (is_signed) {
1796 /* There is no non-temporal-hint version of LDPSW */
1797 unallocated_encoding(s);
1798 return;
1799 }
1800 postindex = false;
1801 break;
1802 case 2: /* signed offset, rn not updated */
1803 postindex = false;
1804 break;
1805 case 3: /* pre-index */
1806 postindex = false;
1807 wback = true;
1808 break;
1809 }
1810
1811 offset <<= size;
1812
1813 if (rn == 31) {
1814 gen_check_sp_alignment(s);
1815 }
1816
1817 tcg_addr = read_cpu_reg_sp(s, rn, 1);
1818
1819 if (!postindex) {
1820 tcg_gen_addi_i64(tcg_addr, tcg_addr, offset);
1821 }
1822
1823 if (is_vector) {
1824 if (is_load) {
1825 do_fp_ld(s, rt, tcg_addr, size);
1826 } else {
1827 do_fp_st(s, rt, tcg_addr, size);
1828 }
1829 } else {
1830 TCGv_i64 tcg_rt = cpu_reg(s, rt);
1831 if (is_load) {
1832 do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, false);
1833 } else {
1834 do_gpr_st(s, tcg_rt, tcg_addr, size);
1835 }
1836 }
1837 tcg_gen_addi_i64(tcg_addr, tcg_addr, 1 << size);
1838 if (is_vector) {
1839 if (is_load) {
1840 do_fp_ld(s, rt2, tcg_addr, size);
1841 } else {
1842 do_fp_st(s, rt2, tcg_addr, size);
1843 }
1844 } else {
1845 TCGv_i64 tcg_rt2 = cpu_reg(s, rt2);
1846 if (is_load) {
1847 do_gpr_ld(s, tcg_rt2, tcg_addr, size, is_signed, false);
1848 } else {
1849 do_gpr_st(s, tcg_rt2, tcg_addr, size);
1850 }
1851 }
1852
1853 if (wback) {
1854 if (postindex) {
1855 tcg_gen_addi_i64(tcg_addr, tcg_addr, offset - (1 << size));
1856 } else {
1857 tcg_gen_subi_i64(tcg_addr, tcg_addr, 1 << size);
1858 }
1859 tcg_gen_mov_i64(cpu_reg_sp(s, rn), tcg_addr);
1860 }
1861 }
1862
1863 /*
1864 * C3.3.8 Load/store (immediate post-indexed)
1865 * C3.3.9 Load/store (immediate pre-indexed)
1866 * C3.3.12 Load/store (unscaled immediate)
1867 *
1868 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
1869 * +----+-------+---+-----+-----+---+--------+-----+------+------+
1870 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
1871 * +----+-------+---+-----+-----+---+--------+-----+------+------+
1872 *
1873 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
1874 10 -> unprivileged
1875 * V = 0 -> non-vector
1876 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
1877 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
1878 */
1879 static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn)
1880 {
1881 int rt = extract32(insn, 0, 5);
1882 int rn = extract32(insn, 5, 5);
1883 int imm9 = sextract32(insn, 12, 9);
1884 int opc = extract32(insn, 22, 2);
1885 int size = extract32(insn, 30, 2);
1886 int idx = extract32(insn, 10, 2);
1887 bool is_signed = false;
1888 bool is_store = false;
1889 bool is_extended = false;
1890 bool is_unpriv = (idx == 2);
1891 bool is_vector = extract32(insn, 26, 1);
1892 bool post_index;
1893 bool writeback;
1894
1895 TCGv_i64 tcg_addr;
1896
1897 if (is_vector) {
1898 size |= (opc & 2) << 1;
1899 if (size > 4 || is_unpriv) {
1900 unallocated_encoding(s);
1901 return;
1902 }
1903 is_store = ((opc & 1) == 0);
1904 } else {
1905 if (size == 3 && opc == 2) {
1906 /* PRFM - prefetch */
1907 if (is_unpriv) {
1908 unallocated_encoding(s);
1909 return;
1910 }
1911 return;
1912 }
1913 if (opc == 3 && size > 1) {
1914 unallocated_encoding(s);
1915 return;
1916 }
1917 is_store = (opc == 0);
1918 is_signed = opc & (1<<1);
1919 is_extended = (size < 3) && (opc & 1);
1920 }
1921
1922 switch (idx) {
1923 case 0:
1924 case 2:
1925 post_index = false;
1926 writeback = false;
1927 break;
1928 case 1:
1929 post_index = true;
1930 writeback = true;
1931 break;
1932 case 3:
1933 post_index = false;
1934 writeback = true;
1935 break;
1936 }
1937
1938 if (rn == 31) {
1939 gen_check_sp_alignment(s);
1940 }
1941 tcg_addr = read_cpu_reg_sp(s, rn, 1);
1942
1943 if (!post_index) {
1944 tcg_gen_addi_i64(tcg_addr, tcg_addr, imm9);
1945 }
1946
1947 if (is_vector) {
1948 if (is_store) {
1949 do_fp_st(s, rt, tcg_addr, size);
1950 } else {
1951 do_fp_ld(s, rt, tcg_addr, size);
1952 }
1953 } else {
1954 TCGv_i64 tcg_rt = cpu_reg(s, rt);
1955 int memidx = is_unpriv ? 1 : get_mem_index(s);
1956
1957 if (is_store) {
1958 do_gpr_st_memidx(s, tcg_rt, tcg_addr, size, memidx);
1959 } else {
1960 do_gpr_ld_memidx(s, tcg_rt, tcg_addr, size,
1961 is_signed, is_extended, memidx);
1962 }
1963 }
1964
1965 if (writeback) {
1966 TCGv_i64 tcg_rn = cpu_reg_sp(s, rn);
1967 if (post_index) {
1968 tcg_gen_addi_i64(tcg_addr, tcg_addr, imm9);
1969 }
1970 tcg_gen_mov_i64(tcg_rn, tcg_addr);
1971 }
1972 }
1973
1974 /*
1975 * C3.3.10 Load/store (register offset)
1976 *
1977 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
1978 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
1979 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
1980 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
1981 *
1982 * For non-vector:
1983 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
1984 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
1985 * For vector:
1986 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
1987 * opc<0>: 0 -> store, 1 -> load
1988 * V: 1 -> vector/simd
1989 * opt: extend encoding (see DecodeRegExtend)
1990 * S: if S=1 then scale (essentially index by sizeof(size))
1991 * Rt: register to transfer into/out of
1992 * Rn: address register or SP for base
1993 * Rm: offset register or ZR for offset
1994 */
1995 static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn)
1996 {
1997 int rt = extract32(insn, 0, 5);
1998 int rn = extract32(insn, 5, 5);
1999 int shift = extract32(insn, 12, 1);
2000 int rm = extract32(insn, 16, 5);
2001 int opc = extract32(insn, 22, 2);
2002 int opt = extract32(insn, 13, 3);
2003 int size = extract32(insn, 30, 2);
2004 bool is_signed = false;
2005 bool is_store = false;
2006 bool is_extended = false;
2007 bool is_vector = extract32(insn, 26, 1);
2008
2009 TCGv_i64 tcg_rm;
2010 TCGv_i64 tcg_addr;
2011
2012 if (extract32(opt, 1, 1) == 0) {
2013 unallocated_encoding(s);
2014 return;
2015 }
2016
2017 if (is_vector) {
2018 size |= (opc & 2) << 1;
2019 if (size > 4) {
2020 unallocated_encoding(s);
2021 return;
2022 }
2023 is_store = !extract32(opc, 0, 1);
2024 } else {
2025 if (size == 3 && opc == 2) {
2026 /* PRFM - prefetch */
2027 return;
2028 }
2029 if (opc == 3 && size > 1) {
2030 unallocated_encoding(s);
2031 return;
2032 }
2033 is_store = (opc == 0);
2034 is_signed = extract32(opc, 1, 1);
2035 is_extended = (size < 3) && extract32(opc, 0, 1);
2036 }
2037
2038 if (rn == 31) {
2039 gen_check_sp_alignment(s);
2040 }
2041 tcg_addr = read_cpu_reg_sp(s, rn, 1);
2042
2043 tcg_rm = read_cpu_reg(s, rm, 1);
2044 ext_and_shift_reg(tcg_rm, tcg_rm, opt, shift ? size : 0);
2045
2046 tcg_gen_add_i64(tcg_addr, tcg_addr, tcg_rm);
2047
2048 if (is_vector) {
2049 if (is_store) {
2050 do_fp_st(s, rt, tcg_addr, size);
2051 } else {
2052 do_fp_ld(s, rt, tcg_addr, size);
2053 }
2054 } else {
2055 TCGv_i64 tcg_rt = cpu_reg(s, rt);
2056 if (is_store) {
2057 do_gpr_st(s, tcg_rt, tcg_addr, size);
2058 } else {
2059 do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, is_extended);
2060 }
2061 }
2062 }
2063
2064 /*
2065 * C3.3.13 Load/store (unsigned immediate)
2066 *
2067 * 31 30 29 27 26 25 24 23 22 21 10 9 5
2068 * +----+-------+---+-----+-----+------------+-------+------+
2069 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
2070 * +----+-------+---+-----+-----+------------+-------+------+
2071 *
2072 * For non-vector:
2073 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2074 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2075 * For vector:
2076 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2077 * opc<0>: 0 -> store, 1 -> load
2078 * Rn: base address register (inc SP)
2079 * Rt: target register
2080 */
2081 static void disas_ldst_reg_unsigned_imm(DisasContext *s, uint32_t insn)
2082 {
2083 int rt = extract32(insn, 0, 5);
2084 int rn = extract32(insn, 5, 5);
2085 unsigned int imm12 = extract32(insn, 10, 12);
2086 bool is_vector = extract32(insn, 26, 1);
2087 int size = extract32(insn, 30, 2);
2088 int opc = extract32(insn, 22, 2);
2089 unsigned int offset;
2090
2091 TCGv_i64 tcg_addr;
2092
2093 bool is_store;
2094 bool is_signed = false;
2095 bool is_extended = false;
2096
2097 if (is_vector) {
2098 size |= (opc & 2) << 1;
2099 if (size > 4) {
2100 unallocated_encoding(s);
2101 return;
2102 }
2103 is_store = !extract32(opc, 0, 1);
2104 } else {
2105 if (size == 3 && opc == 2) {
2106 /* PRFM - prefetch */
2107 return;
2108 }
2109 if (opc == 3 && size > 1) {
2110 unallocated_encoding(s);
2111 return;
2112 }
2113 is_store = (opc == 0);
2114 is_signed = extract32(opc, 1, 1);
2115 is_extended = (size < 3) && extract32(opc, 0, 1);
2116 }
2117
2118 if (rn == 31) {
2119 gen_check_sp_alignment(s);
2120 }
2121 tcg_addr = read_cpu_reg_sp(s, rn, 1);
2122 offset = imm12 << size;
2123 tcg_gen_addi_i64(tcg_addr, tcg_addr, offset);
2124
2125 if (is_vector) {
2126 if (is_store) {
2127 do_fp_st(s, rt, tcg_addr, size);
2128 } else {
2129 do_fp_ld(s, rt, tcg_addr, size);
2130 }
2131 } else {
2132 TCGv_i64 tcg_rt = cpu_reg(s, rt);
2133 if (is_store) {
2134 do_gpr_st(s, tcg_rt, tcg_addr, size);
2135 } else {
2136 do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, is_extended);
2137 }
2138 }
2139 }
2140
2141 /* Load/store register (all forms) */
2142 static void disas_ldst_reg(DisasContext *s, uint32_t insn)
2143 {
2144 switch (extract32(insn, 24, 2)) {
2145 case 0:
2146 if (extract32(insn, 21, 1) == 1 && extract32(insn, 10, 2) == 2) {
2147 disas_ldst_reg_roffset(s, insn);
2148 } else {
2149 /* Load/store register (unscaled immediate)
2150 * Load/store immediate pre/post-indexed
2151 * Load/store register unprivileged
2152 */
2153 disas_ldst_reg_imm9(s, insn);
2154 }
2155 break;
2156 case 1:
2157 disas_ldst_reg_unsigned_imm(s, insn);
2158 break;
2159 default:
2160 unallocated_encoding(s);
2161 break;
2162 }
2163 }
2164
2165 /* C3.3.1 AdvSIMD load/store multiple structures
2166 *
2167 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
2168 * +---+---+---------------+---+-------------+--------+------+------+------+
2169 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
2170 * +---+---+---------------+---+-------------+--------+------+------+------+
2171 *
2172 * C3.3.2 AdvSIMD load/store multiple structures (post-indexed)
2173 *
2174 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
2175 * +---+---+---------------+---+---+---------+--------+------+------+------+
2176 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
2177 * +---+---+---------------+---+---+---------+--------+------+------+------+
2178 *
2179 * Rt: first (or only) SIMD&FP register to be transferred
2180 * Rn: base address or SP
2181 * Rm (post-index only): post-index register (when !31) or size dependent #imm
2182 */
2183 static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn)
2184 {
2185 int rt = extract32(insn, 0, 5);
2186 int rn = extract32(insn, 5, 5);
2187 int size = extract32(insn, 10, 2);
2188 int opcode = extract32(insn, 12, 4);
2189 bool is_store = !extract32(insn, 22, 1);
2190 bool is_postidx = extract32(insn, 23, 1);
2191 bool is_q = extract32(insn, 30, 1);
2192 TCGv_i64 tcg_addr, tcg_rn;
2193
2194 int ebytes = 1 << size;
2195 int elements = (is_q ? 128 : 64) / (8 << size);
2196 int rpt; /* num iterations */
2197 int selem; /* structure elements */
2198 int r;
2199
2200 if (extract32(insn, 31, 1) || extract32(insn, 21, 1)) {
2201 unallocated_encoding(s);
2202 return;
2203 }
2204
2205 /* From the shared decode logic */
2206 switch (opcode) {
2207 case 0x0:
2208 rpt = 1;
2209 selem = 4;
2210 break;
2211 case 0x2:
2212 rpt = 4;
2213 selem = 1;
2214 break;
2215 case 0x4:
2216 rpt = 1;
2217 selem = 3;
2218 break;
2219 case 0x6:
2220 rpt = 3;
2221 selem = 1;
2222 break;
2223 case 0x7:
2224 rpt = 1;
2225 selem = 1;
2226 break;
2227 case 0x8:
2228 rpt = 1;
2229 selem = 2;
2230 break;
2231 case 0xa:
2232 rpt = 2;
2233 selem = 1;
2234 break;
2235 default:
2236 unallocated_encoding(s);
2237 return;
2238 }
2239
2240 if (size == 3 && !is_q && selem != 1) {
2241 /* reserved */
2242 unallocated_encoding(s);
2243 return;
2244 }
2245
2246 if (rn == 31) {
2247 gen_check_sp_alignment(s);
2248 }
2249
2250 tcg_rn = cpu_reg_sp(s, rn);
2251 tcg_addr = tcg_temp_new_i64();
2252 tcg_gen_mov_i64(tcg_addr, tcg_rn);
2253
2254 for (r = 0; r < rpt; r++) {
2255 int e;
2256 for (e = 0; e < elements; e++) {
2257 int tt = (rt + r) % 32;
2258 int xs;
2259 for (xs = 0; xs < selem; xs++) {
2260 if (is_store) {
2261 do_vec_st(s, tt, e, tcg_addr, size);
2262 } else {
2263 do_vec_ld(s, tt, e, tcg_addr, size);
2264
2265 /* For non-quad operations, setting a slice of the low
2266 * 64 bits of the register clears the high 64 bits (in
2267 * the ARM ARM pseudocode this is implicit in the fact
2268 * that 'rval' is a 64 bit wide variable). We optimize
2269 * by noticing that we only need to do this the first
2270 * time we touch a register.
2271 */
2272 if (!is_q && e == 0 && (r == 0 || xs == selem - 1)) {
2273 clear_vec_high(s, tt);
2274 }
2275 }
2276 tcg_gen_addi_i64(tcg_addr, tcg_addr, ebytes);
2277 tt = (tt + 1) % 32;
2278 }
2279 }
2280 }
2281
2282 if (is_postidx) {
2283 int rm = extract32(insn, 16, 5);
2284 if (rm == 31) {
2285 tcg_gen_mov_i64(tcg_rn, tcg_addr);
2286 } else {
2287 tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm));
2288 }
2289 }
2290 tcg_temp_free_i64(tcg_addr);
2291 }
2292
2293 /* C3.3.3 AdvSIMD load/store single structure
2294 *
2295 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2296 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2297 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
2298 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2299 *
2300 * C3.3.4 AdvSIMD load/store single structure (post-indexed)
2301 *
2302 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2303 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2304 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
2305 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2306 *
2307 * Rt: first (or only) SIMD&FP register to be transferred
2308 * Rn: base address or SP
2309 * Rm (post-index only): post-index register (when !31) or size dependent #imm
2310 * index = encoded in Q:S:size dependent on size
2311 *
2312 * lane_size = encoded in R, opc
2313 * transfer width = encoded in opc, S, size
2314 */
2315 static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)
2316 {
2317 int rt = extract32(insn, 0, 5);
2318 int rn = extract32(insn, 5, 5);
2319 int size = extract32(insn, 10, 2);
2320 int S = extract32(insn, 12, 1);
2321 int opc = extract32(insn, 13, 3);
2322 int R = extract32(insn, 21, 1);
2323 int is_load = extract32(insn, 22, 1);
2324 int is_postidx = extract32(insn, 23, 1);
2325 int is_q = extract32(insn, 30, 1);
2326
2327 int scale = extract32(opc, 1, 2);
2328 int selem = (extract32(opc, 0, 1) << 1 | R) + 1;
2329 bool replicate = false;
2330 int index = is_q << 3 | S << 2 | size;
2331 int ebytes, xs;
2332 TCGv_i64 tcg_addr, tcg_rn;
2333
2334 switch (scale) {
2335 case 3:
2336 if (!is_load || S) {
2337 unallocated_encoding(s);
2338 return;
2339 }
2340 scale = size;
2341 replicate = true;
2342 break;
2343 case 0:
2344 break;
2345 case 1:
2346 if (extract32(size, 0, 1)) {
2347 unallocated_encoding(s);
2348 return;
2349 }
2350 index >>= 1;
2351 break;
2352 case 2:
2353 if (extract32(size, 1, 1)) {
2354 unallocated_encoding(s);
2355 return;
2356 }
2357 if (!extract32(size, 0, 1)) {
2358 index >>= 2;
2359 } else {
2360 if (S) {
2361 unallocated_encoding(s);
2362 return;
2363 }
2364 index >>= 3;
2365 scale = 3;
2366 }
2367 break;
2368 default:
2369 g_assert_not_reached();
2370 }
2371
2372 ebytes = 1 << scale;
2373
2374 if (rn == 31) {
2375 gen_check_sp_alignment(s);
2376 }
2377
2378 tcg_rn = cpu_reg_sp(s, rn);
2379 tcg_addr = tcg_temp_new_i64();
2380 tcg_gen_mov_i64(tcg_addr, tcg_rn);
2381
2382 for (xs = 0; xs < selem; xs++) {
2383 if (replicate) {
2384 /* Load and replicate to all elements */
2385 uint64_t mulconst;
2386 TCGv_i64 tcg_tmp = tcg_temp_new_i64();
2387
2388 tcg_gen_qemu_ld_i64(tcg_tmp, tcg_addr,
2389 get_mem_index(s), MO_TE + scale);
2390 switch (scale) {
2391 case 0:
2392 mulconst = 0x0101010101010101ULL;
2393 break;
2394 case 1:
2395 mulconst = 0x0001000100010001ULL;
2396 break;
2397 case 2:
2398 mulconst = 0x0000000100000001ULL;
2399 break;
2400 case 3:
2401 mulconst = 0;
2402 break;
2403 default:
2404 g_assert_not_reached();
2405 }
2406 if (mulconst) {
2407 tcg_gen_muli_i64(tcg_tmp, tcg_tmp, mulconst);
2408 }
2409 write_vec_element(s, tcg_tmp, rt, 0, MO_64);
2410 if (is_q) {
2411 write_vec_element(s, tcg_tmp, rt, 1, MO_64);
2412 } else {
2413 clear_vec_high(s, rt);
2414 }
2415 tcg_temp_free_i64(tcg_tmp);
2416 } else {
2417 /* Load/store one element per register */
2418 if (is_load) {
2419 do_vec_ld(s, rt, index, tcg_addr, MO_TE + scale);
2420 } else {
2421 do_vec_st(s, rt, index, tcg_addr, MO_TE + scale);
2422 }
2423 }
2424 tcg_gen_addi_i64(tcg_addr, tcg_addr, ebytes);
2425 rt = (rt + 1) % 32;
2426 }
2427
2428 if (is_postidx) {
2429 int rm = extract32(insn, 16, 5);
2430 if (rm == 31) {
2431 tcg_gen_mov_i64(tcg_rn, tcg_addr);
2432 } else {
2433 tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm));
2434 }
2435 }
2436 tcg_temp_free_i64(tcg_addr);
2437 }
2438
2439 /* C3.3 Loads and stores */
2440 static void disas_ldst(DisasContext *s, uint32_t insn)
2441 {
2442 switch (extract32(insn, 24, 6)) {
2443 case 0x08: /* Load/store exclusive */
2444 disas_ldst_excl(s, insn);
2445 break;
2446 case 0x18: case 0x1c: /* Load register (literal) */
2447 disas_ld_lit(s, insn);
2448 break;
2449 case 0x28: case 0x29:
2450 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
2451 disas_ldst_pair(s, insn);
2452 break;
2453 case 0x38: case 0x39:
2454 case 0x3c: case 0x3d: /* Load/store register (all forms) */
2455 disas_ldst_reg(s, insn);
2456 break;
2457 case 0x0c: /* AdvSIMD load/store multiple structures */
2458 disas_ldst_multiple_struct(s, insn);
2459 break;
2460 case 0x0d: /* AdvSIMD load/store single structure */
2461 disas_ldst_single_struct(s, insn);
2462 break;
2463 default:
2464 unallocated_encoding(s);
2465 break;
2466 }
2467 }
2468
2469 /* C3.4.6 PC-rel. addressing
2470 * 31 30 29 28 24 23 5 4 0
2471 * +----+-------+-----------+-------------------+------+
2472 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
2473 * +----+-------+-----------+-------------------+------+
2474 */
2475 static void disas_pc_rel_adr(DisasContext *s, uint32_t insn)
2476 {
2477 unsigned int page, rd;
2478 uint64_t base;
2479 int64_t offset;
2480
2481 page = extract32(insn, 31, 1);
2482 /* SignExtend(immhi:immlo) -> offset */
2483 offset = ((int64_t)sextract32(insn, 5, 19) << 2) | extract32(insn, 29, 2);
2484 rd = extract32(insn, 0, 5);
2485 base = s->pc - 4;
2486
2487 if (page) {
2488 /* ADRP (page based) */
2489 base &= ~0xfff;
2490 offset <<= 12;
2491 }
2492
2493 tcg_gen_movi_i64(cpu_reg(s, rd), base + offset);
2494 }
2495
2496 /*
2497 * C3.4.1 Add/subtract (immediate)
2498 *
2499 * 31 30 29 28 24 23 22 21 10 9 5 4 0
2500 * +--+--+--+-----------+-----+-------------+-----+-----+
2501 * |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd |
2502 * +--+--+--+-----------+-----+-------------+-----+-----+
2503 *
2504 * sf: 0 -> 32bit, 1 -> 64bit
2505 * op: 0 -> add , 1 -> sub
2506 * S: 1 -> set flags
2507 * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12
2508 */
2509 static void disas_add_sub_imm(DisasContext *s, uint32_t insn)
2510 {
2511 int rd = extract32(insn, 0, 5);
2512 int rn = extract32(insn, 5, 5);
2513 uint64_t imm = extract32(insn, 10, 12);
2514 int shift = extract32(insn, 22, 2);
2515 bool setflags = extract32(insn, 29, 1);
2516 bool sub_op = extract32(insn, 30, 1);
2517 bool is_64bit = extract32(insn, 31, 1);
2518
2519 TCGv_i64 tcg_rn = cpu_reg_sp(s, rn);
2520 TCGv_i64 tcg_rd = setflags ? cpu_reg(s, rd) : cpu_reg_sp(s, rd);
2521 TCGv_i64 tcg_result;
2522
2523 switch (shift) {
2524 case 0x0:
2525 break;
2526 case 0x1:
2527 imm <<= 12;
2528 break;
2529 default:
2530 unallocated_encoding(s);
2531 return;
2532 }
2533
2534 tcg_result = tcg_temp_new_i64();
2535 if (!setflags) {
2536 if (sub_op) {
2537 tcg_gen_subi_i64(tcg_result, tcg_rn, imm);
2538 } else {
2539 tcg_gen_addi_i64(tcg_result, tcg_rn, imm);
2540 }
2541 } else {
2542 TCGv_i64 tcg_imm = tcg_const_i64(imm);
2543 if (sub_op) {
2544 gen_sub_CC(is_64bit, tcg_result, tcg_rn, tcg_imm);
2545 } else {
2546 gen_add_CC(is_64bit, tcg_result, tcg_rn, tcg_imm);
2547 }
2548 tcg_temp_free_i64(tcg_imm);
2549 }
2550
2551 if (is_64bit) {
2552 tcg_gen_mov_i64(tcg_rd, tcg_result);
2553 } else {
2554 tcg_gen_ext32u_i64(tcg_rd, tcg_result);
2555 }
2556
2557 tcg_temp_free_i64(tcg_result);
2558 }
2559
2560 /* The input should be a value in the bottom e bits (with higher
2561 * bits zero); returns that value replicated into every element
2562 * of size e in a 64 bit integer.
2563 */
2564 static uint64_t bitfield_replicate(uint64_t mask, unsigned int e)
2565 {
2566 assert(e != 0);
2567 while (e < 64) {
2568 mask |= mask << e;
2569 e *= 2;
2570 }
2571 return mask;
2572 }
2573
2574 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
2575 static inline uint64_t bitmask64(unsigned int length)
2576 {
2577 assert(length > 0 && length <= 64);
2578 return ~0ULL >> (64 - length);
2579 }
2580
2581 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
2582 * only require the wmask. Returns false if the imms/immr/immn are a reserved
2583 * value (ie should cause a guest UNDEF exception), and true if they are
2584 * valid, in which case the decoded bit pattern is written to result.
2585 */
2586 static bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn,
2587 unsigned int imms, unsigned int immr)
2588 {
2589 uint64_t mask;
2590 unsigned e, levels, s, r;
2591 int len;
2592
2593 assert(immn < 2 && imms < 64 && immr < 64);
2594
2595 /* The bit patterns we create here are 64 bit patterns which
2596 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
2597 * 64 bits each. Each element contains the same value: a run
2598 * of between 1 and e-1 non-zero bits, rotated within the
2599 * element by between 0 and e-1 bits.
2600 *
2601 * The element size and run length are encoded into immn (1 bit)
2602 * and imms (6 bits) as follows:
2603 * 64 bit elements: immn = 1, imms = <length of run - 1>
2604 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
2605 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
2606 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
2607 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
2608 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
2609 * Notice that immn = 0, imms = 11111x is the only combination
2610 * not covered by one of the above options; this is reserved.
2611 * Further, <length of run - 1> all-ones is a reserved pattern.
2612 *
2613 * In all cases the rotation is by immr % e (and immr is 6 bits).
2614 */
2615
2616 /* First determine the element size */
2617 len = 31 - clz32((immn << 6) | (~imms & 0x3f));
2618 if (len < 1) {
2619 /* This is the immn == 0, imms == 0x11111x case */
2620 return false;
2621 }
2622 e = 1 << len;
2623
2624 levels = e - 1;
2625 s = imms & levels;
2626 r = immr & levels;
2627
2628 if (s == levels) {
2629 /* <length of run - 1> mustn't be all-ones. */
2630 return false;
2631 }
2632
2633 /* Create the value of one element: s+1 set bits rotated
2634 * by r within the element (which is e bits wide)...
2635 */
2636 mask = bitmask64(s + 1);
2637 mask = (mask >> r) | (mask << (e - r));
2638 /* ...then replicate the element over the whole 64 bit value */
2639 mask = bitfield_replicate(mask, e);
2640 *result = mask;
2641 return true;
2642 }
2643
2644 /* C3.4.4 Logical (immediate)
2645 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
2646 * +----+-----+-------------+---+------+------+------+------+
2647 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
2648 * +----+-----+-------------+---+------+------+------+------+
2649 */
2650 static void disas_logic_imm(DisasContext *s, uint32_t insn)
2651 {
2652 unsigned int sf, opc, is_n, immr, imms, rn, rd;
2653 TCGv_i64 tcg_rd, tcg_rn;
2654 uint64_t wmask;
2655 bool is_and = false;
2656
2657 sf = extract32(insn, 31, 1);
2658 opc = extract32(insn, 29, 2);
2659 is_n = extract32(insn, 22, 1);
2660 immr = extract32(insn, 16, 6);
2661 imms = extract32(insn, 10, 6);
2662 rn = extract32(insn, 5, 5);
2663 rd = extract32(insn, 0, 5);
2664
2665 if (!sf && is_n) {
2666 unallocated_encoding(s);
2667 return;
2668 }
2669
2670 if (opc == 0x3) { /* ANDS */
2671 tcg_rd = cpu_reg(s, rd);
2672 } else {
2673 tcg_rd = cpu_reg_sp(s, rd);
2674 }
2675 tcg_rn = cpu_reg(s, rn);
2676
2677 if (!logic_imm_decode_wmask(&wmask, is_n, imms, immr)) {
2678 /* some immediate field values are reserved */
2679 unallocated_encoding(s);
2680 return;
2681 }
2682
2683 if (!sf) {
2684 wmask &= 0xffffffff;
2685 }
2686
2687 switch (opc) {
2688 case 0x3: /* ANDS */
2689 case 0x0: /* AND */
2690 tcg_gen_andi_i64(tcg_rd, tcg_rn, wmask);
2691 is_and = true;
2692 break;
2693 case 0x1: /* ORR */
2694 tcg_gen_ori_i64(tcg_rd, tcg_rn, wmask);
2695 break;
2696 case 0x2: /* EOR */
2697 tcg_gen_xori_i64(tcg_rd, tcg_rn, wmask);
2698 break;
2699 default:
2700 assert(FALSE); /* must handle all above */
2701 break;
2702 }
2703
2704 if (!sf && !is_and) {
2705 /* zero extend final result; we know we can skip this for AND
2706 * since the immediate had the high 32 bits clear.
2707 */
2708 tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
2709 }
2710
2711 if (opc == 3) { /* ANDS */
2712 gen_logic_CC(sf, tcg_rd);
2713 }
2714 }
2715
2716 /*
2717 * C3.4.5 Move wide (immediate)
2718 *
2719 * 31 30 29 28 23 22 21 20 5 4 0
2720 * +--+-----+-------------+-----+----------------+------+
2721 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
2722 * +--+-----+-------------+-----+----------------+------+
2723 *
2724 * sf: 0 -> 32 bit, 1 -> 64 bit
2725 * opc: 00 -> N, 10 -> Z, 11 -> K
2726 * hw: shift/16 (0,16, and sf only 32, 48)
2727 */
2728 static void disas_movw_imm(DisasContext *s, uint32_t insn)
2729 {
2730 int rd = extract32(insn, 0, 5);
2731 uint64_t imm = extract32(insn, 5, 16);
2732 int sf = extract32(insn, 31, 1);
2733 int opc = extract32(insn, 29, 2);
2734 int pos = extract32(insn, 21, 2) << 4;
2735 TCGv_i64 tcg_rd = cpu_reg(s, rd);
2736 TCGv_i64 tcg_imm;
2737
2738 if (!sf && (pos >= 32)) {
2739 unallocated_encoding(s);
2740 return;
2741 }
2742
2743 switch (opc) {
2744 case 0: /* MOVN */
2745 case 2: /* MOVZ */
2746 imm <<= pos;
2747 if (opc == 0) {
2748 imm = ~imm;
2749 }
2750 if (!sf) {
2751 imm &= 0xffffffffu;
2752 }
2753 tcg_gen_movi_i64(tcg_rd, imm);
2754 break;
2755 case 3: /* MOVK */
2756 tcg_imm = tcg_const_i64(imm);
2757 tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_imm, pos, 16);
2758 tcg_temp_free_i64(tcg_imm);
2759 if (!sf) {
2760 tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
2761 }
2762 break;
2763 default:
2764 unallocated_encoding(s);
2765 break;
2766 }
2767 }
2768
2769 /* C3.4.2 Bitfield
2770 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
2771 * +----+-----+-------------+---+------+------+------+------+
2772 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
2773 * +----+-----+-------------+---+------+------+------+------+
2774 */
2775 static void disas_bitfield(DisasContext *s, uint32_t insn)
2776 {
2777 unsigned int sf, n, opc, ri, si, rn, rd, bitsize, pos, len;
2778 TCGv_i64 tcg_rd, tcg_tmp;
2779
2780 sf = extract32(insn, 31, 1);
2781 opc = extract32(insn, 29, 2);
2782 n = extract32(insn, 22, 1);
2783 ri = extract32(insn, 16, 6);
2784 si = extract32(insn, 10, 6);
2785 rn = extract32(insn, 5, 5);
2786 rd = extract32(insn, 0, 5);
2787 bitsize = sf ? 64 : 32;
2788
2789 if (sf != n || ri >= bitsize || si >= bitsize || opc > 2) {
2790 unallocated_encoding(s);
2791 return;
2792 }
2793
2794 tcg_rd = cpu_reg(s, rd);
2795 tcg_tmp = read_cpu_reg(s, rn, sf);
2796
2797 /* OPTME: probably worth recognizing common cases of ext{8,16,32}{u,s} */
2798
2799 if (opc != 1) { /* SBFM or UBFM */
2800 tcg_gen_movi_i64(tcg_rd, 0);
2801 }
2802
2803 /* do the bit move operation */
2804 if (si >= ri) {
2805 /* Wd<s-r:0> = Wn<s:r> */
2806 tcg_gen_shri_i64(tcg_tmp, tcg_tmp, ri);
2807 pos = 0;
2808 len = (si - ri) + 1;
2809 } else {
2810 /* Wd<32+s-r,32-r> = Wn<s:0> */
2811 pos = bitsize - ri;
2812 len = si + 1;
2813 }
2814
2815 tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, pos, len);
2816
2817 if (opc == 0) { /* SBFM - sign extend the destination field */
2818 tcg_gen_shli_i64(tcg_rd, tcg_rd, 64 - (pos + len));
2819 tcg_gen_sari_i64(tcg_rd, tcg_rd, 64 - (pos + len));
2820 }
2821
2822 if (!sf) { /* zero extend final result */
2823 tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
2824 }
2825 }
2826
2827 /* C3.4.3 Extract
2828 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
2829 * +----+------+-------------+---+----+------+--------+------+------+
2830 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
2831 * +----+------+-------------+---+----+------+--------+------+------+
2832 */
2833 static void disas_extract(DisasContext *s, uint32_t insn)
2834 {
2835 unsigned int sf, n, rm, imm, rn, rd, bitsize, op21, op0;
2836
2837 sf = extract32(insn, 31, 1);
2838 n = extract32(insn, 22, 1);
2839 rm = extract32(insn, 16, 5);
2840 imm = extract32(insn, 10, 6);
2841 rn = extract32(insn, 5, 5);
2842 rd = extract32(insn, 0, 5);
2843 op21 = extract32(insn, 29, 2);
2844 op0 = extract32(insn, 21, 1);
2845 bitsize = sf ? 64 : 32;
2846
2847 if (sf != n || op21 || op0 || imm >= bitsize) {
2848 unallocated_encoding(s);
2849 } else {
2850 TCGv_i64 tcg_rd, tcg_rm, tcg_rn;
2851
2852 tcg_rd = cpu_reg(s, rd);
2853
2854 if (imm) {
2855 /* OPTME: we can special case rm==rn as a rotate */
2856 tcg_rm = read_cpu_reg(s, rm, sf);
2857 tcg_rn = read_cpu_reg(s, rn, sf);
2858 tcg_gen_shri_i64(tcg_rm, tcg_rm, imm);
2859 tcg_gen_shli_i64(tcg_rn, tcg_rn, bitsize - imm);
2860 tcg_gen_or_i64(tcg_rd, tcg_rm, tcg_rn);
2861 if (!sf) {
2862 tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
2863 }
2864 } else {
2865 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
2866 * so an extract from bit 0 is a special case.
2867 */
2868 if (sf) {
2869 tcg_gen_mov_i64(tcg_rd, cpu_reg(s, rm));
2870 } else {
2871 tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rm));
2872 }
2873 }
2874
2875 }
2876 }
2877
2878 /* C3.4 Data processing - immediate */
2879 static void disas_data_proc_imm(DisasContext *s, uint32_t insn)
2880 {
2881 switch (extract32(insn, 23, 6)) {
2882 case 0x20: case 0x21: /* PC-rel. addressing */
2883 disas_pc_rel_adr(s, insn);
2884 break;
2885 case 0x22: case 0x23: /* Add/subtract (immediate) */
2886 disas_add_sub_imm(s, insn);
2887 break;
2888 case 0x24: /* Logical (immediate) */
2889 disas_logic_imm(s, insn);
2890 break;
2891 case 0x25: /* Move wide (immediate) */
2892 disas_movw_imm(s, insn);
2893 break;
2894 case 0x26: /* Bitfield */
2895 disas_bitfield(s, insn);
2896 break;
2897 case 0x27: /* Extract */
2898 disas_extract(s, insn);
2899 break;
2900 default:
2901 unallocated_encoding(s);
2902 break;
2903 }
2904 }
2905
2906 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
2907 * Note that it is the caller's responsibility to ensure that the
2908 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
2909 * mandated semantics for out of range shifts.
2910 */
2911 static void shift_reg(TCGv_i64 dst, TCGv_i64 src, int sf,
2912 enum a64_shift_type shift_type, TCGv_i64 shift_amount)
2913 {
2914 switch (shift_type) {
2915 case A64_SHIFT_TYPE_LSL:
2916 tcg_gen_shl_i64(dst, src, shift_amount);
2917 break;
2918 case A64_SHIFT_TYPE_LSR:
2919 tcg_gen_shr_i64(dst, src, shift_amount);
2920 break;
2921 case A64_SHIFT_TYPE_ASR:
2922 if (!sf) {
2923 tcg_gen_ext32s_i64(dst, src);
2924 }
2925 tcg_gen_sar_i64(dst, sf ? src : dst, shift_amount);
2926 break;
2927 case A64_SHIFT_TYPE_ROR:
2928 if (sf) {
2929 tcg_gen_rotr_i64(dst, src, shift_amount);
2930 } else {
2931 TCGv_i32 t0, t1;
2932 t0 = tcg_temp_new_i32();
2933 t1 = tcg_temp_new_i32();
2934 tcg_gen_trunc_i64_i32(t0, src);
2935 tcg_gen_trunc_i64_i32(t1, shift_amount);
2936 tcg_gen_rotr_i32(t0, t0, t1);
2937 tcg_gen_extu_i32_i64(dst, t0);
2938 tcg_temp_free_i32(t0);
2939 tcg_temp_free_i32(t1);
2940 }
2941 break;
2942 default:
2943 assert(FALSE); /* all shift types should be handled */
2944 break;
2945 }
2946
2947 if (!sf) { /* zero extend final result */
2948 tcg_gen_ext32u_i64(dst, dst);
2949 }
2950 }
2951
2952 /* Shift a TCGv src by immediate, put result in dst.
2953 * The shift amount must be in range (this should always be true as the
2954 * relevant instructions will UNDEF on bad shift immediates).
2955 */
2956 static void shift_reg_imm(TCGv_i64 dst, TCGv_i64 src, int sf,
2957 enum a64_shift_type shift_type, unsigned int shift_i)
2958 {
2959 assert(shift_i < (sf ? 64 : 32));
2960
2961 if (shift_i == 0) {
2962 tcg_gen_mov_i64(dst, src);
2963 } else {
2964 TCGv_i64 shift_const;
2965
2966 shift_const = tcg_const_i64(shift_i);
2967 shift_reg(dst, src, sf, shift_type, shift_const);
2968 tcg_temp_free_i64(shift_const);
2969 }
2970 }
2971
2972 /* C3.5.10 Logical (shifted register)
2973 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
2974 * +----+-----+-----------+-------+---+------+--------+------+------+
2975 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
2976 * +----+-----+-----------+-------+---+------+--------+------+------+
2977 */
2978 static void disas_logic_reg(DisasContext *s, uint32_t insn)
2979 {
2980 TCGv_i64 tcg_rd, tcg_rn, tcg_rm;
2981 unsigned int sf, opc, shift_type, invert, rm, shift_amount, rn, rd;
2982
2983 sf = extract32(insn, 31, 1);
2984 opc = extract32(insn, 29, 2);
2985 shift_type = extract32(insn, 22, 2);
2986 invert = extract32(insn, 21, 1);
2987 rm = extract32(insn, 16, 5);
2988 shift_amount = extract32(insn, 10, 6);
2989 rn = extract32(insn, 5, 5);
2990 rd = extract32(insn, 0, 5);
2991
2992 if (!sf && (shift_amount & (1 << 5))) {
2993 unallocated_encoding(s);
2994 return;
2995 }
2996
2997 tcg_rd = cpu_reg(s, rd);
2998
2999 if (opc == 1 && shift_amount == 0 && shift_type == 0 && rn == 31) {
3000 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
3001 * register-register MOV and MVN, so it is worth special casing.
3002 */
3003 tcg_rm = cpu_reg(s, rm);
3004 if (invert) {
3005 tcg_gen_not_i64(tcg_rd, tcg_rm);
3006 if (!sf) {
3007 tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
3008 }
3009 } else {
3010 if (sf) {
3011 tcg_gen_mov_i64(tcg_rd, tcg_rm);
3012 } else {
3013 tcg_gen_ext32u_i64(tcg_rd, tcg_rm);
3014 }
3015 }
3016 return;
3017 }
3018
3019 tcg_rm = read_cpu_reg(s, rm, sf);
3020
3021 if (shift_amount) {
3022 shift_reg_imm(tcg_rm, tcg_rm, sf, shift_type, shift_amount);
3023 }
3024
3025 tcg_rn = cpu_reg(s, rn);
3026
3027 switch (opc | (invert << 2)) {
3028 case 0: /* AND */
3029 case 3: /* ANDS */
3030 tcg_gen_and_i64(tcg_rd, tcg_rn, tcg_rm);
3031 break;
3032 case 1: /* ORR */
3033 tcg_gen_or_i64(tcg_rd, tcg_rn, tcg_rm);
3034 break;
3035 case 2: /* EOR */
3036 tcg_gen_xor_i64(tcg_rd, tcg_rn, tcg_rm);
3037 break;
3038 case 4: /* BIC */
3039 case 7: /* BICS */
3040 tcg_gen_andc_i64(tcg_rd, tcg_rn, tcg_rm);
3041 break;
3042 case 5: /* ORN */
3043 tcg_gen_orc_i64(tcg_rd, tcg_rn, tcg_rm);
3044 break;
3045 case 6: /* EON */
3046 tcg_gen_eqv_i64(tcg_rd, tcg_rn, tcg_rm);
3047 break;
3048 default:
3049 assert(FALSE);
3050 break;
3051 }
3052
3053 if (!sf) {
3054 tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
3055 }
3056
3057 if (opc == 3) {
3058 gen_logic_CC(sf, tcg_rd);
3059 }
3060 }
3061
3062 /*
3063 * C3.5.1 Add/subtract (extended register)
3064 *
3065 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
3066 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3067 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
3068 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3069 *
3070 * sf: 0 -> 32bit, 1 -> 64bit
3071 * op: 0 -> add , 1 -> sub
3072 * S: 1 -> set flags
3073 * opt: 00
3074 * option: extension type (see DecodeRegExtend)
3075 * imm3: optional shift to Rm
3076 *
3077 * Rd = Rn + LSL(extend(Rm), amount)
3078 */
3079 static void disas_add_sub_ext_reg(DisasContext *s, uint32_t insn)
3080 {
3081 int rd = extract32(insn, 0, 5);
3082 int rn = extract32(insn, 5, 5);
3083 int imm3 = extract32(insn, 10, 3);
3084 int option = extract32(insn, 13, 3);
3085 int rm = extract32(insn, 16, 5);
3086 bool setflags = extract32(insn, 29, 1);
3087 bool sub_op = extract32(insn, 30, 1);
3088 bool sf = extract32(insn, 31, 1);
3089
3090 TCGv_i64 tcg_rm, tcg_rn; /* temps */
3091 TCGv_i64 tcg_rd;
3092 TCGv_i64 tcg_result;
3093
3094 if (imm3 > 4) {
3095 unallocated_encoding(s);
3096 return;
3097 }
3098
3099 /* non-flag setting ops may use SP */
3100 if (!setflags) {
3101 tcg_rd = cpu_reg_sp(s, rd);
3102 } else {
3103 tcg_rd = cpu_reg(s, rd);
3104 }
3105 tcg_rn = read_cpu_reg_sp(s, rn, sf);
3106
3107 tcg_rm = read_cpu_reg(s, rm, sf);
3108 ext_and_shift_reg(tcg_rm, tcg_rm, option, imm3);
3109
3110 tcg_result = tcg_temp_new_i64();
3111
3112 if (!setflags) {
3113 if (sub_op) {
3114 tcg_gen_sub_i64(tcg_result, tcg_rn, tcg_rm);
3115 } else {
3116 tcg_gen_add_i64(tcg_result, tcg_rn, tcg_rm);
3117 }
3118 } else {
3119 if (sub_op) {
3120 gen_sub_CC(sf, tcg_result, tcg_rn, tcg_rm);
3121 } else {
3122 gen_add_CC(sf, tcg_result, tcg_rn, tcg_rm);
3123 }
3124 }
3125
3126 if (sf) {
3127 tcg_gen_mov_i64(tcg_rd, tcg_result);
3128 } else {
3129 tcg_gen_ext32u_i64(tcg_rd, tcg_result);
3130 }
3131
3132 tcg_temp_free_i64(tcg_result);
3133 }
3134
3135 /*
3136 * C3.5.2 Add/subtract (shifted register)
3137 *
3138 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
3139 * +--+--+--+-----------+-----+--+-------+---------+------+------+
3140 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
3141 * +--+--+--+-----------+-----+--+-------+---------+------+------+
3142 *
3143 * sf: 0 -> 32bit, 1 -> 64bit
3144 * op: 0 -> add , 1 -> sub
3145 * S: 1 -> set flags
3146 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
3147 * imm6: Shift amount to apply to Rm before the add/sub
3148 */
3149 static void disas_add_sub_reg(DisasContext *s, uint32_t insn)
3150 {
3151 int rd = extract32(insn, 0, 5);
3152 int rn = extract32(insn, 5, 5);
3153 int imm6 = extract32(insn, 10, 6);
3154 int rm = extract32(insn, 16, 5);
3155 int shift_type = extract32(insn, 22, 2);
3156 bool setflags = extract32(insn, 29, 1);
3157 bool sub_op = extract32(insn, 30, 1);
3158 bool sf = extract32(insn, 31, 1);
3159
3160 TCGv_i64 tcg_rd = cpu_reg(s, rd);
3161 TCGv_i64 tcg_rn, tcg_rm;
3162 TCGv_i64 tcg_result;
3163
3164 if ((shift_type == 3) || (!sf && (imm6 > 31))) {
3165 unallocated_encoding(s);
3166 return;
3167 }
3168
3169 tcg_rn = read_cpu_reg(s, rn, sf);
3170 tcg_rm = read_cpu_reg(s, rm, sf);
3171
3172 shift_reg_imm(tcg_rm, tcg_rm, sf, shift_type, imm6);
3173
3174 tcg_result = tcg_temp_new_i64();
3175
3176 if (!setflags) {
3177 if (sub_op) {
3178 tcg_gen_sub_i64(tcg_result, tcg_rn, tcg_rm);
3179 } else {
3180 tcg_gen_add_i64(tcg_result, tcg_rn, tcg_rm);
3181 }
3182 } else {
3183 if (sub_op) {
3184 gen_sub_CC(sf, tcg_result, tcg_rn, tcg_rm);
3185 } else {
3186 gen_add_CC(sf, tcg_result, tcg_rn, tcg_rm);
3187 }
3188 }
3189
3190 if (sf) {
3191 tcg_gen_mov_i64(tcg_rd, tcg_result);
3192 } else {
3193 tcg_gen_ext32u_i64(tcg_rd, tcg_result);
3194 }
3195
3196 tcg_temp_free_i64(tcg_result);
3197 }
3198
3199 /* C3.5.9 Data-processing (3 source)
3200
3201 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
3202 +--+------+-----------+------+------+----+------+------+------+
3203 |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
3204 +--+------+-----------+------+------+----+------+------+------+
3205
3206 */
3207 static void disas_data_proc_3src(DisasContext *s, uint32_t insn)
3208 {
3209 int rd = extract32(insn, 0, 5);
3210 int rn = extract32(insn, 5, 5);
3211 int ra = extract32(insn, 10, 5);
3212 int rm = extract32(insn, 16, 5);