target-arm: Fix A64 Neon MLS
[qemu.git] / target-arm / translate-a64.c
1 /*
2 * AArch64 translation
3 *
4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdarg.h>
20 #include <stdlib.h>
21 #include <stdio.h>
22 #include <string.h>
23 #include <inttypes.h>
24
25 #include "cpu.h"
26 #include "tcg-op.h"
27 #include "qemu/log.h"
28 #include "translate.h"
29 #include "qemu/host-utils.h"
30
31 #include "exec/gen-icount.h"
32
33 #include "helper.h"
34 #define GEN_HELPER 1
35 #include "helper.h"
36
37 static TCGv_i64 cpu_X[32];
38 static TCGv_i64 cpu_pc;
39 static TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF;
40
41 /* Load/store exclusive handling */
42 static TCGv_i64 cpu_exclusive_addr;
43 static TCGv_i64 cpu_exclusive_val;
44 static TCGv_i64 cpu_exclusive_high;
45 #ifdef CONFIG_USER_ONLY
46 static TCGv_i64 cpu_exclusive_test;
47 static TCGv_i32 cpu_exclusive_info;
48 #endif
49
50 static const char *regnames[] = {
51 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
52 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
53 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
54 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
55 };
56
57 enum a64_shift_type {
58 A64_SHIFT_TYPE_LSL = 0,
59 A64_SHIFT_TYPE_LSR = 1,
60 A64_SHIFT_TYPE_ASR = 2,
61 A64_SHIFT_TYPE_ROR = 3
62 };
63
64 /* Table based decoder typedefs - used when the relevant bits for decode
65 * are too awkwardly scattered across the instruction (eg SIMD).
66 */
67 typedef void AArch64DecodeFn(DisasContext *s, uint32_t insn);
68
69 typedef struct AArch64DecodeTable {
70 uint32_t pattern;
71 uint32_t mask;
72 AArch64DecodeFn *disas_fn;
73 } AArch64DecodeTable;
74
75 /* Function prototype for gen_ functions for calling Neon helpers */
76 typedef void NeonGenOneOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32);
77 typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32);
78 typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
79 typedef void NeonGenTwo64OpFn(TCGv_i64, TCGv_i64, TCGv_i64);
80 typedef void NeonGenTwo64OpEnvFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64);
81 typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64);
82 typedef void NeonGenNarrowEnvFn(TCGv_i32, TCGv_ptr, TCGv_i64);
83 typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32);
84 typedef void NeonGenTwoSingleOPFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr);
85 typedef void NeonGenTwoDoubleOPFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr);
86 typedef void NeonGenOneOpFn(TCGv_i64, TCGv_i64);
87
88 /* initialize TCG globals. */
89 void a64_translate_init(void)
90 {
91 int i;
92
93 cpu_pc = tcg_global_mem_new_i64(TCG_AREG0,
94 offsetof(CPUARMState, pc),
95 "pc");
96 for (i = 0; i < 32; i++) {
97 cpu_X[i] = tcg_global_mem_new_i64(TCG_AREG0,
98 offsetof(CPUARMState, xregs[i]),
99 regnames[i]);
100 }
101
102 cpu_NF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, NF), "NF");
103 cpu_ZF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, ZF), "ZF");
104 cpu_CF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, CF), "CF");
105 cpu_VF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, VF), "VF");
106
107 cpu_exclusive_addr = tcg_global_mem_new_i64(TCG_AREG0,
108 offsetof(CPUARMState, exclusive_addr), "exclusive_addr");
109 cpu_exclusive_val = tcg_global_mem_new_i64(TCG_AREG0,
110 offsetof(CPUARMState, exclusive_val), "exclusive_val");
111 cpu_exclusive_high = tcg_global_mem_new_i64(TCG_AREG0,
112 offsetof(CPUARMState, exclusive_high), "exclusive_high");
113 #ifdef CONFIG_USER_ONLY
114 cpu_exclusive_test = tcg_global_mem_new_i64(TCG_AREG0,
115 offsetof(CPUARMState, exclusive_test), "exclusive_test");
116 cpu_exclusive_info = tcg_global_mem_new_i32(TCG_AREG0,
117 offsetof(CPUARMState, exclusive_info), "exclusive_info");
118 #endif
119 }
120
121 void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
122 fprintf_function cpu_fprintf, int flags)
123 {
124 ARMCPU *cpu = ARM_CPU(cs);
125 CPUARMState *env = &cpu->env;
126 uint32_t psr = pstate_read(env);
127 int i;
128
129 cpu_fprintf(f, "PC=%016"PRIx64" SP=%016"PRIx64"\n",
130 env->pc, env->xregs[31]);
131 for (i = 0; i < 31; i++) {
132 cpu_fprintf(f, "X%02d=%016"PRIx64, i, env->xregs[i]);
133 if ((i % 4) == 3) {
134 cpu_fprintf(f, "\n");
135 } else {
136 cpu_fprintf(f, " ");
137 }
138 }
139 cpu_fprintf(f, "PSTATE=%08x (flags %c%c%c%c)\n",
140 psr,
141 psr & PSTATE_N ? 'N' : '-',
142 psr & PSTATE_Z ? 'Z' : '-',
143 psr & PSTATE_C ? 'C' : '-',
144 psr & PSTATE_V ? 'V' : '-');
145 cpu_fprintf(f, "\n");
146
147 if (flags & CPU_DUMP_FPU) {
148 int numvfpregs = 32;
149 for (i = 0; i < numvfpregs; i += 2) {
150 uint64_t vlo = float64_val(env->vfp.regs[i * 2]);
151 uint64_t vhi = float64_val(env->vfp.regs[(i * 2) + 1]);
152 cpu_fprintf(f, "q%02d=%016" PRIx64 ":%016" PRIx64 " ",
153 i, vhi, vlo);
154 vlo = float64_val(env->vfp.regs[(i + 1) * 2]);
155 vhi = float64_val(env->vfp.regs[((i + 1) * 2) + 1]);
156 cpu_fprintf(f, "q%02d=%016" PRIx64 ":%016" PRIx64 "\n",
157 i + 1, vhi, vlo);
158 }
159 cpu_fprintf(f, "FPCR: %08x FPSR: %08x\n",
160 vfp_get_fpcr(env), vfp_get_fpsr(env));
161 }
162 }
163
164 static int get_mem_index(DisasContext *s)
165 {
166 #ifdef CONFIG_USER_ONLY
167 return 1;
168 #else
169 return s->user;
170 #endif
171 }
172
173 void gen_a64_set_pc_im(uint64_t val)
174 {
175 tcg_gen_movi_i64(cpu_pc, val);
176 }
177
178 static void gen_exception(int excp)
179 {
180 TCGv_i32 tmp = tcg_temp_new_i32();
181 tcg_gen_movi_i32(tmp, excp);
182 gen_helper_exception(cpu_env, tmp);
183 tcg_temp_free_i32(tmp);
184 }
185
186 static void gen_exception_insn(DisasContext *s, int offset, int excp)
187 {
188 gen_a64_set_pc_im(s->pc - offset);
189 gen_exception(excp);
190 s->is_jmp = DISAS_EXC;
191 }
192
193 static inline bool use_goto_tb(DisasContext *s, int n, uint64_t dest)
194 {
195 /* No direct tb linking with singlestep or deterministic io */
196 if (s->singlestep_enabled || (s->tb->cflags & CF_LAST_IO)) {
197 return false;
198 }
199
200 /* Only link tbs from inside the same guest page */
201 if ((s->tb->pc & TARGET_PAGE_MASK) != (dest & TARGET_PAGE_MASK)) {
202 return false;
203 }
204
205 return true;
206 }
207
208 static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest)
209 {
210 TranslationBlock *tb;
211
212 tb = s->tb;
213 if (use_goto_tb(s, n, dest)) {
214 tcg_gen_goto_tb(n);
215 gen_a64_set_pc_im(dest);
216 tcg_gen_exit_tb((intptr_t)tb + n);
217 s->is_jmp = DISAS_TB_JUMP;
218 } else {
219 gen_a64_set_pc_im(dest);
220 if (s->singlestep_enabled) {
221 gen_exception(EXCP_DEBUG);
222 }
223 tcg_gen_exit_tb(0);
224 s->is_jmp = DISAS_JUMP;
225 }
226 }
227
228 static void unallocated_encoding(DisasContext *s)
229 {
230 gen_exception_insn(s, 4, EXCP_UDEF);
231 }
232
233 #define unsupported_encoding(s, insn) \
234 do { \
235 qemu_log_mask(LOG_UNIMP, \
236 "%s:%d: unsupported instruction encoding 0x%08x " \
237 "at pc=%016" PRIx64 "\n", \
238 __FILE__, __LINE__, insn, s->pc - 4); \
239 unallocated_encoding(s); \
240 } while (0);
241
242 static void init_tmp_a64_array(DisasContext *s)
243 {
244 #ifdef CONFIG_DEBUG_TCG
245 int i;
246 for (i = 0; i < ARRAY_SIZE(s->tmp_a64); i++) {
247 TCGV_UNUSED_I64(s->tmp_a64[i]);
248 }
249 #endif
250 s->tmp_a64_count = 0;
251 }
252
253 static void free_tmp_a64(DisasContext *s)
254 {
255 int i;
256 for (i = 0; i < s->tmp_a64_count; i++) {
257 tcg_temp_free_i64(s->tmp_a64[i]);
258 }
259 init_tmp_a64_array(s);
260 }
261
262 static TCGv_i64 new_tmp_a64(DisasContext *s)
263 {
264 assert(s->tmp_a64_count < TMP_A64_MAX);
265 return s->tmp_a64[s->tmp_a64_count++] = tcg_temp_new_i64();
266 }
267
268 static TCGv_i64 new_tmp_a64_zero(DisasContext *s)
269 {
270 TCGv_i64 t = new_tmp_a64(s);
271 tcg_gen_movi_i64(t, 0);
272 return t;
273 }
274
275 /*
276 * Register access functions
277 *
278 * These functions are used for directly accessing a register in where
279 * changes to the final register value are likely to be made. If you
280 * need to use a register for temporary calculation (e.g. index type
281 * operations) use the read_* form.
282 *
283 * B1.2.1 Register mappings
284 *
285 * In instruction register encoding 31 can refer to ZR (zero register) or
286 * the SP (stack pointer) depending on context. In QEMU's case we map SP
287 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
288 * This is the point of the _sp forms.
289 */
290 static TCGv_i64 cpu_reg(DisasContext *s, int reg)
291 {
292 if (reg == 31) {
293 return new_tmp_a64_zero(s);
294 } else {
295 return cpu_X[reg];
296 }
297 }
298
299 /* register access for when 31 == SP */
300 static TCGv_i64 cpu_reg_sp(DisasContext *s, int reg)
301 {
302 return cpu_X[reg];
303 }
304
305 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
306 * representing the register contents. This TCGv is an auto-freed
307 * temporary so it need not be explicitly freed, and may be modified.
308 */
309 static TCGv_i64 read_cpu_reg(DisasContext *s, int reg, int sf)
310 {
311 TCGv_i64 v = new_tmp_a64(s);
312 if (reg != 31) {
313 if (sf) {
314 tcg_gen_mov_i64(v, cpu_X[reg]);
315 } else {
316 tcg_gen_ext32u_i64(v, cpu_X[reg]);
317 }
318 } else {
319 tcg_gen_movi_i64(v, 0);
320 }
321 return v;
322 }
323
324 static TCGv_i64 read_cpu_reg_sp(DisasContext *s, int reg, int sf)
325 {
326 TCGv_i64 v = new_tmp_a64(s);
327 if (sf) {
328 tcg_gen_mov_i64(v, cpu_X[reg]);
329 } else {
330 tcg_gen_ext32u_i64(v, cpu_X[reg]);
331 }
332 return v;
333 }
334
335 /* Return the offset into CPUARMState of an element of specified
336 * size, 'element' places in from the least significant end of
337 * the FP/vector register Qn.
338 */
339 static inline int vec_reg_offset(int regno, int element, TCGMemOp size)
340 {
341 int offs = offsetof(CPUARMState, vfp.regs[regno * 2]);
342 #ifdef HOST_WORDS_BIGENDIAN
343 /* This is complicated slightly because vfp.regs[2n] is
344 * still the low half and vfp.regs[2n+1] the high half
345 * of the 128 bit vector, even on big endian systems.
346 * Calculate the offset assuming a fully bigendian 128 bits,
347 * then XOR to account for the order of the two 64 bit halves.
348 */
349 offs += (16 - ((element + 1) * (1 << size)));
350 offs ^= 8;
351 #else
352 offs += element * (1 << size);
353 #endif
354 return offs;
355 }
356
357 /* Return the offset into CPUARMState of a slice (from
358 * the least significant end) of FP register Qn (ie
359 * Dn, Sn, Hn or Bn).
360 * (Note that this is not the same mapping as for A32; see cpu.h)
361 */
362 static inline int fp_reg_offset(int regno, TCGMemOp size)
363 {
364 int offs = offsetof(CPUARMState, vfp.regs[regno * 2]);
365 #ifdef HOST_WORDS_BIGENDIAN
366 offs += (8 - (1 << size));
367 #endif
368 return offs;
369 }
370
371 /* Offset of the high half of the 128 bit vector Qn */
372 static inline int fp_reg_hi_offset(int regno)
373 {
374 return offsetof(CPUARMState, vfp.regs[regno * 2 + 1]);
375 }
376
377 /* Convenience accessors for reading and writing single and double
378 * FP registers. Writing clears the upper parts of the associated
379 * 128 bit vector register, as required by the architecture.
380 * Note that unlike the GP register accessors, the values returned
381 * by the read functions must be manually freed.
382 */
383 static TCGv_i64 read_fp_dreg(DisasContext *s, int reg)
384 {
385 TCGv_i64 v = tcg_temp_new_i64();
386
387 tcg_gen_ld_i64(v, cpu_env, fp_reg_offset(reg, MO_64));
388 return v;
389 }
390
391 static TCGv_i32 read_fp_sreg(DisasContext *s, int reg)
392 {
393 TCGv_i32 v = tcg_temp_new_i32();
394
395 tcg_gen_ld_i32(v, cpu_env, fp_reg_offset(reg, MO_32));
396 return v;
397 }
398
399 static void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v)
400 {
401 TCGv_i64 tcg_zero = tcg_const_i64(0);
402
403 tcg_gen_st_i64(v, cpu_env, fp_reg_offset(reg, MO_64));
404 tcg_gen_st_i64(tcg_zero, cpu_env, fp_reg_hi_offset(reg));
405 tcg_temp_free_i64(tcg_zero);
406 }
407
408 static void write_fp_sreg(DisasContext *s, int reg, TCGv_i32 v)
409 {
410 TCGv_i64 tmp = tcg_temp_new_i64();
411
412 tcg_gen_extu_i32_i64(tmp, v);
413 write_fp_dreg(s, reg, tmp);
414 tcg_temp_free_i64(tmp);
415 }
416
417 static TCGv_ptr get_fpstatus_ptr(void)
418 {
419 TCGv_ptr statusptr = tcg_temp_new_ptr();
420 int offset;
421
422 /* In A64 all instructions (both FP and Neon) use the FPCR;
423 * there is no equivalent of the A32 Neon "standard FPSCR value"
424 * and all operations use vfp.fp_status.
425 */
426 offset = offsetof(CPUARMState, vfp.fp_status);
427 tcg_gen_addi_ptr(statusptr, cpu_env, offset);
428 return statusptr;
429 }
430
431 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
432 * than the 32 bit equivalent.
433 */
434 static inline void gen_set_NZ64(TCGv_i64 result)
435 {
436 TCGv_i64 flag = tcg_temp_new_i64();
437
438 tcg_gen_setcondi_i64(TCG_COND_NE, flag, result, 0);
439 tcg_gen_trunc_i64_i32(cpu_ZF, flag);
440 tcg_gen_shri_i64(flag, result, 32);
441 tcg_gen_trunc_i64_i32(cpu_NF, flag);
442 tcg_temp_free_i64(flag);
443 }
444
445 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
446 static inline void gen_logic_CC(int sf, TCGv_i64 result)
447 {
448 if (sf) {
449 gen_set_NZ64(result);
450 } else {
451 tcg_gen_trunc_i64_i32(cpu_ZF, result);
452 tcg_gen_trunc_i64_i32(cpu_NF, result);
453 }
454 tcg_gen_movi_i32(cpu_CF, 0);
455 tcg_gen_movi_i32(cpu_VF, 0);
456 }
457
458 /* dest = T0 + T1; compute C, N, V and Z flags */
459 static void gen_add_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1)
460 {
461 if (sf) {
462 TCGv_i64 result, flag, tmp;
463 result = tcg_temp_new_i64();
464 flag = tcg_temp_new_i64();
465 tmp = tcg_temp_new_i64();
466
467 tcg_gen_movi_i64(tmp, 0);
468 tcg_gen_add2_i64(result, flag, t0, tmp, t1, tmp);
469
470 tcg_gen_trunc_i64_i32(cpu_CF, flag);
471
472 gen_set_NZ64(result);
473
474 tcg_gen_xor_i64(flag, result, t0);
475 tcg_gen_xor_i64(tmp, t0, t1);
476 tcg_gen_andc_i64(flag, flag, tmp);
477 tcg_temp_free_i64(tmp);
478 tcg_gen_shri_i64(flag, flag, 32);
479 tcg_gen_trunc_i64_i32(cpu_VF, flag);
480
481 tcg_gen_mov_i64(dest, result);
482 tcg_temp_free_i64(result);
483 tcg_temp_free_i64(flag);
484 } else {
485 /* 32 bit arithmetic */
486 TCGv_i32 t0_32 = tcg_temp_new_i32();
487 TCGv_i32 t1_32 = tcg_temp_new_i32();
488 TCGv_i32 tmp = tcg_temp_new_i32();
489
490 tcg_gen_movi_i32(tmp, 0);
491 tcg_gen_trunc_i64_i32(t0_32, t0);
492 tcg_gen_trunc_i64_i32(t1_32, t1);
493 tcg_gen_add2_i32(cpu_NF, cpu_CF, t0_32, tmp, t1_32, tmp);
494 tcg_gen_mov_i32(cpu_ZF, cpu_NF);
495 tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32);
496 tcg_gen_xor_i32(tmp, t0_32, t1_32);
497 tcg_gen_andc_i32(cpu_VF, cpu_VF, tmp);
498 tcg_gen_extu_i32_i64(dest, cpu_NF);
499
500 tcg_temp_free_i32(tmp);
501 tcg_temp_free_i32(t0_32);
502 tcg_temp_free_i32(t1_32);
503 }
504 }
505
506 /* dest = T0 - T1; compute C, N, V and Z flags */
507 static void gen_sub_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1)
508 {
509 if (sf) {
510 /* 64 bit arithmetic */
511 TCGv_i64 result, flag, tmp;
512
513 result = tcg_temp_new_i64();
514 flag = tcg_temp_new_i64();
515 tcg_gen_sub_i64(result, t0, t1);
516
517 gen_set_NZ64(result);
518
519 tcg_gen_setcond_i64(TCG_COND_GEU, flag, t0, t1);
520 tcg_gen_trunc_i64_i32(cpu_CF, flag);
521
522 tcg_gen_xor_i64(flag, result, t0);
523 tmp = tcg_temp_new_i64();
524 tcg_gen_xor_i64(tmp, t0, t1);
525 tcg_gen_and_i64(flag, flag, tmp);
526 tcg_temp_free_i64(tmp);
527 tcg_gen_shri_i64(flag, flag, 32);
528 tcg_gen_trunc_i64_i32(cpu_VF, flag);
529 tcg_gen_mov_i64(dest, result);
530 tcg_temp_free_i64(flag);
531 tcg_temp_free_i64(result);
532 } else {
533 /* 32 bit arithmetic */
534 TCGv_i32 t0_32 = tcg_temp_new_i32();
535 TCGv_i32 t1_32 = tcg_temp_new_i32();
536 TCGv_i32 tmp;
537
538 tcg_gen_trunc_i64_i32(t0_32, t0);
539 tcg_gen_trunc_i64_i32(t1_32, t1);
540 tcg_gen_sub_i32(cpu_NF, t0_32, t1_32);
541 tcg_gen_mov_i32(cpu_ZF, cpu_NF);
542 tcg_gen_setcond_i32(TCG_COND_GEU, cpu_CF, t0_32, t1_32);
543 tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32);
544 tmp = tcg_temp_new_i32();
545 tcg_gen_xor_i32(tmp, t0_32, t1_32);
546 tcg_temp_free_i32(t0_32);
547 tcg_temp_free_i32(t1_32);
548 tcg_gen_and_i32(cpu_VF, cpu_VF, tmp);
549 tcg_temp_free_i32(tmp);
550 tcg_gen_extu_i32_i64(dest, cpu_NF);
551 }
552 }
553
554 /* dest = T0 + T1 + CF; do not compute flags. */
555 static void gen_adc(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1)
556 {
557 TCGv_i64 flag = tcg_temp_new_i64();
558 tcg_gen_extu_i32_i64(flag, cpu_CF);
559 tcg_gen_add_i64(dest, t0, t1);
560 tcg_gen_add_i64(dest, dest, flag);
561 tcg_temp_free_i64(flag);
562
563 if (!sf) {
564 tcg_gen_ext32u_i64(dest, dest);
565 }
566 }
567
568 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
569 static void gen_adc_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1)
570 {
571 if (sf) {
572 TCGv_i64 result, cf_64, vf_64, tmp;
573 result = tcg_temp_new_i64();
574 cf_64 = tcg_temp_new_i64();
575 vf_64 = tcg_temp_new_i64();
576 tmp = tcg_const_i64(0);
577
578 tcg_gen_extu_i32_i64(cf_64, cpu_CF);
579 tcg_gen_add2_i64(result, cf_64, t0, tmp, cf_64, tmp);
580 tcg_gen_add2_i64(result, cf_64, result, cf_64, t1, tmp);
581 tcg_gen_trunc_i64_i32(cpu_CF, cf_64);
582 gen_set_NZ64(result);
583
584 tcg_gen_xor_i64(vf_64, result, t0);
585 tcg_gen_xor_i64(tmp, t0, t1);
586 tcg_gen_andc_i64(vf_64, vf_64, tmp);
587 tcg_gen_shri_i64(vf_64, vf_64, 32);
588 tcg_gen_trunc_i64_i32(cpu_VF, vf_64);
589
590 tcg_gen_mov_i64(dest, result);
591
592 tcg_temp_free_i64(tmp);
593 tcg_temp_free_i64(vf_64);
594 tcg_temp_free_i64(cf_64);
595 tcg_temp_free_i64(result);
596 } else {
597 TCGv_i32 t0_32, t1_32, tmp;
598 t0_32 = tcg_temp_new_i32();
599 t1_32 = tcg_temp_new_i32();
600 tmp = tcg_const_i32(0);
601
602 tcg_gen_trunc_i64_i32(t0_32, t0);
603 tcg_gen_trunc_i64_i32(t1_32, t1);
604 tcg_gen_add2_i32(cpu_NF, cpu_CF, t0_32, tmp, cpu_CF, tmp);
605 tcg_gen_add2_i32(cpu_NF, cpu_CF, cpu_NF, cpu_CF, t1_32, tmp);
606
607 tcg_gen_mov_i32(cpu_ZF, cpu_NF);
608 tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32);
609 tcg_gen_xor_i32(tmp, t0_32, t1_32);
610 tcg_gen_andc_i32(cpu_VF, cpu_VF, tmp);
611 tcg_gen_extu_i32_i64(dest, cpu_NF);
612
613 tcg_temp_free_i32(tmp);
614 tcg_temp_free_i32(t1_32);
615 tcg_temp_free_i32(t0_32);
616 }
617 }
618
619 /*
620 * Load/Store generators
621 */
622
623 /*
624 * Store from GPR register to memory.
625 */
626 static void do_gpr_st_memidx(DisasContext *s, TCGv_i64 source,
627 TCGv_i64 tcg_addr, int size, int memidx)
628 {
629 g_assert(size <= 3);
630 tcg_gen_qemu_st_i64(source, tcg_addr, memidx, MO_TE + size);
631 }
632
633 static void do_gpr_st(DisasContext *s, TCGv_i64 source,
634 TCGv_i64 tcg_addr, int size)
635 {
636 do_gpr_st_memidx(s, source, tcg_addr, size, get_mem_index(s));
637 }
638
639 /*
640 * Load from memory to GPR register
641 */
642 static void do_gpr_ld_memidx(DisasContext *s, TCGv_i64 dest, TCGv_i64 tcg_addr,
643 int size, bool is_signed, bool extend, int memidx)
644 {
645 TCGMemOp memop = MO_TE + size;
646
647 g_assert(size <= 3);
648
649 if (is_signed) {
650 memop += MO_SIGN;
651 }
652
653 tcg_gen_qemu_ld_i64(dest, tcg_addr, memidx, memop);
654
655 if (extend && is_signed) {
656 g_assert(size < 3);
657 tcg_gen_ext32u_i64(dest, dest);
658 }
659 }
660
661 static void do_gpr_ld(DisasContext *s, TCGv_i64 dest, TCGv_i64 tcg_addr,
662 int size, bool is_signed, bool extend)
663 {
664 do_gpr_ld_memidx(s, dest, tcg_addr, size, is_signed, extend,
665 get_mem_index(s));
666 }
667
668 /*
669 * Store from FP register to memory
670 */
671 static void do_fp_st(DisasContext *s, int srcidx, TCGv_i64 tcg_addr, int size)
672 {
673 /* This writes the bottom N bits of a 128 bit wide vector to memory */
674 TCGv_i64 tmp = tcg_temp_new_i64();
675 tcg_gen_ld_i64(tmp, cpu_env, fp_reg_offset(srcidx, MO_64));
676 if (size < 4) {
677 tcg_gen_qemu_st_i64(tmp, tcg_addr, get_mem_index(s), MO_TE + size);
678 } else {
679 TCGv_i64 tcg_hiaddr = tcg_temp_new_i64();
680 tcg_gen_qemu_st_i64(tmp, tcg_addr, get_mem_index(s), MO_TEQ);
681 tcg_gen_qemu_st64(tmp, tcg_addr, get_mem_index(s));
682 tcg_gen_ld_i64(tmp, cpu_env, fp_reg_hi_offset(srcidx));
683 tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8);
684 tcg_gen_qemu_st_i64(tmp, tcg_hiaddr, get_mem_index(s), MO_TEQ);
685 tcg_temp_free_i64(tcg_hiaddr);
686 }
687
688 tcg_temp_free_i64(tmp);
689 }
690
691 /*
692 * Load from memory to FP register
693 */
694 static void do_fp_ld(DisasContext *s, int destidx, TCGv_i64 tcg_addr, int size)
695 {
696 /* This always zero-extends and writes to a full 128 bit wide vector */
697 TCGv_i64 tmplo = tcg_temp_new_i64();
698 TCGv_i64 tmphi;
699
700 if (size < 4) {
701 TCGMemOp memop = MO_TE + size;
702 tmphi = tcg_const_i64(0);
703 tcg_gen_qemu_ld_i64(tmplo, tcg_addr, get_mem_index(s), memop);
704 } else {
705 TCGv_i64 tcg_hiaddr;
706 tmphi = tcg_temp_new_i64();
707 tcg_hiaddr = tcg_temp_new_i64();
708
709 tcg_gen_qemu_ld_i64(tmplo, tcg_addr, get_mem_index(s), MO_TEQ);
710 tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8);
711 tcg_gen_qemu_ld_i64(tmphi, tcg_hiaddr, get_mem_index(s), MO_TEQ);
712 tcg_temp_free_i64(tcg_hiaddr);
713 }
714
715 tcg_gen_st_i64(tmplo, cpu_env, fp_reg_offset(destidx, MO_64));
716 tcg_gen_st_i64(tmphi, cpu_env, fp_reg_hi_offset(destidx));
717
718 tcg_temp_free_i64(tmplo);
719 tcg_temp_free_i64(tmphi);
720 }
721
722 /*
723 * Vector load/store helpers.
724 *
725 * The principal difference between this and a FP load is that we don't
726 * zero extend as we are filling a partial chunk of the vector register.
727 * These functions don't support 128 bit loads/stores, which would be
728 * normal load/store operations.
729 *
730 * The _i32 versions are useful when operating on 32 bit quantities
731 * (eg for floating point single or using Neon helper functions).
732 */
733
734 /* Get value of an element within a vector register */
735 static void read_vec_element(DisasContext *s, TCGv_i64 tcg_dest, int srcidx,
736 int element, TCGMemOp memop)
737 {
738 int vect_off = vec_reg_offset(srcidx, element, memop & MO_SIZE);
739 switch (memop) {
740 case MO_8:
741 tcg_gen_ld8u_i64(tcg_dest, cpu_env, vect_off);
742 break;
743 case MO_16:
744 tcg_gen_ld16u_i64(tcg_dest, cpu_env, vect_off);
745 break;
746 case MO_32:
747 tcg_gen_ld32u_i64(tcg_dest, cpu_env, vect_off);
748 break;
749 case MO_8|MO_SIGN:
750 tcg_gen_ld8s_i64(tcg_dest, cpu_env, vect_off);
751 break;
752 case MO_16|MO_SIGN:
753 tcg_gen_ld16s_i64(tcg_dest, cpu_env, vect_off);
754 break;
755 case MO_32|MO_SIGN:
756 tcg_gen_ld32s_i64(tcg_dest, cpu_env, vect_off);
757 break;
758 case MO_64:
759 case MO_64|MO_SIGN:
760 tcg_gen_ld_i64(tcg_dest, cpu_env, vect_off);
761 break;
762 default:
763 g_assert_not_reached();
764 }
765 }
766
767 static void read_vec_element_i32(DisasContext *s, TCGv_i32 tcg_dest, int srcidx,
768 int element, TCGMemOp memop)
769 {
770 int vect_off = vec_reg_offset(srcidx, element, memop & MO_SIZE);
771 switch (memop) {
772 case MO_8:
773 tcg_gen_ld8u_i32(tcg_dest, cpu_env, vect_off);
774 break;
775 case MO_16:
776 tcg_gen_ld16u_i32(tcg_dest, cpu_env, vect_off);
777 break;
778 case MO_8|MO_SIGN:
779 tcg_gen_ld8s_i32(tcg_dest, cpu_env, vect_off);
780 break;
781 case MO_16|MO_SIGN:
782 tcg_gen_ld16s_i32(tcg_dest, cpu_env, vect_off);
783 break;
784 case MO_32:
785 case MO_32|MO_SIGN:
786 tcg_gen_ld_i32(tcg_dest, cpu_env, vect_off);
787 break;
788 default:
789 g_assert_not_reached();
790 }
791 }
792
793 /* Set value of an element within a vector register */
794 static void write_vec_element(DisasContext *s, TCGv_i64 tcg_src, int destidx,
795 int element, TCGMemOp memop)
796 {
797 int vect_off = vec_reg_offset(destidx, element, memop & MO_SIZE);
798 switch (memop) {
799 case MO_8:
800 tcg_gen_st8_i64(tcg_src, cpu_env, vect_off);
801 break;
802 case MO_16:
803 tcg_gen_st16_i64(tcg_src, cpu_env, vect_off);
804 break;
805 case MO_32:
806 tcg_gen_st32_i64(tcg_src, cpu_env, vect_off);
807 break;
808 case MO_64:
809 tcg_gen_st_i64(tcg_src, cpu_env, vect_off);
810 break;
811 default:
812 g_assert_not_reached();
813 }
814 }
815
816 static void write_vec_element_i32(DisasContext *s, TCGv_i32 tcg_src,
817 int destidx, int element, TCGMemOp memop)
818 {
819 int vect_off = vec_reg_offset(destidx, element, memop & MO_SIZE);
820 switch (memop) {
821 case MO_8:
822 tcg_gen_st8_i32(tcg_src, cpu_env, vect_off);
823 break;
824 case MO_16:
825 tcg_gen_st16_i32(tcg_src, cpu_env, vect_off);
826 break;
827 case MO_32:
828 tcg_gen_st_i32(tcg_src, cpu_env, vect_off);
829 break;
830 default:
831 g_assert_not_reached();
832 }
833 }
834
835 /* Clear the high 64 bits of a 128 bit vector (in general non-quad
836 * vector ops all need to do this).
837 */
838 static void clear_vec_high(DisasContext *s, int rd)
839 {
840 TCGv_i64 tcg_zero = tcg_const_i64(0);
841
842 write_vec_element(s, tcg_zero, rd, 1, MO_64);
843 tcg_temp_free_i64(tcg_zero);
844 }
845
846 /* Store from vector register to memory */
847 static void do_vec_st(DisasContext *s, int srcidx, int element,
848 TCGv_i64 tcg_addr, int size)
849 {
850 TCGMemOp memop = MO_TE + size;
851 TCGv_i64 tcg_tmp = tcg_temp_new_i64();
852
853 read_vec_element(s, tcg_tmp, srcidx, element, size);
854 tcg_gen_qemu_st_i64(tcg_tmp, tcg_addr, get_mem_index(s), memop);
855
856 tcg_temp_free_i64(tcg_tmp);
857 }
858
859 /* Load from memory to vector register */
860 static void do_vec_ld(DisasContext *s, int destidx, int element,
861 TCGv_i64 tcg_addr, int size)
862 {
863 TCGMemOp memop = MO_TE + size;
864 TCGv_i64 tcg_tmp = tcg_temp_new_i64();
865
866 tcg_gen_qemu_ld_i64(tcg_tmp, tcg_addr, get_mem_index(s), memop);
867 write_vec_element(s, tcg_tmp, destidx, element, size);
868
869 tcg_temp_free_i64(tcg_tmp);
870 }
871
872 /*
873 * This utility function is for doing register extension with an
874 * optional shift. You will likely want to pass a temporary for the
875 * destination register. See DecodeRegExtend() in the ARM ARM.
876 */
877 static void ext_and_shift_reg(TCGv_i64 tcg_out, TCGv_i64 tcg_in,
878 int option, unsigned int shift)
879 {
880 int extsize = extract32(option, 0, 2);
881 bool is_signed = extract32(option, 2, 1);
882
883 if (is_signed) {
884 switch (extsize) {
885 case 0:
886 tcg_gen_ext8s_i64(tcg_out, tcg_in);
887 break;
888 case 1:
889 tcg_gen_ext16s_i64(tcg_out, tcg_in);
890 break;
891 case 2:
892 tcg_gen_ext32s_i64(tcg_out, tcg_in);
893 break;
894 case 3:
895 tcg_gen_mov_i64(tcg_out, tcg_in);
896 break;
897 }
898 } else {
899 switch (extsize) {
900 case 0:
901 tcg_gen_ext8u_i64(tcg_out, tcg_in);
902 break;
903 case 1:
904 tcg_gen_ext16u_i64(tcg_out, tcg_in);
905 break;
906 case 2:
907 tcg_gen_ext32u_i64(tcg_out, tcg_in);
908 break;
909 case 3:
910 tcg_gen_mov_i64(tcg_out, tcg_in);
911 break;
912 }
913 }
914
915 if (shift) {
916 tcg_gen_shli_i64(tcg_out, tcg_out, shift);
917 }
918 }
919
920 static inline void gen_check_sp_alignment(DisasContext *s)
921 {
922 /* The AArch64 architecture mandates that (if enabled via PSTATE
923 * or SCTLR bits) there is a check that SP is 16-aligned on every
924 * SP-relative load or store (with an exception generated if it is not).
925 * In line with general QEMU practice regarding misaligned accesses,
926 * we omit these checks for the sake of guest program performance.
927 * This function is provided as a hook so we can more easily add these
928 * checks in future (possibly as a "favour catching guest program bugs
929 * over speed" user selectable option).
930 */
931 }
932
933 /*
934 * This provides a simple table based table lookup decoder. It is
935 * intended to be used when the relevant bits for decode are too
936 * awkwardly placed and switch/if based logic would be confusing and
937 * deeply nested. Since it's a linear search through the table, tables
938 * should be kept small.
939 *
940 * It returns the first handler where insn & mask == pattern, or
941 * NULL if there is no match.
942 * The table is terminated by an empty mask (i.e. 0)
943 */
944 static inline AArch64DecodeFn *lookup_disas_fn(const AArch64DecodeTable *table,
945 uint32_t insn)
946 {
947 const AArch64DecodeTable *tptr = table;
948
949 while (tptr->mask) {
950 if ((insn & tptr->mask) == tptr->pattern) {
951 return tptr->disas_fn;
952 }
953 tptr++;
954 }
955 return NULL;
956 }
957
958 /*
959 * the instruction disassembly implemented here matches
960 * the instruction encoding classifications in chapter 3 (C3)
961 * of the ARM Architecture Reference Manual (DDI0487A_a)
962 */
963
964 /* C3.2.7 Unconditional branch (immediate)
965 * 31 30 26 25 0
966 * +----+-----------+-------------------------------------+
967 * | op | 0 0 1 0 1 | imm26 |
968 * +----+-----------+-------------------------------------+
969 */
970 static void disas_uncond_b_imm(DisasContext *s, uint32_t insn)
971 {
972 uint64_t addr = s->pc + sextract32(insn, 0, 26) * 4 - 4;
973
974 if (insn & (1 << 31)) {
975 /* C5.6.26 BL Branch with link */
976 tcg_gen_movi_i64(cpu_reg(s, 30), s->pc);
977 }
978
979 /* C5.6.20 B Branch / C5.6.26 BL Branch with link */
980 gen_goto_tb(s, 0, addr);
981 }
982
983 /* C3.2.1 Compare & branch (immediate)
984 * 31 30 25 24 23 5 4 0
985 * +----+-------------+----+---------------------+--------+
986 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
987 * +----+-------------+----+---------------------+--------+
988 */
989 static void disas_comp_b_imm(DisasContext *s, uint32_t insn)
990 {
991 unsigned int sf, op, rt;
992 uint64_t addr;
993 int label_match;
994 TCGv_i64 tcg_cmp;
995
996 sf = extract32(insn, 31, 1);
997 op = extract32(insn, 24, 1); /* 0: CBZ; 1: CBNZ */
998 rt = extract32(insn, 0, 5);
999 addr = s->pc + sextract32(insn, 5, 19) * 4 - 4;
1000
1001 tcg_cmp = read_cpu_reg(s, rt, sf);
1002 label_match = gen_new_label();
1003
1004 tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ,
1005 tcg_cmp, 0, label_match);
1006
1007 gen_goto_tb(s, 0, s->pc);
1008 gen_set_label(label_match);
1009 gen_goto_tb(s, 1, addr);
1010 }
1011
1012 /* C3.2.5 Test & branch (immediate)
1013 * 31 30 25 24 23 19 18 5 4 0
1014 * +----+-------------+----+-------+-------------+------+
1015 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
1016 * +----+-------------+----+-------+-------------+------+
1017 */
1018 static void disas_test_b_imm(DisasContext *s, uint32_t insn)
1019 {
1020 unsigned int bit_pos, op, rt;
1021 uint64_t addr;
1022 int label_match;
1023 TCGv_i64 tcg_cmp;
1024
1025 bit_pos = (extract32(insn, 31, 1) << 5) | extract32(insn, 19, 5);
1026 op = extract32(insn, 24, 1); /* 0: TBZ; 1: TBNZ */
1027 addr = s->pc + sextract32(insn, 5, 14) * 4 - 4;
1028 rt = extract32(insn, 0, 5);
1029
1030 tcg_cmp = tcg_temp_new_i64();
1031 tcg_gen_andi_i64(tcg_cmp, cpu_reg(s, rt), (1ULL << bit_pos));
1032 label_match = gen_new_label();
1033 tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ,
1034 tcg_cmp, 0, label_match);
1035 tcg_temp_free_i64(tcg_cmp);
1036 gen_goto_tb(s, 0, s->pc);
1037 gen_set_label(label_match);
1038 gen_goto_tb(s, 1, addr);
1039 }
1040
1041 /* C3.2.2 / C5.6.19 Conditional branch (immediate)
1042 * 31 25 24 23 5 4 3 0
1043 * +---------------+----+---------------------+----+------+
1044 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
1045 * +---------------+----+---------------------+----+------+
1046 */
1047 static void disas_cond_b_imm(DisasContext *s, uint32_t insn)
1048 {
1049 unsigned int cond;
1050 uint64_t addr;
1051
1052 if ((insn & (1 << 4)) || (insn & (1 << 24))) {
1053 unallocated_encoding(s);
1054 return;
1055 }
1056 addr = s->pc + sextract32(insn, 5, 19) * 4 - 4;
1057 cond = extract32(insn, 0, 4);
1058
1059 if (cond < 0x0e) {
1060 /* genuinely conditional branches */
1061 int label_match = gen_new_label();
1062 arm_gen_test_cc(cond, label_match);
1063 gen_goto_tb(s, 0, s->pc);
1064 gen_set_label(label_match);
1065 gen_goto_tb(s, 1, addr);
1066 } else {
1067 /* 0xe and 0xf are both "always" conditions */
1068 gen_goto_tb(s, 0, addr);
1069 }
1070 }
1071
1072 /* C5.6.68 HINT */
1073 static void handle_hint(DisasContext *s, uint32_t insn,
1074 unsigned int op1, unsigned int op2, unsigned int crm)
1075 {
1076 unsigned int selector = crm << 3 | op2;
1077
1078 if (op1 != 3) {
1079 unallocated_encoding(s);
1080 return;
1081 }
1082
1083 switch (selector) {
1084 case 0: /* NOP */
1085 return;
1086 case 3: /* WFI */
1087 s->is_jmp = DISAS_WFI;
1088 return;
1089 case 1: /* YIELD */
1090 case 2: /* WFE */
1091 case 4: /* SEV */
1092 case 5: /* SEVL */
1093 /* we treat all as NOP at least for now */
1094 return;
1095 default:
1096 /* default specified as NOP equivalent */
1097 return;
1098 }
1099 }
1100
1101 static void gen_clrex(DisasContext *s, uint32_t insn)
1102 {
1103 tcg_gen_movi_i64(cpu_exclusive_addr, -1);
1104 }
1105
1106 /* CLREX, DSB, DMB, ISB */
1107 static void handle_sync(DisasContext *s, uint32_t insn,
1108 unsigned int op1, unsigned int op2, unsigned int crm)
1109 {
1110 if (op1 != 3) {
1111 unallocated_encoding(s);
1112 return;
1113 }
1114
1115 switch (op2) {
1116 case 2: /* CLREX */
1117 gen_clrex(s, insn);
1118 return;
1119 case 4: /* DSB */
1120 case 5: /* DMB */
1121 case 6: /* ISB */
1122 /* We don't emulate caches so barriers are no-ops */
1123 return;
1124 default:
1125 unallocated_encoding(s);
1126 return;
1127 }
1128 }
1129
1130 /* C5.6.130 MSR (immediate) - move immediate to processor state field */
1131 static void handle_msr_i(DisasContext *s, uint32_t insn,
1132 unsigned int op1, unsigned int op2, unsigned int crm)
1133 {
1134 int op = op1 << 3 | op2;
1135 switch (op) {
1136 case 0x05: /* SPSel */
1137 if (s->current_pl == 0) {
1138 unallocated_encoding(s);
1139 return;
1140 }
1141 /* fall through */
1142 case 0x1e: /* DAIFSet */
1143 case 0x1f: /* DAIFClear */
1144 {
1145 TCGv_i32 tcg_imm = tcg_const_i32(crm);
1146 TCGv_i32 tcg_op = tcg_const_i32(op);
1147 gen_a64_set_pc_im(s->pc - 4);
1148 gen_helper_msr_i_pstate(cpu_env, tcg_op, tcg_imm);
1149 tcg_temp_free_i32(tcg_imm);
1150 tcg_temp_free_i32(tcg_op);
1151 s->is_jmp = DISAS_UPDATE;
1152 break;
1153 }
1154 default:
1155 unallocated_encoding(s);
1156 return;
1157 }
1158 }
1159
1160 static void gen_get_nzcv(TCGv_i64 tcg_rt)
1161 {
1162 TCGv_i32 tmp = tcg_temp_new_i32();
1163 TCGv_i32 nzcv = tcg_temp_new_i32();
1164
1165 /* build bit 31, N */
1166 tcg_gen_andi_i32(nzcv, cpu_NF, (1 << 31));
1167 /* build bit 30, Z */
1168 tcg_gen_setcondi_i32(TCG_COND_EQ, tmp, cpu_ZF, 0);
1169 tcg_gen_deposit_i32(nzcv, nzcv, tmp, 30, 1);
1170 /* build bit 29, C */
1171 tcg_gen_deposit_i32(nzcv, nzcv, cpu_CF, 29, 1);
1172 /* build bit 28, V */
1173 tcg_gen_shri_i32(tmp, cpu_VF, 31);
1174 tcg_gen_deposit_i32(nzcv, nzcv, tmp, 28, 1);
1175 /* generate result */
1176 tcg_gen_extu_i32_i64(tcg_rt, nzcv);
1177
1178 tcg_temp_free_i32(nzcv);
1179 tcg_temp_free_i32(tmp);
1180 }
1181
1182 static void gen_set_nzcv(TCGv_i64 tcg_rt)
1183
1184 {
1185 TCGv_i32 nzcv = tcg_temp_new_i32();
1186
1187 /* take NZCV from R[t] */
1188 tcg_gen_trunc_i64_i32(nzcv, tcg_rt);
1189
1190 /* bit 31, N */
1191 tcg_gen_andi_i32(cpu_NF, nzcv, (1 << 31));
1192 /* bit 30, Z */
1193 tcg_gen_andi_i32(cpu_ZF, nzcv, (1 << 30));
1194 tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_ZF, cpu_ZF, 0);
1195 /* bit 29, C */
1196 tcg_gen_andi_i32(cpu_CF, nzcv, (1 << 29));
1197 tcg_gen_shri_i32(cpu_CF, cpu_CF, 29);
1198 /* bit 28, V */
1199 tcg_gen_andi_i32(cpu_VF, nzcv, (1 << 28));
1200 tcg_gen_shli_i32(cpu_VF, cpu_VF, 3);
1201 tcg_temp_free_i32(nzcv);
1202 }
1203
1204 /* C5.6.129 MRS - move from system register
1205 * C5.6.131 MSR (register) - move to system register
1206 * C5.6.204 SYS
1207 * C5.6.205 SYSL
1208 * These are all essentially the same insn in 'read' and 'write'
1209 * versions, with varying op0 fields.
1210 */
1211 static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
1212 unsigned int op0, unsigned int op1, unsigned int op2,
1213 unsigned int crn, unsigned int crm, unsigned int rt)
1214 {
1215 const ARMCPRegInfo *ri;
1216 TCGv_i64 tcg_rt;
1217
1218 ri = get_arm_cp_reginfo(s->cp_regs,
1219 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP,
1220 crn, crm, op0, op1, op2));
1221
1222 if (!ri) {
1223 /* Unknown register; this might be a guest error or a QEMU
1224 * unimplemented feature.
1225 */
1226 qemu_log_mask(LOG_UNIMP, "%s access to unsupported AArch64 "
1227 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
1228 isread ? "read" : "write", op0, op1, crn, crm, op2);
1229 unallocated_encoding(s);
1230 return;
1231 }
1232
1233 /* Check access permissions */
1234 if (!cp_access_ok(s->current_pl, ri, isread)) {
1235 unallocated_encoding(s);
1236 return;
1237 }
1238
1239 if (ri->accessfn) {
1240 /* Emit code to perform further access permissions checks at
1241 * runtime; this may result in an exception.
1242 */
1243 TCGv_ptr tmpptr;
1244 gen_a64_set_pc_im(s->pc - 4);
1245 tmpptr = tcg_const_ptr(ri);
1246 gen_helper_access_check_cp_reg(cpu_env, tmpptr);
1247 tcg_temp_free_ptr(tmpptr);
1248 }
1249
1250 /* Handle special cases first */
1251 switch (ri->type & ~(ARM_CP_FLAG_MASK & ~ARM_CP_SPECIAL)) {
1252 case ARM_CP_NOP:
1253 return;
1254 case ARM_CP_NZCV:
1255 tcg_rt = cpu_reg(s, rt);
1256 if (isread) {
1257 gen_get_nzcv(tcg_rt);
1258 } else {
1259 gen_set_nzcv(tcg_rt);
1260 }
1261 return;
1262 case ARM_CP_CURRENTEL:
1263 /* Reads as current EL value from pstate, which is
1264 * guaranteed to be constant by the tb flags.
1265 */
1266 tcg_rt = cpu_reg(s, rt);
1267 tcg_gen_movi_i64(tcg_rt, s->current_pl << 2);
1268 return;
1269 default:
1270 break;
1271 }
1272
1273 if (use_icount && (ri->type & ARM_CP_IO)) {
1274 gen_io_start();
1275 }
1276
1277 tcg_rt = cpu_reg(s, rt);
1278
1279 if (isread) {
1280 if (ri->type & ARM_CP_CONST) {
1281 tcg_gen_movi_i64(tcg_rt, ri->resetvalue);
1282 } else if (ri->readfn) {
1283 TCGv_ptr tmpptr;
1284 tmpptr = tcg_const_ptr(ri);
1285 gen_helper_get_cp_reg64(tcg_rt, cpu_env, tmpptr);
1286 tcg_temp_free_ptr(tmpptr);
1287 } else {
1288 tcg_gen_ld_i64(tcg_rt, cpu_env, ri->fieldoffset);
1289 }
1290 } else {
1291 if (ri->type & ARM_CP_CONST) {
1292 /* If not forbidden by access permissions, treat as WI */
1293 return;
1294 } else if (ri->writefn) {
1295 TCGv_ptr tmpptr;
1296 tmpptr = tcg_const_ptr(ri);
1297 gen_helper_set_cp_reg64(cpu_env, tmpptr, tcg_rt);
1298 tcg_temp_free_ptr(tmpptr);
1299 } else {
1300 tcg_gen_st_i64(tcg_rt, cpu_env, ri->fieldoffset);
1301 }
1302 }
1303
1304 if (use_icount && (ri->type & ARM_CP_IO)) {
1305 /* I/O operations must end the TB here (whether read or write) */
1306 gen_io_end();
1307 s->is_jmp = DISAS_UPDATE;
1308 } else if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) {
1309 /* We default to ending the TB on a coprocessor register write,
1310 * but allow this to be suppressed by the register definition
1311 * (usually only necessary to work around guest bugs).
1312 */
1313 s->is_jmp = DISAS_UPDATE;
1314 }
1315 }
1316
1317 /* C3.2.4 System
1318 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
1319 * +---------------------+---+-----+-----+-------+-------+-----+------+
1320 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
1321 * +---------------------+---+-----+-----+-------+-------+-----+------+
1322 */
1323 static void disas_system(DisasContext *s, uint32_t insn)
1324 {
1325 unsigned int l, op0, op1, crn, crm, op2, rt;
1326 l = extract32(insn, 21, 1);
1327 op0 = extract32(insn, 19, 2);
1328 op1 = extract32(insn, 16, 3);
1329 crn = extract32(insn, 12, 4);
1330 crm = extract32(insn, 8, 4);
1331 op2 = extract32(insn, 5, 3);
1332 rt = extract32(insn, 0, 5);
1333
1334 if (op0 == 0) {
1335 if (l || rt != 31) {
1336 unallocated_encoding(s);
1337 return;
1338 }
1339 switch (crn) {
1340 case 2: /* C5.6.68 HINT */
1341 handle_hint(s, insn, op1, op2, crm);
1342 break;
1343 case 3: /* CLREX, DSB, DMB, ISB */
1344 handle_sync(s, insn, op1, op2, crm);
1345 break;
1346 case 4: /* C5.6.130 MSR (immediate) */
1347 handle_msr_i(s, insn, op1, op2, crm);
1348 break;
1349 default:
1350 unallocated_encoding(s);
1351 break;
1352 }
1353 return;
1354 }
1355 handle_sys(s, insn, l, op0, op1, op2, crn, crm, rt);
1356 }
1357
1358 /* C3.2.3 Exception generation
1359 *
1360 * 31 24 23 21 20 5 4 2 1 0
1361 * +-----------------+-----+------------------------+-----+----+
1362 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
1363 * +-----------------------+------------------------+----------+
1364 */
1365 static void disas_exc(DisasContext *s, uint32_t insn)
1366 {
1367 int opc = extract32(insn, 21, 3);
1368 int op2_ll = extract32(insn, 0, 5);
1369
1370 switch (opc) {
1371 case 0:
1372 /* SVC, HVC, SMC; since we don't support the Virtualization
1373 * or TrustZone extensions these all UNDEF except SVC.
1374 */
1375 if (op2_ll != 1) {
1376 unallocated_encoding(s);
1377 break;
1378 }
1379 gen_exception_insn(s, 0, EXCP_SWI);
1380 break;
1381 case 1:
1382 if (op2_ll != 0) {
1383 unallocated_encoding(s);
1384 break;
1385 }
1386 /* BRK */
1387 gen_exception_insn(s, 0, EXCP_BKPT);
1388 break;
1389 case 2:
1390 if (op2_ll != 0) {
1391 unallocated_encoding(s);
1392 break;
1393 }
1394 /* HLT */
1395 unsupported_encoding(s, insn);
1396 break;
1397 case 5:
1398 if (op2_ll < 1 || op2_ll > 3) {
1399 unallocated_encoding(s);
1400 break;
1401 }
1402 /* DCPS1, DCPS2, DCPS3 */
1403 unsupported_encoding(s, insn);
1404 break;
1405 default:
1406 unallocated_encoding(s);
1407 break;
1408 }
1409 }
1410
1411 /* C3.2.7 Unconditional branch (register)
1412 * 31 25 24 21 20 16 15 10 9 5 4 0
1413 * +---------------+-------+-------+-------+------+-------+
1414 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
1415 * +---------------+-------+-------+-------+------+-------+
1416 */
1417 static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
1418 {
1419 unsigned int opc, op2, op3, rn, op4;
1420
1421 opc = extract32(insn, 21, 4);
1422 op2 = extract32(insn, 16, 5);
1423 op3 = extract32(insn, 10, 6);
1424 rn = extract32(insn, 5, 5);
1425 op4 = extract32(insn, 0, 5);
1426
1427 if (op4 != 0x0 || op3 != 0x0 || op2 != 0x1f) {
1428 unallocated_encoding(s);
1429 return;
1430 }
1431
1432 switch (opc) {
1433 case 0: /* BR */
1434 case 2: /* RET */
1435 break;
1436 case 1: /* BLR */
1437 tcg_gen_movi_i64(cpu_reg(s, 30), s->pc);
1438 break;
1439 case 4: /* ERET */
1440 case 5: /* DRPS */
1441 if (rn != 0x1f) {
1442 unallocated_encoding(s);
1443 } else {
1444 unsupported_encoding(s, insn);
1445 }
1446 return;
1447 default:
1448 unallocated_encoding(s);
1449 return;
1450 }
1451
1452 tcg_gen_mov_i64(cpu_pc, cpu_reg(s, rn));
1453 s->is_jmp = DISAS_JUMP;
1454 }
1455
1456 /* C3.2 Branches, exception generating and system instructions */
1457 static void disas_b_exc_sys(DisasContext *s, uint32_t insn)
1458 {
1459 switch (extract32(insn, 25, 7)) {
1460 case 0x0a: case 0x0b:
1461 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
1462 disas_uncond_b_imm(s, insn);
1463 break;
1464 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
1465 disas_comp_b_imm(s, insn);
1466 break;
1467 case 0x1b: case 0x5b: /* Test & branch (immediate) */
1468 disas_test_b_imm(s, insn);
1469 break;
1470 case 0x2a: /* Conditional branch (immediate) */
1471 disas_cond_b_imm(s, insn);
1472 break;
1473 case 0x6a: /* Exception generation / System */
1474 if (insn & (1 << 24)) {
1475 disas_system(s, insn);
1476 } else {
1477 disas_exc(s, insn);
1478 }
1479 break;
1480 case 0x6b: /* Unconditional branch (register) */
1481 disas_uncond_b_reg(s, insn);
1482 break;
1483 default:
1484 unallocated_encoding(s);
1485 break;
1486 }
1487 }
1488
1489 /*
1490 * Load/Store exclusive instructions are implemented by remembering
1491 * the value/address loaded, and seeing if these are the same
1492 * when the store is performed. This is not actually the architecturally
1493 * mandated semantics, but it works for typical guest code sequences
1494 * and avoids having to monitor regular stores.
1495 *
1496 * In system emulation mode only one CPU will be running at once, so
1497 * this sequence is effectively atomic. In user emulation mode we
1498 * throw an exception and handle the atomic operation elsewhere.
1499 */
1500 static void gen_load_exclusive(DisasContext *s, int rt, int rt2,
1501 TCGv_i64 addr, int size, bool is_pair)
1502 {
1503 TCGv_i64 tmp = tcg_temp_new_i64();
1504 TCGMemOp memop = MO_TE + size;
1505
1506 g_assert(size <= 3);
1507 tcg_gen_qemu_ld_i64(tmp, addr, get_mem_index(s), memop);
1508
1509 if (is_pair) {
1510 TCGv_i64 addr2 = tcg_temp_new_i64();
1511 TCGv_i64 hitmp = tcg_temp_new_i64();
1512
1513 g_assert(size >= 2);
1514 tcg_gen_addi_i64(addr2, addr, 1 << size);
1515 tcg_gen_qemu_ld_i64(hitmp, addr2, get_mem_index(s), memop);
1516 tcg_temp_free_i64(addr2);
1517 tcg_gen_mov_i64(cpu_exclusive_high, hitmp);
1518 tcg_gen_mov_i64(cpu_reg(s, rt2), hitmp);
1519 tcg_temp_free_i64(hitmp);
1520 }
1521
1522 tcg_gen_mov_i64(cpu_exclusive_val, tmp);
1523 tcg_gen_mov_i64(cpu_reg(s, rt), tmp);
1524
1525 tcg_temp_free_i64(tmp);
1526 tcg_gen_mov_i64(cpu_exclusive_addr, addr);
1527 }
1528
1529 #ifdef CONFIG_USER_ONLY
1530 static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
1531 TCGv_i64 addr, int size, int is_pair)
1532 {
1533 tcg_gen_mov_i64(cpu_exclusive_test, addr);
1534 tcg_gen_movi_i32(cpu_exclusive_info,
1535 size | is_pair << 2 | (rd << 4) | (rt << 9) | (rt2 << 14));
1536 gen_exception_insn(s, 4, EXCP_STREX);
1537 }
1538 #else
1539 static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
1540 TCGv_i64 inaddr, int size, int is_pair)
1541 {
1542 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
1543 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
1544 * [addr] = {Rt};
1545 * if (is_pair) {
1546 * [addr + datasize] = {Rt2};
1547 * }
1548 * {Rd} = 0;
1549 * } else {
1550 * {Rd} = 1;
1551 * }
1552 * env->exclusive_addr = -1;
1553 */
1554 int fail_label = gen_new_label();
1555 int done_label = gen_new_label();
1556 TCGv_i64 addr = tcg_temp_local_new_i64();
1557 TCGv_i64 tmp;
1558
1559 /* Copy input into a local temp so it is not trashed when the
1560 * basic block ends at the branch insn.
1561 */
1562 tcg_gen_mov_i64(addr, inaddr);
1563 tcg_gen_brcond_i64(TCG_COND_NE, addr, cpu_exclusive_addr, fail_label);
1564
1565 tmp = tcg_temp_new_i64();
1566 tcg_gen_qemu_ld_i64(tmp, addr, get_mem_index(s), MO_TE + size);
1567 tcg_gen_brcond_i64(TCG_COND_NE, tmp, cpu_exclusive_val, fail_label);
1568 tcg_temp_free_i64(tmp);
1569
1570 if (is_pair) {
1571 TCGv_i64 addrhi = tcg_temp_new_i64();
1572 TCGv_i64 tmphi = tcg_temp_new_i64();
1573
1574 tcg_gen_addi_i64(addrhi, addr, 1 << size);
1575 tcg_gen_qemu_ld_i64(tmphi, addrhi, get_mem_index(s), MO_TE + size);
1576 tcg_gen_brcond_i64(TCG_COND_NE, tmphi, cpu_exclusive_high, fail_label);
1577
1578 tcg_temp_free_i64(tmphi);
1579 tcg_temp_free_i64(addrhi);
1580 }
1581
1582 /* We seem to still have the exclusive monitor, so do the store */
1583 tcg_gen_qemu_st_i64(cpu_reg(s, rt), addr, get_mem_index(s), MO_TE + size);
1584 if (is_pair) {
1585 TCGv_i64 addrhi = tcg_temp_new_i64();
1586
1587 tcg_gen_addi_i64(addrhi, addr, 1 << size);
1588 tcg_gen_qemu_st_i64(cpu_reg(s, rt2), addrhi,
1589 get_mem_index(s), MO_TE + size);
1590 tcg_temp_free_i64(addrhi);
1591 }
1592
1593 tcg_temp_free_i64(addr);
1594
1595 tcg_gen_movi_i64(cpu_reg(s, rd), 0);
1596 tcg_gen_br(done_label);
1597 gen_set_label(fail_label);
1598 tcg_gen_movi_i64(cpu_reg(s, rd), 1);
1599 gen_set_label(done_label);
1600 tcg_gen_movi_i64(cpu_exclusive_addr, -1);
1601
1602 }
1603 #endif
1604
1605 /* C3.3.6 Load/store exclusive
1606 *
1607 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
1608 * +-----+-------------+----+---+----+------+----+-------+------+------+
1609 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
1610 * +-----+-------------+----+---+----+------+----+-------+------+------+
1611 *
1612 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
1613 * L: 0 -> store, 1 -> load
1614 * o2: 0 -> exclusive, 1 -> not
1615 * o1: 0 -> single register, 1 -> register pair
1616 * o0: 1 -> load-acquire/store-release, 0 -> not
1617 *
1618 * o0 == 0 AND o2 == 1 is un-allocated
1619 * o1 == 1 is un-allocated except for 32 and 64 bit sizes
1620 */
1621 static void disas_ldst_excl(DisasContext *s, uint32_t insn)
1622 {
1623 int rt = extract32(insn, 0, 5);
1624 int rn = extract32(insn, 5, 5);
1625 int rt2 = extract32(insn, 10, 5);
1626 int is_lasr = extract32(insn, 15, 1);
1627 int rs = extract32(insn, 16, 5);
1628 int is_pair = extract32(insn, 21, 1);
1629 int is_store = !extract32(insn, 22, 1);
1630 int is_excl = !extract32(insn, 23, 1);
1631 int size = extract32(insn, 30, 2);
1632 TCGv_i64 tcg_addr;
1633
1634 if ((!is_excl && !is_lasr) ||
1635 (is_pair && size < 2)) {
1636 unallocated_encoding(s);
1637 return;
1638 }
1639
1640 if (rn == 31) {
1641 gen_check_sp_alignment(s);
1642 }
1643 tcg_addr = read_cpu_reg_sp(s, rn, 1);
1644
1645 /* Note that since TCG is single threaded load-acquire/store-release
1646 * semantics require no extra if (is_lasr) { ... } handling.
1647 */
1648
1649 if (is_excl) {
1650 if (!is_store) {
1651 gen_load_exclusive(s, rt, rt2, tcg_addr, size, is_pair);
1652 } else {
1653 gen_store_exclusive(s, rs, rt, rt2, tcg_addr, size, is_pair);
1654 }
1655 } else {
1656 TCGv_i64 tcg_rt = cpu_reg(s, rt);
1657 if (is_store) {
1658 do_gpr_st(s, tcg_rt, tcg_addr, size);
1659 } else {
1660 do_gpr_ld(s, tcg_rt, tcg_addr, size, false, false);
1661 }
1662 if (is_pair) {
1663 TCGv_i64 tcg_rt2 = cpu_reg(s, rt);
1664 tcg_gen_addi_i64(tcg_addr, tcg_addr, 1 << size);
1665 if (is_store) {
1666 do_gpr_st(s, tcg_rt2, tcg_addr, size);
1667 } else {
1668 do_gpr_ld(s, tcg_rt2, tcg_addr, size, false, false);
1669 }
1670 }
1671 }
1672 }
1673
1674 /*
1675 * C3.3.5 Load register (literal)
1676 *
1677 * 31 30 29 27 26 25 24 23 5 4 0
1678 * +-----+-------+---+-----+-------------------+-------+
1679 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
1680 * +-----+-------+---+-----+-------------------+-------+
1681 *
1682 * V: 1 -> vector (simd/fp)
1683 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
1684 * 10-> 32 bit signed, 11 -> prefetch
1685 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
1686 */
1687 static void disas_ld_lit(DisasContext *s, uint32_t insn)
1688 {
1689 int rt = extract32(insn, 0, 5);
1690 int64_t imm = sextract32(insn, 5, 19) << 2;
1691 bool is_vector = extract32(insn, 26, 1);
1692 int opc = extract32(insn, 30, 2);
1693 bool is_signed = false;
1694 int size = 2;
1695 TCGv_i64 tcg_rt, tcg_addr;
1696
1697 if (is_vector) {
1698 if (opc == 3) {
1699 unallocated_encoding(s);
1700 return;
1701 }
1702 size = 2 + opc;
1703 } else {
1704 if (opc == 3) {
1705 /* PRFM (literal) : prefetch */
1706 return;
1707 }
1708 size = 2 + extract32(opc, 0, 1);
1709 is_signed = extract32(opc, 1, 1);
1710 }
1711
1712 tcg_rt = cpu_reg(s, rt);
1713
1714 tcg_addr = tcg_const_i64((s->pc - 4) + imm);
1715 if (is_vector) {
1716 do_fp_ld(s, rt, tcg_addr, size);
1717 } else {
1718 do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, false);
1719 }
1720 tcg_temp_free_i64(tcg_addr);
1721 }
1722
1723 /*
1724 * C5.6.80 LDNP (Load Pair - non-temporal hint)
1725 * C5.6.81 LDP (Load Pair - non vector)
1726 * C5.6.82 LDPSW (Load Pair Signed Word - non vector)
1727 * C5.6.176 STNP (Store Pair - non-temporal hint)
1728 * C5.6.177 STP (Store Pair - non vector)
1729 * C6.3.165 LDNP (Load Pair of SIMD&FP - non-temporal hint)
1730 * C6.3.165 LDP (Load Pair of SIMD&FP)
1731 * C6.3.284 STNP (Store Pair of SIMD&FP - non-temporal hint)
1732 * C6.3.284 STP (Store Pair of SIMD&FP)
1733 *
1734 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
1735 * +-----+-------+---+---+-------+---+-----------------------------+
1736 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
1737 * +-----+-------+---+---+-------+---+-------+-------+------+------+
1738 *
1739 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
1740 * LDPSW 01
1741 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
1742 * V: 0 -> GPR, 1 -> Vector
1743 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
1744 * 10 -> signed offset, 11 -> pre-index
1745 * L: 0 -> Store 1 -> Load
1746 *
1747 * Rt, Rt2 = GPR or SIMD registers to be stored
1748 * Rn = general purpose register containing address
1749 * imm7 = signed offset (multiple of 4 or 8 depending on size)
1750 */
1751 static void disas_ldst_pair(DisasContext *s, uint32_t insn)
1752 {
1753 int rt = extract32(insn, 0, 5);
1754 int rn = extract32(insn, 5, 5);
1755 int rt2 = extract32(insn, 10, 5);
1756 int64_t offset = sextract32(insn, 15, 7);
1757 int index = extract32(insn, 23, 2);
1758 bool is_vector = extract32(insn, 26, 1);
1759 bool is_load = extract32(insn, 22, 1);
1760 int opc = extract32(insn, 30, 2);
1761
1762 bool is_signed = false;
1763 bool postindex = false;
1764 bool wback = false;
1765
1766 TCGv_i64 tcg_addr; /* calculated address */
1767 int size;
1768
1769 if (opc == 3) {
1770 unallocated_encoding(s);
1771 return;
1772 }
1773
1774 if (is_vector) {
1775 size = 2 + opc;
1776 } else {
1777 size = 2 + extract32(opc, 1, 1);
1778 is_signed = extract32(opc, 0, 1);
1779 if (!is_load && is_signed) {
1780 unallocated_encoding(s);
1781 return;
1782 }
1783 }
1784
1785 switch (index) {
1786 case 1: /* post-index */
1787 postindex = true;
1788 wback = true;
1789 break;
1790 case 0:
1791 /* signed offset with "non-temporal" hint. Since we don't emulate
1792 * caches we don't care about hints to the cache system about
1793 * data access patterns, and handle this identically to plain
1794 * signed offset.
1795 */
1796 if (is_signed) {
1797 /* There is no non-temporal-hint version of LDPSW */
1798 unallocated_encoding(s);
1799 return;
1800 }
1801 postindex = false;
1802 break;
1803 case 2: /* signed offset, rn not updated */
1804 postindex = false;
1805 break;
1806 case 3: /* pre-index */
1807 postindex = false;
1808 wback = true;
1809 break;
1810 }
1811
1812 offset <<= size;
1813
1814 if (rn == 31) {
1815 gen_check_sp_alignment(s);
1816 }
1817
1818 tcg_addr = read_cpu_reg_sp(s, rn, 1);
1819
1820 if (!postindex) {
1821 tcg_gen_addi_i64(tcg_addr, tcg_addr, offset);
1822 }
1823
1824 if (is_vector) {
1825 if (is_load) {
1826 do_fp_ld(s, rt, tcg_addr, size);
1827 } else {
1828 do_fp_st(s, rt, tcg_addr, size);
1829 }
1830 } else {
1831 TCGv_i64 tcg_rt = cpu_reg(s, rt);
1832 if (is_load) {
1833 do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, false);
1834 } else {
1835 do_gpr_st(s, tcg_rt, tcg_addr, size);
1836 }
1837 }
1838 tcg_gen_addi_i64(tcg_addr, tcg_addr, 1 << size);
1839 if (is_vector) {
1840 if (is_load) {
1841 do_fp_ld(s, rt2, tcg_addr, size);
1842 } else {
1843 do_fp_st(s, rt2, tcg_addr, size);
1844 }
1845 } else {
1846 TCGv_i64 tcg_rt2 = cpu_reg(s, rt2);
1847 if (is_load) {
1848 do_gpr_ld(s, tcg_rt2, tcg_addr, size, is_signed, false);
1849 } else {
1850 do_gpr_st(s, tcg_rt2, tcg_addr, size);
1851 }
1852 }
1853
1854 if (wback) {
1855 if (postindex) {
1856 tcg_gen_addi_i64(tcg_addr, tcg_addr, offset - (1 << size));
1857 } else {
1858 tcg_gen_subi_i64(tcg_addr, tcg_addr, 1 << size);
1859 }
1860 tcg_gen_mov_i64(cpu_reg_sp(s, rn), tcg_addr);
1861 }
1862 }
1863
1864 /*
1865 * C3.3.8 Load/store (immediate post-indexed)
1866 * C3.3.9 Load/store (immediate pre-indexed)
1867 * C3.3.12 Load/store (unscaled immediate)
1868 *
1869 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
1870 * +----+-------+---+-----+-----+---+--------+-----+------+------+
1871 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
1872 * +----+-------+---+-----+-----+---+--------+-----+------+------+
1873 *
1874 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
1875 10 -> unprivileged
1876 * V = 0 -> non-vector
1877 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
1878 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
1879 */
1880 static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn)
1881 {
1882 int rt = extract32(insn, 0, 5);
1883 int rn = extract32(insn, 5, 5);
1884 int imm9 = sextract32(insn, 12, 9);
1885 int opc = extract32(insn, 22, 2);
1886 int size = extract32(insn, 30, 2);
1887 int idx = extract32(insn, 10, 2);
1888 bool is_signed = false;
1889 bool is_store = false;
1890 bool is_extended = false;
1891 bool is_unpriv = (idx == 2);
1892 bool is_vector = extract32(insn, 26, 1);
1893 bool post_index;
1894 bool writeback;
1895
1896 TCGv_i64 tcg_addr;
1897
1898 if (is_vector) {
1899 size |= (opc & 2) << 1;
1900 if (size > 4 || is_unpriv) {
1901 unallocated_encoding(s);
1902 return;
1903 }
1904 is_store = ((opc & 1) == 0);
1905 } else {
1906 if (size == 3 && opc == 2) {
1907 /* PRFM - prefetch */
1908 if (is_unpriv) {
1909 unallocated_encoding(s);
1910 return;
1911 }
1912 return;
1913 }
1914 if (opc == 3 && size > 1) {
1915 unallocated_encoding(s);
1916 return;
1917 }
1918 is_store = (opc == 0);
1919 is_signed = opc & (1<<1);
1920 is_extended = (size < 3) && (opc & 1);
1921 }
1922
1923 switch (idx) {
1924 case 0:
1925 case 2:
1926 post_index = false;
1927 writeback = false;
1928 break;
1929 case 1:
1930 post_index = true;
1931 writeback = true;
1932 break;
1933 case 3:
1934 post_index = false;
1935 writeback = true;
1936 break;
1937 }
1938
1939 if (rn == 31) {
1940 gen_check_sp_alignment(s);
1941 }
1942 tcg_addr = read_cpu_reg_sp(s, rn, 1);
1943
1944 if (!post_index) {
1945 tcg_gen_addi_i64(tcg_addr, tcg_addr, imm9);
1946 }
1947
1948 if (is_vector) {
1949 if (is_store) {
1950 do_fp_st(s, rt, tcg_addr, size);
1951 } else {
1952 do_fp_ld(s, rt, tcg_addr, size);
1953 }
1954 } else {
1955 TCGv_i64 tcg_rt = cpu_reg(s, rt);
1956 int memidx = is_unpriv ? 1 : get_mem_index(s);
1957
1958 if (is_store) {
1959 do_gpr_st_memidx(s, tcg_rt, tcg_addr, size, memidx);
1960 } else {
1961 do_gpr_ld_memidx(s, tcg_rt, tcg_addr, size,
1962 is_signed, is_extended, memidx);
1963 }
1964 }
1965
1966 if (writeback) {
1967 TCGv_i64 tcg_rn = cpu_reg_sp(s, rn);
1968 if (post_index) {
1969 tcg_gen_addi_i64(tcg_addr, tcg_addr, imm9);
1970 }
1971 tcg_gen_mov_i64(tcg_rn, tcg_addr);
1972 }
1973 }
1974
1975 /*
1976 * C3.3.10 Load/store (register offset)
1977 *
1978 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
1979 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
1980 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
1981 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
1982 *
1983 * For non-vector:
1984 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
1985 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
1986 * For vector:
1987 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
1988 * opc<0>: 0 -> store, 1 -> load
1989 * V: 1 -> vector/simd
1990 * opt: extend encoding (see DecodeRegExtend)
1991 * S: if S=1 then scale (essentially index by sizeof(size))
1992 * Rt: register to transfer into/out of
1993 * Rn: address register or SP for base
1994 * Rm: offset register or ZR for offset
1995 */
1996 static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn)
1997 {
1998 int rt = extract32(insn, 0, 5);
1999 int rn = extract32(insn, 5, 5);
2000 int shift = extract32(insn, 12, 1);
2001 int rm = extract32(insn, 16, 5);
2002 int opc = extract32(insn, 22, 2);
2003 int opt = extract32(insn, 13, 3);
2004 int size = extract32(insn, 30, 2);
2005 bool is_signed = false;
2006 bool is_store = false;
2007 bool is_extended = false;
2008 bool is_vector = extract32(insn, 26, 1);
2009
2010 TCGv_i64 tcg_rm;
2011 TCGv_i64 tcg_addr;
2012
2013 if (extract32(opt, 1, 1) == 0) {
2014 unallocated_encoding(s);
2015 return;
2016 }
2017
2018 if (is_vector) {
2019 size |= (opc & 2) << 1;
2020 if (size > 4) {
2021 unallocated_encoding(s);
2022 return;
2023 }
2024 is_store = !extract32(opc, 0, 1);
2025 } else {
2026 if (size == 3 && opc == 2) {
2027 /* PRFM - prefetch */
2028 return;
2029 }
2030 if (opc == 3 && size > 1) {
2031 unallocated_encoding(s);
2032 return;
2033 }
2034 is_store = (opc == 0);
2035 is_signed = extract32(opc, 1, 1);
2036 is_extended = (size < 3) && extract32(opc, 0, 1);
2037 }
2038
2039 if (rn == 31) {
2040 gen_check_sp_alignment(s);
2041 }
2042 tcg_addr = read_cpu_reg_sp(s, rn, 1);
2043
2044 tcg_rm = read_cpu_reg(s, rm, 1);
2045 ext_and_shift_reg(tcg_rm, tcg_rm, opt, shift ? size : 0);
2046
2047 tcg_gen_add_i64(tcg_addr, tcg_addr, tcg_rm);
2048
2049 if (is_vector) {
2050 if (is_store) {
2051 do_fp_st(s, rt, tcg_addr, size);
2052 } else {
2053 do_fp_ld(s, rt, tcg_addr, size);
2054 }
2055 } else {
2056 TCGv_i64 tcg_rt = cpu_reg(s, rt);
2057 if (is_store) {
2058 do_gpr_st(s, tcg_rt, tcg_addr, size);
2059 } else {
2060 do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, is_extended);
2061 }
2062 }
2063 }
2064
2065 /*
2066 * C3.3.13 Load/store (unsigned immediate)
2067 *
2068 * 31 30 29 27 26 25 24 23 22 21 10 9 5
2069 * +----+-------+---+-----+-----+------------+-------+------+
2070 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
2071 * +----+-------+---+-----+-----+------------+-------+------+
2072 *
2073 * For non-vector:
2074 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2075 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2076 * For vector:
2077 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2078 * opc<0>: 0 -> store, 1 -> load
2079 * Rn: base address register (inc SP)
2080 * Rt: target register
2081 */
2082 static void disas_ldst_reg_unsigned_imm(DisasContext *s, uint32_t insn)
2083 {
2084 int rt = extract32(insn, 0, 5);
2085 int rn = extract32(insn, 5, 5);
2086 unsigned int imm12 = extract32(insn, 10, 12);
2087 bool is_vector = extract32(insn, 26, 1);
2088 int size = extract32(insn, 30, 2);
2089 int opc = extract32(insn, 22, 2);
2090 unsigned int offset;
2091
2092 TCGv_i64 tcg_addr;
2093
2094 bool is_store;
2095 bool is_signed = false;
2096 bool is_extended = false;
2097
2098 if (is_vector) {
2099 size |= (opc & 2) << 1;
2100 if (size > 4) {
2101 unallocated_encoding(s);
2102 return;
2103 }
2104 is_store = !extract32(opc, 0, 1);
2105 } else {
2106 if (size == 3 && opc == 2) {
2107 /* PRFM - prefetch */
2108 return;
2109 }
2110 if (opc == 3 && size > 1) {
2111 unallocated_encoding(s);
2112 return;
2113 }
2114 is_store = (opc == 0);
2115 is_signed = extract32(opc, 1, 1);
2116 is_extended = (size < 3) && extract32(opc, 0, 1);
2117 }
2118
2119 if (rn == 31) {
2120 gen_check_sp_alignment(s);
2121 }
2122 tcg_addr = read_cpu_reg_sp(s, rn, 1);
2123 offset = imm12 << size;
2124 tcg_gen_addi_i64(tcg_addr, tcg_addr, offset);
2125
2126 if (is_vector) {
2127 if (is_store) {
2128 do_fp_st(s, rt, tcg_addr, size);
2129 } else {
2130 do_fp_ld(s, rt, tcg_addr, size);
2131 }
2132 } else {
2133 TCGv_i64 tcg_rt = cpu_reg(s, rt);
2134 if (is_store) {
2135 do_gpr_st(s, tcg_rt, tcg_addr, size);
2136 } else {
2137 do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, is_extended);
2138 }
2139 }
2140 }
2141
2142 /* Load/store register (all forms) */
2143 static void disas_ldst_reg(DisasContext *s, uint32_t insn)
2144 {
2145 switch (extract32(insn, 24, 2)) {
2146 case 0:
2147 if (extract32(insn, 21, 1) == 1 && extract32(insn, 10, 2) == 2) {
2148 disas_ldst_reg_roffset(s, insn);
2149 } else {
2150 /* Load/store register (unscaled immediate)
2151 * Load/store immediate pre/post-indexed
2152 * Load/store register unprivileged
2153 */
2154 disas_ldst_reg_imm9(s, insn);
2155 }
2156 break;
2157 case 1:
2158 disas_ldst_reg_unsigned_imm(s, insn);
2159 break;
2160 default:
2161 unallocated_encoding(s);
2162 break;
2163 }
2164 }
2165
2166 /* C3.3.1 AdvSIMD load/store multiple structures
2167 *
2168 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
2169 * +---+---+---------------+---+-------------+--------+------+------+------+
2170 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
2171 * +---+---+---------------+---+-------------+--------+------+------+------+
2172 *
2173 * C3.3.2 AdvSIMD load/store multiple structures (post-indexed)
2174 *
2175 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
2176 * +---+---+---------------+---+---+---------+--------+------+------+------+
2177 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
2178 * +---+---+---------------+---+---+---------+--------+------+------+------+
2179 *
2180 * Rt: first (or only) SIMD&FP register to be transferred
2181 * Rn: base address or SP
2182 * Rm (post-index only): post-index register (when !31) or size dependent #imm
2183 */
2184 static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn)
2185 {
2186 int rt = extract32(insn, 0, 5);
2187 int rn = extract32(insn, 5, 5);
2188 int size = extract32(insn, 10, 2);
2189 int opcode = extract32(insn, 12, 4);
2190 bool is_store = !extract32(insn, 22, 1);
2191 bool is_postidx = extract32(insn, 23, 1);
2192 bool is_q = extract32(insn, 30, 1);
2193 TCGv_i64 tcg_addr, tcg_rn;
2194
2195 int ebytes = 1 << size;
2196 int elements = (is_q ? 128 : 64) / (8 << size);
2197 int rpt; /* num iterations */
2198 int selem; /* structure elements */
2199 int r;
2200
2201 if (extract32(insn, 31, 1) || extract32(insn, 21, 1)) {
2202 unallocated_encoding(s);
2203 return;
2204 }
2205
2206 /* From the shared decode logic */
2207 switch (opcode) {
2208 case 0x0:
2209 rpt = 1;
2210 selem = 4;
2211 break;
2212 case 0x2:
2213 rpt = 4;
2214 selem = 1;
2215 break;
2216 case 0x4:
2217 rpt = 1;
2218 selem = 3;
2219 break;
2220 case 0x6:
2221 rpt = 3;
2222 selem = 1;
2223 break;
2224 case 0x7:
2225 rpt = 1;
2226 selem = 1;
2227 break;
2228 case 0x8:
2229 rpt = 1;
2230 selem = 2;
2231 break;
2232 case 0xa:
2233 rpt = 2;
2234 selem = 1;
2235 break;
2236 default:
2237 unallocated_encoding(s);
2238 return;
2239 }
2240
2241 if (size == 3 && !is_q && selem != 1) {
2242 /* reserved */
2243 unallocated_encoding(s);
2244 return;
2245 }
2246
2247 if (rn == 31) {
2248 gen_check_sp_alignment(s);
2249 }
2250
2251 tcg_rn = cpu_reg_sp(s, rn);
2252 tcg_addr = tcg_temp_new_i64();
2253 tcg_gen_mov_i64(tcg_addr, tcg_rn);
2254
2255 for (r = 0; r < rpt; r++) {
2256 int e;
2257 for (e = 0; e < elements; e++) {
2258 int tt = (rt + r) % 32;
2259 int xs;
2260 for (xs = 0; xs < selem; xs++) {
2261 if (is_store) {
2262 do_vec_st(s, tt, e, tcg_addr, size);
2263 } else {
2264 do_vec_ld(s, tt, e, tcg_addr, size);
2265
2266 /* For non-quad operations, setting a slice of the low
2267 * 64 bits of the register clears the high 64 bits (in
2268 * the ARM ARM pseudocode this is implicit in the fact
2269 * that 'rval' is a 64 bit wide variable). We optimize
2270 * by noticing that we only need to do this the first
2271 * time we touch a register.
2272 */
2273 if (!is_q && e == 0 && (r == 0 || xs == selem - 1)) {
2274 clear_vec_high(s, tt);
2275 }
2276 }
2277 tcg_gen_addi_i64(tcg_addr, tcg_addr, ebytes);
2278 tt = (tt + 1) % 32;
2279 }
2280 }
2281 }
2282
2283 if (is_postidx) {
2284 int rm = extract32(insn, 16, 5);
2285 if (rm == 31) {
2286 tcg_gen_mov_i64(tcg_rn, tcg_addr);
2287 } else {
2288 tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm));
2289 }
2290 }
2291 tcg_temp_free_i64(tcg_addr);
2292 }
2293
2294 /* C3.3.3 AdvSIMD load/store single structure
2295 *
2296 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2297 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2298 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
2299 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2300 *
2301 * C3.3.4 AdvSIMD load/store single structure (post-indexed)
2302 *
2303 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2304 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2305 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
2306 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2307 *
2308 * Rt: first (or only) SIMD&FP register to be transferred
2309 * Rn: base address or SP
2310 * Rm (post-index only): post-index register (when !31) or size dependent #imm
2311 * index = encoded in Q:S:size dependent on size
2312 *
2313 * lane_size = encoded in R, opc
2314 * transfer width = encoded in opc, S, size
2315 */
2316 static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)
2317 {
2318 int rt = extract32(insn, 0, 5);
2319 int rn = extract32(insn, 5, 5);
2320 int size = extract32(insn, 10, 2);
2321 int S = extract32(insn, 12, 1);
2322 int opc = extract32(insn, 13, 3);
2323 int R = extract32(insn, 21, 1);
2324 int is_load = extract32(insn, 22, 1);
2325 int is_postidx = extract32(insn, 23, 1);
2326 int is_q = extract32(insn, 30, 1);
2327
2328 int scale = extract32(opc, 1, 2);
2329 int selem = (extract32(opc, 0, 1) << 1 | R) + 1;
2330 bool replicate = false;
2331 int index = is_q << 3 | S << 2 | size;
2332 int ebytes, xs;
2333 TCGv_i64 tcg_addr, tcg_rn;
2334
2335 switch (scale) {
2336 case 3:
2337 if (!is_load || S) {
2338 unallocated_encoding(s);
2339 return;
2340 }
2341 scale = size;
2342 replicate = true;
2343 break;
2344 case 0:
2345 break;
2346 case 1:
2347 if (extract32(size, 0, 1)) {
2348 unallocated_encoding(s);
2349 return;
2350 }
2351 index >>= 1;
2352 break;
2353 case 2:
2354 if (extract32(size, 1, 1)) {
2355 unallocated_encoding(s);
2356 return;
2357 }
2358 if (!extract32(size, 0, 1)) {
2359 index >>= 2;
2360 } else {
2361 if (S) {
2362 unallocated_encoding(s);
2363 return;
2364 }
2365 index >>= 3;
2366 scale = 3;
2367 }
2368 break;
2369 default:
2370 g_assert_not_reached();
2371 }
2372
2373 ebytes = 1 << scale;
2374
2375 if (rn == 31) {
2376 gen_check_sp_alignment(s);
2377 }
2378
2379 tcg_rn = cpu_reg_sp(s, rn);
2380 tcg_addr = tcg_temp_new_i64();
2381 tcg_gen_mov_i64(tcg_addr, tcg_rn);
2382
2383 for (xs = 0; xs < selem; xs++) {
2384 if (replicate) {
2385 /* Load and replicate to all elements */
2386 uint64_t mulconst;
2387 TCGv_i64 tcg_tmp = tcg_temp_new_i64();
2388
2389 tcg_gen_qemu_ld_i64(tcg_tmp, tcg_addr,
2390 get_mem_index(s), MO_TE + scale);
2391 switch (scale) {
2392 case 0:
2393 mulconst = 0x0101010101010101ULL;
2394 break;
2395 case 1:
2396 mulconst = 0x0001000100010001ULL;
2397 break;
2398 case 2:
2399 mulconst = 0x0000000100000001ULL;
2400 break;
2401 case 3:
2402 mulconst = 0;
2403 break;
2404 default:
2405 g_assert_not_reached();
2406 }
2407 if (mulconst) {
2408 tcg_gen_muli_i64(tcg_tmp, tcg_tmp, mulconst);
2409 }
2410 write_vec_element(s, tcg_tmp, rt, 0, MO_64);
2411 if (is_q) {
2412 write_vec_element(s, tcg_tmp, rt, 1, MO_64);
2413 } else {
2414 clear_vec_high(s, rt);
2415 }
2416 tcg_temp_free_i64(tcg_tmp);
2417 } else {
2418 /* Load/store one element per register */
2419 if (is_load) {
2420 do_vec_ld(s, rt, index, tcg_addr, MO_TE + scale);
2421 } else {
2422 do_vec_st(s, rt, index, tcg_addr, MO_TE + scale);
2423 }
2424 }
2425 tcg_gen_addi_i64(tcg_addr, tcg_addr, ebytes);
2426 rt = (rt + 1) % 32;
2427 }
2428
2429 if (is_postidx) {
2430 int rm = extract32(insn, 16, 5);
2431 if (rm == 31) {
2432 tcg_gen_mov_i64(tcg_rn, tcg_addr);
2433 } else {
2434 tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm));
2435 }
2436 }
2437 tcg_temp_free_i64(tcg_addr);
2438 }
2439
2440 /* C3.3 Loads and stores */
2441 static void disas_ldst(DisasContext *s, uint32_t insn)
2442 {
2443 switch (extract32(insn, 24, 6)) {
2444 case 0x08: /* Load/store exclusive */
2445 disas_ldst_excl(s, insn);
2446 break;
2447 case 0x18: case 0x1c: /* Load register (literal) */
2448 disas_ld_lit(s, insn);
2449 break;
2450 case 0x28: case 0x29:
2451 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
2452 disas_ldst_pair(s, insn);
2453 break;
2454 case 0x38: case 0x39:
2455 case 0x3c: case 0x3d: /* Load/store register (all forms) */
2456 disas_ldst_reg(s, insn);
2457 break;
2458 case 0x0c: /* AdvSIMD load/store multiple structures */
2459 disas_ldst_multiple_struct(s, insn);
2460 break;
2461 case 0x0d: /* AdvSIMD load/store single structure */
2462 disas_ldst_single_struct(s, insn);
2463 break;
2464 default:
2465 unallocated_encoding(s);
2466 break;
2467 }
2468 }
2469
2470 /* C3.4.6 PC-rel. addressing
2471 * 31 30 29 28 24 23 5 4 0
2472 * +----+-------+-----------+-------------------+------+
2473 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
2474 * +----+-------+-----------+-------------------+------+
2475 */
2476 static void disas_pc_rel_adr(DisasContext *s, uint32_t insn)
2477 {
2478 unsigned int page, rd;
2479 uint64_t base;
2480 int64_t offset;
2481
2482 page = extract32(insn, 31, 1);
2483 /* SignExtend(immhi:immlo) -> offset */
2484 offset = ((int64_t)sextract32(insn, 5, 19) << 2) | extract32(insn, 29, 2);
2485 rd = extract32(insn, 0, 5);
2486 base = s->pc - 4;
2487
2488 if (page) {
2489 /* ADRP (page based) */
2490 base &= ~0xfff;
2491 offset <<= 12;
2492 }
2493
2494 tcg_gen_movi_i64(cpu_reg(s, rd), base + offset);
2495 }
2496
2497 /*
2498 * C3.4.1 Add/subtract (immediate)
2499 *
2500 * 31 30 29 28 24 23 22 21 10 9 5 4 0
2501 * +--+--+--+-----------+-----+-------------+-----+-----+
2502 * |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd |
2503 * +--+--+--+-----------+-----+-------------+-----+-----+
2504 *
2505 * sf: 0 -> 32bit, 1 -> 64bit
2506 * op: 0 -> add , 1 -> sub
2507 * S: 1 -> set flags
2508 * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12
2509 */
2510 static void disas_add_sub_imm(DisasContext *s, uint32_t insn)
2511 {
2512 int rd = extract32(insn, 0, 5);
2513 int rn = extract32(insn, 5, 5);
2514 uint64_t imm = extract32(insn, 10, 12);
2515 int shift = extract32(insn, 22, 2);
2516 bool setflags = extract32(insn, 29, 1);
2517 bool sub_op = extract32(insn, 30, 1);
2518 bool is_64bit = extract32(insn, 31, 1);
2519
2520 TCGv_i64 tcg_rn = cpu_reg_sp(s, rn);
2521 TCGv_i64 tcg_rd = setflags ? cpu_reg(s, rd) : cpu_reg_sp(s, rd);
2522 TCGv_i64 tcg_result;
2523
2524 switch (shift) {
2525 case 0x0:
2526 break;
2527 case 0x1:
2528 imm <<= 12;
2529 break;
2530 default:
2531 unallocated_encoding(s);
2532 return;
2533 }
2534
2535 tcg_result = tcg_temp_new_i64();
2536 if (!setflags) {
2537 if (sub_op) {
2538 tcg_gen_subi_i64(tcg_result, tcg_rn, imm);
2539 } else {
2540 tcg_gen_addi_i64(tcg_result, tcg_rn, imm);
2541 }
2542 } else {
2543 TCGv_i64 tcg_imm = tcg_const_i64(imm);
2544 if (sub_op) {
2545 gen_sub_CC(is_64bit, tcg_result, tcg_rn, tcg_imm);
2546 } else {
2547 gen_add_CC(is_64bit, tcg_result, tcg_rn, tcg_imm);
2548 }
2549 tcg_temp_free_i64(tcg_imm);
2550 }
2551
2552 if (is_64bit) {
2553 tcg_gen_mov_i64(tcg_rd, tcg_result);
2554 } else {
2555 tcg_gen_ext32u_i64(tcg_rd, tcg_result);
2556 }
2557
2558 tcg_temp_free_i64(tcg_result);
2559 }
2560
2561 /* The input should be a value in the bottom e bits (with higher
2562 * bits zero); returns that value replicated into every element
2563 * of size e in a 64 bit integer.
2564 */
2565 static uint64_t bitfield_replicate(uint64_t mask, unsigned int e)
2566 {
2567 assert(e != 0);
2568 while (e < 64) {
2569 mask |= mask << e;
2570 e *= 2;
2571 }
2572 return mask;
2573 }
2574
2575 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
2576 static inline uint64_t bitmask64(unsigned int length)
2577 {
2578 assert(length > 0 && length <= 64);
2579 return ~0ULL >> (64 - length);
2580 }
2581
2582 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
2583 * only require the wmask. Returns false if the imms/immr/immn are a reserved
2584 * value (ie should cause a guest UNDEF exception), and true if they are
2585 * valid, in which case the decoded bit pattern is written to result.
2586 */
2587 static bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn,
2588 unsigned int imms, unsigned int immr)
2589 {
2590 uint64_t mask;
2591 unsigned e, levels, s, r;
2592 int len;
2593
2594 assert(immn < 2 && imms < 64 && immr < 64);
2595
2596 /* The bit patterns we create here are 64 bit patterns which
2597 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
2598 * 64 bits each. Each element contains the same value: a run
2599 * of between 1 and e-1 non-zero bits, rotated within the
2600 * element by between 0 and e-1 bits.
2601 *
2602 * The element size and run length are encoded into immn (1 bit)
2603 * and imms (6 bits) as follows:
2604 * 64 bit elements: immn = 1, imms = <length of run - 1>
2605 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
2606 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
2607 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
2608 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
2609 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
2610 * Notice that immn = 0, imms = 11111x is the only combination
2611 * not covered by one of the above options; this is reserved.
2612 * Further, <length of run - 1> all-ones is a reserved pattern.
2613 *
2614 * In all cases the rotation is by immr % e (and immr is 6 bits).
2615 */
2616
2617 /* First determine the element size */
2618 len = 31 - clz32((immn << 6) | (~imms & 0x3f));
2619 if (len < 1) {
2620 /* This is the immn == 0, imms == 0x11111x case */
2621 return false;
2622 }
2623 e = 1 << len;
2624
2625 levels = e - 1;
2626 s = imms & levels;
2627 r = immr & levels;
2628
2629 if (s == levels) {
2630 /* <length of run - 1> mustn't be all-ones. */
2631 return false;
2632 }
2633
2634 /* Create the value of one element: s+1 set bits rotated
2635 * by r within the element (which is e bits wide)...
2636 */
2637 mask = bitmask64(s + 1);
2638 mask = (mask >> r) | (mask << (e - r));
2639 /* ...then replicate the element over the whole 64 bit value */
2640 mask = bitfield_replicate(mask, e);
2641 *result = mask;
2642 return true;
2643 }
2644
2645 /* C3.4.4 Logical (immediate)
2646 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
2647 * +----+-----+-------------+---+------+------+------+------+
2648 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
2649 * +----+-----+-------------+---+------+------+------+------+
2650 */
2651 static void disas_logic_imm(DisasContext *s, uint32_t insn)
2652 {
2653 unsigned int sf, opc, is_n, immr, imms, rn, rd;
2654 TCGv_i64 tcg_rd, tcg_rn;
2655 uint64_t wmask;
2656 bool is_and = false;
2657
2658 sf = extract32(insn, 31, 1);
2659 opc = extract32(insn, 29, 2);
2660 is_n = extract32(insn, 22, 1);
2661 immr = extract32(insn, 16, 6);
2662 imms = extract32(insn, 10, 6);
2663 rn = extract32(insn, 5, 5);
2664 rd = extract32(insn, 0, 5);
2665
2666 if (!sf && is_n) {
2667 unallocated_encoding(s);
2668 return;
2669 }
2670
2671 if (opc == 0x3) { /* ANDS */
2672 tcg_rd = cpu_reg(s, rd);
2673 } else {
2674 tcg_rd = cpu_reg_sp(s, rd);
2675 }
2676 tcg_rn = cpu_reg(s, rn);
2677
2678 if (!logic_imm_decode_wmask(&wmask, is_n, imms, immr)) {
2679 /* some immediate field values are reserved */
2680 unallocated_encoding(s);
2681 return;
2682 }
2683
2684 if (!sf) {
2685 wmask &= 0xffffffff;
2686 }
2687
2688 switch (opc) {
2689 case 0x3: /* ANDS */
2690 case 0x0: /* AND */
2691 tcg_gen_andi_i64(tcg_rd, tcg_rn, wmask);
2692 is_and = true;
2693 break;
2694 case 0x1: /* ORR */
2695 tcg_gen_ori_i64(tcg_rd, tcg_rn, wmask);
2696 break;
2697 case 0x2: /* EOR */
2698 tcg_gen_xori_i64(tcg_rd, tcg_rn, wmask);
2699 break;
2700 default:
2701 assert(FALSE); /* must handle all above */
2702 break;
2703 }
2704
2705 if (!sf && !is_and) {
2706 /* zero extend final result; we know we can skip this for AND
2707 * since the immediate had the high 32 bits clear.
2708 */
2709 tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
2710 }
2711
2712 if (opc == 3) { /* ANDS */
2713 gen_logic_CC(sf, tcg_rd);
2714 }
2715 }
2716
2717 /*
2718 * C3.4.5 Move wide (immediate)
2719 *
2720 * 31 30 29 28 23 22 21 20 5 4 0
2721 * +--+-----+-------------+-----+----------------+------+
2722 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
2723 * +--+-----+-------------+-----+----------------+------+
2724 *
2725 * sf: 0 -> 32 bit, 1 -> 64 bit
2726 * opc: 00 -> N, 10 -> Z, 11 -> K
2727 * hw: shift/16 (0,16, and sf only 32, 48)
2728 */
2729 static void disas_movw_imm(DisasContext *s, uint32_t insn)
2730 {
2731 int rd = extract32(insn, 0, 5);
2732 uint64_t imm = extract32(insn, 5, 16);
2733 int sf = extract32(insn, 31, 1);
2734 int opc = extract32(insn, 29, 2);
2735 int pos = extract32(insn, 21, 2) << 4;
2736 TCGv_i64 tcg_rd = cpu_reg(s, rd);
2737 TCGv_i64 tcg_imm;
2738
2739 if (!sf && (pos >= 32)) {
2740 unallocated_encoding(s);
2741 return;
2742 }
2743
2744 switch (opc) {
2745 case 0: /* MOVN */
2746 case 2: /* MOVZ */
2747 imm <<= pos;
2748 if (opc == 0) {
2749 imm = ~imm;
2750 }
2751 if (!sf) {
2752 imm &= 0xffffffffu;
2753 }
2754 tcg_gen_movi_i64(tcg_rd, imm);
2755 break;
2756 case 3: /* MOVK */
2757 tcg_imm = tcg_const_i64(imm);
2758 tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_imm, pos, 16);
2759 tcg_temp_free_i64(tcg_imm);
2760 if (!sf) {
2761 tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
2762 }
2763 break;
2764 default:
2765 unallocated_encoding(s);
2766 break;
2767 }
2768 }
2769
2770 /* C3.4.2 Bitfield
2771 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
2772 * +----+-----+-------------+---+------+------+------+------+
2773 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
2774 * +----+-----+-------------+---+------+------+------+------+
2775 */
2776 static void disas_bitfield(DisasContext *s, uint32_t insn)
2777 {
2778 unsigned int sf, n, opc, ri, si, rn, rd, bitsize, pos, len;
2779 TCGv_i64 tcg_rd, tcg_tmp;
2780
2781 sf = extract32(insn, 31, 1);
2782 opc = extract32(insn, 29, 2);
2783 n = extract32(insn, 22, 1);
2784 ri = extract32(insn, 16, 6);
2785 si = extract32(insn, 10, 6);
2786 rn = extract32(insn, 5, 5);
2787 rd = extract32(insn, 0, 5);
2788 bitsize = sf ? 64 : 32;
2789
2790 if (sf != n || ri >= bitsize || si >= bitsize || opc > 2) {
2791 unallocated_encoding(s);
2792 return;
2793 }
2794
2795 tcg_rd = cpu_reg(s, rd);
2796 tcg_tmp = read_cpu_reg(s, rn, sf);
2797
2798 /* OPTME: probably worth recognizing common cases of ext{8,16,32}{u,s} */
2799
2800 if (opc != 1) { /* SBFM or UBFM */
2801 tcg_gen_movi_i64(tcg_rd, 0);
2802 }
2803
2804 /* do the bit move operation */
2805 if (si >= ri) {
2806 /* Wd<s-r:0> = Wn<s:r> */
2807 tcg_gen_shri_i64(tcg_tmp, tcg_tmp, ri);
2808 pos = 0;
2809 len = (si - ri) + 1;
2810 } else {
2811 /* Wd<32+s-r,32-r> = Wn<s:0> */
2812 pos = bitsize - ri;
2813 len = si + 1;
2814 }
2815
2816 tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, pos, len);
2817
2818 if (opc == 0) { /* SBFM - sign extend the destination field */
2819 tcg_gen_shli_i64(tcg_rd, tcg_rd, 64 - (pos + len));
2820 tcg_gen_sari_i64(tcg_rd, tcg_rd, 64 - (pos + len));
2821 }
2822
2823 if (!sf) { /* zero extend final result */
2824 tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
2825 }
2826 }
2827
2828 /* C3.4.3 Extract
2829 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
2830 * +----+------+-------------+---+----+------+--------+------+------+
2831 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
2832 * +----+------+-------------+---+----+------+--------+------+------+
2833 */
2834 static void disas_extract(DisasContext *s, uint32_t insn)
2835 {
2836 unsigned int sf, n, rm, imm, rn, rd, bitsize, op21, op0;
2837
2838 sf = extract32(insn, 31, 1);
2839 n = extract32(insn, 22, 1);
2840 rm = extract32(insn, 16, 5);
2841 imm = extract32(insn, 10, 6);
2842 rn = extract32(insn, 5, 5);
2843 rd = extract32(insn, 0, 5);
2844 op21 = extract32(insn, 29, 2);
2845 op0 = extract32(insn, 21, 1);
2846 bitsize = sf ? 64 : 32;
2847
2848 if (sf != n || op21 || op0 || imm >= bitsize) {
2849 unallocated_encoding(s);
2850 } else {
2851 TCGv_i64 tcg_rd, tcg_rm, tcg_rn;
2852
2853 tcg_rd = cpu_reg(s, rd);
2854
2855 if (imm) {
2856 /* OPTME: we can special case rm==rn as a rotate */
2857 tcg_rm = read_cpu_reg(s, rm, sf);
2858 tcg_rn = read_cpu_reg(s, rn, sf);
2859 tcg_gen_shri_i64(tcg_rm, tcg_rm, imm);
2860 tcg_gen_shli_i64(tcg_rn, tcg_rn, bitsize - imm);
2861 tcg_gen_or_i64(tcg_rd, tcg_rm, tcg_rn);
2862 if (!sf) {
2863 tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
2864 }
2865 } else {
2866 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
2867 * so an extract from bit 0 is a special case.
2868 */
2869 if (sf) {
2870 tcg_gen_mov_i64(tcg_rd, cpu_reg(s, rm));
2871 } else {
2872 tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rm));
2873 }
2874 }
2875
2876 }
2877 }
2878
2879 /* C3.4 Data processing - immediate */
2880 static void disas_data_proc_imm(DisasContext *s, uint32_t insn)
2881 {
2882 switch (extract32(insn, 23, 6)) {
2883 case 0x20: case 0x21: /* PC-rel. addressing */
2884 disas_pc_rel_adr(s, insn);
2885 break;
2886 case 0x22: case 0x23: /* Add/subtract (immediate) */
2887 disas_add_sub_imm(s, insn);
2888 break;
2889 case 0x24: /* Logical (immediate) */
2890 disas_logic_imm(s, insn);
2891 break;
2892 case 0x25: /* Move wide (immediate) */
2893 disas_movw_imm(s, insn);
2894 break;
2895 case 0x26: /* Bitfield */
2896 disas_bitfield(s, insn);
2897 break;
2898 case 0x27: /* Extract */
2899 disas_extract(s, insn);
2900 break;
2901 default:
2902 unallocated_encoding(s);
2903 break;
2904 }
2905 }
2906
2907 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
2908 * Note that it is the caller's responsibility to ensure that the
2909 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
2910 * mandated semantics for out of range shifts.
2911 */
2912 static void shift_reg(TCGv_i64 dst, TCGv_i64 src, int sf,
2913 enum a64_shift_type shift_type, TCGv_i64 shift_amount)
2914 {
2915 switch (shift_type) {
2916 case A64_SHIFT_TYPE_LSL:
2917 tcg_gen_shl_i64(dst, src, shift_amount);
2918 break;
2919 case A64_SHIFT_TYPE_LSR:
2920 tcg_gen_shr_i64(dst, src, shift_amount);
2921 break;
2922 case A64_SHIFT_TYPE_ASR:
2923 if (!sf) {
2924 tcg_gen_ext32s_i64(dst, src);
2925 }
2926 tcg_gen_sar_i64(dst, sf ? src : dst, shift_amount);
2927 break;
2928 case A64_SHIFT_TYPE_ROR:
2929 if (sf) {
2930 tcg_gen_rotr_i64(dst, src, shift_amount);
2931 } else {
2932 TCGv_i32 t0, t1;
2933 t0 = tcg_temp_new_i32();
2934 t1 = tcg_temp_new_i32();
2935 tcg_gen_trunc_i64_i32(t0, src);
2936 tcg_gen_trunc_i64_i32(t1, shift_amount);
2937 tcg_gen_rotr_i32(t0, t0, t1);
2938 tcg_gen_extu_i32_i64(dst, t0);
2939 tcg_temp_free_i32(t0);
2940 tcg_temp_free_i32(t1);
2941 }
2942 break;
2943 default:
2944 assert(FALSE); /* all shift types should be handled */
2945 break;
2946 }
2947
2948 if (!sf) { /* zero extend final result */
2949 tcg_gen_ext32u_i64(dst, dst);
2950 }
2951 }
2952
2953 /* Shift a TCGv src by immediate, put result in dst.
2954 * The shift amount must be in range (this should always be true as the
2955 * relevant instructions will UNDEF on bad shift immediates).
2956 */
2957 static void shift_reg_imm(TCGv_i64 dst, TCGv_i64 src, int sf,
2958 enum a64_shift_type shift_type, unsigned int shift_i)
2959 {
2960 assert(shift_i < (sf ? 64 : 32));
2961
2962 if (shift_i == 0) {
2963 tcg_gen_mov_i64(dst, src);
2964 } else {
2965 TCGv_i64 shift_const;
2966
2967 shift_const = tcg_const_i64(shift_i);
2968 shift_reg(dst, src, sf, shift_type, shift_const);
2969 tcg_temp_free_i64(shift_const);
2970 }
2971 }
2972
2973 /* C3.5.10 Logical (shifted register)
2974 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
2975 * +----+-----+-----------+-------+---+------+--------+------+------+
2976 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
2977 * +----+-----+-----------+-------+---+------+--------+------+------+
2978 */
2979 static void disas_logic_reg(DisasContext *s, uint32_t insn)
2980 {
2981 TCGv_i64 tcg_rd, tcg_rn, tcg_rm;
2982 unsigned int sf, opc, shift_type, invert, rm, shift_amount, rn, rd;
2983
2984 sf = extract32(insn, 31, 1);
2985 opc = extract32(insn, 29, 2);
2986 shift_type = extract32(insn, 22, 2);
2987 invert = extract32(insn, 21, 1);
2988 rm = extract32(insn, 16, 5);
2989 shift_amount = extract32(insn, 10, 6);
2990 rn = extract32(insn, 5, 5);
2991 rd = extract32(insn, 0, 5);
2992
2993 if (!sf && (shift_amount & (1 << 5))) {
2994 unallocated_encoding(s);
2995 return;
2996 }
2997
2998 tcg_rd = cpu_reg(s, rd);
2999
3000 if (opc == 1 && shift_amount == 0 && shift_type == 0 && rn == 31) {
3001 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
3002 * register-register MOV and MVN, so it is worth special casing.
3003 */
3004 tcg_rm = cpu_reg(s, rm);
3005 if (invert) {
3006 tcg_gen_not_i64(tcg_rd, tcg_rm);
3007 if (!sf) {
3008 tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
3009 }
3010 } else {
3011 if (sf) {
3012 tcg_gen_mov_i64(tcg_rd, tcg_rm);
3013 } else {
3014 tcg_gen_ext32u_i64(tcg_rd, tcg_rm);
3015 }
3016 }
3017 return;
3018 }
3019
3020 tcg_rm = read_cpu_reg(s, rm, sf);
3021
3022 if (shift_amount) {
3023 shift_reg_imm(tcg_rm, tcg_rm, sf, shift_type, shift_amount);
3024 }
3025
3026 tcg_rn = cpu_reg(s, rn);
3027
3028 switch (opc | (invert << 2)) {
3029 case 0: /* AND */
3030 case 3: /* ANDS */
3031 tcg_gen_and_i64(tcg_rd, tcg_rn, tcg_rm);
3032 break;
3033 case 1: /* ORR */
3034 tcg_gen_or_i64(tcg_rd, tcg_rn, tcg_rm);
3035 break;
3036 case 2: /* EOR */
3037 tcg_gen_xor_i64(tcg_rd, tcg_rn, tcg_rm);
3038 break;
3039 case 4: /* BIC */
3040 case 7: /* BICS */
3041 tcg_gen_andc_i64(tcg_rd, tcg_rn, tcg_rm);
3042 break;
3043 case 5: /* ORN */
3044 tcg_gen_orc_i64(tcg_rd, tcg_rn, tcg_rm);
3045 break;
3046 case 6: /* EON */
3047 tcg_gen_eqv_i64(tcg_rd, tcg_rn, tcg_rm);
3048 break;
3049 default:
3050 assert(FALSE);
3051 break;
3052 }
3053
3054 if (!sf) {
3055 tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
3056 }
3057
3058 if (opc == 3) {
3059 gen_logic_CC(sf, tcg_rd);
3060 }
3061 }
3062
3063 /*
3064 * C3.5.1 Add/subtract (extended register)
3065 *
3066 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
3067 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3068 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
3069 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3070 *
3071 * sf: 0 -> 32bit, 1 -> 64bit
3072 * op: 0 -> add , 1 -> sub
3073 * S: 1 -> set flags
3074 * opt: 00
3075 * option: extension type (see DecodeRegExtend)
3076 * imm3: optional shift to Rm
3077 *
3078 * Rd = Rn + LSL(extend(Rm), amount)
3079 */
3080 static void disas_add_sub_ext_reg(DisasContext *s, uint32_t insn)
3081 {
3082 int rd = extract32(insn, 0, 5);
3083 int rn = extract32(insn, 5, 5);
3084 int imm3 = extract32(insn, 10, 3);
3085 int option = extract32(insn, 13, 3);
3086 int rm = extract32(insn, 16, 5);
3087 bool setflags = extract32(insn, 29, 1);
3088 bool sub_op = extract32(insn, 30, 1);
3089 bool sf = extract32(insn, 31, 1);
3090
3091 TCGv_i64 tcg_rm, tcg_rn; /* temps */
3092 TCGv_i64 tcg_rd;
3093 TCGv_i64 tcg_result;
3094
3095 if (imm3 > 4) {
3096 unallocated_encoding(s);
3097 return;
3098 }
3099
3100 /* non-flag setting ops may use SP */
3101 if (!setflags) {
3102 tcg_rd = cpu_reg_sp(s, rd);
3103 } else {
3104 tcg_rd = cpu_reg(s, rd);
3105 }
3106 tcg_rn = read_cpu_reg_sp(s, rn, sf);
3107
3108 tcg_rm = read_cpu_reg(s, rm, sf);
3109 ext_and_shift_reg(tcg_rm, tcg_rm, option, imm3);
3110
3111 tcg_result = tcg_temp_new_i64();
3112
3113 if (!setflags) {
3114 if (sub_op) {
3115 tcg_gen_sub_i64(tcg_result, tcg_rn, tcg_rm);
3116 } else {
3117 tcg_gen_add_i64(tcg_result, tcg_rn, tcg_rm);
3118 }
3119 } else {
3120 if (sub_op) {
3121 gen_sub_CC(sf, tcg_result, tcg_rn, tcg_rm);
3122 } else {
3123 gen_add_CC(sf, tcg_result, tcg_rn, tcg_rm);
3124 }
3125 }
3126
3127 if (sf) {
3128 tcg_gen_mov_i64(tcg_rd, tcg_result);
3129 } else {
3130 tcg_gen_ext32u_i64(tcg_rd, tcg_result);
3131 }
3132
3133 tcg_temp_free_i64(tcg_result);
3134 }
3135
3136 /*
3137 * C3.5.2 Add/subtract (shifted register)
3138 *
3139 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
3140 * +--+--+--+-----------+-----+--+-------+---------+------+------+
3141 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
3142 * +--+--+--+-----------+-----+--+-------+---------+------+------+
3143 *
3144 * sf: 0 -> 32bit, 1 -> 64bit
3145 * op: 0 -> add , 1 -> sub
3146 * S: 1 -> set flags
3147 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
3148 * imm6: Shift amount to apply to Rm before the add/sub
3149 */
3150 static void disas_add_sub_reg(DisasContext *s, uint32_t insn)
3151 {
3152 int rd = extract32(insn, 0, 5);
3153 int rn = extract32(insn, 5, 5);
3154 int imm6 = extract32(insn, 10, 6);
3155 int rm = extract32(insn, 16, 5);
3156 int shift_type = extract32(insn, 22, 2);
3157 bool setflags = extract32(insn, 29, 1);
3158 bool sub_op = extract32(insn, 30, 1);
3159 bool sf = extract32(insn, 31, 1);
3160
3161 TCGv_i64 tcg_rd = cpu_reg(s, rd);
3162 TCGv_i64 tcg_rn, tcg_rm;
3163 TCGv_i64 tcg_result;
3164
3165 if ((shift_type == 3) || (!sf && (imm6 > 31))) {
3166 unallocated_encoding(s);
3167 return;
3168 }
3169
3170 tcg_rn = read_cpu_reg(s, rn, sf);
3171 tcg_rm = read_cpu_reg(s, rm, sf);
3172
3173 shift_reg_imm(tcg_rm, tcg_rm, sf, shift_type, imm6);
3174
3175 tcg_result = tcg_temp_new_i64();
3176
3177 if (!setflags) {
3178 if (sub_op) {
3179 tcg_gen_sub_i64(tcg_result, tcg_rn, tcg_rm);
3180 } else {
3181 tcg_gen_add_i64(tcg_result, tcg_rn, tcg_rm);
3182 }
3183 } else {
3184 if (sub_op) {
3185 gen_sub_CC(sf, tcg_result, tcg_rn, tcg_rm);
3186 } else {
3187 gen_add_CC(sf, tcg_result, tcg_rn, tcg_rm);
3188 }
3189 }
3190
3191 if (sf) {
3192 tcg_gen_mov_i64(tcg_rd, tcg_result);
3193 } else {
3194 tcg_gen_ext32u_i64(tcg_rd, tcg_result);
3195 }
3196
3197 tcg_temp_free_i64(tcg_result);
3198 }
3199
3200 /* C3.5.9 Data-processing (3 source)
3201
3202 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
3203 +--+------+-----------+------+------+----+------+------+------+
3204 |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
3205 +--+------+-----------+------+------+----+------+------+------+
3206
3207 */
3208 static void disas_data_proc_3src(DisasContext *s, uint32_t insn)
3209 {
3210 int rd = extract32(insn, 0, 5);
3211 int rn = extract32(insn, 5, 5);
3212 int ra = extract32(insn, 10, 5);
3213 int rm