cpu: Move breakpoints field from CPU_COMMON to CPUState
[qemu.git] / target-cris / cpu.c
1 /*
2 * QEMU CRIS CPU
3 *
4 * Copyright (c) 2008 AXIS Communications AB
5 * Written by Edgar E. Iglesias.
6 *
7 * Copyright (c) 2012 SUSE LINUX Products GmbH
8 *
9 * This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU Lesser General Public
11 * License as published by the Free Software Foundation; either
12 * version 2.1 of the License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * Lesser General Public License for more details.
18 *
19 * You should have received a copy of the GNU Lesser General Public
20 * License along with this library; if not, see
21 * <http://www.gnu.org/licenses/lgpl-2.1.html>
22 */
23
24 #include "cpu.h"
25 #include "qemu-common.h"
26 #include "mmu.h"
27
28
29 static void cris_cpu_set_pc(CPUState *cs, vaddr value)
30 {
31 CRISCPU *cpu = CRIS_CPU(cs);
32
33 cpu->env.pc = value;
34 }
35
36 static bool cris_cpu_has_work(CPUState *cs)
37 {
38 return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
39 }
40
41 /* CPUClass::reset() */
42 static void cris_cpu_reset(CPUState *s)
43 {
44 CRISCPU *cpu = CRIS_CPU(s);
45 CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(cpu);
46 CPUCRISState *env = &cpu->env;
47 uint32_t vr;
48
49 ccc->parent_reset(s);
50
51 vr = env->pregs[PR_VR];
52 memset(env, 0, offsetof(CPUCRISState, load_info));
53 env->pregs[PR_VR] = vr;
54 tlb_flush(env, 1);
55
56 #if defined(CONFIG_USER_ONLY)
57 /* start in user mode with interrupts enabled. */
58 env->pregs[PR_CCS] |= U_FLAG | I_FLAG | P_FLAG;
59 #else
60 cris_mmu_init(env);
61 env->pregs[PR_CCS] = 0;
62 #endif
63 }
64
65 static ObjectClass *cris_cpu_class_by_name(const char *cpu_model)
66 {
67 ObjectClass *oc;
68 char *typename;
69
70 if (cpu_model == NULL) {
71 return NULL;
72 }
73
74 #if defined(CONFIG_USER_ONLY)
75 if (strcasecmp(cpu_model, "any") == 0) {
76 return object_class_by_name("crisv32-" TYPE_CRIS_CPU);
77 }
78 #endif
79
80 typename = g_strdup_printf("%s-" TYPE_CRIS_CPU, cpu_model);
81 oc = object_class_by_name(typename);
82 g_free(typename);
83 if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_CRIS_CPU) ||
84 object_class_is_abstract(oc))) {
85 oc = NULL;
86 }
87 return oc;
88 }
89
90 CRISCPU *cpu_cris_init(const char *cpu_model)
91 {
92 return CRIS_CPU(cpu_generic_init(TYPE_CRIS_CPU, cpu_model));
93 }
94
95 /* Sort alphabetically by VR. */
96 static gint cris_cpu_list_compare(gconstpointer a, gconstpointer b)
97 {
98 CRISCPUClass *ccc_a = CRIS_CPU_CLASS(a);
99 CRISCPUClass *ccc_b = CRIS_CPU_CLASS(b);
100
101 /* */
102 if (ccc_a->vr > ccc_b->vr) {
103 return 1;
104 } else if (ccc_a->vr < ccc_b->vr) {
105 return -1;
106 } else {
107 return 0;
108 }
109 }
110
111 static void cris_cpu_list_entry(gpointer data, gpointer user_data)
112 {
113 ObjectClass *oc = data;
114 CPUListState *s = user_data;
115 const char *typename = object_class_get_name(oc);
116 char *name;
117
118 name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_CRIS_CPU));
119 (*s->cpu_fprintf)(s->file, " %s\n", name);
120 g_free(name);
121 }
122
123 void cris_cpu_list(FILE *f, fprintf_function cpu_fprintf)
124 {
125 CPUListState s = {
126 .file = f,
127 .cpu_fprintf = cpu_fprintf,
128 };
129 GSList *list;
130
131 list = object_class_get_list(TYPE_CRIS_CPU, false);
132 list = g_slist_sort(list, cris_cpu_list_compare);
133 (*cpu_fprintf)(f, "Available CPUs:\n");
134 g_slist_foreach(list, cris_cpu_list_entry, &s);
135 g_slist_free(list);
136 }
137
138 static void cris_cpu_realizefn(DeviceState *dev, Error **errp)
139 {
140 CPUState *cs = CPU(dev);
141 CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(dev);
142
143 cpu_reset(cs);
144 qemu_init_vcpu(cs);
145
146 ccc->parent_realize(dev, errp);
147 }
148
149 #ifndef CONFIG_USER_ONLY
150 static void cris_cpu_set_irq(void *opaque, int irq, int level)
151 {
152 CRISCPU *cpu = opaque;
153 CPUState *cs = CPU(cpu);
154 int type = irq == CRIS_CPU_IRQ ? CPU_INTERRUPT_HARD : CPU_INTERRUPT_NMI;
155
156 if (level) {
157 cpu_interrupt(cs, type);
158 } else {
159 cpu_reset_interrupt(cs, type);
160 }
161 }
162 #endif
163
164 static void cris_cpu_initfn(Object *obj)
165 {
166 CPUState *cs = CPU(obj);
167 CRISCPU *cpu = CRIS_CPU(obj);
168 CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(obj);
169 CPUCRISState *env = &cpu->env;
170 static bool tcg_initialized;
171
172 cs->env_ptr = env;
173 cpu_exec_init(env);
174
175 env->pregs[PR_VR] = ccc->vr;
176
177 #ifndef CONFIG_USER_ONLY
178 /* IRQ and NMI lines. */
179 qdev_init_gpio_in(DEVICE(cpu), cris_cpu_set_irq, 2);
180 #endif
181
182 if (tcg_enabled() && !tcg_initialized) {
183 tcg_initialized = true;
184 if (env->pregs[PR_VR] < 32) {
185 cris_initialize_crisv10_tcg();
186 } else {
187 cris_initialize_tcg();
188 }
189 }
190 }
191
192 static void crisv8_cpu_class_init(ObjectClass *oc, void *data)
193 {
194 CPUClass *cc = CPU_CLASS(oc);
195 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
196
197 ccc->vr = 8;
198 cc->do_interrupt = crisv10_cpu_do_interrupt;
199 cc->gdb_read_register = crisv10_cpu_gdb_read_register;
200 }
201
202 static void crisv9_cpu_class_init(ObjectClass *oc, void *data)
203 {
204 CPUClass *cc = CPU_CLASS(oc);
205 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
206
207 ccc->vr = 9;
208 cc->do_interrupt = crisv10_cpu_do_interrupt;
209 cc->gdb_read_register = crisv10_cpu_gdb_read_register;
210 }
211
212 static void crisv10_cpu_class_init(ObjectClass *oc, void *data)
213 {
214 CPUClass *cc = CPU_CLASS(oc);
215 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
216
217 ccc->vr = 10;
218 cc->do_interrupt = crisv10_cpu_do_interrupt;
219 cc->gdb_read_register = crisv10_cpu_gdb_read_register;
220 }
221
222 static void crisv11_cpu_class_init(ObjectClass *oc, void *data)
223 {
224 CPUClass *cc = CPU_CLASS(oc);
225 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
226
227 ccc->vr = 11;
228 cc->do_interrupt = crisv10_cpu_do_interrupt;
229 cc->gdb_read_register = crisv10_cpu_gdb_read_register;
230 }
231
232 static void crisv32_cpu_class_init(ObjectClass *oc, void *data)
233 {
234 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
235
236 ccc->vr = 32;
237 }
238
239 #define TYPE(model) model "-" TYPE_CRIS_CPU
240
241 static const TypeInfo cris_cpu_model_type_infos[] = {
242 {
243 .name = TYPE("crisv8"),
244 .parent = TYPE_CRIS_CPU,
245 .class_init = crisv8_cpu_class_init,
246 }, {
247 .name = TYPE("crisv9"),
248 .parent = TYPE_CRIS_CPU,
249 .class_init = crisv9_cpu_class_init,
250 }, {
251 .name = TYPE("crisv10"),
252 .parent = TYPE_CRIS_CPU,
253 .class_init = crisv10_cpu_class_init,
254 }, {
255 .name = TYPE("crisv11"),
256 .parent = TYPE_CRIS_CPU,
257 .class_init = crisv11_cpu_class_init,
258 }, {
259 .name = TYPE("crisv32"),
260 .parent = TYPE_CRIS_CPU,
261 .class_init = crisv32_cpu_class_init,
262 }
263 };
264
265 #undef TYPE
266
267 static void cris_cpu_class_init(ObjectClass *oc, void *data)
268 {
269 DeviceClass *dc = DEVICE_CLASS(oc);
270 CPUClass *cc = CPU_CLASS(oc);
271 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
272
273 ccc->parent_realize = dc->realize;
274 dc->realize = cris_cpu_realizefn;
275
276 ccc->parent_reset = cc->reset;
277 cc->reset = cris_cpu_reset;
278
279 cc->class_by_name = cris_cpu_class_by_name;
280 cc->has_work = cris_cpu_has_work;
281 cc->do_interrupt = cris_cpu_do_interrupt;
282 cc->dump_state = cris_cpu_dump_state;
283 cc->set_pc = cris_cpu_set_pc;
284 cc->gdb_read_register = cris_cpu_gdb_read_register;
285 cc->gdb_write_register = cris_cpu_gdb_write_register;
286 #ifdef CONFIG_USER_ONLY
287 cc->handle_mmu_fault = cris_cpu_handle_mmu_fault;
288 #else
289 cc->get_phys_page_debug = cris_cpu_get_phys_page_debug;
290 #endif
291
292 cc->gdb_num_core_regs = 49;
293 }
294
295 static const TypeInfo cris_cpu_type_info = {
296 .name = TYPE_CRIS_CPU,
297 .parent = TYPE_CPU,
298 .instance_size = sizeof(CRISCPU),
299 .instance_init = cris_cpu_initfn,
300 .abstract = true,
301 .class_size = sizeof(CRISCPUClass),
302 .class_init = cris_cpu_class_init,
303 };
304
305 static void cris_cpu_register_types(void)
306 {
307 int i;
308
309 type_register_static(&cris_cpu_type_info);
310 for (i = 0; i < ARRAY_SIZE(cris_cpu_model_type_infos); i++) {
311 type_register_static(&cris_cpu_model_type_infos[i]);
312 }
313 }
314
315 type_init(cris_cpu_register_types)