scsi: esp: check buffer length before reading scsi command
[qemu.git] / target-cris / cpu.c
1 /*
2 * QEMU CRIS CPU
3 *
4 * Copyright (c) 2008 AXIS Communications AB
5 * Written by Edgar E. Iglesias.
6 *
7 * Copyright (c) 2012 SUSE LINUX Products GmbH
8 *
9 * This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU Lesser General Public
11 * License as published by the Free Software Foundation; either
12 * version 2.1 of the License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * Lesser General Public License for more details.
18 *
19 * You should have received a copy of the GNU Lesser General Public
20 * License along with this library; if not, see
21 * <http://www.gnu.org/licenses/lgpl-2.1.html>
22 */
23
24 #include "qemu/osdep.h"
25 #include "qapi/error.h"
26 #include "cpu.h"
27 #include "qemu-common.h"
28 #include "mmu.h"
29 #include "exec/exec-all.h"
30
31
32 static void cris_cpu_set_pc(CPUState *cs, vaddr value)
33 {
34 CRISCPU *cpu = CRIS_CPU(cs);
35
36 cpu->env.pc = value;
37 }
38
39 static bool cris_cpu_has_work(CPUState *cs)
40 {
41 return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
42 }
43
44 /* CPUClass::reset() */
45 static void cris_cpu_reset(CPUState *s)
46 {
47 CRISCPU *cpu = CRIS_CPU(s);
48 CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(cpu);
49 CPUCRISState *env = &cpu->env;
50 uint32_t vr;
51
52 ccc->parent_reset(s);
53
54 vr = env->pregs[PR_VR];
55 memset(env, 0, offsetof(CPUCRISState, load_info));
56 env->pregs[PR_VR] = vr;
57 tlb_flush(s, 1);
58
59 #if defined(CONFIG_USER_ONLY)
60 /* start in user mode with interrupts enabled. */
61 env->pregs[PR_CCS] |= U_FLAG | I_FLAG | P_FLAG;
62 #else
63 cris_mmu_init(env);
64 env->pregs[PR_CCS] = 0;
65 #endif
66 }
67
68 static ObjectClass *cris_cpu_class_by_name(const char *cpu_model)
69 {
70 ObjectClass *oc;
71 char *typename;
72
73 if (cpu_model == NULL) {
74 return NULL;
75 }
76
77 #if defined(CONFIG_USER_ONLY)
78 if (strcasecmp(cpu_model, "any") == 0) {
79 return object_class_by_name("crisv32-" TYPE_CRIS_CPU);
80 }
81 #endif
82
83 typename = g_strdup_printf("%s-" TYPE_CRIS_CPU, cpu_model);
84 oc = object_class_by_name(typename);
85 g_free(typename);
86 if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_CRIS_CPU) ||
87 object_class_is_abstract(oc))) {
88 oc = NULL;
89 }
90 return oc;
91 }
92
93 CRISCPU *cpu_cris_init(const char *cpu_model)
94 {
95 return CRIS_CPU(cpu_generic_init(TYPE_CRIS_CPU, cpu_model));
96 }
97
98 /* Sort alphabetically by VR. */
99 static gint cris_cpu_list_compare(gconstpointer a, gconstpointer b)
100 {
101 CRISCPUClass *ccc_a = CRIS_CPU_CLASS(a);
102 CRISCPUClass *ccc_b = CRIS_CPU_CLASS(b);
103
104 /* */
105 if (ccc_a->vr > ccc_b->vr) {
106 return 1;
107 } else if (ccc_a->vr < ccc_b->vr) {
108 return -1;
109 } else {
110 return 0;
111 }
112 }
113
114 static void cris_cpu_list_entry(gpointer data, gpointer user_data)
115 {
116 ObjectClass *oc = data;
117 CPUListState *s = user_data;
118 const char *typename = object_class_get_name(oc);
119 char *name;
120
121 name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_CRIS_CPU));
122 (*s->cpu_fprintf)(s->file, " %s\n", name);
123 g_free(name);
124 }
125
126 void cris_cpu_list(FILE *f, fprintf_function cpu_fprintf)
127 {
128 CPUListState s = {
129 .file = f,
130 .cpu_fprintf = cpu_fprintf,
131 };
132 GSList *list;
133
134 list = object_class_get_list(TYPE_CRIS_CPU, false);
135 list = g_slist_sort(list, cris_cpu_list_compare);
136 (*cpu_fprintf)(f, "Available CPUs:\n");
137 g_slist_foreach(list, cris_cpu_list_entry, &s);
138 g_slist_free(list);
139 }
140
141 static void cris_cpu_realizefn(DeviceState *dev, Error **errp)
142 {
143 CPUState *cs = CPU(dev);
144 CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(dev);
145
146 cpu_reset(cs);
147 qemu_init_vcpu(cs);
148
149 ccc->parent_realize(dev, errp);
150 }
151
152 #ifndef CONFIG_USER_ONLY
153 static void cris_cpu_set_irq(void *opaque, int irq, int level)
154 {
155 CRISCPU *cpu = opaque;
156 CPUState *cs = CPU(cpu);
157 int type = irq == CRIS_CPU_IRQ ? CPU_INTERRUPT_HARD : CPU_INTERRUPT_NMI;
158
159 if (level) {
160 cpu_interrupt(cs, type);
161 } else {
162 cpu_reset_interrupt(cs, type);
163 }
164 }
165 #endif
166
167 static void cris_disas_set_info(CPUState *cpu, disassemble_info *info)
168 {
169 CRISCPU *cc = CRIS_CPU(cpu);
170 CPUCRISState *env = &cc->env;
171
172 if (env->pregs[PR_VR] != 32) {
173 info->mach = bfd_mach_cris_v0_v10;
174 info->print_insn = print_insn_crisv10;
175 } else {
176 info->mach = bfd_mach_cris_v32;
177 info->print_insn = print_insn_crisv32;
178 }
179 }
180
181 static void cris_cpu_initfn(Object *obj)
182 {
183 CPUState *cs = CPU(obj);
184 CRISCPU *cpu = CRIS_CPU(obj);
185 CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(obj);
186 CPUCRISState *env = &cpu->env;
187 static bool tcg_initialized;
188
189 cs->env_ptr = env;
190 cpu_exec_init(cs, &error_abort);
191
192 env->pregs[PR_VR] = ccc->vr;
193
194 #ifndef CONFIG_USER_ONLY
195 /* IRQ and NMI lines. */
196 qdev_init_gpio_in(DEVICE(cpu), cris_cpu_set_irq, 2);
197 #endif
198
199 if (tcg_enabled() && !tcg_initialized) {
200 tcg_initialized = true;
201 if (env->pregs[PR_VR] < 32) {
202 cris_initialize_crisv10_tcg();
203 } else {
204 cris_initialize_tcg();
205 }
206 }
207 }
208
209 static void crisv8_cpu_class_init(ObjectClass *oc, void *data)
210 {
211 CPUClass *cc = CPU_CLASS(oc);
212 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
213
214 ccc->vr = 8;
215 cc->do_interrupt = crisv10_cpu_do_interrupt;
216 cc->gdb_read_register = crisv10_cpu_gdb_read_register;
217 }
218
219 static void crisv9_cpu_class_init(ObjectClass *oc, void *data)
220 {
221 CPUClass *cc = CPU_CLASS(oc);
222 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
223
224 ccc->vr = 9;
225 cc->do_interrupt = crisv10_cpu_do_interrupt;
226 cc->gdb_read_register = crisv10_cpu_gdb_read_register;
227 }
228
229 static void crisv10_cpu_class_init(ObjectClass *oc, void *data)
230 {
231 CPUClass *cc = CPU_CLASS(oc);
232 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
233
234 ccc->vr = 10;
235 cc->do_interrupt = crisv10_cpu_do_interrupt;
236 cc->gdb_read_register = crisv10_cpu_gdb_read_register;
237 }
238
239 static void crisv11_cpu_class_init(ObjectClass *oc, void *data)
240 {
241 CPUClass *cc = CPU_CLASS(oc);
242 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
243
244 ccc->vr = 11;
245 cc->do_interrupt = crisv10_cpu_do_interrupt;
246 cc->gdb_read_register = crisv10_cpu_gdb_read_register;
247 }
248
249 static void crisv32_cpu_class_init(ObjectClass *oc, void *data)
250 {
251 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
252
253 ccc->vr = 32;
254 }
255
256 #define TYPE(model) model "-" TYPE_CRIS_CPU
257
258 static const TypeInfo cris_cpu_model_type_infos[] = {
259 {
260 .name = TYPE("crisv8"),
261 .parent = TYPE_CRIS_CPU,
262 .class_init = crisv8_cpu_class_init,
263 }, {
264 .name = TYPE("crisv9"),
265 .parent = TYPE_CRIS_CPU,
266 .class_init = crisv9_cpu_class_init,
267 }, {
268 .name = TYPE("crisv10"),
269 .parent = TYPE_CRIS_CPU,
270 .class_init = crisv10_cpu_class_init,
271 }, {
272 .name = TYPE("crisv11"),
273 .parent = TYPE_CRIS_CPU,
274 .class_init = crisv11_cpu_class_init,
275 }, {
276 .name = TYPE("crisv32"),
277 .parent = TYPE_CRIS_CPU,
278 .class_init = crisv32_cpu_class_init,
279 }
280 };
281
282 #undef TYPE
283
284 static void cris_cpu_class_init(ObjectClass *oc, void *data)
285 {
286 DeviceClass *dc = DEVICE_CLASS(oc);
287 CPUClass *cc = CPU_CLASS(oc);
288 CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
289
290 ccc->parent_realize = dc->realize;
291 dc->realize = cris_cpu_realizefn;
292
293 ccc->parent_reset = cc->reset;
294 cc->reset = cris_cpu_reset;
295
296 cc->class_by_name = cris_cpu_class_by_name;
297 cc->has_work = cris_cpu_has_work;
298 cc->do_interrupt = cris_cpu_do_interrupt;
299 cc->cpu_exec_interrupt = cris_cpu_exec_interrupt;
300 cc->dump_state = cris_cpu_dump_state;
301 cc->set_pc = cris_cpu_set_pc;
302 cc->gdb_read_register = cris_cpu_gdb_read_register;
303 cc->gdb_write_register = cris_cpu_gdb_write_register;
304 #ifdef CONFIG_USER_ONLY
305 cc->handle_mmu_fault = cris_cpu_handle_mmu_fault;
306 #else
307 cc->get_phys_page_debug = cris_cpu_get_phys_page_debug;
308 dc->vmsd = &vmstate_cris_cpu;
309 #endif
310
311 cc->gdb_num_core_regs = 49;
312 cc->gdb_stop_before_watchpoint = true;
313
314 cc->disas_set_info = cris_disas_set_info;
315
316 /*
317 * Reason: cris_cpu_initfn() calls cpu_exec_init(), which saves
318 * the object in cpus -> dangling pointer after final
319 * object_unref().
320 */
321 dc->cannot_destroy_with_object_finalize_yet = true;
322 }
323
324 static const TypeInfo cris_cpu_type_info = {
325 .name = TYPE_CRIS_CPU,
326 .parent = TYPE_CPU,
327 .instance_size = sizeof(CRISCPU),
328 .instance_init = cris_cpu_initfn,
329 .abstract = true,
330 .class_size = sizeof(CRISCPUClass),
331 .class_init = cris_cpu_class_init,
332 };
333
334 static void cris_cpu_register_types(void)
335 {
336 int i;
337
338 type_register_static(&cris_cpu_type_info);
339 for (i = 0; i < ARRAY_SIZE(cris_cpu_model_type_infos); i++) {
340 type_register_static(&cris_cpu_model_type_infos[i]);
341 }
342 }
343
344 type_init(cris_cpu_register_types)