cpu: Move halted and interrupt_request fields to CPUState
[qemu.git] / target-cris / cpu.h
1 /*
2 * CRIS virtual CPU header
3 *
4 * Copyright (c) 2007 AXIS Communications AB
5 * Written by Edgar E. Iglesias
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20 #ifndef CPU_CRIS_H
21 #define CPU_CRIS_H
22
23 #include "config.h"
24 #include "qemu-common.h"
25
26 #define TARGET_LONG_BITS 32
27
28 #define CPUArchState struct CPUCRISState
29
30 #include "exec/cpu-defs.h"
31
32 #define TARGET_HAS_ICE 1
33
34 #define ELF_MACHINE EM_CRIS
35
36 #define EXCP_NMI 1
37 #define EXCP_GURU 2
38 #define EXCP_BUSFAULT 3
39 #define EXCP_IRQ 4
40 #define EXCP_BREAK 5
41
42 /* CRIS-specific interrupt pending bits. */
43 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
44
45 /* Register aliases. R0 - R15 */
46 #define R_FP 8
47 #define R_SP 14
48 #define R_ACR 15
49
50 /* Support regs, P0 - P15 */
51 #define PR_BZ 0
52 #define PR_VR 1
53 #define PR_PID 2
54 #define PR_SRS 3
55 #define PR_WZ 4
56 #define PR_EXS 5
57 #define PR_EDA 6
58 #define PR_PREFIX 6 /* On CRISv10 P6 is reserved, we use it as prefix. */
59 #define PR_MOF 7
60 #define PR_DZ 8
61 #define PR_EBP 9
62 #define PR_ERP 10
63 #define PR_SRP 11
64 #define PR_NRP 12
65 #define PR_CCS 13
66 #define PR_USP 14
67 #define PRV10_BRP 14
68 #define PR_SPC 15
69
70 /* CPU flags. */
71 #define Q_FLAG 0x80000000
72 #define M_FLAG_V32 0x40000000
73 #define PFIX_FLAG 0x800 /* CRISv10 Only. */
74 #define F_FLAG_V10 0x400
75 #define P_FLAG_V10 0x200
76 #define S_FLAG 0x200
77 #define R_FLAG 0x100
78 #define P_FLAG 0x80
79 #define M_FLAG_V10 0x80
80 #define U_FLAG 0x40
81 #define I_FLAG 0x20
82 #define X_FLAG 0x10
83 #define N_FLAG 0x08
84 #define Z_FLAG 0x04
85 #define V_FLAG 0x02
86 #define C_FLAG 0x01
87 #define ALU_FLAGS 0x1F
88
89 /* Condition codes. */
90 #define CC_CC 0
91 #define CC_CS 1
92 #define CC_NE 2
93 #define CC_EQ 3
94 #define CC_VC 4
95 #define CC_VS 5
96 #define CC_PL 6
97 #define CC_MI 7
98 #define CC_LS 8
99 #define CC_HI 9
100 #define CC_GE 10
101 #define CC_LT 11
102 #define CC_GT 12
103 #define CC_LE 13
104 #define CC_A 14
105 #define CC_P 15
106
107 #define NB_MMU_MODES 2
108
109 typedef struct CPUCRISState {
110 uint32_t regs[16];
111 /* P0 - P15 are referred to as special registers in the docs. */
112 uint32_t pregs[16];
113
114 /* Pseudo register for the PC. Not directly accessible on CRIS. */
115 uint32_t pc;
116
117 /* Pseudo register for the kernel stack. */
118 uint32_t ksp;
119
120 /* Branch. */
121 int dslot;
122 int btaken;
123 uint32_t btarget;
124
125 /* Condition flag tracking. */
126 uint32_t cc_op;
127 uint32_t cc_mask;
128 uint32_t cc_dest;
129 uint32_t cc_src;
130 uint32_t cc_result;
131 /* size of the operation, 1 = byte, 2 = word, 4 = dword. */
132 int cc_size;
133 /* X flag at the time of cc snapshot. */
134 int cc_x;
135
136 /* CRIS has certain insns that lockout interrupts. */
137 int locked_irq;
138 int interrupt_vector;
139 int fault_vector;
140 int trap_vector;
141
142 /* FIXME: add a check in the translator to avoid writing to support
143 register sets beyond the 4th. The ISA allows up to 256! but in
144 practice there is no core that implements more than 4.
145
146 Support function registers are used to control units close to the
147 core. Accesses do not pass down the normal hierarchy.
148 */
149 uint32_t sregs[4][16];
150
151 /* Linear feedback shift reg in the mmu. Used to provide pseudo
152 randomness for the 'hint' the mmu gives to sw for chosing valid
153 sets on TLB refills. */
154 uint32_t mmu_rand_lfsr;
155
156 /*
157 * We just store the stores to the tlbset here for later evaluation
158 * when the hw needs access to them.
159 *
160 * One for I and another for D.
161 */
162 struct
163 {
164 uint32_t hi;
165 uint32_t lo;
166 } tlbsets[2][4][16];
167
168 CPU_COMMON
169
170 /* Members after CPU_COMMON are preserved across resets. */
171 void *load_info;
172 } CPUCRISState;
173
174 #include "cpu-qom.h"
175
176 CRISCPU *cpu_cris_init(const char *cpu_model);
177 int cpu_cris_exec(CPUCRISState *s);
178 void do_interrupt(CPUCRISState *env);
179 /* you can call this signal handler from your SIGBUS and SIGSEGV
180 signal handlers to inform the virtual CPU of exceptions. non zero
181 is returned if the signal was handled by the virtual CPU. */
182 int cpu_cris_signal_handler(int host_signum, void *pinfo,
183 void *puc);
184
185 void cris_initialize_tcg(void);
186 void cris_initialize_crisv10_tcg(void);
187
188 enum {
189 CC_OP_DYNAMIC, /* Use env->cc_op */
190 CC_OP_FLAGS,
191 CC_OP_CMP,
192 CC_OP_MOVE,
193 CC_OP_ADD,
194 CC_OP_ADDC,
195 CC_OP_MCP,
196 CC_OP_ADDU,
197 CC_OP_SUB,
198 CC_OP_SUBU,
199 CC_OP_NEG,
200 CC_OP_BTST,
201 CC_OP_MULS,
202 CC_OP_MULU,
203 CC_OP_DSTEP,
204 CC_OP_MSTEP,
205 CC_OP_BOUND,
206
207 CC_OP_OR,
208 CC_OP_AND,
209 CC_OP_XOR,
210 CC_OP_LSL,
211 CC_OP_LSR,
212 CC_OP_ASR,
213 CC_OP_LZ
214 };
215
216 /* CRIS uses 8k pages. */
217 #define TARGET_PAGE_BITS 13
218 #define MMAP_SHIFT TARGET_PAGE_BITS
219
220 #define TARGET_PHYS_ADDR_SPACE_BITS 32
221 #define TARGET_VIRT_ADDR_SPACE_BITS 32
222
223 static inline CPUCRISState *cpu_init(const char *cpu_model)
224 {
225 CRISCPU *cpu = cpu_cris_init(cpu_model);
226 if (cpu == NULL) {
227 return NULL;
228 }
229 return &cpu->env;
230 }
231
232 #define cpu_exec cpu_cris_exec
233 #define cpu_gen_code cpu_cris_gen_code
234 #define cpu_signal_handler cpu_cris_signal_handler
235
236 #define CPU_SAVE_VERSION 1
237
238 /* MMU modes definitions */
239 #define MMU_MODE0_SUFFIX _kernel
240 #define MMU_MODE1_SUFFIX _user
241 #define MMU_USER_IDX 1
242 static inline int cpu_mmu_index (CPUCRISState *env)
243 {
244 return !!(env->pregs[PR_CCS] & U_FLAG);
245 }
246
247 int cpu_cris_handle_mmu_fault(CPUCRISState *env, target_ulong address, int rw,
248 int mmu_idx);
249 #define cpu_handle_mmu_fault cpu_cris_handle_mmu_fault
250
251 #if defined(CONFIG_USER_ONLY)
252 static inline void cpu_clone_regs(CPUCRISState *env, target_ulong newsp)
253 {
254 if (newsp)
255 env->regs[14] = newsp;
256 env->regs[10] = 0;
257 }
258 #endif
259
260 static inline void cpu_set_tls(CPUCRISState *env, target_ulong newtls)
261 {
262 env->pregs[PR_PID] = (env->pregs[PR_PID] & 0xff) | newtls;
263 }
264
265 /* Support function regs. */
266 #define SFR_RW_GC_CFG 0][0
267 #define SFR_RW_MM_CFG env->pregs[PR_SRS]][0
268 #define SFR_RW_MM_KBASE_LO env->pregs[PR_SRS]][1
269 #define SFR_RW_MM_KBASE_HI env->pregs[PR_SRS]][2
270 #define SFR_R_MM_CAUSE env->pregs[PR_SRS]][3
271 #define SFR_RW_MM_TLB_SEL env->pregs[PR_SRS]][4
272 #define SFR_RW_MM_TLB_LO env->pregs[PR_SRS]][5
273 #define SFR_RW_MM_TLB_HI env->pregs[PR_SRS]][6
274
275 #include "exec/cpu-all.h"
276
277 static inline void cpu_get_tb_cpu_state(CPUCRISState *env, target_ulong *pc,
278 target_ulong *cs_base, int *flags)
279 {
280 *pc = env->pc;
281 *cs_base = 0;
282 *flags = env->dslot |
283 (env->pregs[PR_CCS] & (S_FLAG | P_FLAG | U_FLAG
284 | X_FLAG | PFIX_FLAG));
285 }
286
287 #define cpu_list cris_cpu_list
288 void cris_cpu_list(FILE *f, fprintf_function cpu_fprintf);
289
290 static inline bool cpu_has_work(CPUState *cpu)
291 {
292 return cpu->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
293 }
294
295 #include "exec/exec-all.h"
296
297 static inline void cpu_pc_from_tb(CPUCRISState *env, TranslationBlock *tb)
298 {
299 env->pc = tb->pc;
300 }
301 #endif