linux-user: add SO_PEERCRED support for getsockopt
[qemu.git] / target-cris / cpu.h
1 /*
2 * CRIS virtual CPU header
3 *
4 * Copyright (c) 2007 AXIS Communications AB
5 * Written by Edgar E. Iglesias
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20 #ifndef CPU_CRIS_H
21 #define CPU_CRIS_H
22
23 #define TARGET_LONG_BITS 32
24
25 #define CPUState struct CPUCRISState
26
27 #include "cpu-defs.h"
28
29 #define TARGET_HAS_ICE 1
30
31 #define ELF_MACHINE EM_CRIS
32
33 #define EXCP_NMI 1
34 #define EXCP_GURU 2
35 #define EXCP_BUSFAULT 3
36 #define EXCP_IRQ 4
37 #define EXCP_BREAK 5
38
39 /* CRIS-specific interrupt pending bits. */
40 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
41
42 /* Register aliases. R0 - R15 */
43 #define R_FP 8
44 #define R_SP 14
45 #define R_ACR 15
46
47 /* Support regs, P0 - P15 */
48 #define PR_BZ 0
49 #define PR_VR 1
50 #define PR_PID 2
51 #define PR_SRS 3
52 #define PR_WZ 4
53 #define PR_EXS 5
54 #define PR_EDA 6
55 #define PR_PREFIX 6 /* On CRISv10 P6 is reserved, we use it as prefix. */
56 #define PR_MOF 7
57 #define PR_DZ 8
58 #define PR_EBP 9
59 #define PR_ERP 10
60 #define PR_SRP 11
61 #define PR_NRP 12
62 #define PR_CCS 13
63 #define PR_USP 14
64 #define PR_SPC 15
65
66 /* CPU flags. */
67 #define Q_FLAG 0x80000000
68 #define M_FLAG 0x40000000
69 #define PFIX_FLAG 0x800 /* CRISv10 Only. */
70 #define F_FLAG_V10 0x400
71 #define P_FLAG_V10 0x200
72 #define S_FLAG 0x200
73 #define R_FLAG 0x100
74 #define P_FLAG 0x80
75 #define U_FLAG 0x40
76 #define I_FLAG 0x20
77 #define X_FLAG 0x10
78 #define N_FLAG 0x08
79 #define Z_FLAG 0x04
80 #define V_FLAG 0x02
81 #define C_FLAG 0x01
82 #define ALU_FLAGS 0x1F
83
84 /* Condition codes. */
85 #define CC_CC 0
86 #define CC_CS 1
87 #define CC_NE 2
88 #define CC_EQ 3
89 #define CC_VC 4
90 #define CC_VS 5
91 #define CC_PL 6
92 #define CC_MI 7
93 #define CC_LS 8
94 #define CC_HI 9
95 #define CC_GE 10
96 #define CC_LT 11
97 #define CC_GT 12
98 #define CC_LE 13
99 #define CC_A 14
100 #define CC_P 15
101
102 #define NB_MMU_MODES 2
103
104 typedef struct CPUCRISState {
105 uint32_t regs[16];
106 /* P0 - P15 are referred to as special registers in the docs. */
107 uint32_t pregs[16];
108
109 /* Pseudo register for the PC. Not directly accessible on CRIS. */
110 uint32_t pc;
111
112 /* Pseudo register for the kernel stack. */
113 uint32_t ksp;
114
115 /* Branch. */
116 int dslot;
117 int btaken;
118 uint32_t btarget;
119
120 /* Condition flag tracking. */
121 uint32_t cc_op;
122 uint32_t cc_mask;
123 uint32_t cc_dest;
124 uint32_t cc_src;
125 uint32_t cc_result;
126 /* size of the operation, 1 = byte, 2 = word, 4 = dword. */
127 int cc_size;
128 /* X flag at the time of cc snapshot. */
129 int cc_x;
130
131 /* CRIS has certain insns that lockout interrupts. */
132 int locked_irq;
133 int interrupt_vector;
134 int fault_vector;
135 int trap_vector;
136
137 /* FIXME: add a check in the translator to avoid writing to support
138 register sets beyond the 4th. The ISA allows up to 256! but in
139 practice there is no core that implements more than 4.
140
141 Support function registers are used to control units close to the
142 core. Accesses do not pass down the normal hierarchy.
143 */
144 uint32_t sregs[4][16];
145
146 /* Linear feedback shift reg in the mmu. Used to provide pseudo
147 randomness for the 'hint' the mmu gives to sw for chosing valid
148 sets on TLB refills. */
149 uint32_t mmu_rand_lfsr;
150
151 /*
152 * We just store the stores to the tlbset here for later evaluation
153 * when the hw needs access to them.
154 *
155 * One for I and another for D.
156 */
157 struct
158 {
159 uint32_t hi;
160 uint32_t lo;
161 } tlbsets[2][4][16];
162
163 CPU_COMMON
164
165 /* Members after CPU_COMMON are preserved across resets. */
166 void *load_info;
167 } CPUCRISState;
168
169 CPUCRISState *cpu_cris_init(const char *cpu_model);
170 int cpu_cris_exec(CPUCRISState *s);
171 void cpu_cris_close(CPUCRISState *s);
172 void do_interrupt(CPUCRISState *env);
173 /* you can call this signal handler from your SIGBUS and SIGSEGV
174 signal handlers to inform the virtual CPU of exceptions. non zero
175 is returned if the signal was handled by the virtual CPU. */
176 int cpu_cris_signal_handler(int host_signum, void *pinfo,
177 void *puc);
178
179 enum {
180 CC_OP_DYNAMIC, /* Use env->cc_op */
181 CC_OP_FLAGS,
182 CC_OP_CMP,
183 CC_OP_MOVE,
184 CC_OP_ADD,
185 CC_OP_ADDC,
186 CC_OP_MCP,
187 CC_OP_ADDU,
188 CC_OP_SUB,
189 CC_OP_SUBU,
190 CC_OP_NEG,
191 CC_OP_BTST,
192 CC_OP_MULS,
193 CC_OP_MULU,
194 CC_OP_DSTEP,
195 CC_OP_MSTEP,
196 CC_OP_BOUND,
197
198 CC_OP_OR,
199 CC_OP_AND,
200 CC_OP_XOR,
201 CC_OP_LSL,
202 CC_OP_LSR,
203 CC_OP_ASR,
204 CC_OP_LZ
205 };
206
207 /* CRIS uses 8k pages. */
208 #define TARGET_PAGE_BITS 13
209 #define MMAP_SHIFT TARGET_PAGE_BITS
210
211 #define TARGET_PHYS_ADDR_SPACE_BITS 32
212 #define TARGET_VIRT_ADDR_SPACE_BITS 32
213
214 #define cpu_init cpu_cris_init
215 #define cpu_exec cpu_cris_exec
216 #define cpu_gen_code cpu_cris_gen_code
217 #define cpu_signal_handler cpu_cris_signal_handler
218
219 #define CPU_SAVE_VERSION 1
220
221 /* MMU modes definitions */
222 #define MMU_MODE0_SUFFIX _kernel
223 #define MMU_MODE1_SUFFIX _user
224 #define MMU_USER_IDX 1
225 static inline int cpu_mmu_index (CPUState *env)
226 {
227 return !!(env->pregs[PR_CCS] & U_FLAG);
228 }
229
230 int cpu_cris_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
231 int mmu_idx);
232 #define cpu_handle_mmu_fault cpu_cris_handle_mmu_fault
233
234 #if defined(CONFIG_USER_ONLY)
235 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
236 {
237 if (newsp)
238 env->regs[14] = newsp;
239 env->regs[10] = 0;
240 }
241 #endif
242
243 static inline void cpu_set_tls(CPUCRISState *env, target_ulong newtls)
244 {
245 env->pregs[PR_PID] = (env->pregs[PR_PID] & 0xff) | newtls;
246 }
247
248 /* Support function regs. */
249 #define SFR_RW_GC_CFG 0][0
250 #define SFR_RW_MM_CFG env->pregs[PR_SRS]][0
251 #define SFR_RW_MM_KBASE_LO env->pregs[PR_SRS]][1
252 #define SFR_RW_MM_KBASE_HI env->pregs[PR_SRS]][2
253 #define SFR_R_MM_CAUSE env->pregs[PR_SRS]][3
254 #define SFR_RW_MM_TLB_SEL env->pregs[PR_SRS]][4
255 #define SFR_RW_MM_TLB_LO env->pregs[PR_SRS]][5
256 #define SFR_RW_MM_TLB_HI env->pregs[PR_SRS]][6
257
258 #include "cpu-all.h"
259
260 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
261 target_ulong *cs_base, int *flags)
262 {
263 *pc = env->pc;
264 *cs_base = 0;
265 *flags = env->dslot |
266 (env->pregs[PR_CCS] & (S_FLAG | P_FLAG | U_FLAG
267 | X_FLAG | PFIX_FLAG));
268 }
269
270 #define cpu_list cris_cpu_list
271 void cris_cpu_list(FILE *f, fprintf_function cpu_fprintf);
272
273 static inline bool cpu_has_work(CPUState *env)
274 {
275 return env->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
276 }
277
278 #include "exec-all.h"
279
280 static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
281 {
282 env->pc = tb->pc;
283 }
284 #endif