cpu: Move breakpoints field from CPU_COMMON to CPUState
[qemu.git] / target-cris / cpu.h
1 /*
2 * CRIS virtual CPU header
3 *
4 * Copyright (c) 2007 AXIS Communications AB
5 * Written by Edgar E. Iglesias
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20 #ifndef CPU_CRIS_H
21 #define CPU_CRIS_H
22
23 #include "config.h"
24 #include "qemu-common.h"
25
26 #define TARGET_LONG_BITS 32
27
28 #define CPUArchState struct CPUCRISState
29
30 #include "exec/cpu-defs.h"
31
32 #define TARGET_HAS_ICE 1
33
34 #define ELF_MACHINE EM_CRIS
35
36 #define EXCP_NMI 1
37 #define EXCP_GURU 2
38 #define EXCP_BUSFAULT 3
39 #define EXCP_IRQ 4
40 #define EXCP_BREAK 5
41
42 /* CRIS-specific interrupt pending bits. */
43 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
44
45 /* CRUS CPU device objects interrupt lines. */
46 #define CRIS_CPU_IRQ 0
47 #define CRIS_CPU_NMI 1
48
49 /* Register aliases. R0 - R15 */
50 #define R_FP 8
51 #define R_SP 14
52 #define R_ACR 15
53
54 /* Support regs, P0 - P15 */
55 #define PR_BZ 0
56 #define PR_VR 1
57 #define PR_PID 2
58 #define PR_SRS 3
59 #define PR_WZ 4
60 #define PR_EXS 5
61 #define PR_EDA 6
62 #define PR_PREFIX 6 /* On CRISv10 P6 is reserved, we use it as prefix. */
63 #define PR_MOF 7
64 #define PR_DZ 8
65 #define PR_EBP 9
66 #define PR_ERP 10
67 #define PR_SRP 11
68 #define PR_NRP 12
69 #define PR_CCS 13
70 #define PR_USP 14
71 #define PRV10_BRP 14
72 #define PR_SPC 15
73
74 /* CPU flags. */
75 #define Q_FLAG 0x80000000
76 #define M_FLAG_V32 0x40000000
77 #define PFIX_FLAG 0x800 /* CRISv10 Only. */
78 #define F_FLAG_V10 0x400
79 #define P_FLAG_V10 0x200
80 #define S_FLAG 0x200
81 #define R_FLAG 0x100
82 #define P_FLAG 0x80
83 #define M_FLAG_V10 0x80
84 #define U_FLAG 0x40
85 #define I_FLAG 0x20
86 #define X_FLAG 0x10
87 #define N_FLAG 0x08
88 #define Z_FLAG 0x04
89 #define V_FLAG 0x02
90 #define C_FLAG 0x01
91 #define ALU_FLAGS 0x1F
92
93 /* Condition codes. */
94 #define CC_CC 0
95 #define CC_CS 1
96 #define CC_NE 2
97 #define CC_EQ 3
98 #define CC_VC 4
99 #define CC_VS 5
100 #define CC_PL 6
101 #define CC_MI 7
102 #define CC_LS 8
103 #define CC_HI 9
104 #define CC_GE 10
105 #define CC_LT 11
106 #define CC_GT 12
107 #define CC_LE 13
108 #define CC_A 14
109 #define CC_P 15
110
111 #define NB_MMU_MODES 2
112
113 typedef struct CPUCRISState {
114 uint32_t regs[16];
115 /* P0 - P15 are referred to as special registers in the docs. */
116 uint32_t pregs[16];
117
118 /* Pseudo register for the PC. Not directly accessible on CRIS. */
119 uint32_t pc;
120
121 /* Pseudo register for the kernel stack. */
122 uint32_t ksp;
123
124 /* Branch. */
125 int dslot;
126 int btaken;
127 uint32_t btarget;
128
129 /* Condition flag tracking. */
130 uint32_t cc_op;
131 uint32_t cc_mask;
132 uint32_t cc_dest;
133 uint32_t cc_src;
134 uint32_t cc_result;
135 /* size of the operation, 1 = byte, 2 = word, 4 = dword. */
136 int cc_size;
137 /* X flag at the time of cc snapshot. */
138 int cc_x;
139
140 /* CRIS has certain insns that lockout interrupts. */
141 int locked_irq;
142 int interrupt_vector;
143 int fault_vector;
144 int trap_vector;
145
146 /* FIXME: add a check in the translator to avoid writing to support
147 register sets beyond the 4th. The ISA allows up to 256! but in
148 practice there is no core that implements more than 4.
149
150 Support function registers are used to control units close to the
151 core. Accesses do not pass down the normal hierarchy.
152 */
153 uint32_t sregs[4][16];
154
155 /* Linear feedback shift reg in the mmu. Used to provide pseudo
156 randomness for the 'hint' the mmu gives to sw for chosing valid
157 sets on TLB refills. */
158 uint32_t mmu_rand_lfsr;
159
160 /*
161 * We just store the stores to the tlbset here for later evaluation
162 * when the hw needs access to them.
163 *
164 * One for I and another for D.
165 */
166 struct
167 {
168 uint32_t hi;
169 uint32_t lo;
170 } tlbsets[2][4][16];
171
172 CPU_COMMON
173
174 /* Members from load_info on are preserved across resets. */
175 void *load_info;
176 } CPUCRISState;
177
178 #include "cpu-qom.h"
179
180 CRISCPU *cpu_cris_init(const char *cpu_model);
181 int cpu_cris_exec(CPUCRISState *s);
182 /* you can call this signal handler from your SIGBUS and SIGSEGV
183 signal handlers to inform the virtual CPU of exceptions. non zero
184 is returned if the signal was handled by the virtual CPU. */
185 int cpu_cris_signal_handler(int host_signum, void *pinfo,
186 void *puc);
187
188 void cris_initialize_tcg(void);
189 void cris_initialize_crisv10_tcg(void);
190
191 enum {
192 CC_OP_DYNAMIC, /* Use env->cc_op */
193 CC_OP_FLAGS,
194 CC_OP_CMP,
195 CC_OP_MOVE,
196 CC_OP_ADD,
197 CC_OP_ADDC,
198 CC_OP_MCP,
199 CC_OP_ADDU,
200 CC_OP_SUB,
201 CC_OP_SUBU,
202 CC_OP_NEG,
203 CC_OP_BTST,
204 CC_OP_MULS,
205 CC_OP_MULU,
206 CC_OP_DSTEP,
207 CC_OP_MSTEP,
208 CC_OP_BOUND,
209
210 CC_OP_OR,
211 CC_OP_AND,
212 CC_OP_XOR,
213 CC_OP_LSL,
214 CC_OP_LSR,
215 CC_OP_ASR,
216 CC_OP_LZ
217 };
218
219 /* CRIS uses 8k pages. */
220 #define TARGET_PAGE_BITS 13
221 #define MMAP_SHIFT TARGET_PAGE_BITS
222
223 #define TARGET_PHYS_ADDR_SPACE_BITS 32
224 #define TARGET_VIRT_ADDR_SPACE_BITS 32
225
226 static inline CPUCRISState *cpu_init(const char *cpu_model)
227 {
228 CRISCPU *cpu = cpu_cris_init(cpu_model);
229 if (cpu == NULL) {
230 return NULL;
231 }
232 return &cpu->env;
233 }
234
235 #define cpu_exec cpu_cris_exec
236 #define cpu_gen_code cpu_cris_gen_code
237 #define cpu_signal_handler cpu_cris_signal_handler
238
239 #define CPU_SAVE_VERSION 1
240
241 /* MMU modes definitions */
242 #define MMU_MODE0_SUFFIX _kernel
243 #define MMU_MODE1_SUFFIX _user
244 #define MMU_USER_IDX 1
245 static inline int cpu_mmu_index (CPUCRISState *env)
246 {
247 return !!(env->pregs[PR_CCS] & U_FLAG);
248 }
249
250 int cris_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
251 int mmu_idx);
252
253 /* Support function regs. */
254 #define SFR_RW_GC_CFG 0][0
255 #define SFR_RW_MM_CFG env->pregs[PR_SRS]][0
256 #define SFR_RW_MM_KBASE_LO env->pregs[PR_SRS]][1
257 #define SFR_RW_MM_KBASE_HI env->pregs[PR_SRS]][2
258 #define SFR_R_MM_CAUSE env->pregs[PR_SRS]][3
259 #define SFR_RW_MM_TLB_SEL env->pregs[PR_SRS]][4
260 #define SFR_RW_MM_TLB_LO env->pregs[PR_SRS]][5
261 #define SFR_RW_MM_TLB_HI env->pregs[PR_SRS]][6
262
263 #include "exec/cpu-all.h"
264
265 static inline void cpu_get_tb_cpu_state(CPUCRISState *env, target_ulong *pc,
266 target_ulong *cs_base, int *flags)
267 {
268 *pc = env->pc;
269 *cs_base = 0;
270 *flags = env->dslot |
271 (env->pregs[PR_CCS] & (S_FLAG | P_FLAG | U_FLAG
272 | X_FLAG | PFIX_FLAG));
273 }
274
275 #define cpu_list cris_cpu_list
276 void cris_cpu_list(FILE *f, fprintf_function cpu_fprintf);
277
278 #include "exec/exec-all.h"
279
280 #endif