scsi: esp: check buffer length before reading scsi command
[qemu.git] / target-cris / cpu.h
1 /*
2 * CRIS virtual CPU header
3 *
4 * Copyright (c) 2007 AXIS Communications AB
5 * Written by Edgar E. Iglesias
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20 #ifndef CPU_CRIS_H
21 #define CPU_CRIS_H
22
23 #include "qemu-common.h"
24 #include "cpu-qom.h"
25
26 #define TARGET_LONG_BITS 32
27
28 #define CPUArchState struct CPUCRISState
29
30 #include "exec/cpu-defs.h"
31
32 #define EXCP_NMI 1
33 #define EXCP_GURU 2
34 #define EXCP_BUSFAULT 3
35 #define EXCP_IRQ 4
36 #define EXCP_BREAK 5
37
38 /* CRIS-specific interrupt pending bits. */
39 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
40
41 /* CRUS CPU device objects interrupt lines. */
42 #define CRIS_CPU_IRQ 0
43 #define CRIS_CPU_NMI 1
44
45 /* Register aliases. R0 - R15 */
46 #define R_FP 8
47 #define R_SP 14
48 #define R_ACR 15
49
50 /* Support regs, P0 - P15 */
51 #define PR_BZ 0
52 #define PR_VR 1
53 #define PR_PID 2
54 #define PR_SRS 3
55 #define PR_WZ 4
56 #define PR_EXS 5
57 #define PR_EDA 6
58 #define PR_PREFIX 6 /* On CRISv10 P6 is reserved, we use it as prefix. */
59 #define PR_MOF 7
60 #define PR_DZ 8
61 #define PR_EBP 9
62 #define PR_ERP 10
63 #define PR_SRP 11
64 #define PR_NRP 12
65 #define PR_CCS 13
66 #define PR_USP 14
67 #define PRV10_BRP 14
68 #define PR_SPC 15
69
70 /* CPU flags. */
71 #define Q_FLAG 0x80000000
72 #define M_FLAG_V32 0x40000000
73 #define PFIX_FLAG 0x800 /* CRISv10 Only. */
74 #define F_FLAG_V10 0x400
75 #define P_FLAG_V10 0x200
76 #define S_FLAG 0x200
77 #define R_FLAG 0x100
78 #define P_FLAG 0x80
79 #define M_FLAG_V10 0x80
80 #define U_FLAG 0x40
81 #define I_FLAG 0x20
82 #define X_FLAG 0x10
83 #define N_FLAG 0x08
84 #define Z_FLAG 0x04
85 #define V_FLAG 0x02
86 #define C_FLAG 0x01
87 #define ALU_FLAGS 0x1F
88
89 /* Condition codes. */
90 #define CC_CC 0
91 #define CC_CS 1
92 #define CC_NE 2
93 #define CC_EQ 3
94 #define CC_VC 4
95 #define CC_VS 5
96 #define CC_PL 6
97 #define CC_MI 7
98 #define CC_LS 8
99 #define CC_HI 9
100 #define CC_GE 10
101 #define CC_LT 11
102 #define CC_GT 12
103 #define CC_LE 13
104 #define CC_A 14
105 #define CC_P 15
106
107 #define NB_MMU_MODES 2
108
109 typedef struct {
110 uint32_t hi;
111 uint32_t lo;
112 } TLBSet;
113
114 typedef struct CPUCRISState {
115 uint32_t regs[16];
116 /* P0 - P15 are referred to as special registers in the docs. */
117 uint32_t pregs[16];
118
119 /* Pseudo register for the PC. Not directly accessible on CRIS. */
120 uint32_t pc;
121
122 /* Pseudo register for the kernel stack. */
123 uint32_t ksp;
124
125 /* Branch. */
126 int dslot;
127 int btaken;
128 uint32_t btarget;
129
130 /* Condition flag tracking. */
131 uint32_t cc_op;
132 uint32_t cc_mask;
133 uint32_t cc_dest;
134 uint32_t cc_src;
135 uint32_t cc_result;
136 /* size of the operation, 1 = byte, 2 = word, 4 = dword. */
137 int cc_size;
138 /* X flag at the time of cc snapshot. */
139 int cc_x;
140
141 /* CRIS has certain insns that lockout interrupts. */
142 int locked_irq;
143 int interrupt_vector;
144 int fault_vector;
145 int trap_vector;
146
147 /* FIXME: add a check in the translator to avoid writing to support
148 register sets beyond the 4th. The ISA allows up to 256! but in
149 practice there is no core that implements more than 4.
150
151 Support function registers are used to control units close to the
152 core. Accesses do not pass down the normal hierarchy.
153 */
154 uint32_t sregs[4][16];
155
156 /* Linear feedback shift reg in the mmu. Used to provide pseudo
157 randomness for the 'hint' the mmu gives to sw for choosing valid
158 sets on TLB refills. */
159 uint32_t mmu_rand_lfsr;
160
161 /*
162 * We just store the stores to the tlbset here for later evaluation
163 * when the hw needs access to them.
164 *
165 * One for I and another for D.
166 */
167 TLBSet tlbsets[2][4][16];
168
169 CPU_COMMON
170
171 /* Members from load_info on are preserved across resets. */
172 void *load_info;
173 } CPUCRISState;
174
175 /**
176 * CRISCPU:
177 * @env: #CPUCRISState
178 *
179 * A CRIS CPU.
180 */
181 struct CRISCPU {
182 /*< private >*/
183 CPUState parent_obj;
184 /*< public >*/
185
186 CPUCRISState env;
187 };
188
189 static inline CRISCPU *cris_env_get_cpu(CPUCRISState *env)
190 {
191 return container_of(env, CRISCPU, env);
192 }
193
194 #define ENV_GET_CPU(e) CPU(cris_env_get_cpu(e))
195
196 #define ENV_OFFSET offsetof(CRISCPU, env)
197
198 #ifndef CONFIG_USER_ONLY
199 extern const struct VMStateDescription vmstate_cris_cpu;
200 #endif
201
202 void cris_cpu_do_interrupt(CPUState *cpu);
203 void crisv10_cpu_do_interrupt(CPUState *cpu);
204 bool cris_cpu_exec_interrupt(CPUState *cpu, int int_req);
205
206 void cris_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
207 int flags);
208
209 hwaddr cris_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
210
211 int crisv10_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
212 int cris_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
213 int cris_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
214
215 CRISCPU *cpu_cris_init(const char *cpu_model);
216 int cpu_cris_exec(CPUState *cpu);
217 /* you can call this signal handler from your SIGBUS and SIGSEGV
218 signal handlers to inform the virtual CPU of exceptions. non zero
219 is returned if the signal was handled by the virtual CPU. */
220 int cpu_cris_signal_handler(int host_signum, void *pinfo,
221 void *puc);
222
223 void cris_initialize_tcg(void);
224 void cris_initialize_crisv10_tcg(void);
225
226 enum {
227 CC_OP_DYNAMIC, /* Use env->cc_op */
228 CC_OP_FLAGS,
229 CC_OP_CMP,
230 CC_OP_MOVE,
231 CC_OP_ADD,
232 CC_OP_ADDC,
233 CC_OP_MCP,
234 CC_OP_ADDU,
235 CC_OP_SUB,
236 CC_OP_SUBU,
237 CC_OP_NEG,
238 CC_OP_BTST,
239 CC_OP_MULS,
240 CC_OP_MULU,
241 CC_OP_DSTEP,
242 CC_OP_MSTEP,
243 CC_OP_BOUND,
244
245 CC_OP_OR,
246 CC_OP_AND,
247 CC_OP_XOR,
248 CC_OP_LSL,
249 CC_OP_LSR,
250 CC_OP_ASR,
251 CC_OP_LZ
252 };
253
254 /* CRIS uses 8k pages. */
255 #define TARGET_PAGE_BITS 13
256 #define MMAP_SHIFT TARGET_PAGE_BITS
257
258 #define TARGET_PHYS_ADDR_SPACE_BITS 32
259 #define TARGET_VIRT_ADDR_SPACE_BITS 32
260
261 #define cpu_init(cpu_model) CPU(cpu_cris_init(cpu_model))
262
263 #define cpu_exec cpu_cris_exec
264 #define cpu_signal_handler cpu_cris_signal_handler
265
266 /* MMU modes definitions */
267 #define MMU_MODE0_SUFFIX _kernel
268 #define MMU_MODE1_SUFFIX _user
269 #define MMU_USER_IDX 1
270 static inline int cpu_mmu_index (CPUCRISState *env, bool ifetch)
271 {
272 return !!(env->pregs[PR_CCS] & U_FLAG);
273 }
274
275 int cris_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
276 int mmu_idx);
277
278 /* Support function regs. */
279 #define SFR_RW_GC_CFG 0][0
280 #define SFR_RW_MM_CFG env->pregs[PR_SRS]][0
281 #define SFR_RW_MM_KBASE_LO env->pregs[PR_SRS]][1
282 #define SFR_RW_MM_KBASE_HI env->pregs[PR_SRS]][2
283 #define SFR_R_MM_CAUSE env->pregs[PR_SRS]][3
284 #define SFR_RW_MM_TLB_SEL env->pregs[PR_SRS]][4
285 #define SFR_RW_MM_TLB_LO env->pregs[PR_SRS]][5
286 #define SFR_RW_MM_TLB_HI env->pregs[PR_SRS]][6
287
288 #include "exec/cpu-all.h"
289
290 static inline void cpu_get_tb_cpu_state(CPUCRISState *env, target_ulong *pc,
291 target_ulong *cs_base, uint32_t *flags)
292 {
293 *pc = env->pc;
294 *cs_base = 0;
295 *flags = env->dslot |
296 (env->pregs[PR_CCS] & (S_FLAG | P_FLAG | U_FLAG
297 | X_FLAG | PFIX_FLAG));
298 }
299
300 #define cpu_list cris_cpu_list
301 void cris_cpu_list(FILE *f, fprintf_function cpu_fprintf);
302
303 #endif