linux-user: stack_base is now mandatory on all targets
[qemu.git] / target-cris / opcode-cris.h
1 /* cris.h -- Header file for CRIS opcode and register tables.
2 Copyright (C) 2000, 2001, 2004 Free Software Foundation, Inc.
3 Contributed by Axis Communications AB, Lund, Sweden.
4 Originally written for GAS 1.38.1 by Mikael Asker.
5 Updated, BFDized and GNUified by Hans-Peter Nilsson.
6
7 This file is part of GAS, GDB and the GNU binutils.
8
9 GAS, GDB, and GNU binutils is free software; you can redistribute it
10 and/or modify it under the terms of the GNU General Public License as
11 published by the Free Software Foundation; either version 2, or (at your
12 option) any later version.
13
14 GAS, GDB, and GNU binutils are distributed in the hope that they will be
15 useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, see <http://www.gnu.org/licenses/>. */
21
22 #ifndef __CRIS_H_INCLUDED_
23 #define __CRIS_H_INCLUDED_
24
25 #if !defined(__STDC__) && !defined(const)
26 #define const
27 #endif
28
29
30 /* Registers. */
31 #define MAX_REG (15)
32 #define CRIS_REG_SP (14)
33 #define CRIS_REG_PC (15)
34
35 /* CPU version control of disassembly and assembly of instructions.
36 May affect how the instruction is assembled, at least the size of
37 immediate operands. */
38 enum cris_insn_version_usage
39 {
40 /* Any version. */
41 cris_ver_version_all=0,
42
43 /* Indeterminate (intended for disassembly only, or obsolete). */
44 cris_ver_warning,
45
46 /* Only for v0..3 (Etrax 1..4). */
47 cris_ver_v0_3,
48
49 /* Only for v3 or higher (ETRAX 4 and beyond). */
50 cris_ver_v3p,
51
52 /* Only for v8 (Etrax 100). */
53 cris_ver_v8,
54
55 /* Only for v8 or higher (ETRAX 100, ETRAX 100 LX). */
56 cris_ver_v8p,
57
58 /* Only for v0..10. FIXME: Not sure what to do with this. */
59 cris_ver_sim_v0_10,
60
61 /* Only for v0..10. */
62 cris_ver_v0_10,
63
64 /* Only for v3..10. (ETRAX 4, ETRAX 100 and ETRAX 100 LX). */
65 cris_ver_v3_10,
66
67 /* Only for v8..10 (ETRAX 100 and ETRAX 100 LX). */
68 cris_ver_v8_10,
69
70 /* Only for v10 (ETRAX 100 LX) and same series. */
71 cris_ver_v10,
72
73 /* Only for v10 (ETRAX 100 LX) and same series. */
74 cris_ver_v10p,
75
76 /* Only for v32 or higher (codename GUINNESS).
77 Of course some or all these of may change to cris_ver_v32p if/when
78 there's a new revision. */
79 cris_ver_v32p
80 };
81
82
83 /* Special registers. */
84 struct cris_spec_reg
85 {
86 const char *const name;
87 unsigned int number;
88
89 /* The size of the register. */
90 unsigned int reg_size;
91
92 /* What CPU version the special register of that name is implemented
93 in. If cris_ver_warning, emit an unimplemented-warning. */
94 enum cris_insn_version_usage applicable_version;
95
96 /* There might be a specific warning for using a special register
97 here. */
98 const char *const warning;
99 };
100 extern const struct cris_spec_reg cris_spec_regs[];
101
102
103 /* Support registers (kind of special too, but not named as such). */
104 struct cris_support_reg
105 {
106 const char *const name;
107 unsigned int number;
108 };
109 extern const struct cris_support_reg cris_support_regs[];
110
111 struct cris_cond15
112 {
113 /* The name of the condition. */
114 const char *const name;
115
116 /* What CPU version this condition name applies to. */
117 enum cris_insn_version_usage applicable_version;
118 };
119 extern const struct cris_cond15 cris_conds15[];
120
121 /* Opcode-dependent constants. */
122 #define AUTOINCR_BIT (0x04)
123
124 /* Prefixes. */
125 #define BDAP_QUICK_OPCODE (0x0100)
126 #define BDAP_QUICK_Z_BITS (0x0e00)
127
128 #define BIAP_OPCODE (0x0540)
129 #define BIAP_Z_BITS (0x0a80)
130
131 #define DIP_OPCODE (0x0970)
132 #define DIP_Z_BITS (0xf280)
133
134 #define BDAP_INDIR_LOW (0x40)
135 #define BDAP_INDIR_LOW_Z (0x80)
136 #define BDAP_INDIR_HIGH (0x09)
137 #define BDAP_INDIR_HIGH_Z (0x02)
138
139 #define BDAP_INDIR_OPCODE (BDAP_INDIR_HIGH * 0x0100 + BDAP_INDIR_LOW)
140 #define BDAP_INDIR_Z_BITS (BDAP_INDIR_HIGH_Z * 0x100 + BDAP_INDIR_LOW_Z)
141 #define BDAP_PC_LOW (BDAP_INDIR_LOW + CRIS_REG_PC)
142 #define BDAP_INCR_HIGH (BDAP_INDIR_HIGH + AUTOINCR_BIT)
143
144 /* No prefix must have this code for its "match" bits in the
145 opcode-table. "BCC .+2" will do nicely. */
146 #define NO_CRIS_PREFIX 0
147
148 /* Definitions for condition codes. */
149 #define CC_CC 0x0
150 #define CC_HS 0x0
151 #define CC_CS 0x1
152 #define CC_LO 0x1
153 #define CC_NE 0x2
154 #define CC_EQ 0x3
155 #define CC_VC 0x4
156 #define CC_VS 0x5
157 #define CC_PL 0x6
158 #define CC_MI 0x7
159 #define CC_LS 0x8
160 #define CC_HI 0x9
161 #define CC_GE 0xA
162 #define CC_LT 0xB
163 #define CC_GT 0xC
164 #define CC_LE 0xD
165 #define CC_A 0xE
166 #define CC_EXT 0xF
167
168 /* A table of strings "cc", "cs"... indexed with condition code
169 values as above. */
170 extern const char *const cris_cc_strings[];
171
172 /* Bcc quick. */
173 #define BRANCH_QUICK_LOW (0)
174 #define BRANCH_QUICK_HIGH (0)
175 #define BRANCH_QUICK_OPCODE (BRANCH_QUICK_HIGH * 0x0100 + BRANCH_QUICK_LOW)
176 #define BRANCH_QUICK_Z_BITS (0x0F00)
177
178 /* BA quick. */
179 #define BA_QUICK_HIGH (BRANCH_QUICK_HIGH + CC_A * 0x10)
180 #define BA_QUICK_OPCODE (BA_QUICK_HIGH * 0x100 + BRANCH_QUICK_LOW)
181
182 /* Bcc [PC+]. */
183 #define BRANCH_PC_LOW (0xFF)
184 #define BRANCH_INCR_HIGH (0x0D)
185 #define BA_PC_INCR_OPCODE \
186 ((BRANCH_INCR_HIGH + CC_A * 0x10) * 0x0100 + BRANCH_PC_LOW)
187
188 /* Jump. */
189 /* Note that old versions generated special register 8 (in high bits)
190 and not-that-old versions recognized it as a jump-instruction.
191 That opcode now belongs to JUMPU. */
192 #define JUMP_INDIR_OPCODE (0x0930)
193 #define JUMP_INDIR_Z_BITS (0xf2c0)
194 #define JUMP_PC_INCR_OPCODE \
195 (JUMP_INDIR_OPCODE + AUTOINCR_BIT * 0x0100 + CRIS_REG_PC)
196
197 #define MOVE_M_TO_PREG_OPCODE 0x0a30
198 #define MOVE_M_TO_PREG_ZBITS 0x01c0
199
200 /* BDAP.D N,PC. */
201 #define MOVE_PC_INCR_OPCODE_PREFIX \
202 (((BDAP_INCR_HIGH | (CRIS_REG_PC << 4)) << 8) | BDAP_PC_LOW | (2 << 4))
203 #define MOVE_PC_INCR_OPCODE_SUFFIX \
204 (MOVE_M_TO_PREG_OPCODE | CRIS_REG_PC | (AUTOINCR_BIT << 8))
205
206 #define JUMP_PC_INCR_OPCODE_V32 (0x0DBF)
207
208 /* BA DWORD (V32). */
209 #define BA_DWORD_OPCODE (0x0EBF)
210
211 /* Nop. */
212 #define NOP_OPCODE (0x050F)
213 #define NOP_Z_BITS (0xFFFF ^ NOP_OPCODE)
214
215 #define NOP_OPCODE_V32 (0x05B0)
216 #define NOP_Z_BITS_V32 (0xFFFF ^ NOP_OPCODE_V32)
217
218 /* For the compatibility mode, let's use "MOVE R0,P0". Doesn't affect
219 registers or flags. Unfortunately shuts off interrupts for one cycle
220 for < v32, but there doesn't seem to be any alternative without that
221 effect. */
222 #define NOP_OPCODE_COMMON (0x630)
223 #define NOP_OPCODE_ZBITS_COMMON (0xffff & ~NOP_OPCODE_COMMON)
224
225 /* LAPC.D */
226 #define LAPC_DWORD_OPCODE (0x0D7F)
227 #define LAPC_DWORD_Z_BITS (0x0fff & ~LAPC_DWORD_OPCODE)
228
229 /* Structure of an opcode table entry. */
230 enum cris_imm_oprnd_size_type
231 {
232 /* No size is applicable. */
233 SIZE_NONE,
234
235 /* Always 32 bits. */
236 SIZE_FIX_32,
237
238 /* Indicated by size of special register. */
239 SIZE_SPEC_REG,
240
241 /* Indicated by size field, signed. */
242 SIZE_FIELD_SIGNED,
243
244 /* Indicated by size field, unsigned. */
245 SIZE_FIELD_UNSIGNED,
246
247 /* Indicated by size field, no sign implied. */
248 SIZE_FIELD
249 };
250
251 /* For GDB. FIXME: Is this the best way to handle opcode
252 interpretation? */
253 enum cris_op_type
254 {
255 cris_not_implemented_op = 0,
256 cris_abs_op,
257 cris_addi_op,
258 cris_asr_op,
259 cris_asrq_op,
260 cris_ax_ei_setf_op,
261 cris_bdap_prefix,
262 cris_biap_prefix,
263 cris_break_op,
264 cris_btst_nop_op,
265 cris_clearf_di_op,
266 cris_dip_prefix,
267 cris_dstep_logshift_mstep_neg_not_op,
268 cris_eight_bit_offset_branch_op,
269 cris_move_mem_to_reg_movem_op,
270 cris_move_reg_to_mem_movem_op,
271 cris_move_to_preg_op,
272 cris_muls_op,
273 cris_mulu_op,
274 cris_none_reg_mode_add_sub_cmp_and_or_move_op,
275 cris_none_reg_mode_clear_test_op,
276 cris_none_reg_mode_jump_op,
277 cris_none_reg_mode_move_from_preg_op,
278 cris_quick_mode_add_sub_op,
279 cris_quick_mode_and_cmp_move_or_op,
280 cris_quick_mode_bdap_prefix,
281 cris_reg_mode_add_sub_cmp_and_or_move_op,
282 cris_reg_mode_clear_op,
283 cris_reg_mode_jump_op,
284 cris_reg_mode_move_from_preg_op,
285 cris_reg_mode_test_op,
286 cris_scc_op,
287 cris_sixteen_bit_offset_branch_op,
288 cris_three_operand_add_sub_cmp_and_or_op,
289 cris_three_operand_bound_op,
290 cris_two_operand_bound_op,
291 cris_xor_op
292 };
293
294 struct cris_opcode
295 {
296 /* The name of the insn. */
297 const char *name;
298
299 /* Bits that must be 1 for a match. */
300 unsigned int match;
301
302 /* Bits that must be 0 for a match. */
303 unsigned int lose;
304
305 /* See the table in "opcodes/cris-opc.c". */
306 const char *args;
307
308 /* Nonzero if this is a delayed branch instruction. */
309 char delayed;
310
311 /* Size of immediate operands. */
312 enum cris_imm_oprnd_size_type imm_oprnd_size;
313
314 /* Indicates which version this insn was first implemented in. */
315 enum cris_insn_version_usage applicable_version;
316
317 /* What kind of operation this is. */
318 enum cris_op_type op;
319 };
320 extern const struct cris_opcode cris_opcodes[];
321
322
323 /* These macros are for the target-specific flags in disassemble_info
324 used at disassembly. */
325
326 /* This insn accesses memory. This flag is more trustworthy than
327 checking insn_type for "dis_dref" which does not work for
328 e.g. "JSR [foo]". */
329 #define CRIS_DIS_FLAG_MEMREF (1 << 0)
330
331 /* The "target" field holds a register number. */
332 #define CRIS_DIS_FLAG_MEM_TARGET_IS_REG (1 << 1)
333
334 /* The "target2" field holds a register number; add it to "target". */
335 #define CRIS_DIS_FLAG_MEM_TARGET2_IS_REG (1 << 2)
336
337 /* Yet another add-on: the register in "target2" must be multiplied
338 by 2 before adding to "target". */
339 #define CRIS_DIS_FLAG_MEM_TARGET2_MULT2 (1 << 3)
340
341 /* Yet another add-on: the register in "target2" must be multiplied
342 by 4 (mutually exclusive with .._MULT2). */
343 #define CRIS_DIS_FLAG_MEM_TARGET2_MULT4 (1 << 4)
344
345 /* The register in "target2" is an indirect memory reference (of the
346 register there), add to "target". Assumed size is dword (mutually
347 exclusive with .._MULT[24]). */
348 #define CRIS_DIS_FLAG_MEM_TARGET2_MEM (1 << 5)
349
350 /* Add-on to CRIS_DIS_FLAG_MEM_TARGET2_MEM; the memory access is "byte";
351 sign-extended before adding to "target". */
352 #define CRIS_DIS_FLAG_MEM_TARGET2_MEM_BYTE (1 << 6)
353
354 /* Add-on to CRIS_DIS_FLAG_MEM_TARGET2_MEM; the memory access is "word";
355 sign-extended before adding to "target". */
356 #define CRIS_DIS_FLAG_MEM_TARGET2_MEM_WORD (1 << 7)
357
358 #endif /* __CRIS_H_INCLUDED_ */
359
360 /*
361 * Local variables:
362 * eval: (c-set-style "gnu")
363 * indent-tabs-mode: t
364 * End:
365 */