target-i386: Make kvm_default_features an array
[qemu.git] / target-i386 / cpu.c
1 /*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdlib.h>
20 #include <stdio.h>
21 #include <string.h>
22 #include <inttypes.h>
23
24 #include "cpu.h"
25 #include "sysemu/kvm.h"
26 #include "sysemu/cpus.h"
27 #include "topology.h"
28
29 #include "qemu/option.h"
30 #include "qemu/config-file.h"
31 #include "qapi/qmp/qerror.h"
32
33 #include "qapi-types.h"
34 #include "qapi-visit.h"
35 #include "qapi/visitor.h"
36 #include "sysemu/arch_init.h"
37
38 #include "hw/hw.h"
39 #if defined(CONFIG_KVM)
40 #include <linux/kvm_para.h>
41 #endif
42
43 #include "sysemu/sysemu.h"
44 #include "hw/qdev-properties.h"
45 #include "hw/cpu/icc_bus.h"
46 #ifndef CONFIG_USER_ONLY
47 #include "hw/xen/xen.h"
48 #include "hw/i386/apic_internal.h"
49 #endif
50
51
52 /* Cache topology CPUID constants: */
53
54 /* CPUID Leaf 2 Descriptors */
55
56 #define CPUID_2_L1D_32KB_8WAY_64B 0x2c
57 #define CPUID_2_L1I_32KB_8WAY_64B 0x30
58 #define CPUID_2_L2_2MB_8WAY_64B 0x7d
59
60
61 /* CPUID Leaf 4 constants: */
62
63 /* EAX: */
64 #define CPUID_4_TYPE_DCACHE 1
65 #define CPUID_4_TYPE_ICACHE 2
66 #define CPUID_4_TYPE_UNIFIED 3
67
68 #define CPUID_4_LEVEL(l) ((l) << 5)
69
70 #define CPUID_4_SELF_INIT_LEVEL (1 << 8)
71 #define CPUID_4_FULLY_ASSOC (1 << 9)
72
73 /* EDX: */
74 #define CPUID_4_NO_INVD_SHARING (1 << 0)
75 #define CPUID_4_INCLUSIVE (1 << 1)
76 #define CPUID_4_COMPLEX_IDX (1 << 2)
77
78 #define ASSOC_FULL 0xFF
79
80 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */
81 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
82 a == 2 ? 0x2 : \
83 a == 4 ? 0x4 : \
84 a == 8 ? 0x6 : \
85 a == 16 ? 0x8 : \
86 a == 32 ? 0xA : \
87 a == 48 ? 0xB : \
88 a == 64 ? 0xC : \
89 a == 96 ? 0xD : \
90 a == 128 ? 0xE : \
91 a == ASSOC_FULL ? 0xF : \
92 0 /* invalid value */)
93
94
95 /* Definitions of the hardcoded cache entries we expose: */
96
97 /* L1 data cache: */
98 #define L1D_LINE_SIZE 64
99 #define L1D_ASSOCIATIVITY 8
100 #define L1D_SETS 64
101 #define L1D_PARTITIONS 1
102 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
103 #define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
104 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
105 #define L1D_LINES_PER_TAG 1
106 #define L1D_SIZE_KB_AMD 64
107 #define L1D_ASSOCIATIVITY_AMD 2
108
109 /* L1 instruction cache: */
110 #define L1I_LINE_SIZE 64
111 #define L1I_ASSOCIATIVITY 8
112 #define L1I_SETS 64
113 #define L1I_PARTITIONS 1
114 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
115 #define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
116 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
117 #define L1I_LINES_PER_TAG 1
118 #define L1I_SIZE_KB_AMD 64
119 #define L1I_ASSOCIATIVITY_AMD 2
120
121 /* Level 2 unified cache: */
122 #define L2_LINE_SIZE 64
123 #define L2_ASSOCIATIVITY 16
124 #define L2_SETS 4096
125 #define L2_PARTITIONS 1
126 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
127 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
128 #define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
129 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
130 #define L2_LINES_PER_TAG 1
131 #define L2_SIZE_KB_AMD 512
132
133 /* No L3 cache: */
134 #define L3_SIZE_KB 0 /* disabled */
135 #define L3_ASSOCIATIVITY 0 /* disabled */
136 #define L3_LINES_PER_TAG 0 /* disabled */
137 #define L3_LINE_SIZE 0 /* disabled */
138
139 /* TLB definitions: */
140
141 #define L1_DTLB_2M_ASSOC 1
142 #define L1_DTLB_2M_ENTRIES 255
143 #define L1_DTLB_4K_ASSOC 1
144 #define L1_DTLB_4K_ENTRIES 255
145
146 #define L1_ITLB_2M_ASSOC 1
147 #define L1_ITLB_2M_ENTRIES 255
148 #define L1_ITLB_4K_ASSOC 1
149 #define L1_ITLB_4K_ENTRIES 255
150
151 #define L2_DTLB_2M_ASSOC 0 /* disabled */
152 #define L2_DTLB_2M_ENTRIES 0 /* disabled */
153 #define L2_DTLB_4K_ASSOC 4
154 #define L2_DTLB_4K_ENTRIES 512
155
156 #define L2_ITLB_2M_ASSOC 0 /* disabled */
157 #define L2_ITLB_2M_ENTRIES 0 /* disabled */
158 #define L2_ITLB_4K_ASSOC 4
159 #define L2_ITLB_4K_ENTRIES 512
160
161
162
163 static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
164 uint32_t vendor2, uint32_t vendor3)
165 {
166 int i;
167 for (i = 0; i < 4; i++) {
168 dst[i] = vendor1 >> (8 * i);
169 dst[i + 4] = vendor2 >> (8 * i);
170 dst[i + 8] = vendor3 >> (8 * i);
171 }
172 dst[CPUID_VENDOR_SZ] = '\0';
173 }
174
175 /* feature flags taken from "Intel Processor Identification and the CPUID
176 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
177 * between feature naming conventions, aliases may be added.
178 */
179 static const char *feature_name[] = {
180 "fpu", "vme", "de", "pse",
181 "tsc", "msr", "pae", "mce",
182 "cx8", "apic", NULL, "sep",
183 "mtrr", "pge", "mca", "cmov",
184 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
185 NULL, "ds" /* Intel dts */, "acpi", "mmx",
186 "fxsr", "sse", "sse2", "ss",
187 "ht" /* Intel htt */, "tm", "ia64", "pbe",
188 };
189 static const char *ext_feature_name[] = {
190 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
191 "ds_cpl", "vmx", "smx", "est",
192 "tm2", "ssse3", "cid", NULL,
193 "fma", "cx16", "xtpr", "pdcm",
194 NULL, "pcid", "dca", "sse4.1|sse4_1",
195 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
196 "tsc-deadline", "aes", "xsave", "osxsave",
197 "avx", "f16c", "rdrand", "hypervisor",
198 };
199 /* Feature names that are already defined on feature_name[] but are set on
200 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
201 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
202 * if and only if CPU vendor is AMD.
203 */
204 static const char *ext2_feature_name[] = {
205 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
206 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
207 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
208 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
209 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
210 "nx|xd", NULL, "mmxext", NULL /* mmx */,
211 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
212 NULL, "lm|i64", "3dnowext", "3dnow",
213 };
214 static const char *ext3_feature_name[] = {
215 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
216 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
217 "3dnowprefetch", "osvw", "ibs", "xop",
218 "skinit", "wdt", NULL, "lwp",
219 "fma4", "tce", NULL, "nodeid_msr",
220 NULL, "tbm", "topoext", "perfctr_core",
221 "perfctr_nb", NULL, NULL, NULL,
222 NULL, NULL, NULL, NULL,
223 };
224
225 static const char *ext4_feature_name[] = {
226 NULL, NULL, "xstore", "xstore-en",
227 NULL, NULL, "xcrypt", "xcrypt-en",
228 "ace2", "ace2-en", "phe", "phe-en",
229 "pmm", "pmm-en", NULL, NULL,
230 NULL, NULL, NULL, NULL,
231 NULL, NULL, NULL, NULL,
232 NULL, NULL, NULL, NULL,
233 NULL, NULL, NULL, NULL,
234 };
235
236 static const char *kvm_feature_name[] = {
237 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
238 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", "kvm_pv_unhalt",
239 NULL, NULL, NULL, NULL,
240 NULL, NULL, NULL, NULL,
241 NULL, NULL, NULL, NULL,
242 NULL, NULL, NULL, NULL,
243 NULL, NULL, NULL, NULL,
244 NULL, NULL, NULL, NULL,
245 };
246
247 static const char *svm_feature_name[] = {
248 "npt", "lbrv", "svm_lock", "nrip_save",
249 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
250 NULL, NULL, "pause_filter", NULL,
251 "pfthreshold", NULL, NULL, NULL,
252 NULL, NULL, NULL, NULL,
253 NULL, NULL, NULL, NULL,
254 NULL, NULL, NULL, NULL,
255 NULL, NULL, NULL, NULL,
256 };
257
258 static const char *cpuid_7_0_ebx_feature_name[] = {
259 "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
260 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
261 NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
262 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
263 };
264
265 typedef struct FeatureWordInfo {
266 const char **feat_names;
267 uint32_t cpuid_eax; /* Input EAX for CPUID */
268 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
269 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
270 int cpuid_reg; /* output register (R_* constant) */
271 } FeatureWordInfo;
272
273 static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
274 [FEAT_1_EDX] = {
275 .feat_names = feature_name,
276 .cpuid_eax = 1, .cpuid_reg = R_EDX,
277 },
278 [FEAT_1_ECX] = {
279 .feat_names = ext_feature_name,
280 .cpuid_eax = 1, .cpuid_reg = R_ECX,
281 },
282 [FEAT_8000_0001_EDX] = {
283 .feat_names = ext2_feature_name,
284 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
285 },
286 [FEAT_8000_0001_ECX] = {
287 .feat_names = ext3_feature_name,
288 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
289 },
290 [FEAT_C000_0001_EDX] = {
291 .feat_names = ext4_feature_name,
292 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
293 },
294 [FEAT_KVM] = {
295 .feat_names = kvm_feature_name,
296 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
297 },
298 [FEAT_SVM] = {
299 .feat_names = svm_feature_name,
300 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
301 },
302 [FEAT_7_0_EBX] = {
303 .feat_names = cpuid_7_0_ebx_feature_name,
304 .cpuid_eax = 7,
305 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
306 .cpuid_reg = R_EBX,
307 },
308 };
309
310 typedef struct X86RegisterInfo32 {
311 /* Name of register */
312 const char *name;
313 /* QAPI enum value register */
314 X86CPURegister32 qapi_enum;
315 } X86RegisterInfo32;
316
317 #define REGISTER(reg) \
318 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
319 X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
320 REGISTER(EAX),
321 REGISTER(ECX),
322 REGISTER(EDX),
323 REGISTER(EBX),
324 REGISTER(ESP),
325 REGISTER(EBP),
326 REGISTER(ESI),
327 REGISTER(EDI),
328 };
329 #undef REGISTER
330
331 typedef struct ExtSaveArea {
332 uint32_t feature, bits;
333 uint32_t offset, size;
334 } ExtSaveArea;
335
336 static const ExtSaveArea ext_save_areas[] = {
337 [2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
338 .offset = 0x240, .size = 0x100 },
339 [3] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
340 .offset = 0x3c0, .size = 0x40 },
341 [4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
342 .offset = 0x400, .size = 0x40 },
343 };
344
345 const char *get_register_name_32(unsigned int reg)
346 {
347 if (reg >= CPU_NB_REGS32) {
348 return NULL;
349 }
350 return x86_reg_info_32[reg].name;
351 }
352
353 /* collects per-function cpuid data
354 */
355 typedef struct model_features_t {
356 uint32_t *guest_feat;
357 uint32_t *host_feat;
358 FeatureWord feat_word;
359 } model_features_t;
360
361 /* KVM-specific features that are automatically added to all CPU models
362 * when KVM is enabled.
363 */
364 static uint32_t kvm_default_features[FEATURE_WORDS] = {
365 [FEAT_KVM] = (1 << KVM_FEATURE_CLOCKSOURCE) |
366 (1 << KVM_FEATURE_NOP_IO_DELAY) |
367 (1 << KVM_FEATURE_CLOCKSOURCE2) |
368 (1 << KVM_FEATURE_ASYNC_PF) |
369 (1 << KVM_FEATURE_STEAL_TIME) |
370 (1 << KVM_FEATURE_PV_EOI) |
371 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT),
372 };
373
374 void disable_kvm_pv_eoi(void)
375 {
376 kvm_default_features[FEAT_KVM] &= ~(1UL << KVM_FEATURE_PV_EOI);
377 }
378
379 void host_cpuid(uint32_t function, uint32_t count,
380 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
381 {
382 uint32_t vec[4];
383
384 #ifdef __x86_64__
385 asm volatile("cpuid"
386 : "=a"(vec[0]), "=b"(vec[1]),
387 "=c"(vec[2]), "=d"(vec[3])
388 : "0"(function), "c"(count) : "cc");
389 #elif defined(__i386__)
390 asm volatile("pusha \n\t"
391 "cpuid \n\t"
392 "mov %%eax, 0(%2) \n\t"
393 "mov %%ebx, 4(%2) \n\t"
394 "mov %%ecx, 8(%2) \n\t"
395 "mov %%edx, 12(%2) \n\t"
396 "popa"
397 : : "a"(function), "c"(count), "S"(vec)
398 : "memory", "cc");
399 #else
400 abort();
401 #endif
402
403 if (eax)
404 *eax = vec[0];
405 if (ebx)
406 *ebx = vec[1];
407 if (ecx)
408 *ecx = vec[2];
409 if (edx)
410 *edx = vec[3];
411 }
412
413 #define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
414
415 /* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
416 * a substring. ex if !NULL points to the first char after a substring,
417 * otherwise the string is assumed to sized by a terminating nul.
418 * Return lexical ordering of *s1:*s2.
419 */
420 static int sstrcmp(const char *s1, const char *e1, const char *s2,
421 const char *e2)
422 {
423 for (;;) {
424 if (!*s1 || !*s2 || *s1 != *s2)
425 return (*s1 - *s2);
426 ++s1, ++s2;
427 if (s1 == e1 && s2 == e2)
428 return (0);
429 else if (s1 == e1)
430 return (*s2);
431 else if (s2 == e2)
432 return (*s1);
433 }
434 }
435
436 /* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
437 * '|' delimited (possibly empty) strings in which case search for a match
438 * within the alternatives proceeds left to right. Return 0 for success,
439 * non-zero otherwise.
440 */
441 static int altcmp(const char *s, const char *e, const char *altstr)
442 {
443 const char *p, *q;
444
445 for (q = p = altstr; ; ) {
446 while (*p && *p != '|')
447 ++p;
448 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
449 return (0);
450 if (!*p)
451 return (1);
452 else
453 q = ++p;
454 }
455 }
456
457 /* search featureset for flag *[s..e), if found set corresponding bit in
458 * *pval and return true, otherwise return false
459 */
460 static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
461 const char **featureset)
462 {
463 uint32_t mask;
464 const char **ppc;
465 bool found = false;
466
467 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
468 if (*ppc && !altcmp(s, e, *ppc)) {
469 *pval |= mask;
470 found = true;
471 }
472 }
473 return found;
474 }
475
476 static void add_flagname_to_bitmaps(const char *flagname,
477 FeatureWordArray words)
478 {
479 FeatureWord w;
480 for (w = 0; w < FEATURE_WORDS; w++) {
481 FeatureWordInfo *wi = &feature_word_info[w];
482 if (wi->feat_names &&
483 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
484 break;
485 }
486 }
487 if (w == FEATURE_WORDS) {
488 fprintf(stderr, "CPU feature %s not found\n", flagname);
489 }
490 }
491
492 typedef struct X86CPUDefinition {
493 const char *name;
494 uint32_t level;
495 uint32_t xlevel;
496 uint32_t xlevel2;
497 /* vendor is zero-terminated, 12 character ASCII string */
498 char vendor[CPUID_VENDOR_SZ + 1];
499 int family;
500 int model;
501 int stepping;
502 FeatureWordArray features;
503 char model_id[48];
504 bool cache_info_passthrough;
505 } X86CPUDefinition;
506
507 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
508 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
509 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
510 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
511 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
512 CPUID_PSE36 | CPUID_FXSR)
513 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
514 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
515 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
516 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
517 CPUID_PAE | CPUID_SEP | CPUID_APIC)
518
519 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
520 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
521 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
522 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
523 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
524 /* partly implemented:
525 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
526 CPUID_PSE36 (needed for Solaris) */
527 /* missing:
528 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
529 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
530 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
531 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
532 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
533 /* missing:
534 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
535 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
536 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
537 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_XSAVE,
538 CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C,
539 CPUID_EXT_RDRAND */
540 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
541 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
542 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
543 /* missing:
544 CPUID_EXT2_PDPE1GB */
545 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
546 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
547 #define TCG_SVM_FEATURES 0
548 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP \
549 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX)
550 /* missing:
551 CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
552 CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
553 CPUID_7_0_EBX_RDSEED */
554
555 /* built-in CPU model definitions
556 */
557 static X86CPUDefinition builtin_x86_defs[] = {
558 {
559 .name = "qemu64",
560 .level = 4,
561 .vendor = CPUID_VENDOR_AMD,
562 .family = 6,
563 .model = 6,
564 .stepping = 3,
565 .features[FEAT_1_EDX] =
566 PPRO_FEATURES |
567 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
568 CPUID_PSE36,
569 .features[FEAT_1_ECX] =
570 CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
571 .features[FEAT_8000_0001_EDX] =
572 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
573 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
574 .features[FEAT_8000_0001_ECX] =
575 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
576 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
577 .xlevel = 0x8000000A,
578 },
579 {
580 .name = "phenom",
581 .level = 5,
582 .vendor = CPUID_VENDOR_AMD,
583 .family = 16,
584 .model = 2,
585 .stepping = 3,
586 .features[FEAT_1_EDX] =
587 PPRO_FEATURES |
588 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
589 CPUID_PSE36 | CPUID_VME | CPUID_HT,
590 .features[FEAT_1_ECX] =
591 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
592 CPUID_EXT_POPCNT,
593 .features[FEAT_8000_0001_EDX] =
594 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
595 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
596 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
597 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
598 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
599 CPUID_EXT3_CR8LEG,
600 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
601 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
602 .features[FEAT_8000_0001_ECX] =
603 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
604 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
605 .features[FEAT_SVM] =
606 CPUID_SVM_NPT | CPUID_SVM_LBRV,
607 .xlevel = 0x8000001A,
608 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
609 },
610 {
611 .name = "core2duo",
612 .level = 10,
613 .vendor = CPUID_VENDOR_INTEL,
614 .family = 6,
615 .model = 15,
616 .stepping = 11,
617 .features[FEAT_1_EDX] =
618 PPRO_FEATURES |
619 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
620 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
621 CPUID_HT | CPUID_TM | CPUID_PBE,
622 .features[FEAT_1_ECX] =
623 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
624 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
625 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
626 .features[FEAT_8000_0001_EDX] =
627 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
628 .features[FEAT_8000_0001_ECX] =
629 CPUID_EXT3_LAHF_LM,
630 .xlevel = 0x80000008,
631 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
632 },
633 {
634 .name = "kvm64",
635 .level = 5,
636 .vendor = CPUID_VENDOR_INTEL,
637 .family = 15,
638 .model = 6,
639 .stepping = 1,
640 /* Missing: CPUID_VME, CPUID_HT */
641 .features[FEAT_1_EDX] =
642 PPRO_FEATURES |
643 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
644 CPUID_PSE36,
645 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
646 .features[FEAT_1_ECX] =
647 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
648 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
649 .features[FEAT_8000_0001_EDX] =
650 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
651 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
652 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
653 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
654 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
655 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
656 .features[FEAT_8000_0001_ECX] =
657 0,
658 .xlevel = 0x80000008,
659 .model_id = "Common KVM processor"
660 },
661 {
662 .name = "qemu32",
663 .level = 4,
664 .vendor = CPUID_VENDOR_INTEL,
665 .family = 6,
666 .model = 6,
667 .stepping = 3,
668 .features[FEAT_1_EDX] =
669 PPRO_FEATURES,
670 .features[FEAT_1_ECX] =
671 CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
672 .xlevel = 0x80000004,
673 },
674 {
675 .name = "kvm32",
676 .level = 5,
677 .vendor = CPUID_VENDOR_INTEL,
678 .family = 15,
679 .model = 6,
680 .stepping = 1,
681 .features[FEAT_1_EDX] =
682 PPRO_FEATURES |
683 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
684 .features[FEAT_1_ECX] =
685 CPUID_EXT_SSE3,
686 .features[FEAT_8000_0001_EDX] =
687 PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
688 .features[FEAT_8000_0001_ECX] =
689 0,
690 .xlevel = 0x80000008,
691 .model_id = "Common 32-bit KVM processor"
692 },
693 {
694 .name = "coreduo",
695 .level = 10,
696 .vendor = CPUID_VENDOR_INTEL,
697 .family = 6,
698 .model = 14,
699 .stepping = 8,
700 .features[FEAT_1_EDX] =
701 PPRO_FEATURES | CPUID_VME |
702 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
703 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
704 .features[FEAT_1_ECX] =
705 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
706 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
707 .features[FEAT_8000_0001_EDX] =
708 CPUID_EXT2_NX,
709 .xlevel = 0x80000008,
710 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
711 },
712 {
713 .name = "486",
714 .level = 1,
715 .vendor = CPUID_VENDOR_INTEL,
716 .family = 4,
717 .model = 8,
718 .stepping = 0,
719 .features[FEAT_1_EDX] =
720 I486_FEATURES,
721 .xlevel = 0,
722 },
723 {
724 .name = "pentium",
725 .level = 1,
726 .vendor = CPUID_VENDOR_INTEL,
727 .family = 5,
728 .model = 4,
729 .stepping = 3,
730 .features[FEAT_1_EDX] =
731 PENTIUM_FEATURES,
732 .xlevel = 0,
733 },
734 {
735 .name = "pentium2",
736 .level = 2,
737 .vendor = CPUID_VENDOR_INTEL,
738 .family = 6,
739 .model = 5,
740 .stepping = 2,
741 .features[FEAT_1_EDX] =
742 PENTIUM2_FEATURES,
743 .xlevel = 0,
744 },
745 {
746 .name = "pentium3",
747 .level = 2,
748 .vendor = CPUID_VENDOR_INTEL,
749 .family = 6,
750 .model = 7,
751 .stepping = 3,
752 .features[FEAT_1_EDX] =
753 PENTIUM3_FEATURES,
754 .xlevel = 0,
755 },
756 {
757 .name = "athlon",
758 .level = 2,
759 .vendor = CPUID_VENDOR_AMD,
760 .family = 6,
761 .model = 2,
762 .stepping = 3,
763 .features[FEAT_1_EDX] =
764 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
765 CPUID_MCA,
766 .features[FEAT_8000_0001_EDX] =
767 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
768 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
769 .xlevel = 0x80000008,
770 },
771 {
772 .name = "n270",
773 /* original is on level 10 */
774 .level = 5,
775 .vendor = CPUID_VENDOR_INTEL,
776 .family = 6,
777 .model = 28,
778 .stepping = 2,
779 .features[FEAT_1_EDX] =
780 PPRO_FEATURES |
781 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
782 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
783 /* Some CPUs got no CPUID_SEP */
784 .features[FEAT_1_ECX] =
785 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
786 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR |
787 CPUID_EXT_MOVBE,
788 .features[FEAT_8000_0001_EDX] =
789 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
790 CPUID_EXT2_NX,
791 .features[FEAT_8000_0001_ECX] =
792 CPUID_EXT3_LAHF_LM,
793 .xlevel = 0x8000000A,
794 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
795 },
796 {
797 .name = "Conroe",
798 .level = 4,
799 .vendor = CPUID_VENDOR_INTEL,
800 .family = 6,
801 .model = 15,
802 .stepping = 3,
803 .features[FEAT_1_EDX] =
804 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
805 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
806 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
807 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
808 CPUID_DE | CPUID_FP87,
809 .features[FEAT_1_ECX] =
810 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
811 .features[FEAT_8000_0001_EDX] =
812 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
813 .features[FEAT_8000_0001_ECX] =
814 CPUID_EXT3_LAHF_LM,
815 .xlevel = 0x8000000A,
816 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
817 },
818 {
819 .name = "Penryn",
820 .level = 4,
821 .vendor = CPUID_VENDOR_INTEL,
822 .family = 6,
823 .model = 23,
824 .stepping = 3,
825 .features[FEAT_1_EDX] =
826 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
827 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
828 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
829 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
830 CPUID_DE | CPUID_FP87,
831 .features[FEAT_1_ECX] =
832 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
833 CPUID_EXT_SSE3,
834 .features[FEAT_8000_0001_EDX] =
835 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
836 .features[FEAT_8000_0001_ECX] =
837 CPUID_EXT3_LAHF_LM,
838 .xlevel = 0x8000000A,
839 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
840 },
841 {
842 .name = "Nehalem",
843 .level = 4,
844 .vendor = CPUID_VENDOR_INTEL,
845 .family = 6,
846 .model = 26,
847 .stepping = 3,
848 .features[FEAT_1_EDX] =
849 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
850 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
851 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
852 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
853 CPUID_DE | CPUID_FP87,
854 .features[FEAT_1_ECX] =
855 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
856 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
857 .features[FEAT_8000_0001_EDX] =
858 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
859 .features[FEAT_8000_0001_ECX] =
860 CPUID_EXT3_LAHF_LM,
861 .xlevel = 0x8000000A,
862 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
863 },
864 {
865 .name = "Westmere",
866 .level = 11,
867 .vendor = CPUID_VENDOR_INTEL,
868 .family = 6,
869 .model = 44,
870 .stepping = 1,
871 .features[FEAT_1_EDX] =
872 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
873 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
874 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
875 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
876 CPUID_DE | CPUID_FP87,
877 .features[FEAT_1_ECX] =
878 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
879 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
880 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
881 .features[FEAT_8000_0001_EDX] =
882 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
883 .features[FEAT_8000_0001_ECX] =
884 CPUID_EXT3_LAHF_LM,
885 .xlevel = 0x8000000A,
886 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
887 },
888 {
889 .name = "SandyBridge",
890 .level = 0xd,
891 .vendor = CPUID_VENDOR_INTEL,
892 .family = 6,
893 .model = 42,
894 .stepping = 1,
895 .features[FEAT_1_EDX] =
896 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
897 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
898 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
899 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
900 CPUID_DE | CPUID_FP87,
901 .features[FEAT_1_ECX] =
902 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
903 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
904 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
905 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
906 CPUID_EXT_SSE3,
907 .features[FEAT_8000_0001_EDX] =
908 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
909 CPUID_EXT2_SYSCALL,
910 .features[FEAT_8000_0001_ECX] =
911 CPUID_EXT3_LAHF_LM,
912 .xlevel = 0x8000000A,
913 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
914 },
915 {
916 .name = "Haswell",
917 .level = 0xd,
918 .vendor = CPUID_VENDOR_INTEL,
919 .family = 6,
920 .model = 60,
921 .stepping = 1,
922 .features[FEAT_1_EDX] =
923 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
924 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
925 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
926 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
927 CPUID_DE | CPUID_FP87,
928 .features[FEAT_1_ECX] =
929 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
930 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
931 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
932 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
933 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
934 CPUID_EXT_PCID,
935 .features[FEAT_8000_0001_EDX] =
936 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
937 CPUID_EXT2_SYSCALL,
938 .features[FEAT_8000_0001_ECX] =
939 CPUID_EXT3_LAHF_LM,
940 .features[FEAT_7_0_EBX] =
941 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
942 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
943 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
944 CPUID_7_0_EBX_RTM,
945 .xlevel = 0x8000000A,
946 .model_id = "Intel Core Processor (Haswell)",
947 },
948 {
949 .name = "Opteron_G1",
950 .level = 5,
951 .vendor = CPUID_VENDOR_AMD,
952 .family = 15,
953 .model = 6,
954 .stepping = 1,
955 .features[FEAT_1_EDX] =
956 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
957 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
958 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
959 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
960 CPUID_DE | CPUID_FP87,
961 .features[FEAT_1_ECX] =
962 CPUID_EXT_SSE3,
963 .features[FEAT_8000_0001_EDX] =
964 CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
965 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
966 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
967 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
968 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
969 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
970 .xlevel = 0x80000008,
971 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
972 },
973 {
974 .name = "Opteron_G2",
975 .level = 5,
976 .vendor = CPUID_VENDOR_AMD,
977 .family = 15,
978 .model = 6,
979 .stepping = 1,
980 .features[FEAT_1_EDX] =
981 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
982 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
983 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
984 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
985 CPUID_DE | CPUID_FP87,
986 .features[FEAT_1_ECX] =
987 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
988 .features[FEAT_8000_0001_EDX] =
989 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
990 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
991 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
992 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
993 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
994 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
995 CPUID_EXT2_DE | CPUID_EXT2_FPU,
996 .features[FEAT_8000_0001_ECX] =
997 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
998 .xlevel = 0x80000008,
999 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
1000 },
1001 {
1002 .name = "Opteron_G3",
1003 .level = 5,
1004 .vendor = CPUID_VENDOR_AMD,
1005 .family = 15,
1006 .model = 6,
1007 .stepping = 1,
1008 .features[FEAT_1_EDX] =
1009 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1010 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1011 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1012 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1013 CPUID_DE | CPUID_FP87,
1014 .features[FEAT_1_ECX] =
1015 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
1016 CPUID_EXT_SSE3,
1017 .features[FEAT_8000_0001_EDX] =
1018 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
1019 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1020 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1021 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1022 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1023 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1024 CPUID_EXT2_DE | CPUID_EXT2_FPU,
1025 .features[FEAT_8000_0001_ECX] =
1026 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
1027 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
1028 .xlevel = 0x80000008,
1029 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1030 },
1031 {
1032 .name = "Opteron_G4",
1033 .level = 0xd,
1034 .vendor = CPUID_VENDOR_AMD,
1035 .family = 21,
1036 .model = 1,
1037 .stepping = 2,
1038 .features[FEAT_1_EDX] =
1039 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1040 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1041 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1042 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1043 CPUID_DE | CPUID_FP87,
1044 .features[FEAT_1_ECX] =
1045 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1046 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1047 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1048 CPUID_EXT_SSE3,
1049 .features[FEAT_8000_0001_EDX] =
1050 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
1051 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1052 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1053 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1054 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1055 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1056 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
1057 .features[FEAT_8000_0001_ECX] =
1058 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
1059 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1060 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1061 CPUID_EXT3_LAHF_LM,
1062 .xlevel = 0x8000001A,
1063 .model_id = "AMD Opteron 62xx class CPU",
1064 },
1065 {
1066 .name = "Opteron_G5",
1067 .level = 0xd,
1068 .vendor = CPUID_VENDOR_AMD,
1069 .family = 21,
1070 .model = 2,
1071 .stepping = 0,
1072 .features[FEAT_1_EDX] =
1073 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1074 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1075 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1076 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1077 CPUID_DE | CPUID_FP87,
1078 .features[FEAT_1_ECX] =
1079 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
1080 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1081 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1082 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
1083 .features[FEAT_8000_0001_EDX] =
1084 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
1085 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1086 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1087 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1088 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1089 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1090 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
1091 .features[FEAT_8000_0001_ECX] =
1092 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
1093 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1094 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1095 CPUID_EXT3_LAHF_LM,
1096 .xlevel = 0x8000001A,
1097 .model_id = "AMD Opteron 63xx class CPU",
1098 },
1099 };
1100
1101 /**
1102 * x86_cpu_compat_set_features:
1103 * @cpu_model: CPU model name to be changed. If NULL, all CPU models are changed
1104 * @w: Identifies the feature word to be changed.
1105 * @feat_add: Feature bits to be added to feature word
1106 * @feat_remove: Feature bits to be removed from feature word
1107 *
1108 * Change CPU model feature bits for compatibility.
1109 *
1110 * This function may be used by machine-type compatibility functions
1111 * to enable or disable feature bits on specific CPU models.
1112 */
1113 void x86_cpu_compat_set_features(const char *cpu_model, FeatureWord w,
1114 uint32_t feat_add, uint32_t feat_remove)
1115 {
1116 X86CPUDefinition *def;
1117 int i;
1118 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1119 def = &builtin_x86_defs[i];
1120 if (!cpu_model || !strcmp(cpu_model, def->name)) {
1121 def->features[w] |= feat_add;
1122 def->features[w] &= ~feat_remove;
1123 }
1124 }
1125 }
1126
1127 static int cpu_x86_fill_model_id(char *str)
1128 {
1129 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1130 int i;
1131
1132 for (i = 0; i < 3; i++) {
1133 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1134 memcpy(str + i * 16 + 0, &eax, 4);
1135 memcpy(str + i * 16 + 4, &ebx, 4);
1136 memcpy(str + i * 16 + 8, &ecx, 4);
1137 memcpy(str + i * 16 + 12, &edx, 4);
1138 }
1139 return 0;
1140 }
1141
1142 /* Fill a X86CPUDefinition struct with information about the host CPU, and
1143 * the CPU features supported by the host hardware + host kernel
1144 *
1145 * This function may be called only if KVM is enabled.
1146 */
1147 static void kvm_cpu_fill_host(X86CPUDefinition *x86_cpu_def)
1148 {
1149 KVMState *s = kvm_state;
1150 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1151 FeatureWord w;
1152
1153 assert(kvm_enabled());
1154
1155 x86_cpu_def->name = "host";
1156 x86_cpu_def->cache_info_passthrough = true;
1157 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
1158 x86_cpu_vendor_words2str(x86_cpu_def->vendor, ebx, edx, ecx);
1159
1160 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
1161 x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1162 x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1163 x86_cpu_def->stepping = eax & 0x0F;
1164
1165 x86_cpu_def->level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
1166 x86_cpu_def->xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1167 x86_cpu_def->xlevel2 =
1168 kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
1169
1170 cpu_x86_fill_model_id(x86_cpu_def->model_id);
1171
1172 for (w = 0; w < FEATURE_WORDS; w++) {
1173 FeatureWordInfo *wi = &feature_word_info[w];
1174 x86_cpu_def->features[w] =
1175 kvm_arch_get_supported_cpuid(s, wi->cpuid_eax, wi->cpuid_ecx,
1176 wi->cpuid_reg);
1177 }
1178 }
1179
1180 static int unavailable_host_feature(FeatureWordInfo *f, uint32_t mask)
1181 {
1182 int i;
1183
1184 for (i = 0; i < 32; ++i)
1185 if (1 << i & mask) {
1186 const char *reg = get_register_name_32(f->cpuid_reg);
1187 assert(reg);
1188 fprintf(stderr, "warning: host doesn't support requested feature: "
1189 "CPUID.%02XH:%s%s%s [bit %d]\n",
1190 f->cpuid_eax, reg,
1191 f->feat_names[i] ? "." : "",
1192 f->feat_names[i] ? f->feat_names[i] : "", i);
1193 break;
1194 }
1195 return 0;
1196 }
1197
1198 /* Check if all requested cpu flags are making their way to the guest
1199 *
1200 * Returns 0 if all flags are supported by the host, non-zero otherwise.
1201 *
1202 * This function may be called only if KVM is enabled.
1203 */
1204 static int kvm_check_features_against_host(KVMState *s, X86CPU *cpu)
1205 {
1206 CPUX86State *env = &cpu->env;
1207 int rv = 0;
1208 FeatureWord w;
1209
1210 assert(kvm_enabled());
1211
1212 for (w = 0; w < FEATURE_WORDS; w++) {
1213 FeatureWordInfo *wi = &feature_word_info[w];
1214 uint32_t guest_feat = env->features[w];
1215 uint32_t host_feat = kvm_arch_get_supported_cpuid(s, wi->cpuid_eax,
1216 wi->cpuid_ecx,
1217 wi->cpuid_reg);
1218 uint32_t mask;
1219 for (mask = 1; mask; mask <<= 1) {
1220 if (guest_feat & mask && !(host_feat & mask)) {
1221 unavailable_host_feature(wi, mask);
1222 rv = 1;
1223 }
1224 }
1225 }
1226 return rv;
1227 }
1228
1229 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1230 const char *name, Error **errp)
1231 {
1232 X86CPU *cpu = X86_CPU(obj);
1233 CPUX86State *env = &cpu->env;
1234 int64_t value;
1235
1236 value = (env->cpuid_version >> 8) & 0xf;
1237 if (value == 0xf) {
1238 value += (env->cpuid_version >> 20) & 0xff;
1239 }
1240 visit_type_int(v, &value, name, errp);
1241 }
1242
1243 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1244 const char *name, Error **errp)
1245 {
1246 X86CPU *cpu = X86_CPU(obj);
1247 CPUX86State *env = &cpu->env;
1248 const int64_t min = 0;
1249 const int64_t max = 0xff + 0xf;
1250 int64_t value;
1251
1252 visit_type_int(v, &value, name, errp);
1253 if (error_is_set(errp)) {
1254 return;
1255 }
1256 if (value < min || value > max) {
1257 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1258 name ? name : "null", value, min, max);
1259 return;
1260 }
1261
1262 env->cpuid_version &= ~0xff00f00;
1263 if (value > 0x0f) {
1264 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
1265 } else {
1266 env->cpuid_version |= value << 8;
1267 }
1268 }
1269
1270 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1271 const char *name, Error **errp)
1272 {
1273 X86CPU *cpu = X86_CPU(obj);
1274 CPUX86State *env = &cpu->env;
1275 int64_t value;
1276
1277 value = (env->cpuid_version >> 4) & 0xf;
1278 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1279 visit_type_int(v, &value, name, errp);
1280 }
1281
1282 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1283 const char *name, Error **errp)
1284 {
1285 X86CPU *cpu = X86_CPU(obj);
1286 CPUX86State *env = &cpu->env;
1287 const int64_t min = 0;
1288 const int64_t max = 0xff;
1289 int64_t value;
1290
1291 visit_type_int(v, &value, name, errp);
1292 if (error_is_set(errp)) {
1293 return;
1294 }
1295 if (value < min || value > max) {
1296 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1297 name ? name : "null", value, min, max);
1298 return;
1299 }
1300
1301 env->cpuid_version &= ~0xf00f0;
1302 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
1303 }
1304
1305 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1306 void *opaque, const char *name,
1307 Error **errp)
1308 {
1309 X86CPU *cpu = X86_CPU(obj);
1310 CPUX86State *env = &cpu->env;
1311 int64_t value;
1312
1313 value = env->cpuid_version & 0xf;
1314 visit_type_int(v, &value, name, errp);
1315 }
1316
1317 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1318 void *opaque, const char *name,
1319 Error **errp)
1320 {
1321 X86CPU *cpu = X86_CPU(obj);
1322 CPUX86State *env = &cpu->env;
1323 const int64_t min = 0;
1324 const int64_t max = 0xf;
1325 int64_t value;
1326
1327 visit_type_int(v, &value, name, errp);
1328 if (error_is_set(errp)) {
1329 return;
1330 }
1331 if (value < min || value > max) {
1332 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1333 name ? name : "null", value, min, max);
1334 return;
1335 }
1336
1337 env->cpuid_version &= ~0xf;
1338 env->cpuid_version |= value & 0xf;
1339 }
1340
1341 static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1342 const char *name, Error **errp)
1343 {
1344 X86CPU *cpu = X86_CPU(obj);
1345
1346 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1347 }
1348
1349 static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1350 const char *name, Error **errp)
1351 {
1352 X86CPU *cpu = X86_CPU(obj);
1353
1354 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1355 }
1356
1357 static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1358 const char *name, Error **errp)
1359 {
1360 X86CPU *cpu = X86_CPU(obj);
1361
1362 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1363 }
1364
1365 static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1366 const char *name, Error **errp)
1367 {
1368 X86CPU *cpu = X86_CPU(obj);
1369
1370 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1371 }
1372
1373 static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1374 {
1375 X86CPU *cpu = X86_CPU(obj);
1376 CPUX86State *env = &cpu->env;
1377 char *value;
1378
1379 value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
1380 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1381 env->cpuid_vendor3);
1382 return value;
1383 }
1384
1385 static void x86_cpuid_set_vendor(Object *obj, const char *value,
1386 Error **errp)
1387 {
1388 X86CPU *cpu = X86_CPU(obj);
1389 CPUX86State *env = &cpu->env;
1390 int i;
1391
1392 if (strlen(value) != CPUID_VENDOR_SZ) {
1393 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1394 "vendor", value);
1395 return;
1396 }
1397
1398 env->cpuid_vendor1 = 0;
1399 env->cpuid_vendor2 = 0;
1400 env->cpuid_vendor3 = 0;
1401 for (i = 0; i < 4; i++) {
1402 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1403 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1404 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1405 }
1406 }
1407
1408 static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1409 {
1410 X86CPU *cpu = X86_CPU(obj);
1411 CPUX86State *env = &cpu->env;
1412 char *value;
1413 int i;
1414
1415 value = g_malloc(48 + 1);
1416 for (i = 0; i < 48; i++) {
1417 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1418 }
1419 value[48] = '\0';
1420 return value;
1421 }
1422
1423 static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1424 Error **errp)
1425 {
1426 X86CPU *cpu = X86_CPU(obj);
1427 CPUX86State *env = &cpu->env;
1428 int c, len, i;
1429
1430 if (model_id == NULL) {
1431 model_id = "";
1432 }
1433 len = strlen(model_id);
1434 memset(env->cpuid_model, 0, 48);
1435 for (i = 0; i < 48; i++) {
1436 if (i >= len) {
1437 c = '\0';
1438 } else {
1439 c = (uint8_t)model_id[i];
1440 }
1441 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1442 }
1443 }
1444
1445 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1446 const char *name, Error **errp)
1447 {
1448 X86CPU *cpu = X86_CPU(obj);
1449 int64_t value;
1450
1451 value = cpu->env.tsc_khz * 1000;
1452 visit_type_int(v, &value, name, errp);
1453 }
1454
1455 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1456 const char *name, Error **errp)
1457 {
1458 X86CPU *cpu = X86_CPU(obj);
1459 const int64_t min = 0;
1460 const int64_t max = INT64_MAX;
1461 int64_t value;
1462
1463 visit_type_int(v, &value, name, errp);
1464 if (error_is_set(errp)) {
1465 return;
1466 }
1467 if (value < min || value > max) {
1468 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1469 name ? name : "null", value, min, max);
1470 return;
1471 }
1472
1473 cpu->env.tsc_khz = value / 1000;
1474 }
1475
1476 static void x86_cpuid_get_apic_id(Object *obj, Visitor *v, void *opaque,
1477 const char *name, Error **errp)
1478 {
1479 X86CPU *cpu = X86_CPU(obj);
1480 int64_t value = cpu->env.cpuid_apic_id;
1481
1482 visit_type_int(v, &value, name, errp);
1483 }
1484
1485 static void x86_cpuid_set_apic_id(Object *obj, Visitor *v, void *opaque,
1486 const char *name, Error **errp)
1487 {
1488 X86CPU *cpu = X86_CPU(obj);
1489 DeviceState *dev = DEVICE(obj);
1490 const int64_t min = 0;
1491 const int64_t max = UINT32_MAX;
1492 Error *error = NULL;
1493 int64_t value;
1494
1495 if (dev->realized) {
1496 error_setg(errp, "Attempt to set property '%s' on '%s' after "
1497 "it was realized", name, object_get_typename(obj));
1498 return;
1499 }
1500
1501 visit_type_int(v, &value, name, &error);
1502 if (error) {
1503 error_propagate(errp, error);
1504 return;
1505 }
1506 if (value < min || value > max) {
1507 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1508 " (minimum: %" PRId64 ", maximum: %" PRId64 ")" ,
1509 object_get_typename(obj), name, value, min, max);
1510 return;
1511 }
1512
1513 if ((value != cpu->env.cpuid_apic_id) && cpu_exists(value)) {
1514 error_setg(errp, "CPU with APIC ID %" PRIi64 " exists", value);
1515 return;
1516 }
1517 cpu->env.cpuid_apic_id = value;
1518 }
1519
1520 /* Generic getter for "feature-words" and "filtered-features" properties */
1521 static void x86_cpu_get_feature_words(Object *obj, Visitor *v, void *opaque,
1522 const char *name, Error **errp)
1523 {
1524 uint32_t *array = (uint32_t *)opaque;
1525 FeatureWord w;
1526 Error *err = NULL;
1527 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1528 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1529 X86CPUFeatureWordInfoList *list = NULL;
1530
1531 for (w = 0; w < FEATURE_WORDS; w++) {
1532 FeatureWordInfo *wi = &feature_word_info[w];
1533 X86CPUFeatureWordInfo *qwi = &word_infos[w];
1534 qwi->cpuid_input_eax = wi->cpuid_eax;
1535 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1536 qwi->cpuid_input_ecx = wi->cpuid_ecx;
1537 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
1538 qwi->features = array[w];
1539
1540 /* List will be in reverse order, but order shouldn't matter */
1541 list_entries[w].next = list;
1542 list_entries[w].value = &word_infos[w];
1543 list = &list_entries[w];
1544 }
1545
1546 visit_type_X86CPUFeatureWordInfoList(v, &list, "feature-words", &err);
1547 error_propagate(errp, err);
1548 }
1549
1550 static void x86_get_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1551 const char *name, Error **errp)
1552 {
1553 X86CPU *cpu = X86_CPU(obj);
1554 int64_t value = cpu->hyperv_spinlock_attempts;
1555
1556 visit_type_int(v, &value, name, errp);
1557 }
1558
1559 static void x86_set_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1560 const char *name, Error **errp)
1561 {
1562 const int64_t min = 0xFFF;
1563 const int64_t max = UINT_MAX;
1564 X86CPU *cpu = X86_CPU(obj);
1565 Error *err = NULL;
1566 int64_t value;
1567
1568 visit_type_int(v, &value, name, &err);
1569 if (err) {
1570 error_propagate(errp, err);
1571 return;
1572 }
1573
1574 if (value < min || value > max) {
1575 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1576 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
1577 object_get_typename(obj), name ? name : "null",
1578 value, min, max);
1579 return;
1580 }
1581 cpu->hyperv_spinlock_attempts = value;
1582 }
1583
1584 static PropertyInfo qdev_prop_spinlocks = {
1585 .name = "int",
1586 .get = x86_get_hv_spinlocks,
1587 .set = x86_set_hv_spinlocks,
1588 };
1589
1590 static int cpu_x86_find_by_name(X86CPU *cpu, X86CPUDefinition *x86_cpu_def,
1591 const char *name)
1592 {
1593 X86CPUDefinition *def;
1594 int i;
1595
1596 if (name == NULL) {
1597 return -1;
1598 }
1599 if (kvm_enabled() && strcmp(name, "host") == 0) {
1600 kvm_cpu_fill_host(x86_cpu_def);
1601 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
1602 return 0;
1603 }
1604
1605 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1606 def = &builtin_x86_defs[i];
1607 if (strcmp(name, def->name) == 0) {
1608 memcpy(x86_cpu_def, def, sizeof(*def));
1609 return 0;
1610 }
1611 }
1612
1613 return -1;
1614 }
1615
1616 /* Convert all '_' in a feature string option name to '-', to make feature
1617 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1618 */
1619 static inline void feat2prop(char *s)
1620 {
1621 while ((s = strchr(s, '_'))) {
1622 *s = '-';
1623 }
1624 }
1625
1626 /* Parse "+feature,-feature,feature=foo" CPU feature string
1627 */
1628 static void cpu_x86_parse_featurestr(X86CPU *cpu, char *features, Error **errp)
1629 {
1630 char *featurestr; /* Single 'key=value" string being parsed */
1631 /* Features to be added */
1632 FeatureWordArray plus_features = { 0 };
1633 /* Features to be removed */
1634 FeatureWordArray minus_features = { 0 };
1635 uint32_t numvalue;
1636 CPUX86State *env = &cpu->env;
1637
1638 featurestr = features ? strtok(features, ",") : NULL;
1639
1640 while (featurestr) {
1641 char *val;
1642 if (featurestr[0] == '+') {
1643 add_flagname_to_bitmaps(featurestr + 1, plus_features);
1644 } else if (featurestr[0] == '-') {
1645 add_flagname_to_bitmaps(featurestr + 1, minus_features);
1646 } else if ((val = strchr(featurestr, '='))) {
1647 *val = 0; val++;
1648 feat2prop(featurestr);
1649 if (!strcmp(featurestr, "xlevel")) {
1650 char *err;
1651 char num[32];
1652
1653 numvalue = strtoul(val, &err, 0);
1654 if (!*val || *err) {
1655 error_setg(errp, "bad numerical value %s", val);
1656 goto out;
1657 }
1658 if (numvalue < 0x80000000) {
1659 fprintf(stderr, "xlevel value shall always be >= 0x80000000"
1660 ", fixup will be removed in future versions\n");
1661 numvalue += 0x80000000;
1662 }
1663 snprintf(num, sizeof(num), "%" PRIu32, numvalue);
1664 object_property_parse(OBJECT(cpu), num, featurestr, errp);
1665 } else if (!strcmp(featurestr, "tsc-freq")) {
1666 int64_t tsc_freq;
1667 char *err;
1668 char num[32];
1669
1670 tsc_freq = strtosz_suffix_unit(val, &err,
1671 STRTOSZ_DEFSUFFIX_B, 1000);
1672 if (tsc_freq < 0 || *err) {
1673 error_setg(errp, "bad numerical value %s", val);
1674 goto out;
1675 }
1676 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
1677 object_property_parse(OBJECT(cpu), num, "tsc-frequency", errp);
1678 } else if (!strcmp(featurestr, "hv-spinlocks")) {
1679 char *err;
1680 const int min = 0xFFF;
1681 char num[32];
1682 numvalue = strtoul(val, &err, 0);
1683 if (!*val || *err) {
1684 error_setg(errp, "bad numerical value %s", val);
1685 goto out;
1686 }
1687 if (numvalue < min) {
1688 fprintf(stderr, "hv-spinlocks value shall always be >= 0x%x"
1689 ", fixup will be removed in future versions\n",
1690 min);
1691 numvalue = min;
1692 }
1693 snprintf(num, sizeof(num), "%" PRId32, numvalue);
1694 object_property_parse(OBJECT(cpu), num, featurestr, errp);
1695 } else {
1696 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1697 }
1698 } else {
1699 feat2prop(featurestr);
1700 object_property_parse(OBJECT(cpu), "on", featurestr, errp);
1701 }
1702 if (error_is_set(errp)) {
1703 goto out;
1704 }
1705 featurestr = strtok(NULL, ",");
1706 }
1707 env->features[FEAT_1_EDX] |= plus_features[FEAT_1_EDX];
1708 env->features[FEAT_1_ECX] |= plus_features[FEAT_1_ECX];
1709 env->features[FEAT_8000_0001_EDX] |= plus_features[FEAT_8000_0001_EDX];
1710 env->features[FEAT_8000_0001_ECX] |= plus_features[FEAT_8000_0001_ECX];
1711 env->features[FEAT_C000_0001_EDX] |= plus_features[FEAT_C000_0001_EDX];
1712 env->features[FEAT_KVM] |= plus_features[FEAT_KVM];
1713 env->features[FEAT_SVM] |= plus_features[FEAT_SVM];
1714 env->features[FEAT_7_0_EBX] |= plus_features[FEAT_7_0_EBX];
1715 env->features[FEAT_1_EDX] &= ~minus_features[FEAT_1_EDX];
1716 env->features[FEAT_1_ECX] &= ~minus_features[FEAT_1_ECX];
1717 env->features[FEAT_8000_0001_EDX] &= ~minus_features[FEAT_8000_0001_EDX];
1718 env->features[FEAT_8000_0001_ECX] &= ~minus_features[FEAT_8000_0001_ECX];
1719 env->features[FEAT_C000_0001_EDX] &= ~minus_features[FEAT_C000_0001_EDX];
1720 env->features[FEAT_KVM] &= ~minus_features[FEAT_KVM];
1721 env->features[FEAT_SVM] &= ~minus_features[FEAT_SVM];
1722 env->features[FEAT_7_0_EBX] &= ~minus_features[FEAT_7_0_EBX];
1723
1724 out:
1725 return;
1726 }
1727
1728 /* generate a composite string into buf of all cpuid names in featureset
1729 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1730 * if flags, suppress names undefined in featureset.
1731 */
1732 static void listflags(char *buf, int bufsize, uint32_t fbits,
1733 const char **featureset, uint32_t flags)
1734 {
1735 const char **p = &featureset[31];
1736 char *q, *b, bit;
1737 int nc;
1738
1739 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1740 *buf = '\0';
1741 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1742 if (fbits & 1 << bit && (*p || !flags)) {
1743 if (*p)
1744 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1745 else
1746 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1747 if (bufsize <= nc) {
1748 if (b) {
1749 memcpy(b, "...", sizeof("..."));
1750 }
1751 return;
1752 }
1753 q += nc;
1754 bufsize -= nc;
1755 }
1756 }
1757
1758 /* generate CPU information. */
1759 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1760 {
1761 X86CPUDefinition *def;
1762 char buf[256];
1763 int i;
1764
1765 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1766 def = &builtin_x86_defs[i];
1767 snprintf(buf, sizeof(buf), "%s", def->name);
1768 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
1769 }
1770 #ifdef CONFIG_KVM
1771 (*cpu_fprintf)(f, "x86 %16s %-48s\n", "host",
1772 "KVM processor with all supported host features "
1773 "(only available in KVM mode)");
1774 #endif
1775
1776 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
1777 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
1778 FeatureWordInfo *fw = &feature_word_info[i];
1779
1780 listflags(buf, sizeof(buf), (uint32_t)~0, fw->feat_names, 1);
1781 (*cpu_fprintf)(f, " %s\n", buf);
1782 }
1783 }
1784
1785 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
1786 {
1787 CpuDefinitionInfoList *cpu_list = NULL;
1788 X86CPUDefinition *def;
1789 int i;
1790
1791 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1792 CpuDefinitionInfoList *entry;
1793 CpuDefinitionInfo *info;
1794
1795 def = &builtin_x86_defs[i];
1796 info = g_malloc0(sizeof(*info));
1797 info->name = g_strdup(def->name);
1798
1799 entry = g_malloc0(sizeof(*entry));
1800 entry->value = info;
1801 entry->next = cpu_list;
1802 cpu_list = entry;
1803 }
1804
1805 return cpu_list;
1806 }
1807
1808 static void filter_features_for_kvm(X86CPU *cpu)
1809 {
1810 CPUX86State *env = &cpu->env;
1811 KVMState *s = kvm_state;
1812 FeatureWord w;
1813
1814 for (w = 0; w < FEATURE_WORDS; w++) {
1815 FeatureWordInfo *wi = &feature_word_info[w];
1816 uint32_t host_feat = kvm_arch_get_supported_cpuid(s, wi->cpuid_eax,
1817 wi->cpuid_ecx,
1818 wi->cpuid_reg);
1819 uint32_t requested_features = env->features[w];
1820 env->features[w] &= host_feat;
1821 cpu->filtered_features[w] = requested_features & ~env->features[w];
1822 }
1823 }
1824
1825 /* Load CPU definition for a given CPU model name
1826 */
1827 static void x86_cpu_load_def(X86CPU *cpu, const char *name, Error **errp)
1828 {
1829 CPUX86State *env = &cpu->env;
1830 X86CPUDefinition def1, *def = &def1;
1831 const char *vendor;
1832 char host_vendor[CPUID_VENDOR_SZ + 1];
1833
1834 memset(def, 0, sizeof(*def));
1835
1836 if (cpu_x86_find_by_name(cpu, def, name) < 0) {
1837 error_setg(errp, "Unable to find CPU definition: %s", name);
1838 return;
1839 }
1840
1841 object_property_set_int(OBJECT(cpu), def->level, "level", errp);
1842 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
1843 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
1844 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
1845 env->features[FEAT_1_EDX] = def->features[FEAT_1_EDX];
1846 env->features[FEAT_1_ECX] = def->features[FEAT_1_ECX];
1847 env->features[FEAT_8000_0001_EDX] = def->features[FEAT_8000_0001_EDX];
1848 env->features[FEAT_8000_0001_ECX] = def->features[FEAT_8000_0001_ECX];
1849 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);
1850 env->features[FEAT_KVM] = def->features[FEAT_KVM];
1851 env->features[FEAT_SVM] = def->features[FEAT_SVM];
1852 env->features[FEAT_C000_0001_EDX] = def->features[FEAT_C000_0001_EDX];
1853 env->features[FEAT_7_0_EBX] = def->features[FEAT_7_0_EBX];
1854 env->cpuid_xlevel2 = def->xlevel2;
1855 cpu->cache_info_passthrough = def->cache_info_passthrough;
1856
1857 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
1858
1859 /* Special cases not set in the X86CPUDefinition structs: */
1860 if (kvm_enabled()) {
1861 FeatureWord w;
1862 for (w = 0; w < FEATURE_WORDS; w++) {
1863 env->features[w] |= kvm_default_features[w];
1864 }
1865 }
1866
1867 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
1868
1869 /* sysenter isn't supported in compatibility mode on AMD,
1870 * syscall isn't supported in compatibility mode on Intel.
1871 * Normally we advertise the actual CPU vendor, but you can
1872 * override this using the 'vendor' property if you want to use
1873 * KVM's sysenter/syscall emulation in compatibility mode and
1874 * when doing cross vendor migration
1875 */
1876 vendor = def->vendor;
1877 if (kvm_enabled()) {
1878 uint32_t ebx = 0, ecx = 0, edx = 0;
1879 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
1880 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
1881 vendor = host_vendor;
1882 }
1883
1884 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
1885
1886 }
1887
1888 X86CPU *cpu_x86_create(const char *cpu_model, DeviceState *icc_bridge,
1889 Error **errp)
1890 {
1891 X86CPU *cpu = NULL;
1892 gchar **model_pieces;
1893 char *name, *features;
1894 char *typename;
1895 Error *error = NULL;
1896
1897 model_pieces = g_strsplit(cpu_model, ",", 2);
1898 if (!model_pieces[0]) {
1899 error_setg(&error, "Invalid/empty CPU model name");
1900 goto out;
1901 }
1902 name = model_pieces[0];
1903 features = model_pieces[1];
1904
1905 cpu = X86_CPU(object_new(TYPE_X86_CPU));
1906 x86_cpu_load_def(cpu, name, &error);
1907 if (error) {
1908 goto out;
1909 }
1910
1911 #ifndef CONFIG_USER_ONLY
1912 if (icc_bridge == NULL) {
1913 error_setg(&error, "Invalid icc-bridge value");
1914 goto out;
1915 }
1916 qdev_set_parent_bus(DEVICE(cpu), qdev_get_child_bus(icc_bridge, "icc"));
1917 object_unref(OBJECT(cpu));
1918 #endif
1919
1920 /* Emulate per-model subclasses for global properties */
1921 typename = g_strdup_printf("%s-" TYPE_X86_CPU, name);
1922 qdev_prop_set_globals_for_type(DEVICE(cpu), typename, &error);
1923 g_free(typename);
1924 if (error) {
1925 goto out;
1926 }
1927
1928 cpu_x86_parse_featurestr(cpu, features, &error);
1929 if (error) {
1930 goto out;
1931 }
1932
1933 out:
1934 if (error != NULL) {
1935 error_propagate(errp, error);
1936 object_unref(OBJECT(cpu));
1937 cpu = NULL;
1938 }
1939 g_strfreev(model_pieces);
1940 return cpu;
1941 }
1942
1943 X86CPU *cpu_x86_init(const char *cpu_model)
1944 {
1945 Error *error = NULL;
1946 X86CPU *cpu;
1947
1948 cpu = cpu_x86_create(cpu_model, NULL, &error);
1949 if (error) {
1950 goto out;
1951 }
1952
1953 object_property_set_bool(OBJECT(cpu), true, "realized", &error);
1954
1955 out:
1956 if (error) {
1957 error_report("%s", error_get_pretty(error));
1958 error_free(error);
1959 if (cpu != NULL) {
1960 object_unref(OBJECT(cpu));
1961 cpu = NULL;
1962 }
1963 }
1964 return cpu;
1965 }
1966
1967 #if !defined(CONFIG_USER_ONLY)
1968
1969 void cpu_clear_apic_feature(CPUX86State *env)
1970 {
1971 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
1972 }
1973
1974 #endif /* !CONFIG_USER_ONLY */
1975
1976 /* Initialize list of CPU models, filling some non-static fields if necessary
1977 */
1978 void x86_cpudef_setup(void)
1979 {
1980 int i, j;
1981 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
1982
1983 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
1984 X86CPUDefinition *def = &builtin_x86_defs[i];
1985
1986 /* Look for specific "cpudef" models that */
1987 /* have the QEMU version in .model_id */
1988 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
1989 if (strcmp(model_with_versions[j], def->name) == 0) {
1990 pstrcpy(def->model_id, sizeof(def->model_id),
1991 "QEMU Virtual CPU version ");
1992 pstrcat(def->model_id, sizeof(def->model_id),
1993 qemu_get_version());
1994 break;
1995 }
1996 }
1997 }
1998 }
1999
2000 static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
2001 uint32_t *ecx, uint32_t *edx)
2002 {
2003 *ebx = env->cpuid_vendor1;
2004 *edx = env->cpuid_vendor2;
2005 *ecx = env->cpuid_vendor3;
2006 }
2007
2008 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2009 uint32_t *eax, uint32_t *ebx,
2010 uint32_t *ecx, uint32_t *edx)
2011 {
2012 X86CPU *cpu = x86_env_get_cpu(env);
2013 CPUState *cs = CPU(cpu);
2014
2015 /* test if maximum index reached */
2016 if (index & 0x80000000) {
2017 if (index > env->cpuid_xlevel) {
2018 if (env->cpuid_xlevel2 > 0) {
2019 /* Handle the Centaur's CPUID instruction. */
2020 if (index > env->cpuid_xlevel2) {
2021 index = env->cpuid_xlevel2;
2022 } else if (index < 0xC0000000) {
2023 index = env->cpuid_xlevel;
2024 }
2025 } else {
2026 /* Intel documentation states that invalid EAX input will
2027 * return the same information as EAX=cpuid_level
2028 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2029 */
2030 index = env->cpuid_level;
2031 }
2032 }
2033 } else {
2034 if (index > env->cpuid_level)
2035 index = env->cpuid_level;
2036 }
2037
2038 switch(index) {
2039 case 0:
2040 *eax = env->cpuid_level;
2041 get_cpuid_vendor(env, ebx, ecx, edx);
2042 break;
2043 case 1:
2044 *eax = env->cpuid_version;
2045 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
2046 *ecx = env->features[FEAT_1_ECX];
2047 *edx = env->features[FEAT_1_EDX];
2048 if (cs->nr_cores * cs->nr_threads > 1) {
2049 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
2050 *edx |= 1 << 28; /* HTT bit */
2051 }
2052 break;
2053 case 2:
2054 /* cache info: needed for Pentium Pro compatibility */
2055 if (cpu->cache_info_passthrough) {
2056 host_cpuid(index, 0, eax, ebx, ecx, edx);
2057 break;
2058 }
2059 *eax = 1; /* Number of CPUID[EAX=2] calls required */
2060 *ebx = 0;
2061 *ecx = 0;
2062 *edx = (L1D_DESCRIPTOR << 16) | \
2063 (L1I_DESCRIPTOR << 8) | \
2064 (L2_DESCRIPTOR);
2065 break;
2066 case 4:
2067 /* cache info: needed for Core compatibility */
2068 if (cpu->cache_info_passthrough) {
2069 host_cpuid(index, count, eax, ebx, ecx, edx);
2070 *eax &= ~0xFC000000;
2071 } else {
2072 *eax = 0;
2073 switch (count) {
2074 case 0: /* L1 dcache info */
2075 *eax |= CPUID_4_TYPE_DCACHE | \
2076 CPUID_4_LEVEL(1) | \
2077 CPUID_4_SELF_INIT_LEVEL;
2078 *ebx = (L1D_LINE_SIZE - 1) | \
2079 ((L1D_PARTITIONS - 1) << 12) | \
2080 ((L1D_ASSOCIATIVITY - 1) << 22);
2081 *ecx = L1D_SETS - 1;
2082 *edx = CPUID_4_NO_INVD_SHARING;
2083 break;
2084 case 1: /* L1 icache info */
2085 *eax |= CPUID_4_TYPE_ICACHE | \
2086 CPUID_4_LEVEL(1) | \
2087 CPUID_4_SELF_INIT_LEVEL;
2088 *ebx = (L1I_LINE_SIZE - 1) | \
2089 ((L1I_PARTITIONS - 1) << 12) | \
2090 ((L1I_ASSOCIATIVITY - 1) << 22);
2091 *ecx = L1I_SETS - 1;
2092 *edx = CPUID_4_NO_INVD_SHARING;
2093 break;
2094 case 2: /* L2 cache info */
2095 *eax |= CPUID_4_TYPE_UNIFIED | \
2096 CPUID_4_LEVEL(2) | \
2097 CPUID_4_SELF_INIT_LEVEL;
2098 if (cs->nr_threads > 1) {
2099 *eax |= (cs->nr_threads - 1) << 14;
2100 }
2101 *ebx = (L2_LINE_SIZE - 1) | \
2102 ((L2_PARTITIONS - 1) << 12) | \
2103 ((L2_ASSOCIATIVITY - 1) << 22);
2104 *ecx = L2_SETS - 1;
2105 *edx = CPUID_4_NO_INVD_SHARING;
2106 break;
2107 default: /* end of info */
2108 *eax = 0;
2109 *ebx = 0;
2110 *ecx = 0;
2111 *edx = 0;
2112 break;
2113 }
2114 }
2115
2116 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2117 if ((*eax & 31) && cs->nr_cores > 1) {
2118 *eax |= (cs->nr_cores - 1) << 26;
2119 }
2120 break;
2121 case 5:
2122 /* mwait info: needed for Core compatibility */
2123 *eax = 0; /* Smallest monitor-line size in bytes */
2124 *ebx = 0; /* Largest monitor-line size in bytes */
2125 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2126 *edx = 0;
2127 break;
2128 case 6:
2129 /* Thermal and Power Leaf */
2130 *eax = 0;
2131 *ebx = 0;
2132 *ecx = 0;
2133 *edx = 0;
2134 break;
2135 case 7:
2136 /* Structured Extended Feature Flags Enumeration Leaf */
2137 if (count == 0) {
2138 *eax = 0; /* Maximum ECX value for sub-leaves */
2139 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
2140 *ecx = 0; /* Reserved */
2141 *edx = 0; /* Reserved */
2142 } else {
2143 *eax = 0;
2144 *ebx = 0;
2145 *ecx = 0;
2146 *edx = 0;
2147 }
2148 break;
2149 case 9:
2150 /* Direct Cache Access Information Leaf */
2151 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2152 *ebx = 0;
2153 *ecx = 0;
2154 *edx = 0;
2155 break;
2156 case 0xA:
2157 /* Architectural Performance Monitoring Leaf */
2158 if (kvm_enabled() && cpu->enable_pmu) {
2159 KVMState *s = cs->kvm_state;
2160
2161 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2162 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2163 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2164 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2165 } else {
2166 *eax = 0;
2167 *ebx = 0;
2168 *ecx = 0;
2169 *edx = 0;
2170 }
2171 break;
2172 case 0xD: {
2173 KVMState *s = cs->kvm_state;
2174 uint64_t kvm_mask;
2175 int i;
2176
2177 /* Processor Extended State */
2178 *eax = 0;
2179 *ebx = 0;
2180 *ecx = 0;
2181 *edx = 0;
2182 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) || !kvm_enabled()) {
2183 break;
2184 }
2185 kvm_mask =
2186 kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX) |
2187 ((uint64_t)kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX) << 32);
2188
2189 if (count == 0) {
2190 *ecx = 0x240;
2191 for (i = 2; i < ARRAY_SIZE(ext_save_areas); i++) {
2192 const ExtSaveArea *esa = &ext_save_areas[i];
2193 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2194 (kvm_mask & (1 << i)) != 0) {
2195 if (i < 32) {
2196 *eax |= 1 << i;
2197 } else {
2198 *edx |= 1 << (i - 32);
2199 }
2200 *ecx = MAX(*ecx, esa->offset + esa->size);
2201 }
2202 }
2203 *eax |= kvm_mask & (XSTATE_FP | XSTATE_SSE);
2204 *ebx = *ecx;
2205 } else if (count == 1) {
2206 *eax = kvm_arch_get_supported_cpuid(s, 0xd, 1, R_EAX);
2207 } else if (count < ARRAY_SIZE(ext_save_areas)) {
2208 const ExtSaveArea *esa = &ext_save_areas[count];
2209 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2210 (kvm_mask & (1 << count)) != 0) {
2211 *eax = esa->size;
2212 *ebx = esa->offset;
2213 }
2214 }
2215 break;
2216 }
2217 case 0x80000000:
2218 *eax = env->cpuid_xlevel;
2219 *ebx = env->cpuid_vendor1;
2220 *edx = env->cpuid_vendor2;
2221 *ecx = env->cpuid_vendor3;
2222 break;
2223 case 0x80000001:
2224 *eax = env->cpuid_version;
2225 *ebx = 0;
2226 *ecx = env->features[FEAT_8000_0001_ECX];
2227 *edx = env->features[FEAT_8000_0001_EDX];
2228
2229 /* The Linux kernel checks for the CMPLegacy bit and
2230 * discards multiple thread information if it is set.
2231 * So dont set it here for Intel to make Linux guests happy.
2232 */
2233 if (cs->nr_cores * cs->nr_threads > 1) {
2234 uint32_t tebx, tecx, tedx;
2235 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
2236 if (tebx != CPUID_VENDOR_INTEL_1 ||
2237 tedx != CPUID_VENDOR_INTEL_2 ||
2238 tecx != CPUID_VENDOR_INTEL_3) {
2239 *ecx |= 1 << 1; /* CmpLegacy bit */
2240 }
2241 }
2242 break;
2243 case 0x80000002:
2244 case 0x80000003:
2245 case 0x80000004:
2246 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2247 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2248 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2249 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2250 break;
2251 case 0x80000005:
2252 /* cache info (L1 cache) */
2253 if (cpu->cache_info_passthrough) {
2254 host_cpuid(index, 0, eax, ebx, ecx, edx);
2255 break;
2256 }
2257 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2258 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
2259 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2260 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
2261 *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2262 (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2263 *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2264 (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
2265 break;
2266 case 0x80000006:
2267 /* cache info (L2 cache) */
2268 if (cpu->cache_info_passthrough) {
2269 host_cpuid(index, 0, eax, ebx, ecx, edx);
2270 break;
2271 }
2272 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2273 (L2_DTLB_2M_ENTRIES << 16) | \
2274 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
2275 (L2_ITLB_2M_ENTRIES);
2276 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
2277 (L2_DTLB_4K_ENTRIES << 16) | \
2278 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
2279 (L2_ITLB_4K_ENTRIES);
2280 *ecx = (L2_SIZE_KB_AMD << 16) | \
2281 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
2282 (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
2283 *edx = ((L3_SIZE_KB/512) << 18) | \
2284 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
2285 (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
2286 break;
2287 case 0x80000008:
2288 /* virtual & phys address size in low 2 bytes. */
2289 /* XXX: This value must match the one used in the MMU code. */
2290 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
2291 /* 64 bit processor */
2292 /* XXX: The physical address space is limited to 42 bits in exec.c. */
2293 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
2294 } else {
2295 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
2296 *eax = 0x00000024; /* 36 bits physical */
2297 } else {
2298 *eax = 0x00000020; /* 32 bits physical */
2299 }
2300 }
2301 *ebx = 0;
2302 *ecx = 0;
2303 *edx = 0;
2304 if (cs->nr_cores * cs->nr_threads > 1) {
2305 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
2306 }
2307 break;
2308 case 0x8000000A:
2309 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
2310 *eax = 0x00000001; /* SVM Revision */
2311 *ebx = 0x00000010; /* nr of ASIDs */
2312 *ecx = 0;
2313 *edx = env->features[FEAT_SVM]; /* optional features */
2314 } else {
2315 *eax = 0;
2316 *ebx = 0;
2317 *ecx = 0;
2318 *edx = 0;
2319 }
2320 break;
2321 case 0xC0000000:
2322 *eax = env->cpuid_xlevel2;
2323 *ebx = 0;
2324 *ecx = 0;
2325 *edx = 0;
2326 break;
2327 case 0xC0000001:
2328 /* Support for VIA CPU's CPUID instruction */
2329 *eax = env->cpuid_version;
2330 *ebx = 0;
2331 *ecx = 0;
2332 *edx = env->features[FEAT_C000_0001_EDX];
2333 break;
2334 case 0xC0000002:
2335 case 0xC0000003:
2336 case 0xC0000004:
2337 /* Reserved for the future, and now filled with zero */
2338 *eax = 0;
2339 *ebx = 0;
2340 *ecx = 0;
2341 *edx = 0;
2342 break;
2343 default:
2344 /* reserved values: zero */
2345 *eax = 0;
2346 *ebx = 0;
2347 *ecx = 0;
2348 *edx = 0;
2349 break;
2350 }
2351 }
2352
2353 /* CPUClass::reset() */
2354 static void x86_cpu_reset(CPUState *s)
2355 {
2356 X86CPU *cpu = X86_CPU(s);
2357 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2358 CPUX86State *env = &cpu->env;
2359 int i;
2360
2361 xcc->parent_reset(s);
2362
2363
2364 memset(env, 0, offsetof(CPUX86State, breakpoints));
2365
2366 tlb_flush(env, 1);
2367
2368 env->old_exception = -1;
2369
2370 /* init to reset state */
2371
2372 #ifdef CONFIG_SOFTMMU
2373 env->hflags |= HF_SOFTMMU_MASK;
2374 #endif
2375 env->hflags2 |= HF2_GIF_MASK;
2376
2377 cpu_x86_update_cr0(env, 0x60000010);
2378 env->a20_mask = ~0x0;
2379 env->smbase = 0x30000;
2380
2381 env->idt.limit = 0xffff;
2382 env->gdt.limit = 0xffff;
2383 env->ldt.limit = 0xffff;
2384 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2385 env->tr.limit = 0xffff;
2386 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2387
2388 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2389 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2390 DESC_R_MASK | DESC_A_MASK);
2391 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2392 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2393 DESC_A_MASK);
2394 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2395 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2396 DESC_A_MASK);
2397 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2398 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2399 DESC_A_MASK);
2400 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2401 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2402 DESC_A_MASK);
2403 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2404 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2405 DESC_A_MASK);
2406
2407 env->eip = 0xfff0;
2408 env->regs[R_EDX] = env->cpuid_version;
2409
2410 env->eflags = 0x2;
2411
2412 /* FPU init */
2413 for (i = 0; i < 8; i++) {
2414 env->fptags[i] = 1;
2415 }
2416 env->fpuc = 0x37f;
2417
2418 env->mxcsr = 0x1f80;
2419 env->xstate_bv = XSTATE_FP | XSTATE_SSE;
2420
2421 env->pat = 0x0007040600070406ULL;
2422 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2423
2424 memset(env->dr, 0, sizeof(env->dr));
2425 env->dr[6] = DR6_FIXED_1;
2426 env->dr[7] = DR7_FIXED_1;
2427 cpu_breakpoint_remove_all(env, BP_CPU);
2428 cpu_watchpoint_remove_all(env, BP_CPU);
2429
2430 env->tsc_adjust = 0;
2431 env->tsc = 0;
2432
2433 #if !defined(CONFIG_USER_ONLY)
2434 /* We hard-wire the BSP to the first CPU. */
2435 if (s->cpu_index == 0) {
2436 apic_designate_bsp(cpu->apic_state);
2437 }
2438
2439 s->halted = !cpu_is_bsp(cpu);
2440 #endif
2441 }
2442
2443 #ifndef CONFIG_USER_ONLY
2444 bool cpu_is_bsp(X86CPU *cpu)
2445 {
2446 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
2447 }
2448
2449 /* TODO: remove me, when reset over QOM tree is implemented */
2450 static void x86_cpu_machine_reset_cb(void *opaque)
2451 {
2452 X86CPU *cpu = opaque;
2453 cpu_reset(CPU(cpu));
2454 }
2455 #endif
2456
2457 static void mce_init(X86CPU *cpu)
2458 {
2459 CPUX86State *cenv = &cpu->env;
2460 unsigned int bank;
2461
2462 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
2463 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
2464 (CPUID_MCE | CPUID_MCA)) {
2465 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2466 cenv->mcg_ctl = ~(uint64_t)0;
2467 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2468 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2469 }
2470 }
2471 }
2472
2473 #ifndef CONFIG_USER_ONLY
2474 static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
2475 {
2476 CPUX86State *env = &cpu->env;
2477 DeviceState *dev = DEVICE(cpu);
2478 APICCommonState *apic;
2479 const char *apic_type = "apic";
2480
2481 if (kvm_irqchip_in_kernel()) {
2482 apic_type = "kvm-apic";
2483 } else if (xen_enabled()) {
2484 apic_type = "xen-apic";
2485 }
2486
2487 cpu->apic_state = qdev_try_create(qdev_get_parent_bus(dev), apic_type);
2488 if (cpu->apic_state == NULL) {
2489 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2490 return;
2491 }
2492
2493 object_property_add_child(OBJECT(cpu), "apic",
2494 OBJECT(cpu->apic_state), NULL);
2495 qdev_prop_set_uint8(cpu->apic_state, "id", env->cpuid_apic_id);
2496 /* TODO: convert to link<> */
2497 apic = APIC_COMMON(cpu->apic_state);
2498 apic->cpu = cpu;
2499 }
2500
2501 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2502 {
2503 if (cpu->apic_state == NULL) {
2504 return;
2505 }
2506
2507 if (qdev_init(cpu->apic_state)) {
2508 error_setg(errp, "APIC device '%s' could not be initialized",
2509 object_get_typename(OBJECT(cpu->apic_state)));
2510 return;
2511 }
2512 }
2513 #else
2514 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2515 {
2516 }
2517 #endif
2518
2519 static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
2520 {
2521 CPUState *cs = CPU(dev);
2522 X86CPU *cpu = X86_CPU(dev);
2523 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
2524 CPUX86State *env = &cpu->env;
2525 Error *local_err = NULL;
2526
2527 if (env->features[FEAT_7_0_EBX] && env->cpuid_level < 7) {
2528 env->cpuid_level = 7;
2529 }
2530
2531 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2532 * CPUID[1].EDX.
2533 */
2534 if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
2535 env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
2536 env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
2537 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
2538 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
2539 & CPUID_EXT2_AMD_ALIASES);
2540 }
2541
2542 if (!kvm_enabled()) {
2543 env->features[FEAT_1_EDX] &= TCG_FEATURES;
2544 env->features[FEAT_1_ECX] &= TCG_EXT_FEATURES;
2545 env->features[FEAT_8000_0001_EDX] &= (TCG_EXT2_FEATURES
2546 #ifdef TARGET_X86_64
2547 | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
2548 #endif
2549 );
2550 env->features[FEAT_8000_0001_ECX] &= TCG_EXT3_FEATURES;
2551 env->features[FEAT_SVM] &= TCG_SVM_FEATURES;
2552 } else {
2553 KVMState *s = kvm_state;
2554 if ((cpu->check_cpuid || cpu->enforce_cpuid)
2555 && kvm_check_features_against_host(s, cpu) && cpu->enforce_cpuid) {
2556 error_setg(&local_err,
2557 "Host's CPU doesn't support requested features");
2558 goto out;
2559 }
2560 filter_features_for_kvm(cpu);
2561 }
2562
2563 #ifndef CONFIG_USER_ONLY
2564 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
2565
2566 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
2567 x86_cpu_apic_create(cpu, &local_err);
2568 if (local_err != NULL) {
2569 goto out;
2570 }
2571 }
2572 #endif
2573
2574 mce_init(cpu);
2575 qemu_init_vcpu(cs);
2576
2577 x86_cpu_apic_realize(cpu, &local_err);
2578 if (local_err != NULL) {
2579 goto out;
2580 }
2581 cpu_reset(cs);
2582
2583 xcc->parent_realize(dev, &local_err);
2584 out:
2585 if (local_err != NULL) {
2586 error_propagate(errp, local_err);
2587 return;
2588 }
2589 }
2590
2591 /* Enables contiguous-apic-ID mode, for compatibility */
2592 static bool compat_apic_id_mode;
2593
2594 void enable_compat_apic_id_mode(void)
2595 {
2596 compat_apic_id_mode = true;
2597 }
2598
2599 /* Calculates initial APIC ID for a specific CPU index
2600 *
2601 * Currently we need to be able to calculate the APIC ID from the CPU index
2602 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
2603 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
2604 * all CPUs up to max_cpus.
2605 */
2606 uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
2607 {
2608 uint32_t correct_id;
2609 static bool warned;
2610
2611 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
2612 if (compat_apic_id_mode) {
2613 if (cpu_index != correct_id && !warned) {
2614 error_report("APIC IDs set in compatibility mode, "
2615 "CPU topology won't match the configuration");
2616 warned = true;
2617 }
2618 return cpu_index;
2619 } else {
2620 return correct_id;
2621 }
2622 }
2623
2624 static void x86_cpu_initfn(Object *obj)
2625 {
2626 CPUState *cs = CPU(obj);
2627 X86CPU *cpu = X86_CPU(obj);
2628 CPUX86State *env = &cpu->env;
2629 static int inited;
2630
2631 cs->env_ptr = env;
2632 cpu_exec_init(env);
2633
2634 object_property_add(obj, "family", "int",
2635 x86_cpuid_version_get_family,
2636 x86_cpuid_version_set_family, NULL, NULL, NULL);
2637 object_property_add(obj, "model", "int",
2638 x86_cpuid_version_get_model,
2639 x86_cpuid_version_set_model, NULL, NULL, NULL);
2640 object_property_add(obj, "stepping", "int",
2641 x86_cpuid_version_get_stepping,
2642 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
2643 object_property_add(obj, "level", "int",
2644 x86_cpuid_get_level,
2645 x86_cpuid_set_level, NULL, NULL, NULL);
2646 object_property_add(obj, "xlevel", "int",
2647 x86_cpuid_get_xlevel,
2648 x86_cpuid_set_xlevel, NULL, NULL, NULL);
2649 object_property_add_str(obj, "vendor",
2650 x86_cpuid_get_vendor,
2651 x86_cpuid_set_vendor, NULL);
2652 object_property_add_str(obj, "model-id",
2653 x86_cpuid_get_model_id,
2654 x86_cpuid_set_model_id, NULL);
2655 object_property_add(obj, "tsc-frequency", "int",
2656 x86_cpuid_get_tsc_freq,
2657 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
2658 object_property_add(obj, "apic-id", "int",
2659 x86_cpuid_get_apic_id,
2660 x86_cpuid_set_apic_id, NULL, NULL, NULL);
2661 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
2662 x86_cpu_get_feature_words,
2663 NULL, NULL, (void *)env->features, NULL);
2664 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
2665 x86_cpu_get_feature_words,
2666 NULL, NULL, (void *)cpu->filtered_features, NULL);
2667
2668 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
2669 env->cpuid_apic_id = x86_cpu_apic_id_from_index(cs->cpu_index);
2670
2671 /* init various static tables used in TCG mode */
2672 if (tcg_enabled() && !inited) {
2673 inited = 1;
2674 optimize_flags_init();
2675 #ifndef CONFIG_USER_ONLY
2676 cpu_set_debug_excp_handler(breakpoint_handler);
2677 #endif
2678 }
2679 }
2680
2681 static int64_t x86_cpu_get_arch_id(CPUState *cs)
2682 {
2683 X86CPU *cpu = X86_CPU(cs);
2684 CPUX86State *env = &cpu->env;
2685
2686 return env->cpuid_apic_id;
2687 }
2688
2689 static bool x86_cpu_get_paging_enabled(const CPUState *cs)
2690 {
2691 X86CPU *cpu = X86_CPU(cs);
2692
2693 return cpu->env.cr[0] & CR0_PG_MASK;
2694 }
2695
2696 static void x86_cpu_set_pc(CPUState *cs, vaddr value)
2697 {
2698 X86CPU *cpu = X86_CPU(cs);
2699
2700 cpu->env.eip = value;
2701 }
2702
2703 static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
2704 {
2705 X86CPU *cpu = X86_CPU(cs);
2706
2707 cpu->env.eip = tb->pc - tb->cs_base;
2708 }
2709
2710 static bool x86_cpu_has_work(CPUState *cs)
2711 {
2712 X86CPU *cpu = X86_CPU(cs);
2713 CPUX86State *env = &cpu->env;
2714
2715 return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
2716 CPU_INTERRUPT_POLL)) &&
2717 (env->eflags & IF_MASK)) ||
2718 (cs->interrupt_request & (CPU_INTERRUPT_NMI |
2719 CPU_INTERRUPT_INIT |
2720 CPU_INTERRUPT_SIPI |
2721 CPU_INTERRUPT_MCE));
2722 }
2723
2724 static Property x86_cpu_properties[] = {
2725 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
2726 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
2727 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
2728 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
2729 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
2730 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, false),
2731 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
2732 DEFINE_PROP_END_OF_LIST()
2733 };
2734
2735 static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2736 {
2737 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2738 CPUClass *cc = CPU_CLASS(oc);
2739 DeviceClass *dc = DEVICE_CLASS(oc);
2740
2741 xcc->parent_realize = dc->realize;
2742 dc->realize = x86_cpu_realizefn;
2743 dc->bus_type = TYPE_ICC_BUS;
2744 dc->props = x86_cpu_properties;
2745
2746 xcc->parent_reset = cc->reset;
2747 cc->reset = x86_cpu_reset;
2748 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
2749
2750 cc->has_work = x86_cpu_has_work;
2751 cc->do_interrupt = x86_cpu_do_interrupt;
2752 cc->dump_state = x86_cpu_dump_state;
2753 cc->set_pc = x86_cpu_set_pc;
2754 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
2755 cc->gdb_read_register = x86_cpu_gdb_read_register;
2756 cc->gdb_write_register = x86_cpu_gdb_write_register;
2757 cc->get_arch_id = x86_cpu_get_arch_id;
2758 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
2759 #ifndef CONFIG_USER_ONLY
2760 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
2761 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
2762 cc->write_elf64_note = x86_cpu_write_elf64_note;
2763 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
2764 cc->write_elf32_note = x86_cpu_write_elf32_note;
2765 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
2766 cc->vmsd = &vmstate_x86_cpu;
2767 #endif
2768 cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
2769 }
2770
2771 static const TypeInfo x86_cpu_type_info = {
2772 .name = TYPE_X86_CPU,
2773 .parent = TYPE_CPU,
2774 .instance_size = sizeof(X86CPU),
2775 .instance_init = x86_cpu_initfn,
2776 .abstract = false,
2777 .class_size = sizeof(X86CPUClass),
2778 .class_init = x86_cpu_common_class_init,
2779 };
2780
2781 static void x86_cpu_register_types(void)
2782 {
2783 type_register_static(&x86_cpu_type_info);
2784 }
2785
2786 type_init(x86_cpu_register_types)