apic: move target-dependent definitions to cpu.h
[qemu.git] / target-i386 / cpu.h
1 /*
2 * i386 virtual CPU header
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #ifndef CPU_I386_H
20 #define CPU_I386_H
21
22 #include "qemu-common.h"
23 #include "cpu-qom.h"
24 #include "standard-headers/asm-x86/hyperv.h"
25
26 #ifdef TARGET_X86_64
27 #define TARGET_LONG_BITS 64
28 #else
29 #define TARGET_LONG_BITS 32
30 #endif
31
32 /* Maximum instruction code size */
33 #define TARGET_MAX_INSN_SIZE 16
34
35 /* support for self modifying code even if the modified instruction is
36 close to the modifying instruction */
37 #define TARGET_HAS_PRECISE_SMC
38
39 #ifdef TARGET_X86_64
40 #define I386_ELF_MACHINE EM_X86_64
41 #define ELF_MACHINE_UNAME "x86_64"
42 #else
43 #define I386_ELF_MACHINE EM_386
44 #define ELF_MACHINE_UNAME "i686"
45 #endif
46
47 #define CPUArchState struct CPUX86State
48
49 #include "exec/cpu-defs.h"
50
51 #include "fpu/softfloat.h"
52
53 #define R_EAX 0
54 #define R_ECX 1
55 #define R_EDX 2
56 #define R_EBX 3
57 #define R_ESP 4
58 #define R_EBP 5
59 #define R_ESI 6
60 #define R_EDI 7
61
62 #define R_AL 0
63 #define R_CL 1
64 #define R_DL 2
65 #define R_BL 3
66 #define R_AH 4
67 #define R_CH 5
68 #define R_DH 6
69 #define R_BH 7
70
71 #define R_ES 0
72 #define R_CS 1
73 #define R_SS 2
74 #define R_DS 3
75 #define R_FS 4
76 #define R_GS 5
77
78 /* segment descriptor fields */
79 #define DESC_G_MASK (1 << 23)
80 #define DESC_B_SHIFT 22
81 #define DESC_B_MASK (1 << DESC_B_SHIFT)
82 #define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */
83 #define DESC_L_MASK (1 << DESC_L_SHIFT)
84 #define DESC_AVL_MASK (1 << 20)
85 #define DESC_P_MASK (1 << 15)
86 #define DESC_DPL_SHIFT 13
87 #define DESC_DPL_MASK (3 << DESC_DPL_SHIFT)
88 #define DESC_S_MASK (1 << 12)
89 #define DESC_TYPE_SHIFT 8
90 #define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT)
91 #define DESC_A_MASK (1 << 8)
92
93 #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */
94 #define DESC_C_MASK (1 << 10) /* code: conforming */
95 #define DESC_R_MASK (1 << 9) /* code: readable */
96
97 #define DESC_E_MASK (1 << 10) /* data: expansion direction */
98 #define DESC_W_MASK (1 << 9) /* data: writable */
99
100 #define DESC_TSS_BUSY_MASK (1 << 9)
101
102 /* eflags masks */
103 #define CC_C 0x0001
104 #define CC_P 0x0004
105 #define CC_A 0x0010
106 #define CC_Z 0x0040
107 #define CC_S 0x0080
108 #define CC_O 0x0800
109
110 #define TF_SHIFT 8
111 #define IOPL_SHIFT 12
112 #define VM_SHIFT 17
113
114 #define TF_MASK 0x00000100
115 #define IF_MASK 0x00000200
116 #define DF_MASK 0x00000400
117 #define IOPL_MASK 0x00003000
118 #define NT_MASK 0x00004000
119 #define RF_MASK 0x00010000
120 #define VM_MASK 0x00020000
121 #define AC_MASK 0x00040000
122 #define VIF_MASK 0x00080000
123 #define VIP_MASK 0x00100000
124 #define ID_MASK 0x00200000
125
126 /* hidden flags - used internally by qemu to represent additional cpu
127 states. Only the INHIBIT_IRQ, SMM and SVMI are not redundant. We
128 avoid using the IOPL_MASK, TF_MASK, VM_MASK and AC_MASK bit
129 positions to ease oring with eflags. */
130 /* current cpl */
131 #define HF_CPL_SHIFT 0
132 /* true if soft mmu is being used */
133 #define HF_SOFTMMU_SHIFT 2
134 /* true if hardware interrupts must be disabled for next instruction */
135 #define HF_INHIBIT_IRQ_SHIFT 3
136 /* 16 or 32 segments */
137 #define HF_CS32_SHIFT 4
138 #define HF_SS32_SHIFT 5
139 /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
140 #define HF_ADDSEG_SHIFT 6
141 /* copy of CR0.PE (protected mode) */
142 #define HF_PE_SHIFT 7
143 #define HF_TF_SHIFT 8 /* must be same as eflags */
144 #define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */
145 #define HF_EM_SHIFT 10
146 #define HF_TS_SHIFT 11
147 #define HF_IOPL_SHIFT 12 /* must be same as eflags */
148 #define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */
149 #define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */
150 #define HF_RF_SHIFT 16 /* must be same as eflags */
151 #define HF_VM_SHIFT 17 /* must be same as eflags */
152 #define HF_AC_SHIFT 18 /* must be same as eflags */
153 #define HF_SMM_SHIFT 19 /* CPU in SMM mode */
154 #define HF_SVME_SHIFT 20 /* SVME enabled (copy of EFER.SVME) */
155 #define HF_SVMI_SHIFT 21 /* SVM intercepts are active */
156 #define HF_OSFXSR_SHIFT 22 /* CR4.OSFXSR */
157 #define HF_SMAP_SHIFT 23 /* CR4.SMAP */
158 #define HF_IOBPT_SHIFT 24 /* an io breakpoint enabled */
159 #define HF_MPX_EN_SHIFT 25 /* MPX Enabled (CR4+XCR0+BNDCFGx) */
160 #define HF_MPX_IU_SHIFT 26 /* BND registers in-use */
161
162 #define HF_CPL_MASK (3 << HF_CPL_SHIFT)
163 #define HF_SOFTMMU_MASK (1 << HF_SOFTMMU_SHIFT)
164 #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT)
165 #define HF_CS32_MASK (1 << HF_CS32_SHIFT)
166 #define HF_SS32_MASK (1 << HF_SS32_SHIFT)
167 #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT)
168 #define HF_PE_MASK (1 << HF_PE_SHIFT)
169 #define HF_TF_MASK (1 << HF_TF_SHIFT)
170 #define HF_MP_MASK (1 << HF_MP_SHIFT)
171 #define HF_EM_MASK (1 << HF_EM_SHIFT)
172 #define HF_TS_MASK (1 << HF_TS_SHIFT)
173 #define HF_IOPL_MASK (3 << HF_IOPL_SHIFT)
174 #define HF_LMA_MASK (1 << HF_LMA_SHIFT)
175 #define HF_CS64_MASK (1 << HF_CS64_SHIFT)
176 #define HF_RF_MASK (1 << HF_RF_SHIFT)
177 #define HF_VM_MASK (1 << HF_VM_SHIFT)
178 #define HF_AC_MASK (1 << HF_AC_SHIFT)
179 #define HF_SMM_MASK (1 << HF_SMM_SHIFT)
180 #define HF_SVME_MASK (1 << HF_SVME_SHIFT)
181 #define HF_SVMI_MASK (1 << HF_SVMI_SHIFT)
182 #define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT)
183 #define HF_SMAP_MASK (1 << HF_SMAP_SHIFT)
184 #define HF_IOBPT_MASK (1 << HF_IOBPT_SHIFT)
185 #define HF_MPX_EN_MASK (1 << HF_MPX_EN_SHIFT)
186 #define HF_MPX_IU_MASK (1 << HF_MPX_IU_SHIFT)
187
188 /* hflags2 */
189
190 #define HF2_GIF_SHIFT 0 /* if set CPU takes interrupts */
191 #define HF2_HIF_SHIFT 1 /* value of IF_MASK when entering SVM */
192 #define HF2_NMI_SHIFT 2 /* CPU serving NMI */
193 #define HF2_VINTR_SHIFT 3 /* value of V_INTR_MASKING bit */
194 #define HF2_SMM_INSIDE_NMI_SHIFT 4 /* CPU serving SMI nested inside NMI */
195 #define HF2_MPX_PR_SHIFT 5 /* BNDCFGx.BNDPRESERVE */
196
197 #define HF2_GIF_MASK (1 << HF2_GIF_SHIFT)
198 #define HF2_HIF_MASK (1 << HF2_HIF_SHIFT)
199 #define HF2_NMI_MASK (1 << HF2_NMI_SHIFT)
200 #define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT)
201 #define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT)
202 #define HF2_MPX_PR_MASK (1 << HF2_MPX_PR_SHIFT)
203
204 #define CR0_PE_SHIFT 0
205 #define CR0_MP_SHIFT 1
206
207 #define CR0_PE_MASK (1U << 0)
208 #define CR0_MP_MASK (1U << 1)
209 #define CR0_EM_MASK (1U << 2)
210 #define CR0_TS_MASK (1U << 3)
211 #define CR0_ET_MASK (1U << 4)
212 #define CR0_NE_MASK (1U << 5)
213 #define CR0_WP_MASK (1U << 16)
214 #define CR0_AM_MASK (1U << 18)
215 #define CR0_PG_MASK (1U << 31)
216
217 #define CR4_VME_MASK (1U << 0)
218 #define CR4_PVI_MASK (1U << 1)
219 #define CR4_TSD_MASK (1U << 2)
220 #define CR4_DE_MASK (1U << 3)
221 #define CR4_PSE_MASK (1U << 4)
222 #define CR4_PAE_MASK (1U << 5)
223 #define CR4_MCE_MASK (1U << 6)
224 #define CR4_PGE_MASK (1U << 7)
225 #define CR4_PCE_MASK (1U << 8)
226 #define CR4_OSFXSR_SHIFT 9
227 #define CR4_OSFXSR_MASK (1U << CR4_OSFXSR_SHIFT)
228 #define CR4_OSXMMEXCPT_MASK (1U << 10)
229 #define CR4_VMXE_MASK (1U << 13)
230 #define CR4_SMXE_MASK (1U << 14)
231 #define CR4_FSGSBASE_MASK (1U << 16)
232 #define CR4_PCIDE_MASK (1U << 17)
233 #define CR4_OSXSAVE_MASK (1U << 18)
234 #define CR4_SMEP_MASK (1U << 20)
235 #define CR4_SMAP_MASK (1U << 21)
236 #define CR4_PKE_MASK (1U << 22)
237
238 #define DR6_BD (1 << 13)
239 #define DR6_BS (1 << 14)
240 #define DR6_BT (1 << 15)
241 #define DR6_FIXED_1 0xffff0ff0
242
243 #define DR7_GD (1 << 13)
244 #define DR7_TYPE_SHIFT 16
245 #define DR7_LEN_SHIFT 18
246 #define DR7_FIXED_1 0x00000400
247 #define DR7_GLOBAL_BP_MASK 0xaa
248 #define DR7_LOCAL_BP_MASK 0x55
249 #define DR7_MAX_BP 4
250 #define DR7_TYPE_BP_INST 0x0
251 #define DR7_TYPE_DATA_WR 0x1
252 #define DR7_TYPE_IO_RW 0x2
253 #define DR7_TYPE_DATA_RW 0x3
254
255 #define PG_PRESENT_BIT 0
256 #define PG_RW_BIT 1
257 #define PG_USER_BIT 2
258 #define PG_PWT_BIT 3
259 #define PG_PCD_BIT 4
260 #define PG_ACCESSED_BIT 5
261 #define PG_DIRTY_BIT 6
262 #define PG_PSE_BIT 7
263 #define PG_GLOBAL_BIT 8
264 #define PG_PSE_PAT_BIT 12
265 #define PG_PKRU_BIT 59
266 #define PG_NX_BIT 63
267
268 #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT)
269 #define PG_RW_MASK (1 << PG_RW_BIT)
270 #define PG_USER_MASK (1 << PG_USER_BIT)
271 #define PG_PWT_MASK (1 << PG_PWT_BIT)
272 #define PG_PCD_MASK (1 << PG_PCD_BIT)
273 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
274 #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT)
275 #define PG_PSE_MASK (1 << PG_PSE_BIT)
276 #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT)
277 #define PG_PSE_PAT_MASK (1 << PG_PSE_PAT_BIT)
278 #define PG_ADDRESS_MASK 0x000ffffffffff000LL
279 #define PG_HI_RSVD_MASK (PG_ADDRESS_MASK & ~PHYS_ADDR_MASK)
280 #define PG_HI_USER_MASK 0x7ff0000000000000LL
281 #define PG_PKRU_MASK (15ULL << PG_PKRU_BIT)
282 #define PG_NX_MASK (1ULL << PG_NX_BIT)
283
284 #define PG_ERROR_W_BIT 1
285
286 #define PG_ERROR_P_MASK 0x01
287 #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT)
288 #define PG_ERROR_U_MASK 0x04
289 #define PG_ERROR_RSVD_MASK 0x08
290 #define PG_ERROR_I_D_MASK 0x10
291 #define PG_ERROR_PK_MASK 0x20
292
293 #define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */
294 #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */
295
296 #define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P)
297 #define MCE_BANKS_DEF 10
298
299 #define MCG_CAP_BANKS_MASK 0xff
300
301 #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */
302 #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */
303 #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */
304
305 #define MCI_STATUS_VAL (1ULL<<63) /* valid error */
306 #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */
307 #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */
308 #define MCI_STATUS_EN (1ULL<<60) /* error enabled */
309 #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */
310 #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */
311 #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */
312 #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */
313 #define MCI_STATUS_AR (1ULL<<55) /* Action required */
314
315 /* MISC register defines */
316 #define MCM_ADDR_SEGOFF 0 /* segment offset */
317 #define MCM_ADDR_LINEAR 1 /* linear address */
318 #define MCM_ADDR_PHYS 2 /* physical address */
319 #define MCM_ADDR_MEM 3 /* memory address */
320 #define MCM_ADDR_GENERIC 7 /* generic */
321
322 #define MSR_IA32_TSC 0x10
323 #define MSR_IA32_APICBASE 0x1b
324 #define MSR_IA32_APICBASE_BSP (1<<8)
325 #define MSR_IA32_APICBASE_ENABLE (1<<11)
326 #define MSR_IA32_APICBASE_BASE (0xfffffU<<12)
327 #define MSR_IA32_FEATURE_CONTROL 0x0000003a
328 #define MSR_TSC_ADJUST 0x0000003b
329 #define MSR_IA32_TSCDEADLINE 0x6e0
330
331 #define MSR_P6_PERFCTR0 0xc1
332
333 #define MSR_IA32_SMBASE 0x9e
334 #define MSR_MTRRcap 0xfe
335 #define MSR_MTRRcap_VCNT 8
336 #define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8)
337 #define MSR_MTRRcap_WC_SUPPORTED (1 << 10)
338
339 #define MSR_IA32_SYSENTER_CS 0x174
340 #define MSR_IA32_SYSENTER_ESP 0x175
341 #define MSR_IA32_SYSENTER_EIP 0x176
342
343 #define MSR_MCG_CAP 0x179
344 #define MSR_MCG_STATUS 0x17a
345 #define MSR_MCG_CTL 0x17b
346
347 #define MSR_P6_EVNTSEL0 0x186
348
349 #define MSR_IA32_PERF_STATUS 0x198
350
351 #define MSR_IA32_MISC_ENABLE 0x1a0
352 /* Indicates good rep/movs microcode on some processors: */
353 #define MSR_IA32_MISC_ENABLE_DEFAULT 1
354
355 #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg))
356 #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1)
357
358 #define MSR_MTRRphysIndex(addr) ((((addr) & ~1u) - 0x200) / 2)
359
360 #define MSR_MTRRfix64K_00000 0x250
361 #define MSR_MTRRfix16K_80000 0x258
362 #define MSR_MTRRfix16K_A0000 0x259
363 #define MSR_MTRRfix4K_C0000 0x268
364 #define MSR_MTRRfix4K_C8000 0x269
365 #define MSR_MTRRfix4K_D0000 0x26a
366 #define MSR_MTRRfix4K_D8000 0x26b
367 #define MSR_MTRRfix4K_E0000 0x26c
368 #define MSR_MTRRfix4K_E8000 0x26d
369 #define MSR_MTRRfix4K_F0000 0x26e
370 #define MSR_MTRRfix4K_F8000 0x26f
371
372 #define MSR_PAT 0x277
373
374 #define MSR_MTRRdefType 0x2ff
375
376 #define MSR_CORE_PERF_FIXED_CTR0 0x309
377 #define MSR_CORE_PERF_FIXED_CTR1 0x30a
378 #define MSR_CORE_PERF_FIXED_CTR2 0x30b
379 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d
380 #define MSR_CORE_PERF_GLOBAL_STATUS 0x38e
381 #define MSR_CORE_PERF_GLOBAL_CTRL 0x38f
382 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390
383
384 #define MSR_MC0_CTL 0x400
385 #define MSR_MC0_STATUS 0x401
386 #define MSR_MC0_ADDR 0x402
387 #define MSR_MC0_MISC 0x403
388
389 #define MSR_EFER 0xc0000080
390
391 #define MSR_EFER_SCE (1 << 0)
392 #define MSR_EFER_LME (1 << 8)
393 #define MSR_EFER_LMA (1 << 10)
394 #define MSR_EFER_NXE (1 << 11)
395 #define MSR_EFER_SVME (1 << 12)
396 #define MSR_EFER_FFXSR (1 << 14)
397
398 #define MSR_STAR 0xc0000081
399 #define MSR_LSTAR 0xc0000082
400 #define MSR_CSTAR 0xc0000083
401 #define MSR_FMASK 0xc0000084
402 #define MSR_FSBASE 0xc0000100
403 #define MSR_GSBASE 0xc0000101
404 #define MSR_KERNELGSBASE 0xc0000102
405 #define MSR_TSC_AUX 0xc0000103
406
407 #define MSR_VM_HSAVE_PA 0xc0010117
408
409 #define MSR_IA32_BNDCFGS 0x00000d90
410 #define MSR_IA32_XSS 0x00000da0
411
412 #define XSTATE_FP_BIT 0
413 #define XSTATE_SSE_BIT 1
414 #define XSTATE_YMM_BIT 2
415 #define XSTATE_BNDREGS_BIT 3
416 #define XSTATE_BNDCSR_BIT 4
417 #define XSTATE_OPMASK_BIT 5
418 #define XSTATE_ZMM_Hi256_BIT 6
419 #define XSTATE_Hi16_ZMM_BIT 7
420 #define XSTATE_PKRU_BIT 9
421
422 #define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT)
423 #define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT)
424 #define XSTATE_YMM_MASK (1ULL << XSTATE_YMM_BIT)
425 #define XSTATE_BNDREGS_MASK (1ULL << XSTATE_BNDREGS_BIT)
426 #define XSTATE_BNDCSR_MASK (1ULL << XSTATE_BNDCSR_BIT)
427 #define XSTATE_OPMASK_MASK (1ULL << XSTATE_OPMASK_BIT)
428 #define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT)
429 #define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT)
430 #define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT)
431
432 /* CPUID feature words */
433 typedef enum FeatureWord {
434 FEAT_1_EDX, /* CPUID[1].EDX */
435 FEAT_1_ECX, /* CPUID[1].ECX */
436 FEAT_7_0_EBX, /* CPUID[EAX=7,ECX=0].EBX */
437 FEAT_7_0_ECX, /* CPUID[EAX=7,ECX=0].ECX */
438 FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */
439 FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */
440 FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */
441 FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */
442 FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */
443 FEAT_SVM, /* CPUID[8000_000A].EDX */
444 FEAT_XSAVE, /* CPUID[EAX=0xd,ECX=1].EAX */
445 FEAT_6_EAX, /* CPUID[6].EAX */
446 FEATURE_WORDS,
447 } FeatureWord;
448
449 typedef uint32_t FeatureWordArray[FEATURE_WORDS];
450
451 /* cpuid_features bits */
452 #define CPUID_FP87 (1U << 0)
453 #define CPUID_VME (1U << 1)
454 #define CPUID_DE (1U << 2)
455 #define CPUID_PSE (1U << 3)
456 #define CPUID_TSC (1U << 4)
457 #define CPUID_MSR (1U << 5)
458 #define CPUID_PAE (1U << 6)
459 #define CPUID_MCE (1U << 7)
460 #define CPUID_CX8 (1U << 8)
461 #define CPUID_APIC (1U << 9)
462 #define CPUID_SEP (1U << 11) /* sysenter/sysexit */
463 #define CPUID_MTRR (1U << 12)
464 #define CPUID_PGE (1U << 13)
465 #define CPUID_MCA (1U << 14)
466 #define CPUID_CMOV (1U << 15)
467 #define CPUID_PAT (1U << 16)
468 #define CPUID_PSE36 (1U << 17)
469 #define CPUID_PN (1U << 18)
470 #define CPUID_CLFLUSH (1U << 19)
471 #define CPUID_DTS (1U << 21)
472 #define CPUID_ACPI (1U << 22)
473 #define CPUID_MMX (1U << 23)
474 #define CPUID_FXSR (1U << 24)
475 #define CPUID_SSE (1U << 25)
476 #define CPUID_SSE2 (1U << 26)
477 #define CPUID_SS (1U << 27)
478 #define CPUID_HT (1U << 28)
479 #define CPUID_TM (1U << 29)
480 #define CPUID_IA64 (1U << 30)
481 #define CPUID_PBE (1U << 31)
482
483 #define CPUID_EXT_SSE3 (1U << 0)
484 #define CPUID_EXT_PCLMULQDQ (1U << 1)
485 #define CPUID_EXT_DTES64 (1U << 2)
486 #define CPUID_EXT_MONITOR (1U << 3)
487 #define CPUID_EXT_DSCPL (1U << 4)
488 #define CPUID_EXT_VMX (1U << 5)
489 #define CPUID_EXT_SMX (1U << 6)
490 #define CPUID_EXT_EST (1U << 7)
491 #define CPUID_EXT_TM2 (1U << 8)
492 #define CPUID_EXT_SSSE3 (1U << 9)
493 #define CPUID_EXT_CID (1U << 10)
494 #define CPUID_EXT_FMA (1U << 12)
495 #define CPUID_EXT_CX16 (1U << 13)
496 #define CPUID_EXT_XTPR (1U << 14)
497 #define CPUID_EXT_PDCM (1U << 15)
498 #define CPUID_EXT_PCID (1U << 17)
499 #define CPUID_EXT_DCA (1U << 18)
500 #define CPUID_EXT_SSE41 (1U << 19)
501 #define CPUID_EXT_SSE42 (1U << 20)
502 #define CPUID_EXT_X2APIC (1U << 21)
503 #define CPUID_EXT_MOVBE (1U << 22)
504 #define CPUID_EXT_POPCNT (1U << 23)
505 #define CPUID_EXT_TSC_DEADLINE_TIMER (1U << 24)
506 #define CPUID_EXT_AES (1U << 25)
507 #define CPUID_EXT_XSAVE (1U << 26)
508 #define CPUID_EXT_OSXSAVE (1U << 27)
509 #define CPUID_EXT_AVX (1U << 28)
510 #define CPUID_EXT_F16C (1U << 29)
511 #define CPUID_EXT_RDRAND (1U << 30)
512 #define CPUID_EXT_HYPERVISOR (1U << 31)
513
514 #define CPUID_EXT2_FPU (1U << 0)
515 #define CPUID_EXT2_VME (1U << 1)
516 #define CPUID_EXT2_DE (1U << 2)
517 #define CPUID_EXT2_PSE (1U << 3)
518 #define CPUID_EXT2_TSC (1U << 4)
519 #define CPUID_EXT2_MSR (1U << 5)
520 #define CPUID_EXT2_PAE (1U << 6)
521 #define CPUID_EXT2_MCE (1U << 7)
522 #define CPUID_EXT2_CX8 (1U << 8)
523 #define CPUID_EXT2_APIC (1U << 9)
524 #define CPUID_EXT2_SYSCALL (1U << 11)
525 #define CPUID_EXT2_MTRR (1U << 12)
526 #define CPUID_EXT2_PGE (1U << 13)
527 #define CPUID_EXT2_MCA (1U << 14)
528 #define CPUID_EXT2_CMOV (1U << 15)
529 #define CPUID_EXT2_PAT (1U << 16)
530 #define CPUID_EXT2_PSE36 (1U << 17)
531 #define CPUID_EXT2_MP (1U << 19)
532 #define CPUID_EXT2_NX (1U << 20)
533 #define CPUID_EXT2_MMXEXT (1U << 22)
534 #define CPUID_EXT2_MMX (1U << 23)
535 #define CPUID_EXT2_FXSR (1U << 24)
536 #define CPUID_EXT2_FFXSR (1U << 25)
537 #define CPUID_EXT2_PDPE1GB (1U << 26)
538 #define CPUID_EXT2_RDTSCP (1U << 27)
539 #define CPUID_EXT2_LM (1U << 29)
540 #define CPUID_EXT2_3DNOWEXT (1U << 30)
541 #define CPUID_EXT2_3DNOW (1U << 31)
542
543 /* CPUID[8000_0001].EDX bits that are aliase of CPUID[1].EDX bits on AMD CPUs */
544 #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \
545 CPUID_EXT2_DE | CPUID_EXT2_PSE | \
546 CPUID_EXT2_TSC | CPUID_EXT2_MSR | \
547 CPUID_EXT2_PAE | CPUID_EXT2_MCE | \
548 CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \
549 CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \
550 CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \
551 CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \
552 CPUID_EXT2_MMX | CPUID_EXT2_FXSR)
553
554 #define CPUID_EXT3_LAHF_LM (1U << 0)
555 #define CPUID_EXT3_CMP_LEG (1U << 1)
556 #define CPUID_EXT3_SVM (1U << 2)
557 #define CPUID_EXT3_EXTAPIC (1U << 3)
558 #define CPUID_EXT3_CR8LEG (1U << 4)
559 #define CPUID_EXT3_ABM (1U << 5)
560 #define CPUID_EXT3_SSE4A (1U << 6)
561 #define CPUID_EXT3_MISALIGNSSE (1U << 7)
562 #define CPUID_EXT3_3DNOWPREFETCH (1U << 8)
563 #define CPUID_EXT3_OSVW (1U << 9)
564 #define CPUID_EXT3_IBS (1U << 10)
565 #define CPUID_EXT3_XOP (1U << 11)
566 #define CPUID_EXT3_SKINIT (1U << 12)
567 #define CPUID_EXT3_WDT (1U << 13)
568 #define CPUID_EXT3_LWP (1U << 15)
569 #define CPUID_EXT3_FMA4 (1U << 16)
570 #define CPUID_EXT3_TCE (1U << 17)
571 #define CPUID_EXT3_NODEID (1U << 19)
572 #define CPUID_EXT3_TBM (1U << 21)
573 #define CPUID_EXT3_TOPOEXT (1U << 22)
574 #define CPUID_EXT3_PERFCORE (1U << 23)
575 #define CPUID_EXT3_PERFNB (1U << 24)
576
577 #define CPUID_SVM_NPT (1U << 0)
578 #define CPUID_SVM_LBRV (1U << 1)
579 #define CPUID_SVM_SVMLOCK (1U << 2)
580 #define CPUID_SVM_NRIPSAVE (1U << 3)
581 #define CPUID_SVM_TSCSCALE (1U << 4)
582 #define CPUID_SVM_VMCBCLEAN (1U << 5)
583 #define CPUID_SVM_FLUSHASID (1U << 6)
584 #define CPUID_SVM_DECODEASSIST (1U << 7)
585 #define CPUID_SVM_PAUSEFILTER (1U << 10)
586 #define CPUID_SVM_PFTHRESHOLD (1U << 12)
587
588 #define CPUID_7_0_EBX_FSGSBASE (1U << 0)
589 #define CPUID_7_0_EBX_BMI1 (1U << 3)
590 #define CPUID_7_0_EBX_HLE (1U << 4)
591 #define CPUID_7_0_EBX_AVX2 (1U << 5)
592 #define CPUID_7_0_EBX_SMEP (1U << 7)
593 #define CPUID_7_0_EBX_BMI2 (1U << 8)
594 #define CPUID_7_0_EBX_ERMS (1U << 9)
595 #define CPUID_7_0_EBX_INVPCID (1U << 10)
596 #define CPUID_7_0_EBX_RTM (1U << 11)
597 #define CPUID_7_0_EBX_MPX (1U << 14)
598 #define CPUID_7_0_EBX_AVX512F (1U << 16) /* AVX-512 Foundation */
599 #define CPUID_7_0_EBX_RDSEED (1U << 18)
600 #define CPUID_7_0_EBX_ADX (1U << 19)
601 #define CPUID_7_0_EBX_SMAP (1U << 20)
602 #define CPUID_7_0_EBX_PCOMMIT (1U << 22) /* Persistent Commit */
603 #define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23) /* Flush a Cache Line Optimized */
604 #define CPUID_7_0_EBX_CLWB (1U << 24) /* Cache Line Write Back */
605 #define CPUID_7_0_EBX_AVX512PF (1U << 26) /* AVX-512 Prefetch */
606 #define CPUID_7_0_EBX_AVX512ER (1U << 27) /* AVX-512 Exponential and Reciprocal */
607 #define CPUID_7_0_EBX_AVX512CD (1U << 28) /* AVX-512 Conflict Detection */
608
609 #define CPUID_7_0_ECX_PKU (1U << 3)
610 #define CPUID_7_0_ECX_OSPKE (1U << 4)
611
612 #define CPUID_XSAVE_XSAVEOPT (1U << 0)
613 #define CPUID_XSAVE_XSAVEC (1U << 1)
614 #define CPUID_XSAVE_XGETBV1 (1U << 2)
615 #define CPUID_XSAVE_XSAVES (1U << 3)
616
617 #define CPUID_6_EAX_ARAT (1U << 2)
618
619 /* CPUID[0x80000007].EDX flags: */
620 #define CPUID_APM_INVTSC (1U << 8)
621
622 #define CPUID_VENDOR_SZ 12
623
624 #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */
625 #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */
626 #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */
627 #define CPUID_VENDOR_INTEL "GenuineIntel"
628
629 #define CPUID_VENDOR_AMD_1 0x68747541 /* "Auth" */
630 #define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */
631 #define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */
632 #define CPUID_VENDOR_AMD "AuthenticAMD"
633
634 #define CPUID_VENDOR_VIA "CentaurHauls"
635
636 #define CPUID_MWAIT_IBE (1U << 1) /* Interrupts can exit capability */
637 #define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */
638
639 #ifndef HYPERV_SPINLOCK_NEVER_RETRY
640 #define HYPERV_SPINLOCK_NEVER_RETRY 0xFFFFFFFF
641 #endif
642
643 #define EXCP00_DIVZ 0
644 #define EXCP01_DB 1
645 #define EXCP02_NMI 2
646 #define EXCP03_INT3 3
647 #define EXCP04_INTO 4
648 #define EXCP05_BOUND 5
649 #define EXCP06_ILLOP 6
650 #define EXCP07_PREX 7
651 #define EXCP08_DBLE 8
652 #define EXCP09_XERR 9
653 #define EXCP0A_TSS 10
654 #define EXCP0B_NOSEG 11
655 #define EXCP0C_STACK 12
656 #define EXCP0D_GPF 13
657 #define EXCP0E_PAGE 14
658 #define EXCP10_COPR 16
659 #define EXCP11_ALGN 17
660 #define EXCP12_MCHK 18
661
662 #define EXCP_SYSCALL 0x100 /* only happens in user only emulation
663 for syscall instruction */
664
665 /* i386-specific interrupt pending bits. */
666 #define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1
667 #define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2
668 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
669 #define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4
670 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0
671 #define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_1
672 #define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_2
673
674 /* Use a clearer name for this. */
675 #define CPU_INTERRUPT_INIT CPU_INTERRUPT_RESET
676
677 typedef enum {
678 CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
679 CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC = flags */
680
681 CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
682 CC_OP_MULW,
683 CC_OP_MULL,
684 CC_OP_MULQ,
685
686 CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
687 CC_OP_ADDW,
688 CC_OP_ADDL,
689 CC_OP_ADDQ,
690
691 CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
692 CC_OP_ADCW,
693 CC_OP_ADCL,
694 CC_OP_ADCQ,
695
696 CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
697 CC_OP_SUBW,
698 CC_OP_SUBL,
699 CC_OP_SUBQ,
700
701 CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
702 CC_OP_SBBW,
703 CC_OP_SBBL,
704 CC_OP_SBBQ,
705
706 CC_OP_LOGICB, /* modify all flags, CC_DST = res */
707 CC_OP_LOGICW,
708 CC_OP_LOGICL,
709 CC_OP_LOGICQ,
710
711 CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
712 CC_OP_INCW,
713 CC_OP_INCL,
714 CC_OP_INCQ,
715
716 CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */
717 CC_OP_DECW,
718 CC_OP_DECL,
719 CC_OP_DECQ,
720
721 CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
722 CC_OP_SHLW,
723 CC_OP_SHLL,
724 CC_OP_SHLQ,
725
726 CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
727 CC_OP_SARW,
728 CC_OP_SARL,
729 CC_OP_SARQ,
730
731 CC_OP_BMILGB, /* Z,S via CC_DST, C = SRC==0; O=0; P,A undefined */
732 CC_OP_BMILGW,
733 CC_OP_BMILGL,
734 CC_OP_BMILGQ,
735
736 CC_OP_ADCX, /* CC_DST = C, CC_SRC = rest. */
737 CC_OP_ADOX, /* CC_DST = O, CC_SRC = rest. */
738 CC_OP_ADCOX, /* CC_DST = C, CC_SRC2 = O, CC_SRC = rest. */
739
740 CC_OP_CLR, /* Z set, all other flags clear. */
741
742 CC_OP_NB,
743 } CCOp;
744
745 typedef struct SegmentCache {
746 uint32_t selector;
747 target_ulong base;
748 uint32_t limit;
749 uint32_t flags;
750 } SegmentCache;
751
752 #define MMREG_UNION(n, bits) \
753 union n { \
754 uint8_t _b_##n[(bits)/8]; \
755 uint16_t _w_##n[(bits)/16]; \
756 uint32_t _l_##n[(bits)/32]; \
757 uint64_t _q_##n[(bits)/64]; \
758 float32 _s_##n[(bits)/32]; \
759 float64 _d_##n[(bits)/64]; \
760 }
761
762 typedef MMREG_UNION(ZMMReg, 512) ZMMReg;
763 typedef MMREG_UNION(MMXReg, 64) MMXReg;
764
765 typedef struct BNDReg {
766 uint64_t lb;
767 uint64_t ub;
768 } BNDReg;
769
770 typedef struct BNDCSReg {
771 uint64_t cfgu;
772 uint64_t sts;
773 } BNDCSReg;
774
775 #define BNDCFG_ENABLE 1ULL
776 #define BNDCFG_BNDPRESERVE 2ULL
777 #define BNDCFG_BDIR_MASK TARGET_PAGE_MASK
778
779 #ifdef HOST_WORDS_BIGENDIAN
780 #define ZMM_B(n) _b_ZMMReg[63 - (n)]
781 #define ZMM_W(n) _w_ZMMReg[31 - (n)]
782 #define ZMM_L(n) _l_ZMMReg[15 - (n)]
783 #define ZMM_S(n) _s_ZMMReg[15 - (n)]
784 #define ZMM_Q(n) _q_ZMMReg[7 - (n)]
785 #define ZMM_D(n) _d_ZMMReg[7 - (n)]
786
787 #define MMX_B(n) _b_MMXReg[7 - (n)]
788 #define MMX_W(n) _w_MMXReg[3 - (n)]
789 #define MMX_L(n) _l_MMXReg[1 - (n)]
790 #define MMX_S(n) _s_MMXReg[1 - (n)]
791 #else
792 #define ZMM_B(n) _b_ZMMReg[n]
793 #define ZMM_W(n) _w_ZMMReg[n]
794 #define ZMM_L(n) _l_ZMMReg[n]
795 #define ZMM_S(n) _s_ZMMReg[n]
796 #define ZMM_Q(n) _q_ZMMReg[n]
797 #define ZMM_D(n) _d_ZMMReg[n]
798
799 #define MMX_B(n) _b_MMXReg[n]
800 #define MMX_W(n) _w_MMXReg[n]
801 #define MMX_L(n) _l_MMXReg[n]
802 #define MMX_S(n) _s_MMXReg[n]
803 #endif
804 #define MMX_Q(n) _q_MMXReg[n]
805
806 typedef union {
807 floatx80 d __attribute__((aligned(16)));
808 MMXReg mmx;
809 } FPReg;
810
811 typedef struct {
812 uint64_t base;
813 uint64_t mask;
814 } MTRRVar;
815
816 #define CPU_NB_REGS64 16
817 #define CPU_NB_REGS32 8
818
819 #ifdef TARGET_X86_64
820 #define CPU_NB_REGS CPU_NB_REGS64
821 #else
822 #define CPU_NB_REGS CPU_NB_REGS32
823 #endif
824
825 #define MAX_FIXED_COUNTERS 3
826 #define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0)
827
828 #define NB_MMU_MODES 3
829 #define TARGET_INSN_START_EXTRA_WORDS 1
830
831 #define NB_OPMASK_REGS 8
832
833 typedef enum TPRAccess {
834 TPR_ACCESS_READ,
835 TPR_ACCESS_WRITE,
836 } TPRAccess;
837
838 typedef struct CPUX86State {
839 /* standard registers */
840 target_ulong regs[CPU_NB_REGS];
841 target_ulong eip;
842 target_ulong eflags; /* eflags register. During CPU emulation, CC
843 flags and DF are set to zero because they are
844 stored elsewhere */
845
846 /* emulator internal eflags handling */
847 target_ulong cc_dst;
848 target_ulong cc_src;
849 target_ulong cc_src2;
850 uint32_t cc_op;
851 int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
852 uint32_t hflags; /* TB flags, see HF_xxx constants. These flags
853 are known at translation time. */
854 uint32_t hflags2; /* various other flags, see HF2_xxx constants. */
855
856 /* segments */
857 SegmentCache segs[6]; /* selector values */
858 SegmentCache ldt;
859 SegmentCache tr;
860 SegmentCache gdt; /* only base and limit are used */
861 SegmentCache idt; /* only base and limit are used */
862
863 target_ulong cr[5]; /* NOTE: cr1 is unused */
864 int32_t a20_mask;
865
866 BNDReg bnd_regs[4];
867 BNDCSReg bndcs_regs;
868 uint64_t msr_bndcfgs;
869 uint64_t efer;
870
871 /* Beginning of state preserved by INIT (dummy marker). */
872 struct {} start_init_save;
873
874 /* FPU state */
875 unsigned int fpstt; /* top of stack index */
876 uint16_t fpus;
877 uint16_t fpuc;
878 uint8_t fptags[8]; /* 0 = valid, 1 = empty */
879 FPReg fpregs[8];
880 /* KVM-only so far */
881 uint16_t fpop;
882 uint64_t fpip;
883 uint64_t fpdp;
884
885 /* emulator internal variables */
886 float_status fp_status;
887 floatx80 ft0;
888
889 float_status mmx_status; /* for 3DNow! float ops */
890 float_status sse_status;
891 uint32_t mxcsr;
892 ZMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32];
893 ZMMReg xmm_t0;
894 MMXReg mmx_t0;
895
896 uint64_t opmask_regs[NB_OPMASK_REGS];
897
898 /* sysenter registers */
899 uint32_t sysenter_cs;
900 target_ulong sysenter_esp;
901 target_ulong sysenter_eip;
902 uint64_t star;
903
904 uint64_t vm_hsave;
905
906 #ifdef TARGET_X86_64
907 target_ulong lstar;
908 target_ulong cstar;
909 target_ulong fmask;
910 target_ulong kernelgsbase;
911 #endif
912
913 uint64_t tsc;
914 uint64_t tsc_adjust;
915 uint64_t tsc_deadline;
916
917 uint64_t mcg_status;
918 uint64_t msr_ia32_misc_enable;
919 uint64_t msr_ia32_feature_control;
920
921 uint64_t msr_fixed_ctr_ctrl;
922 uint64_t msr_global_ctrl;
923 uint64_t msr_global_status;
924 uint64_t msr_global_ovf_ctrl;
925 uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS];
926 uint64_t msr_gp_counters[MAX_GP_COUNTERS];
927 uint64_t msr_gp_evtsel[MAX_GP_COUNTERS];
928
929 uint64_t pat;
930 uint32_t smbase;
931
932 /* End of state preserved by INIT (dummy marker). */
933 struct {} end_init_save;
934
935 uint64_t system_time_msr;
936 uint64_t wall_clock_msr;
937 uint64_t steal_time_msr;
938 uint64_t async_pf_en_msr;
939 uint64_t pv_eoi_en_msr;
940
941 uint64_t msr_hv_hypercall;
942 uint64_t msr_hv_guest_os_id;
943 uint64_t msr_hv_vapic;
944 uint64_t msr_hv_tsc;
945 uint64_t msr_hv_crash_params[HV_X64_MSR_CRASH_PARAMS];
946 uint64_t msr_hv_runtime;
947 uint64_t msr_hv_synic_control;
948 uint64_t msr_hv_synic_version;
949 uint64_t msr_hv_synic_evt_page;
950 uint64_t msr_hv_synic_msg_page;
951 uint64_t msr_hv_synic_sint[HV_SYNIC_SINT_COUNT];
952 uint64_t msr_hv_stimer_config[HV_SYNIC_STIMER_COUNT];
953 uint64_t msr_hv_stimer_count[HV_SYNIC_STIMER_COUNT];
954
955 /* exception/interrupt handling */
956 int error_code;
957 int exception_is_int;
958 target_ulong exception_next_eip;
959 target_ulong dr[8]; /* debug registers; note dr4 and dr5 are unused */
960 union {
961 struct CPUBreakpoint *cpu_breakpoint[4];
962 struct CPUWatchpoint *cpu_watchpoint[4];
963 }; /* break/watchpoints for dr[0..3] */
964 int old_exception; /* exception in flight */
965
966 uint64_t vm_vmcb;
967 uint64_t tsc_offset;
968 uint64_t intercept;
969 uint16_t intercept_cr_read;
970 uint16_t intercept_cr_write;
971 uint16_t intercept_dr_read;
972 uint16_t intercept_dr_write;
973 uint32_t intercept_exceptions;
974 uint8_t v_tpr;
975
976 /* KVM states, automatically cleared on reset */
977 uint8_t nmi_injected;
978 uint8_t nmi_pending;
979
980 CPU_COMMON
981
982 /* Fields from here on are preserved across CPU reset. */
983
984 /* processor features (e.g. for CPUID insn) */
985 uint32_t cpuid_level;
986 uint32_t cpuid_xlevel;
987 uint32_t cpuid_xlevel2;
988 uint32_t cpuid_vendor1;
989 uint32_t cpuid_vendor2;
990 uint32_t cpuid_vendor3;
991 uint32_t cpuid_version;
992 FeatureWordArray features;
993 uint32_t cpuid_model[12];
994
995 /* MTRRs */
996 uint64_t mtrr_fixed[11];
997 uint64_t mtrr_deftype;
998 MTRRVar mtrr_var[MSR_MTRRcap_VCNT];
999
1000 /* For KVM */
1001 uint32_t mp_state;
1002 int32_t exception_injected;
1003 int32_t interrupt_injected;
1004 uint8_t soft_interrupt;
1005 uint8_t has_error_code;
1006 uint32_t sipi_vector;
1007 bool tsc_valid;
1008 int64_t tsc_khz;
1009 int64_t user_tsc_khz; /* for sanity check only */
1010 void *kvm_xsave_buf;
1011
1012 uint64_t mcg_cap;
1013 uint64_t mcg_ctl;
1014 uint64_t mce_banks[MCE_BANKS_DEF*4];
1015
1016 uint64_t tsc_aux;
1017
1018 /* vmstate */
1019 uint16_t fpus_vmstate;
1020 uint16_t fptag_vmstate;
1021 uint16_t fpregs_format_vmstate;
1022 uint64_t xstate_bv;
1023
1024 uint64_t xcr0;
1025 uint64_t xss;
1026
1027 uint32_t pkru;
1028
1029 TPRAccess tpr_access_type;
1030 } CPUX86State;
1031
1032 /**
1033 * X86CPU:
1034 * @env: #CPUX86State
1035 * @migratable: If set, only migratable flags will be accepted when "enforce"
1036 * mode is used, and only migratable flags will be included in the "host"
1037 * CPU model.
1038 *
1039 * An x86 CPU.
1040 */
1041 struct X86CPU {
1042 /*< private >*/
1043 CPUState parent_obj;
1044 /*< public >*/
1045
1046 CPUX86State env;
1047
1048 bool hyperv_vapic;
1049 bool hyperv_relaxed_timing;
1050 int hyperv_spinlock_attempts;
1051 char *hyperv_vendor_id;
1052 bool hyperv_time;
1053 bool hyperv_crash;
1054 bool hyperv_reset;
1055 bool hyperv_vpindex;
1056 bool hyperv_runtime;
1057 bool hyperv_synic;
1058 bool hyperv_stimer;
1059 bool check_cpuid;
1060 bool enforce_cpuid;
1061 bool expose_kvm;
1062 bool migratable;
1063 bool host_features;
1064 int64_t apic_id;
1065
1066 /* if true the CPUID code directly forward host cache leaves to the guest */
1067 bool cache_info_passthrough;
1068
1069 /* Features that were filtered out because of missing host capabilities */
1070 uint32_t filtered_features[FEATURE_WORDS];
1071
1072 /* Enable PMU CPUID bits. This can't be enabled by default yet because
1073 * it doesn't have ABI stability guarantees, as it passes all PMU CPUID
1074 * bits returned by GET_SUPPORTED_CPUID (that depend on host CPU and kernel
1075 * capabilities) directly to the guest.
1076 */
1077 bool enable_pmu;
1078
1079 /* in order to simplify APIC support, we leave this pointer to the
1080 user */
1081 struct DeviceState *apic_state;
1082 struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram;
1083 Notifier machine_done;
1084 };
1085
1086 static inline X86CPU *x86_env_get_cpu(CPUX86State *env)
1087 {
1088 return container_of(env, X86CPU, env);
1089 }
1090
1091 #define ENV_GET_CPU(e) CPU(x86_env_get_cpu(e))
1092
1093 #define ENV_OFFSET offsetof(X86CPU, env)
1094
1095 #ifndef CONFIG_USER_ONLY
1096 extern struct VMStateDescription vmstate_x86_cpu;
1097 #endif
1098
1099 /**
1100 * x86_cpu_do_interrupt:
1101 * @cpu: vCPU the interrupt is to be handled by.
1102 */
1103 void x86_cpu_do_interrupt(CPUState *cpu);
1104 bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req);
1105
1106 int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
1107 int cpuid, void *opaque);
1108 int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
1109 int cpuid, void *opaque);
1110 int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
1111 void *opaque);
1112 int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
1113 void *opaque);
1114
1115 void x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
1116 Error **errp);
1117
1118 void x86_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
1119 int flags);
1120
1121 hwaddr x86_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
1122
1123 int x86_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
1124 int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1125
1126 void x86_cpu_exec_enter(CPUState *cpu);
1127 void x86_cpu_exec_exit(CPUState *cpu);
1128
1129 X86CPU *cpu_x86_init(const char *cpu_model);
1130 X86CPU *cpu_x86_create(const char *cpu_model, Error **errp);
1131 int cpu_x86_exec(CPUState *cpu);
1132 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf);
1133 void x86_cpudef_setup(void);
1134 int cpu_x86_support_mca_broadcast(CPUX86State *env);
1135
1136 int cpu_get_pic_interrupt(CPUX86State *s);
1137 /* MSDOS compatibility mode FPU exception support */
1138 void cpu_set_ferr(CPUX86State *s);
1139
1140 /* this function must always be used to load data in the segment
1141 cache: it synchronizes the hflags with the segment cache values */
1142 static inline void cpu_x86_load_seg_cache(CPUX86State *env,
1143 int seg_reg, unsigned int selector,
1144 target_ulong base,
1145 unsigned int limit,
1146 unsigned int flags)
1147 {
1148 SegmentCache *sc;
1149 unsigned int new_hflags;
1150
1151 sc = &env->segs[seg_reg];
1152 sc->selector = selector;
1153 sc->base = base;
1154 sc->limit = limit;
1155 sc->flags = flags;
1156
1157 /* update the hidden flags */
1158 {
1159 if (seg_reg == R_CS) {
1160 #ifdef TARGET_X86_64
1161 if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
1162 /* long mode */
1163 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1164 env->hflags &= ~(HF_ADDSEG_MASK);
1165 } else
1166 #endif
1167 {
1168 /* legacy / compatibility case */
1169 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
1170 >> (DESC_B_SHIFT - HF_CS32_SHIFT);
1171 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) |
1172 new_hflags;
1173 }
1174 }
1175 if (seg_reg == R_SS) {
1176 int cpl = (flags >> DESC_DPL_SHIFT) & 3;
1177 #if HF_CPL_MASK != 3
1178 #error HF_CPL_MASK is hardcoded
1179 #endif
1180 env->hflags = (env->hflags & ~HF_CPL_MASK) | cpl;
1181 }
1182 new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
1183 >> (DESC_B_SHIFT - HF_SS32_SHIFT);
1184 if (env->hflags & HF_CS64_MASK) {
1185 /* zero base assumed for DS, ES and SS in long mode */
1186 } else if (!(env->cr[0] & CR0_PE_MASK) ||
1187 (env->eflags & VM_MASK) ||
1188 !(env->hflags & HF_CS32_MASK)) {
1189 /* XXX: try to avoid this test. The problem comes from the
1190 fact that is real mode or vm86 mode we only modify the
1191 'base' and 'selector' fields of the segment cache to go
1192 faster. A solution may be to force addseg to one in
1193 translate-i386.c. */
1194 new_hflags |= HF_ADDSEG_MASK;
1195 } else {
1196 new_hflags |= ((env->segs[R_DS].base |
1197 env->segs[R_ES].base |
1198 env->segs[R_SS].base) != 0) <<
1199 HF_ADDSEG_SHIFT;
1200 }
1201 env->hflags = (env->hflags &
1202 ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
1203 }
1204 }
1205
1206 static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu,
1207 uint8_t sipi_vector)
1208 {
1209 CPUState *cs = CPU(cpu);
1210 CPUX86State *env = &cpu->env;
1211
1212 env->eip = 0;
1213 cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8,
1214 sipi_vector << 12,
1215 env->segs[R_CS].limit,
1216 env->segs[R_CS].flags);
1217 cs->halted = 0;
1218 }
1219
1220 int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
1221 target_ulong *base, unsigned int *limit,
1222 unsigned int *flags);
1223
1224 /* op_helper.c */
1225 /* used for debug or cpu save/restore */
1226 void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, floatx80 f);
1227 floatx80 cpu_set_fp80(uint64_t mant, uint16_t upper);
1228
1229 /* cpu-exec.c */
1230 /* the following helpers are only usable in user mode simulation as
1231 they can trigger unexpected exceptions */
1232 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
1233 void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32);
1234 void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32);
1235
1236 /* you can call this signal handler from your SIGBUS and SIGSEGV
1237 signal handlers to inform the virtual CPU of exceptions. non zero
1238 is returned if the signal was handled by the virtual CPU. */
1239 int cpu_x86_signal_handler(int host_signum, void *pinfo,
1240 void *puc);
1241
1242 /* cpu.c */
1243 typedef struct ExtSaveArea {
1244 uint32_t feature, bits;
1245 uint32_t offset, size;
1246 } ExtSaveArea;
1247
1248 extern const ExtSaveArea x86_ext_save_areas[];
1249
1250 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1251 uint32_t *eax, uint32_t *ebx,
1252 uint32_t *ecx, uint32_t *edx);
1253 void cpu_clear_apic_feature(CPUX86State *env);
1254 void host_cpuid(uint32_t function, uint32_t count,
1255 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx);
1256
1257 /* helper.c */
1258 int x86_cpu_handle_mmu_fault(CPUState *cpu, vaddr addr,
1259 int is_write, int mmu_idx);
1260 void x86_cpu_set_a20(X86CPU *cpu, int a20_state);
1261
1262 #ifndef CONFIG_USER_ONLY
1263 uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr);
1264 uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr);
1265 uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr);
1266 uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr);
1267 void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val);
1268 void x86_stl_phys_notdirty(CPUState *cs, hwaddr addr, uint32_t val);
1269 void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val);
1270 void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val);
1271 void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val);
1272 #endif
1273
1274 void breakpoint_handler(CPUState *cs);
1275
1276 /* will be suppressed */
1277 void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
1278 void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
1279 void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
1280 void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7);
1281
1282 /* hw/pc.c */
1283 uint64_t cpu_get_tsc(CPUX86State *env);
1284
1285 #define TARGET_PAGE_BITS 12
1286
1287 #ifdef TARGET_X86_64
1288 #define TARGET_PHYS_ADDR_SPACE_BITS 52
1289 /* ??? This is really 48 bits, sign-extended, but the only thing
1290 accessible to userland with bit 48 set is the VSYSCALL, and that
1291 is handled via other mechanisms. */
1292 #define TARGET_VIRT_ADDR_SPACE_BITS 47
1293 #else
1294 #define TARGET_PHYS_ADDR_SPACE_BITS 36
1295 #define TARGET_VIRT_ADDR_SPACE_BITS 32
1296 #endif
1297
1298 /* XXX: This value should match the one returned by CPUID
1299 * and in exec.c */
1300 # if defined(TARGET_X86_64)
1301 # define PHYS_ADDR_MASK 0xffffffffffLL
1302 # else
1303 # define PHYS_ADDR_MASK 0xfffffffffLL
1304 # endif
1305
1306 #define cpu_init(cpu_model) CPU(cpu_x86_init(cpu_model))
1307
1308 #define cpu_exec cpu_x86_exec
1309 #define cpu_signal_handler cpu_x86_signal_handler
1310 #define cpu_list x86_cpu_list
1311 #define cpudef_setup x86_cpudef_setup
1312
1313 /* MMU modes definitions */
1314 #define MMU_MODE0_SUFFIX _ksmap
1315 #define MMU_MODE1_SUFFIX _user
1316 #define MMU_MODE2_SUFFIX _knosmap /* SMAP disabled or CPL<3 && AC=1 */
1317 #define MMU_KSMAP_IDX 0
1318 #define MMU_USER_IDX 1
1319 #define MMU_KNOSMAP_IDX 2
1320 static inline int cpu_mmu_index(CPUX86State *env, bool ifetch)
1321 {
1322 return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX :
1323 (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK))
1324 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX;
1325 }
1326
1327 static inline int cpu_mmu_index_kernel(CPUX86State *env)
1328 {
1329 return !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP_IDX :
1330 ((env->hflags & HF_CPL_MASK) < 3 && (env->eflags & AC_MASK))
1331 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX;
1332 }
1333
1334 #define CC_DST (env->cc_dst)
1335 #define CC_SRC (env->cc_src)
1336 #define CC_SRC2 (env->cc_src2)
1337 #define CC_OP (env->cc_op)
1338
1339 /* n must be a constant to be efficient */
1340 static inline target_long lshift(target_long x, int n)
1341 {
1342 if (n >= 0) {
1343 return x << n;
1344 } else {
1345 return x >> (-n);
1346 }
1347 }
1348
1349 /* float macros */
1350 #define FT0 (env->ft0)
1351 #define ST0 (env->fpregs[env->fpstt].d)
1352 #define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d)
1353 #define ST1 ST(1)
1354
1355 /* translate.c */
1356 void tcg_x86_init(void);
1357
1358 #include "exec/cpu-all.h"
1359 #include "svm.h"
1360
1361 #if !defined(CONFIG_USER_ONLY)
1362 #include "hw/i386/apic.h"
1363 #endif
1364
1365 #include "exec/exec-all.h"
1366
1367 static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *pc,
1368 target_ulong *cs_base, uint32_t *flags)
1369 {
1370 *cs_base = env->segs[R_CS].base;
1371 *pc = *cs_base + env->eip;
1372 *flags = env->hflags |
1373 (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK));
1374 }
1375
1376 void do_cpu_init(X86CPU *cpu);
1377 void do_cpu_sipi(X86CPU *cpu);
1378
1379 #define MCE_INJECT_BROADCAST 1
1380 #define MCE_INJECT_UNCOND_AO 2
1381
1382 void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank,
1383 uint64_t status, uint64_t mcg_status, uint64_t addr,
1384 uint64_t misc, int flags);
1385
1386 /* excp_helper.c */
1387 void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index);
1388 void QEMU_NORETURN raise_exception_ra(CPUX86State *env, int exception_index,
1389 uintptr_t retaddr);
1390 void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_index,
1391 int error_code);
1392 void QEMU_NORETURN raise_exception_err_ra(CPUX86State *env, int exception_index,
1393 int error_code, uintptr_t retaddr);
1394 void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_int,
1395 int error_code, int next_eip_addend);
1396
1397 /* cc_helper.c */
1398 extern const uint8_t parity_table[256];
1399 uint32_t cpu_cc_compute_all(CPUX86State *env1, int op);
1400 void update_fp_status(CPUX86State *env);
1401
1402 static inline uint32_t cpu_compute_eflags(CPUX86State *env)
1403 {
1404 return env->eflags | cpu_cc_compute_all(env, CC_OP) | (env->df & DF_MASK);
1405 }
1406
1407 /* NOTE: the translator must set DisasContext.cc_op to CC_OP_EFLAGS
1408 * after generating a call to a helper that uses this.
1409 */
1410 static inline void cpu_load_eflags(CPUX86State *env, int eflags,
1411 int update_mask)
1412 {
1413 CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
1414 CC_OP = CC_OP_EFLAGS;
1415 env->df = 1 - (2 * ((eflags >> 10) & 1));
1416 env->eflags = (env->eflags & ~update_mask) |
1417 (eflags & update_mask) | 0x2;
1418 }
1419
1420 /* load efer and update the corresponding hflags. XXX: do consistency
1421 checks with cpuid bits? */
1422 static inline void cpu_load_efer(CPUX86State *env, uint64_t val)
1423 {
1424 env->efer = val;
1425 env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK);
1426 if (env->efer & MSR_EFER_LMA) {
1427 env->hflags |= HF_LMA_MASK;
1428 }
1429 if (env->efer & MSR_EFER_SVME) {
1430 env->hflags |= HF_SVME_MASK;
1431 }
1432 }
1433
1434 static inline MemTxAttrs cpu_get_mem_attrs(CPUX86State *env)
1435 {
1436 return ((MemTxAttrs) { .secure = (env->hflags & HF_SMM_MASK) != 0 });
1437 }
1438
1439 /* fpu_helper.c */
1440 void cpu_set_mxcsr(CPUX86State *env, uint32_t val);
1441 void cpu_set_fpuc(CPUX86State *env, uint16_t val);
1442
1443 /* mem_helper.c */
1444 void helper_lock_init(void);
1445
1446 /* svm_helper.c */
1447 void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type,
1448 uint64_t param);
1449 void cpu_vmexit(CPUX86State *nenv, uint32_t exit_code, uint64_t exit_info_1);
1450
1451 /* seg_helper.c */
1452 void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw);
1453
1454 /* smm_helper.c */
1455 void do_smm_enter(X86CPU *cpu);
1456 void cpu_smm_update(X86CPU *cpu);
1457
1458 /* apic.c */
1459 void cpu_report_tpr_access(CPUX86State *env, TPRAccess access);
1460 void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip,
1461 TPRAccess access);
1462
1463
1464 /* Change the value of a KVM-specific default
1465 *
1466 * If value is NULL, no default will be set and the original
1467 * value from the CPU model table will be kept.
1468 *
1469 * It is valid to call this function only for properties that
1470 * are already present in the kvm_default_props table.
1471 */
1472 void x86_cpu_change_kvm_default(const char *prop, const char *value);
1473
1474 /* mpx_helper.c */
1475 void cpu_sync_bndcs_hflags(CPUX86State *env);
1476
1477 /* Return name of 32-bit register, from a R_* constant */
1478 const char *get_register_name_32(unsigned int reg);
1479
1480 void enable_compat_apic_id_mode(void);
1481
1482 #define APIC_DEFAULT_ADDRESS 0xfee00000
1483 #define APIC_SPACE_SIZE 0x100000
1484
1485 void x86_cpu_dump_local_apic_state(CPUState *cs, FILE *f,
1486 fprintf_function cpu_fprintf, int flags);
1487
1488 /* cpu.c */
1489 bool cpu_is_bsp(X86CPU *cpu);
1490
1491 #endif /* CPU_I386_H */