Update version for 1.5.0 release.
[qemu.git] / target-i386 / fpu_helper.c
1 /*
2 * x86 FPU, MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4/PNI helpers
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include <math.h>
21 #include "cpu.h"
22 #include "helper.h"
23 #include "qemu/aes.h"
24 #include "qemu/host-utils.h"
25
26 #if !defined(CONFIG_USER_ONLY)
27 #include "exec/softmmu_exec.h"
28 #endif /* !defined(CONFIG_USER_ONLY) */
29
30 #define FPU_RC_MASK 0xc00
31 #define FPU_RC_NEAR 0x000
32 #define FPU_RC_DOWN 0x400
33 #define FPU_RC_UP 0x800
34 #define FPU_RC_CHOP 0xc00
35
36 #define MAXTAN 9223372036854775808.0
37
38 /* the following deal with x86 long double-precision numbers */
39 #define MAXEXPD 0x7fff
40 #define EXPBIAS 16383
41 #define EXPD(fp) (fp.l.upper & 0x7fff)
42 #define SIGND(fp) ((fp.l.upper) & 0x8000)
43 #define MANTD(fp) (fp.l.lower)
44 #define BIASEXPONENT(fp) fp.l.upper = (fp.l.upper & ~(0x7fff)) | EXPBIAS
45
46 #define FPUS_IE (1 << 0)
47 #define FPUS_DE (1 << 1)
48 #define FPUS_ZE (1 << 2)
49 #define FPUS_OE (1 << 3)
50 #define FPUS_UE (1 << 4)
51 #define FPUS_PE (1 << 5)
52 #define FPUS_SF (1 << 6)
53 #define FPUS_SE (1 << 7)
54 #define FPUS_B (1 << 15)
55
56 #define FPUC_EM 0x3f
57
58 #define floatx80_lg2 make_floatx80(0x3ffd, 0x9a209a84fbcff799LL)
59 #define floatx80_l2e make_floatx80(0x3fff, 0xb8aa3b295c17f0bcLL)
60 #define floatx80_l2t make_floatx80(0x4000, 0xd49a784bcd1b8afeLL)
61
62 static inline void fpush(CPUX86State *env)
63 {
64 env->fpstt = (env->fpstt - 1) & 7;
65 env->fptags[env->fpstt] = 0; /* validate stack entry */
66 }
67
68 static inline void fpop(CPUX86State *env)
69 {
70 env->fptags[env->fpstt] = 1; /* invalidate stack entry */
71 env->fpstt = (env->fpstt + 1) & 7;
72 }
73
74 static inline floatx80 helper_fldt(CPUX86State *env, target_ulong ptr)
75 {
76 CPU_LDoubleU temp;
77
78 temp.l.lower = cpu_ldq_data(env, ptr);
79 temp.l.upper = cpu_lduw_data(env, ptr + 8);
80 return temp.d;
81 }
82
83 static inline void helper_fstt(CPUX86State *env, floatx80 f, target_ulong ptr)
84 {
85 CPU_LDoubleU temp;
86
87 temp.d = f;
88 cpu_stq_data(env, ptr, temp.l.lower);
89 cpu_stw_data(env, ptr + 8, temp.l.upper);
90 }
91
92 /* x87 FPU helpers */
93
94 static inline double floatx80_to_double(CPUX86State *env, floatx80 a)
95 {
96 union {
97 float64 f64;
98 double d;
99 } u;
100
101 u.f64 = floatx80_to_float64(a, &env->fp_status);
102 return u.d;
103 }
104
105 static inline floatx80 double_to_floatx80(CPUX86State *env, double a)
106 {
107 union {
108 float64 f64;
109 double d;
110 } u;
111
112 u.d = a;
113 return float64_to_floatx80(u.f64, &env->fp_status);
114 }
115
116 static void fpu_set_exception(CPUX86State *env, int mask)
117 {
118 env->fpus |= mask;
119 if (env->fpus & (~env->fpuc & FPUC_EM)) {
120 env->fpus |= FPUS_SE | FPUS_B;
121 }
122 }
123
124 static inline floatx80 helper_fdiv(CPUX86State *env, floatx80 a, floatx80 b)
125 {
126 if (floatx80_is_zero(b)) {
127 fpu_set_exception(env, FPUS_ZE);
128 }
129 return floatx80_div(a, b, &env->fp_status);
130 }
131
132 static void fpu_raise_exception(CPUX86State *env)
133 {
134 if (env->cr[0] & CR0_NE_MASK) {
135 raise_exception(env, EXCP10_COPR);
136 }
137 #if !defined(CONFIG_USER_ONLY)
138 else {
139 cpu_set_ferr(env);
140 }
141 #endif
142 }
143
144 void helper_flds_FT0(CPUX86State *env, uint32_t val)
145 {
146 union {
147 float32 f;
148 uint32_t i;
149 } u;
150
151 u.i = val;
152 FT0 = float32_to_floatx80(u.f, &env->fp_status);
153 }
154
155 void helper_fldl_FT0(CPUX86State *env, uint64_t val)
156 {
157 union {
158 float64 f;
159 uint64_t i;
160 } u;
161
162 u.i = val;
163 FT0 = float64_to_floatx80(u.f, &env->fp_status);
164 }
165
166 void helper_fildl_FT0(CPUX86State *env, int32_t val)
167 {
168 FT0 = int32_to_floatx80(val, &env->fp_status);
169 }
170
171 void helper_flds_ST0(CPUX86State *env, uint32_t val)
172 {
173 int new_fpstt;
174 union {
175 float32 f;
176 uint32_t i;
177 } u;
178
179 new_fpstt = (env->fpstt - 1) & 7;
180 u.i = val;
181 env->fpregs[new_fpstt].d = float32_to_floatx80(u.f, &env->fp_status);
182 env->fpstt = new_fpstt;
183 env->fptags[new_fpstt] = 0; /* validate stack entry */
184 }
185
186 void helper_fldl_ST0(CPUX86State *env, uint64_t val)
187 {
188 int new_fpstt;
189 union {
190 float64 f;
191 uint64_t i;
192 } u;
193
194 new_fpstt = (env->fpstt - 1) & 7;
195 u.i = val;
196 env->fpregs[new_fpstt].d = float64_to_floatx80(u.f, &env->fp_status);
197 env->fpstt = new_fpstt;
198 env->fptags[new_fpstt] = 0; /* validate stack entry */
199 }
200
201 void helper_fildl_ST0(CPUX86State *env, int32_t val)
202 {
203 int new_fpstt;
204
205 new_fpstt = (env->fpstt - 1) & 7;
206 env->fpregs[new_fpstt].d = int32_to_floatx80(val, &env->fp_status);
207 env->fpstt = new_fpstt;
208 env->fptags[new_fpstt] = 0; /* validate stack entry */
209 }
210
211 void helper_fildll_ST0(CPUX86State *env, int64_t val)
212 {
213 int new_fpstt;
214
215 new_fpstt = (env->fpstt - 1) & 7;
216 env->fpregs[new_fpstt].d = int64_to_floatx80(val, &env->fp_status);
217 env->fpstt = new_fpstt;
218 env->fptags[new_fpstt] = 0; /* validate stack entry */
219 }
220
221 uint32_t helper_fsts_ST0(CPUX86State *env)
222 {
223 union {
224 float32 f;
225 uint32_t i;
226 } u;
227
228 u.f = floatx80_to_float32(ST0, &env->fp_status);
229 return u.i;
230 }
231
232 uint64_t helper_fstl_ST0(CPUX86State *env)
233 {
234 union {
235 float64 f;
236 uint64_t i;
237 } u;
238
239 u.f = floatx80_to_float64(ST0, &env->fp_status);
240 return u.i;
241 }
242
243 int32_t helper_fist_ST0(CPUX86State *env)
244 {
245 int32_t val;
246
247 val = floatx80_to_int32(ST0, &env->fp_status);
248 if (val != (int16_t)val) {
249 val = -32768;
250 }
251 return val;
252 }
253
254 int32_t helper_fistl_ST0(CPUX86State *env)
255 {
256 int32_t val;
257
258 val = floatx80_to_int32(ST0, &env->fp_status);
259 return val;
260 }
261
262 int64_t helper_fistll_ST0(CPUX86State *env)
263 {
264 int64_t val;
265
266 val = floatx80_to_int64(ST0, &env->fp_status);
267 return val;
268 }
269
270 int32_t helper_fistt_ST0(CPUX86State *env)
271 {
272 int32_t val;
273
274 val = floatx80_to_int32_round_to_zero(ST0, &env->fp_status);
275 if (val != (int16_t)val) {
276 val = -32768;
277 }
278 return val;
279 }
280
281 int32_t helper_fisttl_ST0(CPUX86State *env)
282 {
283 int32_t val;
284
285 val = floatx80_to_int32_round_to_zero(ST0, &env->fp_status);
286 return val;
287 }
288
289 int64_t helper_fisttll_ST0(CPUX86State *env)
290 {
291 int64_t val;
292
293 val = floatx80_to_int64_round_to_zero(ST0, &env->fp_status);
294 return val;
295 }
296
297 void helper_fldt_ST0(CPUX86State *env, target_ulong ptr)
298 {
299 int new_fpstt;
300
301 new_fpstt = (env->fpstt - 1) & 7;
302 env->fpregs[new_fpstt].d = helper_fldt(env, ptr);
303 env->fpstt = new_fpstt;
304 env->fptags[new_fpstt] = 0; /* validate stack entry */
305 }
306
307 void helper_fstt_ST0(CPUX86State *env, target_ulong ptr)
308 {
309 helper_fstt(env, ST0, ptr);
310 }
311
312 void helper_fpush(CPUX86State *env)
313 {
314 fpush(env);
315 }
316
317 void helper_fpop(CPUX86State *env)
318 {
319 fpop(env);
320 }
321
322 void helper_fdecstp(CPUX86State *env)
323 {
324 env->fpstt = (env->fpstt - 1) & 7;
325 env->fpus &= ~0x4700;
326 }
327
328 void helper_fincstp(CPUX86State *env)
329 {
330 env->fpstt = (env->fpstt + 1) & 7;
331 env->fpus &= ~0x4700;
332 }
333
334 /* FPU move */
335
336 void helper_ffree_STN(CPUX86State *env, int st_index)
337 {
338 env->fptags[(env->fpstt + st_index) & 7] = 1;
339 }
340
341 void helper_fmov_ST0_FT0(CPUX86State *env)
342 {
343 ST0 = FT0;
344 }
345
346 void helper_fmov_FT0_STN(CPUX86State *env, int st_index)
347 {
348 FT0 = ST(st_index);
349 }
350
351 void helper_fmov_ST0_STN(CPUX86State *env, int st_index)
352 {
353 ST0 = ST(st_index);
354 }
355
356 void helper_fmov_STN_ST0(CPUX86State *env, int st_index)
357 {
358 ST(st_index) = ST0;
359 }
360
361 void helper_fxchg_ST0_STN(CPUX86State *env, int st_index)
362 {
363 floatx80 tmp;
364
365 tmp = ST(st_index);
366 ST(st_index) = ST0;
367 ST0 = tmp;
368 }
369
370 /* FPU operations */
371
372 static const int fcom_ccval[4] = {0x0100, 0x4000, 0x0000, 0x4500};
373
374 void helper_fcom_ST0_FT0(CPUX86State *env)
375 {
376 int ret;
377
378 ret = floatx80_compare(ST0, FT0, &env->fp_status);
379 env->fpus = (env->fpus & ~0x4500) | fcom_ccval[ret + 1];
380 }
381
382 void helper_fucom_ST0_FT0(CPUX86State *env)
383 {
384 int ret;
385
386 ret = floatx80_compare_quiet(ST0, FT0, &env->fp_status);
387 env->fpus = (env->fpus & ~0x4500) | fcom_ccval[ret + 1];
388 }
389
390 static const int fcomi_ccval[4] = {CC_C, CC_Z, 0, CC_Z | CC_P | CC_C};
391
392 void helper_fcomi_ST0_FT0(CPUX86State *env)
393 {
394 int eflags;
395 int ret;
396
397 ret = floatx80_compare(ST0, FT0, &env->fp_status);
398 eflags = cpu_cc_compute_all(env, CC_OP);
399 eflags = (eflags & ~(CC_Z | CC_P | CC_C)) | fcomi_ccval[ret + 1];
400 CC_SRC = eflags;
401 }
402
403 void helper_fucomi_ST0_FT0(CPUX86State *env)
404 {
405 int eflags;
406 int ret;
407
408 ret = floatx80_compare_quiet(ST0, FT0, &env->fp_status);
409 eflags = cpu_cc_compute_all(env, CC_OP);
410 eflags = (eflags & ~(CC_Z | CC_P | CC_C)) | fcomi_ccval[ret + 1];
411 CC_SRC = eflags;
412 }
413
414 void helper_fadd_ST0_FT0(CPUX86State *env)
415 {
416 ST0 = floatx80_add(ST0, FT0, &env->fp_status);
417 }
418
419 void helper_fmul_ST0_FT0(CPUX86State *env)
420 {
421 ST0 = floatx80_mul(ST0, FT0, &env->fp_status);
422 }
423
424 void helper_fsub_ST0_FT0(CPUX86State *env)
425 {
426 ST0 = floatx80_sub(ST0, FT0, &env->fp_status);
427 }
428
429 void helper_fsubr_ST0_FT0(CPUX86State *env)
430 {
431 ST0 = floatx80_sub(FT0, ST0, &env->fp_status);
432 }
433
434 void helper_fdiv_ST0_FT0(CPUX86State *env)
435 {
436 ST0 = helper_fdiv(env, ST0, FT0);
437 }
438
439 void helper_fdivr_ST0_FT0(CPUX86State *env)
440 {
441 ST0 = helper_fdiv(env, FT0, ST0);
442 }
443
444 /* fp operations between STN and ST0 */
445
446 void helper_fadd_STN_ST0(CPUX86State *env, int st_index)
447 {
448 ST(st_index) = floatx80_add(ST(st_index), ST0, &env->fp_status);
449 }
450
451 void helper_fmul_STN_ST0(CPUX86State *env, int st_index)
452 {
453 ST(st_index) = floatx80_mul(ST(st_index), ST0, &env->fp_status);
454 }
455
456 void helper_fsub_STN_ST0(CPUX86State *env, int st_index)
457 {
458 ST(st_index) = floatx80_sub(ST(st_index), ST0, &env->fp_status);
459 }
460
461 void helper_fsubr_STN_ST0(CPUX86State *env, int st_index)
462 {
463 ST(st_index) = floatx80_sub(ST0, ST(st_index), &env->fp_status);
464 }
465
466 void helper_fdiv_STN_ST0(CPUX86State *env, int st_index)
467 {
468 floatx80 *p;
469
470 p = &ST(st_index);
471 *p = helper_fdiv(env, *p, ST0);
472 }
473
474 void helper_fdivr_STN_ST0(CPUX86State *env, int st_index)
475 {
476 floatx80 *p;
477
478 p = &ST(st_index);
479 *p = helper_fdiv(env, ST0, *p);
480 }
481
482 /* misc FPU operations */
483 void helper_fchs_ST0(CPUX86State *env)
484 {
485 ST0 = floatx80_chs(ST0);
486 }
487
488 void helper_fabs_ST0(CPUX86State *env)
489 {
490 ST0 = floatx80_abs(ST0);
491 }
492
493 void helper_fld1_ST0(CPUX86State *env)
494 {
495 ST0 = floatx80_one;
496 }
497
498 void helper_fldl2t_ST0(CPUX86State *env)
499 {
500 ST0 = floatx80_l2t;
501 }
502
503 void helper_fldl2e_ST0(CPUX86State *env)
504 {
505 ST0 = floatx80_l2e;
506 }
507
508 void helper_fldpi_ST0(CPUX86State *env)
509 {
510 ST0 = floatx80_pi;
511 }
512
513 void helper_fldlg2_ST0(CPUX86State *env)
514 {
515 ST0 = floatx80_lg2;
516 }
517
518 void helper_fldln2_ST0(CPUX86State *env)
519 {
520 ST0 = floatx80_ln2;
521 }
522
523 void helper_fldz_ST0(CPUX86State *env)
524 {
525 ST0 = floatx80_zero;
526 }
527
528 void helper_fldz_FT0(CPUX86State *env)
529 {
530 FT0 = floatx80_zero;
531 }
532
533 uint32_t helper_fnstsw(CPUX86State *env)
534 {
535 return (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
536 }
537
538 uint32_t helper_fnstcw(CPUX86State *env)
539 {
540 return env->fpuc;
541 }
542
543 static void update_fp_status(CPUX86State *env)
544 {
545 int rnd_type;
546
547 /* set rounding mode */
548 switch (env->fpuc & FPU_RC_MASK) {
549 default:
550 case FPU_RC_NEAR:
551 rnd_type = float_round_nearest_even;
552 break;
553 case FPU_RC_DOWN:
554 rnd_type = float_round_down;
555 break;
556 case FPU_RC_UP:
557 rnd_type = float_round_up;
558 break;
559 case FPU_RC_CHOP:
560 rnd_type = float_round_to_zero;
561 break;
562 }
563 set_float_rounding_mode(rnd_type, &env->fp_status);
564 switch ((env->fpuc >> 8) & 3) {
565 case 0:
566 rnd_type = 32;
567 break;
568 case 2:
569 rnd_type = 64;
570 break;
571 case 3:
572 default:
573 rnd_type = 80;
574 break;
575 }
576 set_floatx80_rounding_precision(rnd_type, &env->fp_status);
577 }
578
579 void helper_fldcw(CPUX86State *env, uint32_t val)
580 {
581 env->fpuc = val;
582 update_fp_status(env);
583 }
584
585 void helper_fclex(CPUX86State *env)
586 {
587 env->fpus &= 0x7f00;
588 }
589
590 void helper_fwait(CPUX86State *env)
591 {
592 if (env->fpus & FPUS_SE) {
593 fpu_raise_exception(env);
594 }
595 }
596
597 void helper_fninit(CPUX86State *env)
598 {
599 env->fpus = 0;
600 env->fpstt = 0;
601 env->fpuc = 0x37f;
602 env->fptags[0] = 1;
603 env->fptags[1] = 1;
604 env->fptags[2] = 1;
605 env->fptags[3] = 1;
606 env->fptags[4] = 1;
607 env->fptags[5] = 1;
608 env->fptags[6] = 1;
609 env->fptags[7] = 1;
610 }
611
612 /* BCD ops */
613
614 void helper_fbld_ST0(CPUX86State *env, target_ulong ptr)
615 {
616 floatx80 tmp;
617 uint64_t val;
618 unsigned int v;
619 int i;
620
621 val = 0;
622 for (i = 8; i >= 0; i--) {
623 v = cpu_ldub_data(env, ptr + i);
624 val = (val * 100) + ((v >> 4) * 10) + (v & 0xf);
625 }
626 tmp = int64_to_floatx80(val, &env->fp_status);
627 if (cpu_ldub_data(env, ptr + 9) & 0x80) {
628 floatx80_chs(tmp);
629 }
630 fpush(env);
631 ST0 = tmp;
632 }
633
634 void helper_fbst_ST0(CPUX86State *env, target_ulong ptr)
635 {
636 int v;
637 target_ulong mem_ref, mem_end;
638 int64_t val;
639
640 val = floatx80_to_int64(ST0, &env->fp_status);
641 mem_ref = ptr;
642 mem_end = mem_ref + 9;
643 if (val < 0) {
644 cpu_stb_data(env, mem_end, 0x80);
645 val = -val;
646 } else {
647 cpu_stb_data(env, mem_end, 0x00);
648 }
649 while (mem_ref < mem_end) {
650 if (val == 0) {
651 break;
652 }
653 v = val % 100;
654 val = val / 100;
655 v = ((v / 10) << 4) | (v % 10);
656 cpu_stb_data(env, mem_ref++, v);
657 }
658 while (mem_ref < mem_end) {
659 cpu_stb_data(env, mem_ref++, 0);
660 }
661 }
662
663 void helper_f2xm1(CPUX86State *env)
664 {
665 double val = floatx80_to_double(env, ST0);
666
667 val = pow(2.0, val) - 1.0;
668 ST0 = double_to_floatx80(env, val);
669 }
670
671 void helper_fyl2x(CPUX86State *env)
672 {
673 double fptemp = floatx80_to_double(env, ST0);
674
675 if (fptemp > 0.0) {
676 fptemp = log(fptemp) / log(2.0); /* log2(ST) */
677 fptemp *= floatx80_to_double(env, ST1);
678 ST1 = double_to_floatx80(env, fptemp);
679 fpop(env);
680 } else {
681 env->fpus &= ~0x4700;
682 env->fpus |= 0x400;
683 }
684 }
685
686 void helper_fptan(CPUX86State *env)
687 {
688 double fptemp = floatx80_to_double(env, ST0);
689
690 if ((fptemp > MAXTAN) || (fptemp < -MAXTAN)) {
691 env->fpus |= 0x400;
692 } else {
693 fptemp = tan(fptemp);
694 ST0 = double_to_floatx80(env, fptemp);
695 fpush(env);
696 ST0 = floatx80_one;
697 env->fpus &= ~0x400; /* C2 <-- 0 */
698 /* the above code is for |arg| < 2**52 only */
699 }
700 }
701
702 void helper_fpatan(CPUX86State *env)
703 {
704 double fptemp, fpsrcop;
705
706 fpsrcop = floatx80_to_double(env, ST1);
707 fptemp = floatx80_to_double(env, ST0);
708 ST1 = double_to_floatx80(env, atan2(fpsrcop, fptemp));
709 fpop(env);
710 }
711
712 void helper_fxtract(CPUX86State *env)
713 {
714 CPU_LDoubleU temp;
715
716 temp.d = ST0;
717
718 if (floatx80_is_zero(ST0)) {
719 /* Easy way to generate -inf and raising division by 0 exception */
720 ST0 = floatx80_div(floatx80_chs(floatx80_one), floatx80_zero,
721 &env->fp_status);
722 fpush(env);
723 ST0 = temp.d;
724 } else {
725 int expdif;
726
727 expdif = EXPD(temp) - EXPBIAS;
728 /* DP exponent bias */
729 ST0 = int32_to_floatx80(expdif, &env->fp_status);
730 fpush(env);
731 BIASEXPONENT(temp);
732 ST0 = temp.d;
733 }
734 }
735
736 void helper_fprem1(CPUX86State *env)
737 {
738 double st0, st1, dblq, fpsrcop, fptemp;
739 CPU_LDoubleU fpsrcop1, fptemp1;
740 int expdif;
741 signed long long int q;
742
743 st0 = floatx80_to_double(env, ST0);
744 st1 = floatx80_to_double(env, ST1);
745
746 if (isinf(st0) || isnan(st0) || isnan(st1) || (st1 == 0.0)) {
747 ST0 = double_to_floatx80(env, 0.0 / 0.0); /* NaN */
748 env->fpus &= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */
749 return;
750 }
751
752 fpsrcop = st0;
753 fptemp = st1;
754 fpsrcop1.d = ST0;
755 fptemp1.d = ST1;
756 expdif = EXPD(fpsrcop1) - EXPD(fptemp1);
757
758 if (expdif < 0) {
759 /* optimisation? taken from the AMD docs */
760 env->fpus &= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */
761 /* ST0 is unchanged */
762 return;
763 }
764
765 if (expdif < 53) {
766 dblq = fpsrcop / fptemp;
767 /* round dblq towards nearest integer */
768 dblq = rint(dblq);
769 st0 = fpsrcop - fptemp * dblq;
770
771 /* convert dblq to q by truncating towards zero */
772 if (dblq < 0.0) {
773 q = (signed long long int)(-dblq);
774 } else {
775 q = (signed long long int)dblq;
776 }
777
778 env->fpus &= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */
779 /* (C0,C3,C1) <-- (q2,q1,q0) */
780 env->fpus |= (q & 0x4) << (8 - 2); /* (C0) <-- q2 */
781 env->fpus |= (q & 0x2) << (14 - 1); /* (C3) <-- q1 */
782 env->fpus |= (q & 0x1) << (9 - 0); /* (C1) <-- q0 */
783 } else {
784 env->fpus |= 0x400; /* C2 <-- 1 */
785 fptemp = pow(2.0, expdif - 50);
786 fpsrcop = (st0 / st1) / fptemp;
787 /* fpsrcop = integer obtained by chopping */
788 fpsrcop = (fpsrcop < 0.0) ?
789 -(floor(fabs(fpsrcop))) : floor(fpsrcop);
790 st0 -= (st1 * fpsrcop * fptemp);
791 }
792 ST0 = double_to_floatx80(env, st0);
793 }
794
795 void helper_fprem(CPUX86State *env)
796 {
797 double st0, st1, dblq, fpsrcop, fptemp;
798 CPU_LDoubleU fpsrcop1, fptemp1;
799 int expdif;
800 signed long long int q;
801
802 st0 = floatx80_to_double(env, ST0);
803 st1 = floatx80_to_double(env, ST1);
804
805 if (isinf(st0) || isnan(st0) || isnan(st1) || (st1 == 0.0)) {
806 ST0 = double_to_floatx80(env, 0.0 / 0.0); /* NaN */
807 env->fpus &= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */
808 return;
809 }
810
811 fpsrcop = st0;
812 fptemp = st1;
813 fpsrcop1.d = ST0;
814 fptemp1.d = ST1;
815 expdif = EXPD(fpsrcop1) - EXPD(fptemp1);
816
817 if (expdif < 0) {
818 /* optimisation? taken from the AMD docs */
819 env->fpus &= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */
820 /* ST0 is unchanged */
821 return;
822 }
823
824 if (expdif < 53) {
825 dblq = fpsrcop / fptemp; /* ST0 / ST1 */
826 /* round dblq towards zero */
827 dblq = (dblq < 0.0) ? ceil(dblq) : floor(dblq);
828 st0 = fpsrcop - fptemp * dblq; /* fpsrcop is ST0 */
829
830 /* convert dblq to q by truncating towards zero */
831 if (dblq < 0.0) {
832 q = (signed long long int)(-dblq);
833 } else {
834 q = (signed long long int)dblq;
835 }
836
837 env->fpus &= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */
838 /* (C0,C3,C1) <-- (q2,q1,q0) */
839 env->fpus |= (q & 0x4) << (8 - 2); /* (C0) <-- q2 */
840 env->fpus |= (q & 0x2) << (14 - 1); /* (C3) <-- q1 */
841 env->fpus |= (q & 0x1) << (9 - 0); /* (C1) <-- q0 */
842 } else {
843 int N = 32 + (expdif % 32); /* as per AMD docs */
844
845 env->fpus |= 0x400; /* C2 <-- 1 */
846 fptemp = pow(2.0, (double)(expdif - N));
847 fpsrcop = (st0 / st1) / fptemp;
848 /* fpsrcop = integer obtained by chopping */
849 fpsrcop = (fpsrcop < 0.0) ?
850 -(floor(fabs(fpsrcop))) : floor(fpsrcop);
851 st0 -= (st1 * fpsrcop * fptemp);
852 }
853 ST0 = double_to_floatx80(env, st0);
854 }
855
856 void helper_fyl2xp1(CPUX86State *env)
857 {
858 double fptemp = floatx80_to_double(env, ST0);
859
860 if ((fptemp + 1.0) > 0.0) {
861 fptemp = log(fptemp + 1.0) / log(2.0); /* log2(ST + 1.0) */
862 fptemp *= floatx80_to_double(env, ST1);
863 ST1 = double_to_floatx80(env, fptemp);
864 fpop(env);
865 } else {
866 env->fpus &= ~0x4700;
867 env->fpus |= 0x400;
868 }
869 }
870
871 void helper_fsqrt(CPUX86State *env)
872 {
873 if (floatx80_is_neg(ST0)) {
874 env->fpus &= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */
875 env->fpus |= 0x400;
876 }
877 ST0 = floatx80_sqrt(ST0, &env->fp_status);
878 }
879
880 void helper_fsincos(CPUX86State *env)
881 {
882 double fptemp = floatx80_to_double(env, ST0);
883
884 if ((fptemp > MAXTAN) || (fptemp < -MAXTAN)) {
885 env->fpus |= 0x400;
886 } else {
887 ST0 = double_to_floatx80(env, sin(fptemp));
888 fpush(env);
889 ST0 = double_to_floatx80(env, cos(fptemp));
890 env->fpus &= ~0x400; /* C2 <-- 0 */
891 /* the above code is for |arg| < 2**63 only */
892 }
893 }
894
895 void helper_frndint(CPUX86State *env)
896 {
897 ST0 = floatx80_round_to_int(ST0, &env->fp_status);
898 }
899
900 void helper_fscale(CPUX86State *env)
901 {
902 if (floatx80_is_any_nan(ST1)) {
903 ST0 = ST1;
904 } else {
905 int n = floatx80_to_int32_round_to_zero(ST1, &env->fp_status);
906 ST0 = floatx80_scalbn(ST0, n, &env->fp_status);
907 }
908 }
909
910 void helper_fsin(CPUX86State *env)
911 {
912 double fptemp = floatx80_to_double(env, ST0);
913
914 if ((fptemp > MAXTAN) || (fptemp < -MAXTAN)) {
915 env->fpus |= 0x400;
916 } else {
917 ST0 = double_to_floatx80(env, sin(fptemp));
918 env->fpus &= ~0x400; /* C2 <-- 0 */
919 /* the above code is for |arg| < 2**53 only */
920 }
921 }
922
923 void helper_fcos(CPUX86State *env)
924 {
925 double fptemp = floatx80_to_double(env, ST0);
926
927 if ((fptemp > MAXTAN) || (fptemp < -MAXTAN)) {
928 env->fpus |= 0x400;
929 } else {
930 ST0 = double_to_floatx80(env, cos(fptemp));
931 env->fpus &= ~0x400; /* C2 <-- 0 */
932 /* the above code is for |arg| < 2**63 only */
933 }
934 }
935
936 void helper_fxam_ST0(CPUX86State *env)
937 {
938 CPU_LDoubleU temp;
939 int expdif;
940
941 temp.d = ST0;
942
943 env->fpus &= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */
944 if (SIGND(temp)) {
945 env->fpus |= 0x200; /* C1 <-- 1 */
946 }
947
948 /* XXX: test fptags too */
949 expdif = EXPD(temp);
950 if (expdif == MAXEXPD) {
951 if (MANTD(temp) == 0x8000000000000000ULL) {
952 env->fpus |= 0x500; /* Infinity */
953 } else {
954 env->fpus |= 0x100; /* NaN */
955 }
956 } else if (expdif == 0) {
957 if (MANTD(temp) == 0) {
958 env->fpus |= 0x4000; /* Zero */
959 } else {
960 env->fpus |= 0x4400; /* Denormal */
961 }
962 } else {
963 env->fpus |= 0x400;
964 }
965 }
966
967 void helper_fstenv(CPUX86State *env, target_ulong ptr, int data32)
968 {
969 int fpus, fptag, exp, i;
970 uint64_t mant;
971 CPU_LDoubleU tmp;
972
973 fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
974 fptag = 0;
975 for (i = 7; i >= 0; i--) {
976 fptag <<= 2;
977 if (env->fptags[i]) {
978 fptag |= 3;
979 } else {
980 tmp.d = env->fpregs[i].d;
981 exp = EXPD(tmp);
982 mant = MANTD(tmp);
983 if (exp == 0 && mant == 0) {
984 /* zero */
985 fptag |= 1;
986 } else if (exp == 0 || exp == MAXEXPD
987 || (mant & (1LL << 63)) == 0) {
988 /* NaNs, infinity, denormal */
989 fptag |= 2;
990 }
991 }
992 }
993 if (data32) {
994 /* 32 bit */
995 cpu_stl_data(env, ptr, env->fpuc);
996 cpu_stl_data(env, ptr + 4, fpus);
997 cpu_stl_data(env, ptr + 8, fptag);
998 cpu_stl_data(env, ptr + 12, 0); /* fpip */
999 cpu_stl_data(env, ptr + 16, 0); /* fpcs */
1000 cpu_stl_data(env, ptr + 20, 0); /* fpoo */
1001 cpu_stl_data(env, ptr + 24, 0); /* fpos */
1002 } else {
1003 /* 16 bit */
1004 cpu_stw_data(env, ptr, env->fpuc);
1005 cpu_stw_data(env, ptr + 2, fpus);
1006 cpu_stw_data(env, ptr + 4, fptag);
1007 cpu_stw_data(env, ptr + 6, 0);
1008 cpu_stw_data(env, ptr + 8, 0);
1009 cpu_stw_data(env, ptr + 10, 0);
1010 cpu_stw_data(env, ptr + 12, 0);
1011 }
1012 }
1013
1014 void helper_fldenv(CPUX86State *env, target_ulong ptr, int data32)
1015 {
1016 int i, fpus, fptag;
1017
1018 if (data32) {
1019 env->fpuc = cpu_lduw_data(env, ptr);
1020 fpus = cpu_lduw_data(env, ptr + 4);
1021 fptag = cpu_lduw_data(env, ptr + 8);
1022 } else {
1023 env->fpuc = cpu_lduw_data(env, ptr);
1024 fpus = cpu_lduw_data(env, ptr + 2);
1025 fptag = cpu_lduw_data(env, ptr + 4);
1026 }
1027 env->fpstt = (fpus >> 11) & 7;
1028 env->fpus = fpus & ~0x3800;
1029 for (i = 0; i < 8; i++) {
1030 env->fptags[i] = ((fptag & 3) == 3);
1031 fptag >>= 2;
1032 }
1033 }
1034
1035 void helper_fsave(CPUX86State *env, target_ulong ptr, int data32)
1036 {
1037 floatx80 tmp;
1038 int i;
1039
1040 helper_fstenv(env, ptr, data32);
1041
1042 ptr += (14 << data32);
1043 for (i = 0; i < 8; i++) {
1044 tmp = ST(i);
1045 helper_fstt(env, tmp, ptr);
1046 ptr += 10;
1047 }
1048
1049 /* fninit */
1050 env->fpus = 0;
1051 env->fpstt = 0;
1052 env->fpuc = 0x37f;
1053 env->fptags[0] = 1;
1054 env->fptags[1] = 1;
1055 env->fptags[2] = 1;
1056 env->fptags[3] = 1;
1057 env->fptags[4] = 1;
1058 env->fptags[5] = 1;
1059 env->fptags[6] = 1;
1060 env->fptags[7] = 1;
1061 }
1062
1063 void helper_frstor(CPUX86State *env, target_ulong ptr, int data32)
1064 {
1065 floatx80 tmp;
1066 int i;
1067
1068 helper_fldenv(env, ptr, data32);
1069 ptr += (14 << data32);
1070
1071 for (i = 0; i < 8; i++) {
1072 tmp = helper_fldt(env, ptr);
1073 ST(i) = tmp;
1074 ptr += 10;
1075 }
1076 }
1077
1078 #if defined(CONFIG_USER_ONLY)
1079 void cpu_x86_fsave(CPUX86State *env, target_ulong ptr, int data32)
1080 {
1081 helper_fsave(env, ptr, data32);
1082 }
1083
1084 void cpu_x86_frstor(CPUX86State *env, target_ulong ptr, int data32)
1085 {
1086 helper_frstor(env, ptr, data32);
1087 }
1088 #endif
1089
1090 void helper_fxsave(CPUX86State *env, target_ulong ptr, int data64)
1091 {
1092 int fpus, fptag, i, nb_xmm_regs;
1093 floatx80 tmp;
1094 target_ulong addr;
1095
1096 /* The operand must be 16 byte aligned */
1097 if (ptr & 0xf) {
1098 raise_exception(env, EXCP0D_GPF);
1099 }
1100
1101 fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
1102 fptag = 0;
1103 for (i = 0; i < 8; i++) {
1104 fptag |= (env->fptags[i] << i);
1105 }
1106 cpu_stw_data(env, ptr, env->fpuc);
1107 cpu_stw_data(env, ptr + 2, fpus);
1108 cpu_stw_data(env, ptr + 4, fptag ^ 0xff);
1109 #ifdef TARGET_X86_64
1110 if (data64) {
1111 cpu_stq_data(env, ptr + 0x08, 0); /* rip */
1112 cpu_stq_data(env, ptr + 0x10, 0); /* rdp */
1113 } else
1114 #endif
1115 {
1116 cpu_stl_data(env, ptr + 0x08, 0); /* eip */
1117 cpu_stl_data(env, ptr + 0x0c, 0); /* sel */
1118 cpu_stl_data(env, ptr + 0x10, 0); /* dp */
1119 cpu_stl_data(env, ptr + 0x14, 0); /* sel */
1120 }
1121
1122 addr = ptr + 0x20;
1123 for (i = 0; i < 8; i++) {
1124 tmp = ST(i);
1125 helper_fstt(env, tmp, addr);
1126 addr += 16;
1127 }
1128
1129 if (env->cr[4] & CR4_OSFXSR_MASK) {
1130 /* XXX: finish it */
1131 cpu_stl_data(env, ptr + 0x18, env->mxcsr); /* mxcsr */
1132 cpu_stl_data(env, ptr + 0x1c, 0x0000ffff); /* mxcsr_mask */
1133 if (env->hflags & HF_CS64_MASK) {
1134 nb_xmm_regs = 16;
1135 } else {
1136 nb_xmm_regs = 8;
1137 }
1138 addr = ptr + 0xa0;
1139 /* Fast FXSAVE leaves out the XMM registers */
1140 if (!(env->efer & MSR_EFER_FFXSR)
1141 || (env->hflags & HF_CPL_MASK)
1142 || !(env->hflags & HF_LMA_MASK)) {
1143 for (i = 0; i < nb_xmm_regs; i++) {
1144 cpu_stq_data(env, addr, env->xmm_regs[i].XMM_Q(0));
1145 cpu_stq_data(env, addr + 8, env->xmm_regs[i].XMM_Q(1));
1146 addr += 16;
1147 }
1148 }
1149 }
1150 }
1151
1152 void helper_fxrstor(CPUX86State *env, target_ulong ptr, int data64)
1153 {
1154 int i, fpus, fptag, nb_xmm_regs;
1155 floatx80 tmp;
1156 target_ulong addr;
1157
1158 /* The operand must be 16 byte aligned */
1159 if (ptr & 0xf) {
1160 raise_exception(env, EXCP0D_GPF);
1161 }
1162
1163 env->fpuc = cpu_lduw_data(env, ptr);
1164 fpus = cpu_lduw_data(env, ptr + 2);
1165 fptag = cpu_lduw_data(env, ptr + 4);
1166 env->fpstt = (fpus >> 11) & 7;
1167 env->fpus = fpus & ~0x3800;
1168 fptag ^= 0xff;
1169 for (i = 0; i < 8; i++) {
1170 env->fptags[i] = ((fptag >> i) & 1);
1171 }
1172
1173 addr = ptr + 0x20;
1174 for (i = 0; i < 8; i++) {
1175 tmp = helper_fldt(env, addr);
1176 ST(i) = tmp;
1177 addr += 16;
1178 }
1179
1180 if (env->cr[4] & CR4_OSFXSR_MASK) {
1181 /* XXX: finish it */
1182 env->mxcsr = cpu_ldl_data(env, ptr + 0x18);
1183 /* cpu_ldl_data(env, ptr + 0x1c); */
1184 if (env->hflags & HF_CS64_MASK) {
1185 nb_xmm_regs = 16;
1186 } else {
1187 nb_xmm_regs = 8;
1188 }
1189 addr = ptr + 0xa0;
1190 /* Fast FXRESTORE leaves out the XMM registers */
1191 if (!(env->efer & MSR_EFER_FFXSR)
1192 || (env->hflags & HF_CPL_MASK)
1193 || !(env->hflags & HF_LMA_MASK)) {
1194 for (i = 0; i < nb_xmm_regs; i++) {
1195 env->xmm_regs[i].XMM_Q(0) = cpu_ldq_data(env, addr);
1196 env->xmm_regs[i].XMM_Q(1) = cpu_ldq_data(env, addr + 8);
1197 addr += 16;
1198 }
1199 }
1200 }
1201 }
1202
1203 void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, floatx80 f)
1204 {
1205 CPU_LDoubleU temp;
1206
1207 temp.d = f;
1208 *pmant = temp.l.lower;
1209 *pexp = temp.l.upper;
1210 }
1211
1212 floatx80 cpu_set_fp80(uint64_t mant, uint16_t upper)
1213 {
1214 CPU_LDoubleU temp;
1215
1216 temp.l.upper = upper;
1217 temp.l.lower = mant;
1218 return temp.d;
1219 }
1220
1221 /* MMX/SSE */
1222 /* XXX: optimize by storing fptt and fptags in the static cpu state */
1223
1224 #define SSE_DAZ 0x0040
1225 #define SSE_RC_MASK 0x6000
1226 #define SSE_RC_NEAR 0x0000
1227 #define SSE_RC_DOWN 0x2000
1228 #define SSE_RC_UP 0x4000
1229 #define SSE_RC_CHOP 0x6000
1230 #define SSE_FZ 0x8000
1231
1232 static void update_sse_status(CPUX86State *env)
1233 {
1234 int rnd_type;
1235
1236 /* set rounding mode */
1237 switch (env->mxcsr & SSE_RC_MASK) {
1238 default:
1239 case SSE_RC_NEAR:
1240 rnd_type = float_round_nearest_even;
1241 break;
1242 case SSE_RC_DOWN:
1243 rnd_type = float_round_down;
1244 break;
1245 case SSE_RC_UP:
1246 rnd_type = float_round_up;
1247 break;
1248 case SSE_RC_CHOP:
1249 rnd_type = float_round_to_zero;
1250 break;
1251 }
1252 set_float_rounding_mode(rnd_type, &env->sse_status);
1253
1254 /* set denormals are zero */
1255 set_flush_inputs_to_zero((env->mxcsr & SSE_DAZ) ? 1 : 0, &env->sse_status);
1256
1257 /* set flush to zero */
1258 set_flush_to_zero((env->mxcsr & SSE_FZ) ? 1 : 0, &env->fp_status);
1259 }
1260
1261 void helper_ldmxcsr(CPUX86State *env, uint32_t val)
1262 {
1263 env->mxcsr = val;
1264 update_sse_status(env);
1265 }
1266
1267 void helper_enter_mmx(CPUX86State *env)
1268 {
1269 env->fpstt = 0;
1270 *(uint32_t *)(env->fptags) = 0;
1271 *(uint32_t *)(env->fptags + 4) = 0;
1272 }
1273
1274 void helper_emms(CPUX86State *env)
1275 {
1276 /* set to empty state */
1277 *(uint32_t *)(env->fptags) = 0x01010101;
1278 *(uint32_t *)(env->fptags + 4) = 0x01010101;
1279 }
1280
1281 /* XXX: suppress */
1282 void helper_movq(CPUX86State *env, void *d, void *s)
1283 {
1284 *(uint64_t *)d = *(uint64_t *)s;
1285 }
1286
1287 #define SHIFT 0
1288 #include "ops_sse.h"
1289
1290 #define SHIFT 1
1291 #include "ops_sse.h"